Freescale Semiconductor Technical Data Document number: MM908E626 Rev. 11.0, 2/2013 Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication The 908E626 is an integrated single package solution that includes a high performance HC08 microcontroller with a SMARTMOS analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), internal serial peripheral interface (SPI), and an internal clock generator (ICG) module. The analog control die provides fully protected H-Bridge outputs, voltage regulator, autonomous watchdog, and local interconnect network (LIN) physical layer. 908E626 STEPPER MOTOR DRIVER WITH EMBEDDED MCU AND LIN The single package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well-suited for the control of automotive stepper applications like climate control and light-leveling. EK SUFFIX (PB-FREE) 98ARL10519D 54-PIN SOICW-EP Features • High performance M68HC08EY16 core • 16 KB of on-chip flash memory • 512 B of RAM • Internal clock generation module • Two 16-bit, two-channel timers • 10-bit analog-to-digital converter • Four low RDS(ON) half-bridge outputs • 13 microcontroller I/Os ORDERING INFORMATION Device (Add an R2 suffix for Tape and reel orders) MM908E626AVPEK Temperature Range (TA) Package -40 to 115 °C 54 SOICW EP 908E626 VSP1:3] LIN VREFH VDDA HB1 EVDD VDD HB2 VREFL VSSA EVSS HB3 VSS RST HB4 RST A IRQ IRQ A SS HVDD PTB1/AD1 RXD PTE1/RXD PTD1/TACH1 PORTA I/Os FGEN PORTB I/Os BEMF PORTC I/Os PTD0/TACH0/BEMF GND[1:2] EP N S Figure 1. 908E626 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005-2012. All rights reserved. Bipolar Step Motor Switchable Internal VDD Output Microcontroller Ports 2 DDRA PORT A FLSVPP Security Module Power-ON Reset Module PTE0/TXD PTE1/RXD PTD0/TACH0 PTD1/TACH1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO BEMF Module Prescaler Module PTB0/AD0 PTA5/SPSCK Periodic Wake-up Timebase Module Arbiter Module MOSI PTC1/MOSI Configuration Register Module ADOUT SPSCK MISO SS PTC0/MISO PTE1/RXD Serial Peripheral Interface Module Computer Operating Properly Module PORT C DDRC PTC4/OSC1 PTC3/OSC2 Single External IRQ Module VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS IRQ RST 24 Integral System Integration Module PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 MCU Die PTB0/AD0 VREFH PTC2/MCLK PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 VDDA PTB4/AD4 EVDD PTB3/AD3 EVSS OSC2 Internal Clock OSC1 Generator Module IRQ PTA4/KBD4 VREFL Enhanced Serial Communication Interface Module SS PTA3/KBD3 VSSA Analog Multiplexer VSUP Prescaler Chip Temp Autonomous Watchdog SPI & CONTROL Interrupt Control Module Reset Control Module LIN Physical Layer BEMF BEMF FGEN BEMF FGEN FGEN BEMF FGEN RST_A PTA2/KBD2 RST User Flash Vector Space, 36 Bytes PTB1/AD1 PTA1/KBD1 PTA0/KBD0 PTD1/TACH1 2-channel Timer Interface Module B TXD LIN 2-channel Timer Interface Module A PTE0/TXD FGEN 5-Bit Keyboard Interrupt Module BEMF Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), 1024 Bytes PTD0/TACH0 Single Breakpoint Break Module VSUP VSUP VSUP VSUP Analog Die Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Half Bridge Driver & Diagnostic Switched VDD Driver & Diagnostic Voltage Regulator VSUP1-3 M68HC08 CPU CPU ALU Registers GND1-2 IRQ_A RXD PORT D PORT E DDRD DDRE Internal Bus DDRB PORT B Figure 2. 908E626 Simplified Internal Block Diagram 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor HB4 HB3 HB2 HB1 HVDD VDD VSS PIN CONNECTIONS PIN CONNECTIONS Transparent Top View of Package PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 IRQ RST 9 46 10 45 PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF 11 44 12 43 16 39 RST_A 17 38 IRQ_A SS 18 37 19 36 LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 13 14 15 42 Exposed Pad 41 40 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS NC VDD NC NC NC HVDD NC HB4 VSUP3 GND2 HB3 NC Figure 3. 908E626 Pin Connections Table 1. 908E626 PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin Description section beginning on page 15. Die Pin Pin Name Formal Name Definition MCU 1 2 6 7 8 11 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 Port B I/Os These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. MCU 3 4 5 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK Port C I/Os These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. MCU 9 IRQ External Interrupt Input MCU 10 RST External Reset This pin is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. MCU 12 13 PTD0/TACH0/BEMF PTD1/TACH1 Port D I /Os These pins are special function, bidirectional I /O port pins that are shared with other functional modules in the MCU. This pin is an asynchronous external interrupt input pin. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 908E626 PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin Description section beginning on page 15. Die Pin Pin Name Formal Name Definition – 14, 21, 22, 28, 33, 35, 36, 37, 39 NC No Connect MCU 42 PTE1/ RXD Port E I /O This pin is a special function, bidirectional I/O port pin that can is shared with other functional modules in the MCU. MCU 43 48 VREFL VREFH ADC References These pins are the reference voltage pins for the analog-to-digital converter (ADC). MCU 44 47 VSSA VDDA ADC Supply Pins These pins are the power supply pins for the analog-to-digital converter. MCU 45 46 EVSS EVDD MCU Power Supply Pins These pins are the ground and power supply pins, respectively. The MCU operates from a single power supply. MCU 49 50 52 53 54 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 Port A I /Os These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. MCU 51 FLSVPP Test Pin Analog 15 FGEN Current Limitation Frequency Input Analog 16 BEMF Back Electromagnetic Force Output Analog 17 RST_A Internal Reset Analog 18 IRQ_A Internal Interrupt Output Analog 19 SS Slave Select Analog 20 LIN LIN Bus Analog 23 26 29 32 HB1 HB2 HB3 HB4 Half-bridge Outputs This device includes power MOSFETs configured as four half-bridge driver outputs. These outputs may be configured for step motor drivers, DC motor drivers, or as high side and low side switches. Analog 24 27 31 VSUP1 VSUP2 VSUP3 Power Supply Pins These pins are device power supply pins. Analog 25 30 GND1 GND2 Power Ground Pins These pins are device power ground connections. Analog 34 HVDD Switchable VDD Output Analog 38 VDD Voltage Regulator Output The 5.0 V voltage regulator output pin is intended to supply the embedded microcontroller. Analog 40 VSS Voltage Regulator Ground Ground pin for the connection of all non-power ground connections (microcontroller and sensors). Analog 41 RXD LIN Transceiver Output – EP Exposed Pad Exposed Pad Not connected. For test purposes only. Do not connect in the application. This is the input pin for the half-bridge current limitation PWM frequency. This pin gives the user information about back electromagnetic force (BEMF). This pin is the bidirectional reset pin of the analog die. This pin is the interrupt output pin of the analog die indicating errors or wake-up events. This pin is the SPI slave select pin for the analog chip. This pin represents the single-wire bus transmitter and receiver. This pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3 pin Hall-effect sensors. This pin is the output of LIN transceiver. The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board. 908E626 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to the device. Rating Symbol Value Unit Analog Chip Supply Voltage under Normal Operation (Steadystate) VSUP(SS) - 0.3 to 28 Analog Chip Supply Voltage under Transient Conditions (1) VSUP(PK) - 0.3 to 40 VDD - 0.3 to 6.0 VIN (ANALOG) - 0.3 to 5.5 VIN (MCU) VSS - 0.3 to VDD + 0.3 All Pins Except VDD, VSS, PTA0 : PTA6, PTC0 : PTC1 IPIN(1) ±15 Pins PTA0 : PTA6, PTC0 : PTC1 IPIN(2) ± 25 Maximum Microcontroller VSS Output Current IMVSS 100 mA Maximum Microcontroller VDD Input Current IMVDD 100 mA VBUS(SS) -18 to 28 VBUS(DYNAMIC) 40 ELECTRICAL RATINGS Supply Voltage V Microcontroller Chip Supply Voltage Input Pin Voltage V Analog Chip Microcontroller Chip Maximum Microcontroller Current per Pin mA LIN Supply Voltage V Normal Operation (Steady-state) Transient Conditions (1) ESD Voltage V Human Body Model Machine Model (2) (3) Charge Device Model (4) VESD1 ± 3000 VESD2 ± 150 VESD3 ± 500 Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 3. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 4. ESD3 testing is performed in accordance with Charge Device Model, robotic (CZAP = 4.0 pF). 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to the device. Rating Symbol Value Unit TSTG - 40 to 150 C Operating Case Temperature (5) TC - 40 to 115 C Operating Junction Temperature(6) TJ - 40 to 135 C TPPRT Note 8 C THERMAL RATINGS Storage Temperature Peak Package Reflow Temperature During Solder Mounting (7)(8) Notes 5. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. 6. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation on the analog die. The analog die temperature must not exceed 150 °C under these conditions 7. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 908E626 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 8.0 – 18 V – 20 – – – 75 SUPPLY VOLTAGE Nominal Operating Voltage SUPPLY CURRENT NORMAL Mode VSUP = 12 V, Power Die ON (PSON = 1), MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled STOP Mode (9) VSUP = 12 V, Cyclic Wake-up Disabled IRUN ISTOP mA A DIGITAL INTERFACE RATINGS (ANALOG DIE) V Output Pins RST_A, IRQ_A Low State Output Voltage (IOUT = - 1.5 mA) VOL – – 0.4 High State Output Voltage (IOUT = 1.0 A) VOH 3.85 – – Low State Output Voltage (IOUT = - 1.5 mA) VOL – – 0.4 High State Output Voltage (IOUT = 1.5 mA) VOH 3.85 – – CIN – 4.0 – Input Logic Low Voltage VIL – – 1.5 Input Logic High Voltage VIH 3.5 – – CIN – 4.0 – pF Pins RST_A, IRQ_A – Pull-up Resistor RPULLUP1 – 10 – k Pin SS – Pull-up Resistor RPULLUP2 – 60 – k RPULLDOWN – 60 – k IPULLUP – 35 – A Output Pins BEMF, RXD Output Pin RXD – Capacitance (10) V V Input Pins RST_A, FGEN, SS Input Pins RST_A, FGEN, SS – Capacitance (10) Pins FGEN, MOSI, SPSCK – Pull-down Resistor Pin TXD – Pull-up Current Source pF Notes 9. STOP mode current will increase if VSUP exceeds 15 V. 10. This parameter is guaranteed by process monitoring but is not production tested. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Threshold VHVRON 27 30 33 Hysteresis VHVRH – 1.5 – Threshold VLVRON 3.6 4.0 4.7 V Hysteresis VLVRH – 100 – mV SYSTEM RESETS AND INTERRUPTS V High Voltage Reset Low Voltage Reset High Voltage Interrupt V Threshold VHVION 17.5 21 23 Hysteresis VHVIH – 1.0 – Threshold VLVION 6.5 – 8.0 Hysteresis VLVIH – 0.4 – Threshold TRON – 170 – Hysteresis TRH 5.0 – – Threshold TION – 160 – Hysteresis TIH 5.0 – – 4.75 5.0 5.25 – – 100 4.45 4.7 5.0 V Low Voltage Interrupt C High Temperature Reset (12) C High Temperature Interrupt (13) VOLTAGE REGULATOR Normal Mode Output Voltage Load Regulation VLR IOUT = 80 mA, VSUP = 9.0 V STOP Mode Output Voltage (Maximum Output Current 100 A)(11) V VDDRUN IOUT = 60 mA, 6.0 V < VSUP < 18 V VDDSTOP mV V Notes 11. Tested to be VLVRON < VDDSTOP 12. This parameter is guaranteed by process monitoring but is not production tested. 13. High Temperature Interrupt (HTI) threshold is linked to High Temperature Reset (HTR) threshold (HTR = HTI + 10 C). 908E626 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max – – 1.4 VSUP - 1.0 – – 20 30 60 0.0 – 20 Including Internal Pull-up Resistor, VLIN @ -18 V IBUS_NO_GND – - 600 – Including Internal Pull-up Resistor, VLIN @ +18 V IBUS – 25 – Recessive VIH 0.6VLIN – VSUP Dominant VIL 0 – 0.4VLIN VITH – VSUP / 2 – VIHY 0.01VSUP – 0.1VSUP VWTH – VSUP / 2 – Unit LIN PHYSICAL LAYER Output Low Level VLIN-LOW TXD LOW, 500 Pull-up to VSUP Output High Level V V VLIN-HIGH TXD HIGH, IOUT = 1.0 A Pull-up Resistor to VSUP RSLAVE Leakage Current to GND IBUS_PAS_REC Recessive State (- 0.5 V < VLIN < VSUP) A A Leakage Current to GND (VSUP Disconnected) V LIN Receiver Threshold Input Hysteresis LIN Wake-up Threshold k V HALF-BRIDGE OUTPUTS (HB1 : HB4) Switch ON Resistance @ TJ = 25 C with ILOAD = 1.0 A m High Side RDS(ON)HB_HS – 425 500 Low Side RDS(ON)HB_LS – 400 500 High Side Overcurrent Shutdown IHBHSOC 3.0 – 7.5 A Low Side Overcurrent Shutdown IHBLSOC 2.5 – 7.5 A ICL1 – 55 – Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) ICL2 210 260 315 Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) ICL3 300 370 440 Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) ICL4 450 550 650 Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) ICL5 600 740 880 Half-bridge Output HIGH Threshold for BEMF Detection VBEMFH – - 30 0.0 V Half-bridge Output LOW Threshold for BEMF Detection VBEMFL – - 60 - 5.0 mV VBEMFHY – 30 – mV Low Side Current Limitation @ TJ = 25 C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Hysteresis for BEMF Detection mA Low Side Current-to-Voltage Ratio (VADOUT [V] / IHB [A]) V/A CSA = 1 RATIOH 7.0 12.0 14.0 CSA = 0 RATIOL 1.0 2.0 3.0 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit IHVDDOCT 24 30 40 mA RATIOVSUP 4.8 5.1 5.35 – STTOV – 19 – mV/ °C VT25 1.7 2.1 2.5 V SWITCHABLE VDD OUTPUT (HVDD) Overcurrent Shutdown Threshold VSUP DOWN-SCALER Voltage Ratio (RATIOVSUP = VSUP / VADOUT) INTERNAL DIE TEMPERATURE SENSOR Voltage / Temperature Slope Output Voltage @ 25 °C 908E626 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER s Propagation Delay (14), (15) t TXD-LIN-LOW – – – – - 2.0 - 2.0 – – 4.0 4.0 – – 6.0 6.0 8.0 8.0 2.0 2.0 -1.0 - 2.0 - 3.0 1.0 2.0 3.0 SRS - 2.0 – 2.0 s t OSC – 40 – s TJ < 25 °C 16 27 34 TJ 25 °C 16 22 28 TJ < 25 °C 8.0 13.5 17 TJ 25 °C 8.0 11 14 – 90 – TXD LOW to LIN LOW t TXD-LIN-HIGH TXD HIGH to LIN HIGH t LIN-RXD-LOW LIN LOW to RXD LOW t LIN-RXD-HIGH LIN HIGH to RXD HIGH TXD Symmetry t TXD-SYM RXD Symmetry t RXD-SYM SRF Output Falling Edge Slew Rate (14), (16) 80% to 20% V/s SRR Output Rising Edge Slew Rate (14), (16) 20% to 80%, RBUS > 1.0 k, CBUS < 10 nF LIN Rise / Fall Slew Rate Symmetry (14), (16) V/s AUTONOMOUS WATCHDOG (AWD) AWD Oscillator Period t AWDPH AWD Period Low = 512 t OSC ms t AWDPL AWD Period High = 256 t OSC AWD Cyclic Wake-up On Time ms t AWDHPON s Notes 14. All LIN characteristics are for initial LIN slew rate selection (20 kbaud) (SRS0 : SRS1= 00). 15. See Figure 4, page 12. 16. See Figure 5, page 13. MICROCONTROLLER PARAMETRICS Table 5. MICROCONTROLLER For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet. Module Description Core High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Timer Two 16-Bit Timers with Two Channels (TIM A and TIM B) Flash 16 k Bytes RAM 512 Bytes 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS Table 5. MICROCONTROLLER For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet. Module Description ADC 10 Bit Analog-to-Digital Converter SPI SPI Module ESCI Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud Rate Adjustment ICG Internal Clock Generation Module BEMF Counter Special Counter for SMARTMOS BEMF Output TIMING DIAGRAMS t TXD-LIN-LOW t Tx-LIN-low t TXD-LIN-HIGH tTx-LIN-high TXD Tx TXD LIN LIN Recessive State 0.9 VSUP VSUP 0.9 Recessive State 0.7 VLIN 0.6 VSUP 0.4 VSUP 0.3 VLIN 0.1 SUP 0.1 V VSUP Dominant State Rx RXD t LIN-RXD-LOW t LIN-Rx-low ttLIN-RXD-HIGH LIN-Rx-high Figure 4. LIN Timing Description 908E626 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS FUNCTIONAL DIAGRAMS t Fall-time t Rise-time 0.8 VSUP 0.8 VSUP 0.8 VSUP VSUP V Fall V Rise 0.2 VSUP VSUP 0.2 0.2VSUP VSUP 0.2 Dominant State SRF = V Fall t Fall-time SRR = V Rise t Rise-time Figure 5. LIN Slew Rate Description FUNCTIONAL DIAGRAMS 1.6 1.4 1.2 TJ = 25°C Volts Volts 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Amperes Amperes 4.0 4.5 5.0 H-Bridge Low Side Figure 6. Free Wheel Diode Forward Voltage 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS FUNCTIONAL DIAGRAMS 250 200 Dropout Drop Out(mV) (mV) TA = 125°C 150 100 TA = 25°C 50 TA = -40°C 0 0 5 5.0 10 15 I (mA) I Load (mA) 20 25 LOAD Figure 7. Dropout Voltage on HVDD 908E626 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E626 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E626 is well suited to perform stepper motor control, e.g. for climate or light-levelling control via a 3-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS IC chip. The SMARTMOS IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS IC configured as four half-bridge outputs. Other ports are also provided including a selectable HVDD pin. An internal voltage regulator is provided on the SMARTMOS IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL PIN DESCRIPTION See Figures 1, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on Figures 3 for a depiction of the pin locations on the package. PORT A I /O PINS (PTA0:4) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt pins, KBD0 : KBD4. The PTA5/SPSCK pin is not accessible in this device and is internally connected to the SPI clock pin of the analog die. The PTA6/SS pin is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT B I/O PINS (PTB1, PTB3:7) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. All pins are shared with the ADC module. The PTB6 : PTB7 pins are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT pin of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 pin is not accessible in this device. For details refer to the 68HC908EY16 datasheet. PORT C I/O PINS (PTC2:4) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI pins of the analog die. For details refer to the 68HC908EY16 datasheet. PORT D I /O PINS (PTD0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are special function, bidirectional I /O port pins that can also be programmed to be timer pins. In step motor applications, the PTD0 pin should be connected to the BEMF output of the analog die, to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 pin is recommended for use as an output pin for generating the FGEN signal (PWM signal), if required by the application. PORT E I /O PIN (PTE1) PTE1/ RXD and PTE0/ TXD are special function, bidirectional I/O port pins that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD pin of the analog die.The connection for the receiver must be done externally. EXTERNAL INTERRUPT PIN (IRQ) The IRQ pin is an asynchronous external interrupt pin. This pin contains an internal pull-up resistor that is always activated, even when the IRQ pin is pulled LOW. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET PIN (RST) A logic [0] on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This pin contains an internal pull-up resistor that is always activated, even when the reset pin is pulled LOW. For details refer to the 68HC908EY16 datasheet. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CURRENT LIMITATION FREQUENCY INPUT PIN (FGEN) requirements of the half-bridge driver outputs, multiple VSUP pins are provided. Input pin for the half-bridge current limitation PWM frequency. This input is not a real PWM input pin; it should just supply the period of the PWM. The duty cycle will be generated automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. All VSUP pins must be connected to get full chip functionality. BACK ELECTROMAGNETIC FORCE OUTPUT PIN (BEMF) POWER GROUND PINS (GND1 AND GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs multiple pins are provided. GND1 and GND2 pins must be connected to get full chip functionality. This pin gives the user information about back electromagnetic force (BEMF). This feature allows stall detection and coil failures in step motor applications. In order to evaluate this signal the pin must be directly connected to pin PTD0 / TACH0 / BEMF. The HVDD pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; The output is short-circuit protected. RESET PIN (RST_A) + 5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD) RST_A is the bidirectional reset pin of the analog die. It is an open drain with pull-up resistor and must be connected to the RST pin of the MCU. INTERRUPT PIN (IRQ_A) IRQ_A is the interrupt output pin of the analog die indicating errors or wake-up events. It is an open drain with pull-up resistor and must be connected to the IRQ pin of the MCU. SLAVE SELECT PIN (SS) This pin is the SPI Slave Select pin for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I /O of the microcontroller. LIN BUS PIN (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. HALF-BRIDGE OUTPUT PINS (HB1: HB4) The 908E626 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1: HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high side and low side switches. The HB1: HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low side MOSFETs. POWER SUPPLY PINS (VSUP1: VSUP3) VSUP1: VSUP3 are device power supply pins. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current SWITCHABLE VDD OUTPUT PIN (HVDD) The VDD pin is needed to place an external capacitor to stabilize the regulated output voltage. The VDD pin is intended to supply the embedded microcontroller. Important The VDD pin should not be used to supply other loads; use the HVDD pin for this purpose. The VDD, EVDD, VDDA, and VREFH pins must be connected together. VOLTAGE REGULATOR GROUND PIN (VSS) The VSS pin is the ground pin for the connection of all nonpower ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL pins must be connected together. LIN TRANSCEIVER OUTPUT PIN (RXD) This pin is the output of LIN transceiver. The pin must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD pin). ADC REFERENCE PINS (VREFL AND VREFH) VREFL and VREFH are the reference voltage pins for the ADC. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. ADC SUPPLY PINS (VDDA AND VSSA) VDDA and VSSA are the power supply pins for the analogto-digital converter (ADC). It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. 908E626 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VSSA is the ground pin for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. TEST PIN (FLSVPP) MCU POWER SUPPLY PINS (EVDD AND EVSS) This pin is for test purposes only. This pin should be either left open (not connected) or connected to GND. EVDD and EVSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. EXPOSED PAD PIN The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTERRUPTS The 908E626 has six different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. above the HTI threshold, the HTI flag will be set. If the High Temperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. AUTONOMOUS WATCHDOG INTERRUPT (AWD) LOW VOLTAGE INTERRUPT The Low Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the Low Voltage Interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high side MOSFET only) are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. HIGH VOLTAGE INTERRUPT The High Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high side MOSFET only) are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. HIGH TEMPERATURE INTERRUPT Refer to Autonomous Watchdog (AWD) on page 30. LIN INTERRUPT If the LINIE bit is set, a falling edge on the LIN pin will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up. OVERCURRENT INTERRUPT If an overcurrent condition on a half-bridge or the HVDD output is detected and the OCIE bit is set and an interrupt generated. SYSTEM WAKE-UP System wake-up can be initiated by any of four events: • A falling edge on the LIN pin • A wake-up signal from the AWD • An LVR condition If one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake-up the microcontroller as well as the main voltage regulator (MREG) Figures 8. The High Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is 908E626 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MCU Die Analog Die From Reset Initialize Operate SPI: GS =1 (MREG off) STOP MREG STOP Wait for Action LIN AWD Hallport IRQ Interrupt? Assert IRQ_A SPI: Reason for Interrupt Start MREG Operate MREG = Main Voltage Regulator Figure 8. STOP Mode / Wake-up Procedure INTERRUPT FLAG REGISTER (IFR) • 1 = Falling edge on LIN data line has occurred. • 0 = Falling edge on LIN data line has not occurred since last clear. Register Name and Address: IFR - $05 Read Write Reset Bit 7 6 5 4 3 2 0 0 LINF HTF LVF HVF 0 0 0 0 0 0 1 Bit 0 OCF 0 0 0 LINF — LIN FLAG BIT This read / write flag is set on the falling edge at the LIN data line. Clear LINF by writing a logic [1] to LINF. Reset clears the LINF bit. Writing a logic [0] to LINF has no effect. HTF — HIGH TEMPERATURE FLAG BIT This read / write flag is set on a high temperature condition. Clear HTF by writing a logic [1] to HTF. If a high temperature condition is still present while writing a logic [1] to HTF, the writing has no effect. Therefore, a high temperature interrupt cannot be lost due to inadvertent clearing of HTF. Reset clears the HTF bit. Writing a logic [0] to HTF has no effect. • 1 = High temperature condition has occurred. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • 0 = High temperature condition has not occurred. INTERRUPT MASK REGISTER (IMR) Register Name and Address: IMR - $04 LVF — LOW VOLTAGE FLAG BIT This read / write flag is set on a low voltage condition. Clear LVF by writing a logic [1] to LVF. If a low voltage condition is still present while writing a logic [1] to LVF, the writing has no effect. Therefore, a low voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a logic [0] to LVF has no effect. • 1 = Low voltage condition has occurred. • 0 = Low voltage condition has not occurred. HVF — HIGH VOLTAGE FLAG BIT This read / write flag is set on a high voltage condition. Clear HVF by writing a logic [1] to HVF. If high voltage condition is still present while writing a logic [1] to HVF, the writing has no effect. Therefore, a high voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a logic [0] to HVF has no effect. • 1 = High voltage condition has occurred. • 0 = High voltage condition has not occurred. This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 9, which shows the two signals triggering the OCF. • 1 = High current condition has occurred. • 0 = High current condition has not occurred. HB_OCF Write Reset Bit 7 6 5 4 3 2 1 0 0 LINIE HTIE LVIE HVIE OCIE 0 0 0 0 0 0 0 Bit 0 0 0 LINIE — LIN LINE INTERRUPT ENABLE BIT This read / write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit. • 1 = Interrupt requests from LINF flag enabled. • 0 = Interrupt requests from LINF flag disabled. HTIE — HIGH TEMPERATURE INTERRUPT ENABLE BIT This read / write bit enables CPU interrupts by the high temperature flag, HTF. Reset clears the HTIE bit. • 1 = Interrupt requests from HTF flag enabled. • 0 = Interrupt requests from HTF flag disabled. LVIE — LOW VOLTAGE INTERRUPT ENABLE BIT OCF — OVERCURRENT FLAG BIT HVDD_OCF Read OCF This read / write bit enables CPU interrupts by the low voltage flag, LVF. Reset clears the LVIE bit. • 1 = Interrupt requests from LVF flag enabled. • 0 = Interrupt requests from LVF flag disabled. HVIE — HIGH VOLTAGE INTERRUPT ENABLE BIT This read / write bit enables CPU interrupts by the high voltage flag, HVF. Reset clears the HVIE bit. • 1 = Interrupt requests from HVF flag enabled. • 0 = Interrupt requests from HVF flag disabled. OCIE — OVERCURRENT INTERRUPT ENABLE BIT Figure 9. Principal Implementation for OCF This read / write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit. • 1 = Interrupt requests from OCF flag enabled. • 0 = Interrupt requests from OCF flag disabled. RESET The 908E626 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. Figure 10 depicts the internal reset sources. 908E626 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SPI REGISTERS AWDRE Flag AWD Reset Sensor VDD HVRE Flag High-Voltage Reset Sensor HTRE Flag High-Temperature Reset Sensor RST_A MONO FLOP Low-Voltage Reset Figure 10. Internal Reset Routing RESET INTERNAL SOURCES Reset Mask Register (RMR) Autonomous Watchdog AWD modules generates a reset because of a timeout (watchdog function). High Temperature Reset To prevent damage to the device, a reset will be initiated if the temperature rises above a certain value. The reset is maskable with bit HTRE in the Reset Mask Register. After a reset the high temperature reset is disabled. Register Name and Address: RMR - $06 Bit 7 Read Write Reset TTEST 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 Bit 0 HVRE HTRE 0 0 TTEST — High Temperature Reset Test The LVR is related to the internal VDD. In case the voltage falls below a certain threshold, it will pull down the RST_A pin. This read / write bit is for test purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the HTRE bit. • 1 = Low temperature threshold enabled. • 0 = Low temperature threshold disabled. High Voltage Reset HVRE — High Voltage Reset Enable Bit The HVR is related to the external VSUP voltage. In case the voltage is above a certain threshold, it will pull down the RST_A pin. The reset is maskable with bit HVRE in the Reset Mask Register. After a reset the high voltage reset is disabled. This read / write bit enables resets on high voltage conditions. Reset clears the HVRE bit. • 1 = High voltage reset enabled. • 0 = High voltage reset disabled. Low Voltage Reset HTRE — High Temperature Reset Enable Bit RESET EXTERNAL SOURCE External Reset Pin The microcontroller has the capability of resetting the SMARTMOS device by pulling down the RST pin. This read / write bit enables resets on high temperature conditions. Reset clears the HTRE bit. • 1 = High temperature reset enabled. • 0 = High temperature reset disabled. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SERIAL PERIPHERAL INTERFACE The serial peripheral interface (SPI) creates the communication link between the microcontroller and the 908E626. The interface consists of four pins (see Figure 11): • SS — Slave Select • MOSI — Master-Out Slave-In • MISO — Master-In Slave-Out • SPSCK — Serial Clock (maximum frequency 4.0 MHz) A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address. SS Read/Write, Address, Parity MOSI R/W A4 A3 A2 A1 A0 Data (Register write) P X D7 D6 System Status Register MISO S7 S6 S5 S4 S3 S2 D5 D4 D3 D2 D1 D0 D1 D0 Data (Register read) S1 S0 D7 D6 D5 D4 D3 D2 SPSCK Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data Figure 11. SPI Protocol During the inactive phase of SS, the new data transfer is prepared. The falling edge on the SS line indicates the start of a new data transfer and puts MISO in the low-impedance mode. The first valid data are moved to MISO with the rising edge of SPSCK. The MISO output changes data on a rising edge of SPSCK. The MOSI input is sampled on a falling edge of SPSCK. The data transfer is only valid if exactly 16 sample clock edges are present in the active phase of SS. After a write operation, the transmitted data is latched into the register by the rising edge of SS. Register read data is internally latched into the SPI at the time when the parity bit is transferred. SS HIGH forces MISO to high-impedance. MASTER ADDRESS BYTE • If R/ W = 1, the second byte of master contains no valid information, slave just transmits back register data. • If R/ W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to write operation, write data is latched in the SMARTMOS register on rising edge of SS. Parity P The parity bit is equal to “0” if the number of 1 bits is an even number contained within R/ W, A4 : A0. If the number of 1 bits is odd, P equals “1”. For example, if R/ W = 1, A4 : A0 = 00001, then P equals “0.” The parity bit is only evaluated during a write operation. Bit X A4 : A0 Not used. Contains the address of the desired register. Master Data Byte R/W Contains information about a read or a write operation. Contains data to be written or no valid data during a read operation. 908E626 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 6. List of Registers Addr Register Name R/W $01 H-bridge Output (HBOUT) R W $02 H-bridge Control (HBCTL) W $03 System Control (SYSCTL) W $04 Interrupt Mask (IMR) W $05 Interrupt Flag (IFR) W $06 Reset Mask (RMR) W $07 Analog Multiplexer Configuration (ADMUX) W $08 Reserved $09 Reserved $0a AWD Control (AWDCTL) W $0b Power Output (POUT) W $0c System Status (SYSSTAT) W R Bit 7 6 5 4 3 2 1 0 HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L OFC_EN CSA 0 0 0 CLS2 CLS1 CLS0 PSON SRS1 SRS0 0 0 0 0 0 0 0 LINIE HTIE LVIE HVIE 0 0 LINF HTF LVF HVF 0 0 0 0 0 0 0 0 0 SS3 0 0 0 0 0 0 0 0 0 0 0 R R R R R R TTEST GS 0 OCF 0 HVRE HTRE SS2 SS1 SS0 0 0 0 0 0 0 0 AWDRE AWDIE 0 AWDF AWDR 0 0 0 0 HVDDON 0 HVDD_OC F 0 LVF HVF W R OCIE W R R R 0 AWDRST 0 0 0 LINCL Slave Status Byte HB_OCF HTF Table 6 summarizes the SPI Register addresses and the bit names of each register. up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. ANALOG DIE I / OS TXD Pin LIN Physical Layer The TXD pin is the MCU interface to control the state of the LIN transmitter (see Figure 2). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD pin has an internal pull-up current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. Contains the contents of the System Status Register ($0c) independent of whether it is a write or read operation or which register was selected. Slave Data Byte Contains the contents of selected register. During a write operation it includes the register content prior to a write operation. SPI Register Overview The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low side MOSFET with internal current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull- 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES RXD Pin SS3, SS2, SS1, and SS0 — A / D Input Select Bits The RXD transceiver pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. These read / write bits select the input to the ADC in the microcontroller according to Table 7. Reset clears SS3, SS2, SS1, and SS0 bits. STOP Mode/Wake-up Feature During STOP mode operation the transmitter of the physical layer is disabled. The receiver pin is still active and able to detect wake-up events on the LIN bus line.If LIN interrupt is enabled (LINIE bit in the Interrupt Mask Register is set), a falling edge on the LIN line causes an interrupt. This interrupt switches on the main voltage regulator and generates a system wake-up. Analog Multiplexer /ADOUT Pin The ADOUT pin is the analog output interface to the ADC of the MCU (see Figure 2). An analog multiplexer is used to read six internal diagnostic analog voltages. Current Recopy The analog multiplexer is connected to the four low side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low side MOSFET. High or low resolution is selectable: 5.0 V / 2.5 A or 5.0 V / 500 mA, respectively. (Refer to Half-bridge Current Recopy on page 27.) Temperature Sensor The 908E626 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP Prescaler Table 7. Analog Multiplexer Configuration Register SS3 SS2 SS1 SS0 Channel 0 0 0 0 Current Recopy HB1 0 0 0 1 Current Recopy HB2 0 0 1 0 Current Recopy HB3 0 0 1 1 Current Recopy HB4 0 1 0 0 VSUP Prescaler 0 1 0 1 Temperature Sensor 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Not Used Power Output Register (POUT) The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP / RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. Register Name and Address: POUT - $0b Read Bit 7 6 0 0 Write Analog Multiplexer Configuration Register (ADMUX) Reset Read 6 5 4 0 0 0 0 Write Reset 0 0 0 0 0 4 3 2 1 Bit 0 0 0 0 0 (17) (17) (17) (17) HVDD ON (17) 0 0 0 0 0 0 0 Notes 17. This bit must always be set to 0. Register Name and Address: ADMUX - $07 Bit 7 0 5 3 2 1 Bit 0 SS3 SS2 SS1 SS0 0 0 0 0 HVDDON — HVDD On Bit This read/write bit enables HVDD output. Reset clears the HVDDON bit. • 1 = HVDD enabled. • 0 = HVDD disabled. 908E626 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES HALF-BRIDGES Outputs HB1 : HB4 provide four low resistive half-bridge output stages. The half-bridges can be used in H-Bridge, high side, or low side configurations. Reset clears all bits in the H-Bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1: HB4 output features: • Short-circuit (overcurrent) protection on high side and low side MOSFETs. • Current recopy feature (low side MOSFET). • Overtemperature protection. • Overvoltage and undervoltage protection. • Current limitation feature (low side MOSFET). VSUP Control On/Off High Side Driver Status Charge Pump, Over-temperature Protection, Over-current Protection BEMF HBx On/Off Status Current Limit Low Side Driver Current Recopy, Current Limitation, Over-current Protection GND Figure 12. Half-bridge Push-Pull Output Driver Half-bridge Control Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). HBx_L and HBx_H form one half-bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the high side MOSFET has a higher priority. To avoid both MOSFETs (high side and low side) of one half-bridge being on at the same time, a break-before-make circuit exists.Switching the high side MOSFET on is inhibited as long as the potential between gate and VSS is not below a certain threshold. Switching the low side MOSFET on is blocked as long as the potential between gate and source of the high side MOSFET did not fall below a certain threshold. Half-bridge Output Register (HBOUT) Register Name and Address: HBOUT - $01 Bit 7 Read Write Reset 6 5 4 3 2 1 Bit 0 HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L 0 0 0 0 0 0 0 0 HBx_L — Low Side On / Off Bits These read / write bits turn on the low side MOSFETs. Reset clears the HBx_L bits. • 1 = Low side MOSFET turned on for half-bridge output x. • 0 = Low side MOSFET turned off for half-bridge output x. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES HBx_H — High Side On/Off Bits These read / write bits turn on the high side MOSFETs. Reset clears the HBx_H bits. • 1 = High side MOSFET turned on for half-bridge output x. • 0 = High side MOSFET turned on for half-bridge output x. HALF-BRIDGE CURRENT LIMITATION Each low side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width modulation on the low side MOSFET. The pulse width modulation on the outputs is controlled by the FGEN input and the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics. The recommended frequency range for the FGEN and the PWM is 0.1 kHz to 20 kHz. Functionality Each low side MOSFET switches off if a current above the selected current limit was detected. The 908E626 offers five different current limits (refer to Table 8, for current limit values). The low side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 13). H-Bridge low side MOSFET will be switched off if select current limit is reached. Coil Current H-Bridge low side MOSFET will be turned on with each rising edge of the FGEN input. t (µs) Half-bridge Low Side Output t (µs) FGEN Input (MCU PWM Signal) t (µs) Minimum 50 µs Figure 13. Half-bridge Current Limitation 908E626 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Offset Chopping If bit OFC_EN in the H-bridge Control Register (HBCTL) is set, HB1 and HB2 will continue to switch on the low side MOSFETs with the rising edge of the FGEN signal and HB3 and HB4 will switch on the low side MOSFETs with the falling edge on the FGEN input. In step motor applications, this feature allows the reduction of EMI due to a reduction of the di/dt (Figure 14). Coil1 Current Coil2 Current FGEN Input (MCU PWM Signal) HB1 HB2 HB3 HB4 Coil1….. Coil2….. Current in VSUP Line Figure 14. Offset Chopping for Step Motor Control HALF-BRIDGE CURRENT RECOPY HALF-BRIDGE BEMF GENERATION Each low side MOSFET has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the analog multiplexer. The factor for the current sense amplification can be selected via bit CSA in the System Control Register. • CSA = 1: Low resolution selected (500 mA measurement range). • CSA = 0: High resolution selected (2.5 A measurement range). The BEMF output is set to “1” if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal) (see Figure 15). 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Coil Current Voltage on 1 1 BEMF Signal Figure 15. BEMF Signal Generation HALF-BRIDGE OVERTEMPERATURE PROTECTION The half-bridge outputs provide an overtemperature prewarning with the HTF in the Interrupt Flag Register (IFR). In order to protect the outputs against overtemperature, the High Temperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs. these flags (LVF, HVF) is set, the outputs are automatically disabled. The overvoltage / undervoltage status flags are cleared (and the outputs re-enabled) by writing a logic [1] to the LVF / HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high or low voltage condition is present. Half-bridge Control Register (HBCTL) HALF-BRIDGE OVERCURRENT PROTECTION Register Name and Address: HBCTL - $02 The half-bridges are protected against short to GND, short to VSUP, and load shorts. In the event an overcurrent on the high side is detected, the high side MOSFETs on all HB high side MOSFETs are switched off automatically. In the event an overcurrent on the low side is detected, all HB low side MOSFETs are switched off automatically. In both cases, the overcurrent status flag HB_OCF in the System Status Register (SYSSTAT) is set. The overcurrent status flag is cleared (and the outputs reenabled) by writing a logic [1] to the HB_OCF flag in the System Status Register or by reset. HALF-BRIDGE OVERVOLTAGE / UNDERVOLTAGE The half-bridge outputs are protected against undervoltage and overvoltage conditions. This protection is done by the low and high voltage interrupt circuitry. If one of Bit 7 Read Write Reset 6 OFC_EN CSA 0 0 5 4 3 0 0 0 0 0 0 2 1 Bit 0 CLS2 CLS1 CLS0 0 0 0 OFC_EN — H-bridge Offset Chopping Enable Bit This read / write bit enables offset chopping. Reset clears the OFC_EN bit. • 1 = Offset chopping enabled. • 0 = Offset chopping disabled. CSA — H-bridges Current Sense Amplification Select Bit This read / write bit selects the current sense amplification of the H-bridges. Reset clears the CSA bit. 908E626 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • 1 = Current sense amplification set for measuring 0.5 A. • 0 = Current sense amplification set for measuring 2.5 A. CLS2 : CLS0 — H-Bridge Current Limitation Selection Bits These read / write bits select the current limitation value according to Table 8. Reset clears the CLS2 : CLS0 bits. Table 8. H-Bridge Current Limitation Value Selection Bits Current Limit PSON — Power Stages On Bit This read / write bit enables the power stages (half-bridges, LIN transmitter and HVDD output). Reset clears the PSON bit. • 1 = Power stages enabled. • 0 = Power stages disabled. SRS0 : SRS1 — LIN Slew Rate Selection Bits These read / write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 9. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application. CLS2 CLS1 CLS0 0 0 0 0 0 1 0 1 0 0 1 1 55 mA (typ) 1 0 0 260 mA (typ) SRS1 SRS0 LIN Slew Rate 1 0 1 370 mA (typ) 0 0 Initial Slew Rate (20 kBaud) 1 1 0 550 mA (typ) 0 1 Slow Slew Rate (10 kBaud) 1 1 1 740 mA (typ) 1 0 High Speed II (8 x) 1 1 High Speed I (4 x) No Limit Table 9. LIN Slew Rate Selection Bits Switchable VDD Outputs The HVDD pin is a switchable VDD output pin. It can be used for driving external circuitry that requires a VDD voltage. The output is enabled with bit PSON in the System Control Register and can be switched on / off with bit HVDDON in the Power Output Register. Low or high voltage conditions (LVI / HVI) have no influence on this circuitry. Go to STOP Mode Bit (GS) This write-only bit instructs the 908E626 to power down and go into STOP mode. Reset or CPU interrupt requests clear the GS bit. • 1 = Power down and go into STOP mode • 0 = Not in STOP mode System Status Register (SYSSTAT) HVDD Overtemperature Protection Overtemperature protection is enabled if the high temperature reset is enabled. Register Name and Address: SYSSTAT - $0c Bit 7 Read HVDD Overcurrent Protection The HVDD output is protected against overcurrent. In the event the overcurrent limit is or was reached, the output automatically switches off and the HVDD overcurrent flag in the System Status Register is set. System Control Register (SYSCTL) Register Name and Address: SYSCTL - $03 Bit 7 Read Write Reset 6 5 PSON SRS1 SRS0 0 0 0 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 GS 0 Write Reset 0 0 6 5 LINCL HVDD _OCF 0 0 4 0 0 3 2 1 Bit 0 LVF HVF HB_ OCF HTF 0 0 0 0 LINCL — LIN Current Limitation Bit This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately. • 1 = Transmitter operating in current limitation region. • 0 = Transmitter not operating in current limitation region. HVDD_OCF — HVDD Output Overcurrent Flag Bit This read / write flag is set on an overcurrent condition at the HVDD pin. Clear HVDD_OCF and enable the output by writing a logic [1] to the HVDD_OCF Flag. Reset clears the 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect. • 1 = Overcurrent condition on HVDD has occurred. • 0 = No overcurrent condition on HVDD has occurred. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. LVF — Low Voltage Bit Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. This read only bit is a copy of the LVF bit in the Interrupt Flag Register. • 1 = Low voltage condition has occurred. • 0 = No low voltage condition has occurred. HVF — High Voltage Sensor Bit This read-only bit is a copy of the HVF bit in the Interrupt Flag Register. • 1 = High voltage condition has occurred. • 0 = No high voltage condition has occurred. HB_OCF — H-Bridge Overcurrent Flag Bit This read / write flag is set on an overcurrent condition at the H-Bridges. Clear HB_OCF and enable the H-Bridge driver by writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a logic [0] to HB_OCF has no effect. • 1 = Overcurrent condition on H-Bridges has occurred. • 0 = No overcurrent condition on H-Bridges has occurred. HTF — Overtemperature Status Bit This read-only bit is a copy of the HTF bit in the Interrupt Flag Register. • 1 = Overtemperature condition has occurred. • 0 = No overtemperature condition has occurred. AUTONOMOUS WATCHDOG (AWD) The Autonomous Watchdog module consists of three functions: • Watchdog function for the CPU in RUN mode • Periodic interrupt function in STOP mode The Autonomous Watchdog module allows to protect the CPU against code runaways. The AWD is enabled if AWDIE, AWDRE in the AWDCTL Register is set. If this bit is cleared, the AWD oscillator is disabled and the watchdog switched off. Watchdog The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. PERIODIC INTERRUPT Autonomous Watchdog Control Register (AWDCTL) Register Name and Address: AWDCTL - $0a Read Bit 7 6 5 0 0 0 Write Reset AWDRST 0 0 0 4 3 2 1 Bit 0 AWDRE AWDIE 0(18) 0 AWDR 0 0 0 0 0 Notes 18. This bit must always be set to 0. AWDRST — Autonomous Watchdog Reset Bit This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. • 1 = Reset AWD and restart timeout period. • 0 = No effect. AWDRE — Autonomous Watchdog Reset Enable Bit This read / write bit enables resets on AWD timeouts. A reset on the RST_A is asserted when the Autonomous Watchdog has reached the timeout and the Autonomous Watchdog is enabled. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. • 1 = Autonomous watchdog enabled. • 0 = Autonomous watchdog disabled. Autonomous Watchdog Interrupt Enable Bit (AWDIE) This read/write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit. • 1 = CPU interrupt requests from AWDF enabled • 0 = CPU interrupt requests from AWDF disabled AWDR — Autonomous Watchdog Rate Bit This read / write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. • 1 = Fast rate selected (10 ms). • 0 = Slow rate selected (20 ms). 908E626 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FACTORY TRIMMING AND CALIBRATION VOLTAGE REGULATOR RUN Mode The 908E626 chip contains a low power, low drop voltage regulator to provide internal power and external power for the MCU. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD pin to provide the 5.0 V to the microcontroller. Note: Under loss of power conditions, the discharge of the VDD capacitor may occur relatively slow. Based on the selected external components and external VDD load, additional external load may be required guarantee the MCU POR threshold being reached before the next power up. During RUN mode, the main voltage regulator is on. It provides a regulated supply to all digital sections. STOP Mode During STOP mode the STOP mode regulator supplies a regulated output voltage. The STOP mode regulator has a very limited output current capability. The output voltage will be lower than the output voltage of the main voltage regulator. FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E626, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state: • 0xFD80: 0xFDDF Trim and Calibration Values • 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low frequency base clock (IBASE), will vary as much as ±25%, due to process, temperature, and voltage dependencies. To compensate this dependencies a ICG trim values is located at address $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100 nF) and stabilized (4.7 F) VDD = 5.0 V, TAMBIENT~25 °C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to be copied after every reset. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 31 TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E626 has the MC68HC908EY16 MCU embedded, typically all the development tools available for the MCU also apply for this device. However, due to the fact of the additional analog die circuitry and the nominal +12 V supply voltage some additional items have to be considered: • nominal 12 V rather than 5.0 V or 3.0 V supply • high voltage VTST might be applied not only to IRQ pin, but also the IRQ_A pin For a detailed information on the MCU related development support, see the MC68HC908EY16 datasheet section, development support. The programming is principally possible at two stages in the manufacturing process - first on chip level, before the IC is soldered onto a pcb board, and second, after the IC is soldered onto the pc board. Chip level programming At the Chip level, the easiest way is to only power the MCU with +5.0 V (see Figure 16), and not provide the analog chip with VSUP. In this setup, all the analog pins should be left open (e.g. VSUP[1:3]), and interconnections between the MCU and the analog die have to be separated (e.g. IRQ IRQ_A). This mode is well described in the MC68HC908EY16 datasheet - section, development support. VSUP[1:3] VDD GND[1:2] VSS +5V VREFH VDDA RST EVDD RST_A +5V 1 1µF 16 + 4 C1- GND C2+ V+ + 5 RS232 DB-9 VCC + 3 1µF C1+ 100nF VTST C2- MAX232 V- 7 T2OUT 3 8 R2IN EVSS 1µF 9.8304MHz CLOCK 6 +5V + CLK PTB4/AD4 T2IN 10 6 10k 5 +5V 10k DATA PTA1/KBD1 PTA0/KBD0 10k 4 PTB3/AD3 3 2 10k PTC4/OSC1 1µF 74HC125 5 VSSA + 2 R2OUT 9 MM908E626 IRQ_A 1µF 15 74HC125 2 4.7µF VREFL IRQ 1 Figure 16. Normal Monitor Mode Circuit (MCU only) It is also possible to supply the whole system with VSUP (12 V) instead as described in Figure 17. PCB level programming If the IC is soldered onto the pc board, it is typically not possible to separately power the MCU with +5.0 V. The whole system has to be powered up providing VSUP (see Figure 17). 908E626 32 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS VDD VSUP 47µF + 100nF VSUP[1:3] VDD GND[1:2] VSS VREFH VDDA RST EVDD RST_A VDD 1 1µF + + 3 4 1µF C1- GND C2+ V+ + 5 RS232 DB-9 VCC C1+ 100nF C2- V- MAX232 IRQ_A 1µF 7 T2OUT 3 8 R2IN MM908E626 VSSA 1µF + 2 9.8304MHz CLOCK 6 VDD + CLK 10k PTC4/OSC1 PTB4/AD4 1µF T2IN 10 6 10k DATA PTA1/KBD1 PTA0/KBD0 10k 4 PTB3/AD3 3 2 VDD 10k 5 74HC125 R2OUT 9 4.7µF VREFL EVSS 15 74HC125 2 IRQ VTST 16 1 5 Figure 17. Normal Monitor Mode Circuit Table 10 summarizes the possible configurations and the necessary setups. Table 10. Monitor Mode Signal Requirements and Options Mode IRQ RST Normal VTST VDD Monitor Forced Monitor VDD VDD Reset Vector Serial Communication Mode Selection VDD VDD COP PTA0 PTA1 PTB3 PTB4 X 1 0 0 1 OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 $FFFF (blank) 1 0 X X OFF disabled disabled 9.8304 MHz 2.4576 MHz 9600 ON disabled disabled — Nominal 1.6 MHz Nominal 6300 ON enabled enabled — Nominal 1.6 MHz Nominal 6300 GND User ICG Communication Speed Normal Request Baud Bus Timeout External Clock Frequency Rate not $FFFF X X X X (not blank) Notes 19. PTA0 must have a pull-up resistor to VDD in monitor mode 20. 21. 22. 23. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don’t care VTST is a high voltage VDD + 3.5 V VTST VDD + 4.5 V 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 33 TYPICAL APPLICATIONS EMC/EMI RECOMMENDATIONS This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be found on the Freescale web site, www.freescale.com. MCU digital supply pins (EVDD and EVSS) VSUP Pins (VSUP1:VSUP3) Fast signal transitions on MCU pins place high, short duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. Its recommended to place a high quality ceramic decoupling capacitor close to the VSUP pins to improve EMC/EMI behavior. MCU analog supply pins (VREFH, VDDA, VREFL, and VSSA) To avoid noise on the analog supply pins its important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. Figure 18 and Figure 19 show the recommendations on schematics and layout level and Table 11 indicates recommended external components and layout considerations. LIN Pin For DPI (Direct Power Injection) and ESD (Electrostatic Discharge) its recommended to place a high quality ceramic decoupling capacitor near the LIN pin. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. Voltage Regulator Output Pins (VDD and AGND) Use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP C1 + C2 VSUP1 VDD VSUP2 VSS VSUP3 VREFH L1 VDDA LIN LIN EVDD V1 C5 C3 MM908E626 C4 EVSS VSSA GND1 VREFL GND2 Figure 18. EMC/EMI Recommendations 908E626 34 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS 1 54 2 53 3 52 4 51 5 50 49 7 VREFH 48 8 VDDA 47 9 EVDD 46 10 EVSS 45 11 VSSA 44 12 VREFL 43 13 14 42 NC 908E626 15 41 VSS 17 VDD 36 19 C5 V1 20 LIN 21 NC 22 NC 35 34 NC 24 VSUP1 VSUP3 31 25 GND1 GND2 30 29 26 27 C1 33 32 23 GND C4 38 37 18 L1 40 39 16 LIN C3 6 VSUP2 28 C2 VBAT Figure 19. PCB Layout Recommendations . Table 11. Component Value Recommendation Component Recommended Value(24) C1 Bulk Capacitor C2 100 nF, SMD Ceramic, Low ESR Close (<5.0 mm) to the VSUP1, VSUP2 pins with good ground return C3 100 nF, SMD Ceramic, Low ESR Close (<3.0 mm) to the digital supply pins (EVDD, EVSS) with good ground return. Comments / Signal Routing The positive analog (VREFH, VDDA) and the digital (EVDD) supply should be connected right at the C3. C4 4,7 F, SMD Ceramic, Low ESR Bulk Capacitor C5 180 pF, SMD Ceramic, Low ESR Close (<5.0 mm) to LIN pin. Total Capacitance on LIN has to be below 220 pF. (CTOTAL = CLIN-PIN + C5 + CVARISTOR ~ 10 pF + 180 pF + 15 pF) V1 (25) L1(25) Varistor Type TDK AVR-M1608C270MBAAB Optional (close to LIN connector) SMD Ferrite Bead Type TDK MMZ2012Y202B Optional, (close to LIN connector) Notes 24. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. 25. Components are recommended to improve EMC and ESD performance. 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 35 PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10519D. Dimensions shown are provided for reference ONLY. EK SUFFIX (PB-FREE) 54-PIN 98ARL10519D ISSUE D 908E626 36 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN 98ARL10519D ISSUE D 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 37 PACKAGING PACKAGING DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN 98ARL10519D ISSUE D 908E626 38 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) ADDITIONAL DOCUMENTATION 908E626 THERMAL ADDENDUM (REV 1.0) Introduction This thermal addendum ia provided as a supplement to the MM908E626 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application and packaging information is provided in the data sheet. 54-PIN SOICW-EP Package and Thermal Considerations This MM908E626 is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2 = RJA11 RJA12 RJA21 RJA22 . 98ARL10519D 54-PIN SOICW-EP Note For package dimensions, refer to 98ARL10519D. P1 P2 The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 12. Thermal Performance Comparison Thermal Resistance 1 = Power Chip, 2 = Logic Chip [C/W] m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 RJAmn (1)(2) 23 20 24 RJBmn (2)(3) 9.0 6.0 10 RJAmn (1)(4) 52 47 52 RJCmn (5) 1.0 0 2.0 Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, “infinite” heat sink attached to exposed pad. 1.0 1.0 0.2 0.2 * All measurements are in millimeters Soldermast openings 54 Terminal SOIC-EP 0.65 mm Pitch 17.9 mm x 7.5 mm Body 10.3 mm x 5.1 mm Exposed Pad Thermal vias connected to top buried plane Figure 20. Thermal Land Pattern for Direct Thermal Attachment Per JEDEC JESD51-5Thermal Test Board 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 39 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF RST_A IRQ_A SS LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Exposed Pad 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 A PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS NC VDD NC NC NC HVDD NC HB4 VSUP3 GND2 HB3 NC 908E626 Pin Connections 54-Pin SOICW-EP 0.65 mm Pitch 17.9 mm x 7.5 mm Body 10.3 mm x 5.1 mm Exposed Pad Figure 21. Thermal Test Board Device on Thermal Test Board Material: Outline: Area A: Ambient Conditions: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 13. Thermal Resistance Performance Thermal Resistance RJAmn RJSmn Area A (mm2) 1 = Power Chip, 2 = Logic Chip (C/W) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 0 53 48 53 300 39 34 38 600 35 30 34 0 21 16 20 300 15 11 15 600 14 9.0 13 RJAis the thermal resistance between die junction and ambient air. RJSmn is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 908E626 40 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) Thermal Resistance [ºC/W] 60 50 40 30 20 10 x RJA11 RJA22 RJA12 = RJA21 0 0 300 600 Heat spreading area A [mm²] Figure 22. Device on Thermal Test Board RJA Thermal Resistance [ºC/W] 100 10 1 x 0.1 1.00E-03 1.00E-02 RJA11 RJA22 RJA12 = RJA21 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 23. Transient Thermal Resistance RJA (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2) 908E626 Analog Integrated Circuit Device Data Freescale Semiconductor 41 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 4.0 9/2008 • • • • • • Implemented Revision History page Minor corrections throughout the document Updated to current Freescale format and style Added MM908E626AVEK to the ordering information Corrected package drawing designation Added STOP mode 5.0 7/2009 • Corrected several non-technical cross-references. 6.0 9/2011 • • • • • • • • • • Corrected text for Autonomous Watchdog Interrupt. Page 17. Corrected part number in Go to STOP Mode Bit. Page 30. Removed footnotes in register table for SYSCTL and AWDCTL. Corrected Figure 4 LIN Timing description. Updated Freescale form and style Added MM908E626AVPEK to the ordering information. Removed the DWB package type. Added RoHS image to page 1 and RoHS statement to back page. Changed Peak Package Reflow Temperature During Reflow description Added note (8) 7.0 4/2012 • • • Added MM908E626AVPEK to the ordering information Removed 908E626AVEK/ R2 from the ordering information Updated Freescale form and style 8.0 4/2012 • Corrected Figure 4, LIN Timing Description, replacing VLIN with VSUP 9.0 6/2012 • Added MM908E626AVEK/ R2 to the ordering information 10.0 8/2012 • Corrected broken links within the document. 11.0 2/2013 • • Removed MM908E626AVEK from the ordering information Update format. 908E626 42 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/Policy.aspx?Selector=RT&s=STR0326182960&pc. Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, CWare, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Document Number: MM908E626 Rev. 11.0 2/2013