HT16523 5x7 Dot Character VFD Controller & Driver Feature Applications • Logic voltage: 2.7V~5.5V • Consumer products panel function control • High voltage: 40V (max.) • Industrial measuring instrument panel function control • 3-line serial interface • Other similar application panel function control • Alphanumeric and symbolic display using integrated ROM • Suitable for POS terminals or message displays • 16 x 8-bit display data RAM (DDRAM) • Integrated 5x7 dot ROM containing 248 character set General Description The HT16523 device is a dot matrix Vacuum Fluorescent Display, VFD, controller/driver which displays characters, numerics and symbols. Dot matrix VFD driving signals are received via a 3-line serial interface driven by an externally connected microcontroller. The display data is stored in the internal ROM and RAM for character and symbol display. • 8 user-defined characters stored in character generator RAM (CGRAM) • Additional symbol display data stored in 16 x 8-bit RAM (ADRAM) • Display content: 16 columns by 1 row + 32 symbols - each column has 1 digit character with 2 symbols • Supports display output: 35-segment & 16-grid • Supports symbol output: 2-symbol & 16-grid • Supports 2-pin general output port - static operation • Fully integrated oscillator circuit • 64-pin LQFP package Ordering Information Part Number Rev. 1.00 Information HT16523-002 64-pin LQFP package with ROM code 002 HT16523-003 64-pin LQFP package with ROM code 003 1 January 18, 2012 HT16523 Block Diagram VDD VH VSS CGROM 248w x 35b DDRAM 16w x 8b CGRAM 8w x 35b TEST RST ADRAM 16w x 2b CS SCK SI 8 bit shift register S1 Segment Driver S35 AD1 AD Driver AD2 Address Selector Command decoder Write address counter Read address counter Port Driver Control Circuit Digit control Duty control Timing generator1 OSCI Rev. 1.00 P1 P2 G1 Grid Driver G16 Timing generator2 Oscillator 2 January 18, 2012 HT16523 Pin Assignment VSS OSCI TEST RST CS SCK SI VDD P1 P2 AD2 AD1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 42 7 8 41 HT16523 40 64 LQFP-A 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 1819 202122232425 262728 29303132 VH G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 Pin Description Pin Name I/O Description Power Supply Pins VDD — Positive power supply for logic circuits. VH — Power supply for VFD driver circuits. VSS — VSS - ground pin. Microcontroller Interface Pins CS I Chip select pin When “Low”, the device is active. SCK I Serial clock input Shift clock input with data written on the SCK rising edge. SI I Serial data input. The serial data is first shifted from LSB. RST I Initialize all the internal registers and commands. All segments and digits are fixed at “Low” level. TEST I When “Low” or open, the device is in normal mode. When “High”, the device is in test mode. S1~S35 O High-voltage segment output pins. Output Pins G1~G16 O High-voltage grid output pins. AD1,AD2 O High-voltage additional data segment output pins. P1,P2 O General port output. Static operation output - can drive LEDs I Oscillator input pin Connected to an external resistor and capacitor to generate the oscillation frequency. Oscillator pin OSCI Rev. 1.00 3 January 18, 2012 HT16523 Approximate Internal Connections CS, SCK, SI, RST (For Schmit Trigger Type) P1, P2 S1~S35, G1~G16, AD1, AD2 VDD VH VDD VSS VSS VSS TEST VDD VSS Absolute Maximum Ratings Segment output current......................... -10mA to 4mA AD output current................................. -15mA to 4mA General port output current................. -20mA to 40mA Storage Temperature............................ -55°C to 125°C Operation Temperature.......................... -40°C to 85°C Logic Supply Voltage................ Vss-0.3V to Vss+6.0V Driver Supply Voltage................ Vss-0.3V to Vss+45V Input Voltage... ……………….. Vss-0.3V to VDD+0.3V Output Voltage..........................Vss-0.3V to VDD+0.3V Grid output current................................ -20mA to 4mA Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 4 January 18, 2012 HT16523 D.C. Characteristics Symbol Parameter VH=40V, VSS=0V, Ta=-40°C ~ 85°C Test Condition VDD Condition Min. Typ. Max. Unit VDD Logic Supply Voltage — — 2.7 5.0 5.5 V VH VFD Supply Voltage — — 10 — 40 V 5V fOSC=2MHz, no load, Duty=15/16, Digit=1 to 16. All output lights On, MCU no write data or command, P2 and P1=high — — 2 — — 1 fOSC=2MHz, no load, Duty=15/16, Digit=1 to 16. Stop scan MCU no write data or command, P2 and P1=high — — 2 — — 1 IDD1 VDD Operating Current IDD2 VDD Operating Current ISTB VDD Standby Current IH1 VH Operating Current IH2 VH Operating Current IH_STB VH Standby Current VIH High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current IIL Low Level Input Current 3V 5V 3V VOH3 — — — 20 μA — Standby mode — — 20 μA CS, SCK, SI, RST 0.8VDD — VDD V CS, SCK, SI, RST 0 — 0.2VDD V VIH=VDD, CS, SCK, SI, RST — — 1 μA VIL=0V, CS, SCK, SI, RST -1 — — μA G1~G16, IOH1=-15mA 37 — — V AD1, AD2, IOH2=-7mA 38 — — V S1~S35, IOH3=-1mA 38 — — V IOH4=-2mA 0.9VDD — — IOH4=-1mA 0.9VDD — — G1~G16, IOL1=1mA — — 2 V AD1, AD2, IOL2=1mA — — 2 V S1~S35, IOL3=1mA — — 2 V IOL4=20mA — — 1 IOL4=10mA — — 1 5V 3V 5V 3V 5V 3V 5V 3V 3V 5V 5V 3V 5V 3V 5V VOL4 3V Pull Down Resistor μA fOSC=2MHz, no load, Duty=15/16, Digit=1 to 16, Stop scan MCU no write data or command, P2 and P1=high 5V VOL3 μA 5 mA 3V Low Level Output Voltage 10 1 3V VOL2 2 1 — 5V VOL1 — — — 3V VOH4 mA fOSC=2MHz, no load, Duty=15/16, Digit=1 to 16, All output lights On, MCU no write data or command, P2 and P1=high 5V High Level Output Voltage Standby mode mA — 3V VOH2 Rev. 1.00 5V 5V VOH1 RPD 3V 5V 3V P1, P2 P1, P2 TEST PIN 5 V V — 50 100 KΩ — 100 200 KΩ January 18, 2012 HT16523 A.C. Characteristics Serial Interface Timing TCSH TSTART TSTOP CS TCYC TL-SCK TH-SCK SCK TSETUP THOLD SI CS TDEC TDEC SCK SI Rev. 1.00 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 1st byte 2nd byte 3rd byte 6 January 18, 2012 HT16523 Output Timing tR tF 0.8VH All outputs 0.2VH VH=40V, VSS=0V, Ta =-40oC ~ 85oC Symbol Parameter fOSC Oscillation Frequency fFR Frame Frequency TCYC Write Cycle Time TL-SCK Low Pulse of SCK TH-SCK High Pulse of SCK TSETUP Data Setup Time THOLD Data Hold Time TSTART Command Start Wait Time TSTOP Command Stop Wait Time TCSH CS Off Time TDEC Command/Data Decode Time All Output Slew Rate Rev. 1.00 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V Min. Typ. Max. Unit R1=120kΩ, C1=0.1μF 1.5 2 2.5 MHz Digit=1 to 16, R1=120kΩ, C1=0.1μF 183 244 305 Hz — — 2 — — 2 250 — — 250 — — 250 — — 250 — — 250 — — 250 — — 250 — — 250 — — 250 — — 250 — — 16 — — 16 — — 250 — — 250 — — 8 — — 8 — — Ci=100 pF, tR=20 to 80% — — 2 μs Ci=100 pF, tF=80 to 20% — — 2 μs Condition SCK SCK SCK SCK, SI SCK, SI SCK, SI SCK, CS 5V — 3V 5V — 3V 5V tR tF Test Condition VDD 3V 5V 3V 7 MHz ns ns ns ns ns μs ns μs January 18, 2012 HT16523 Reset and Wake-up Timing Hardware Reset 0.8VDD VDD TRSON 0V TRW TPOF RST VIH 0.5VDD VIL TRSOFF VIH SI VIL Ta=-40oC ~ 85oC Symbol Parameter Test Condition 5V TRSON Oscillator Stable Time 3V 5V 3V 5V TPOF VDD Off Time TRW RST Pulse Width TRSOFF SI Wait Time Condition VDD 3V 5V 3V RST signal is an external input from a microcontroller etc. R2=1kΩ, C2=0.1μF VDD drop down to 0V RST signal is an external input from a microcontroller etc. 5V — 3V Min. Typ. Max. Unit 250 — — 250 — — — 1000 — — 1000 — 40 — — μs 10 — — ms 400 — — 400 — — 3 — — 3 — — ns μs ns μs Wake-up Timing TOS TWU CS SCK SI Ta=-40oC ~ 85oC Symbol Parameter TWU Wake-up Time TOS Oscillation Stable Time Rev. 1.00 Test Condition VDD Min. Typ. Max. Unit — 200 — — ns — 1000 — — μs Condition 5V 3V 5V 3V 8 January 18, 2012 HT16523 Digit Output Timing For 16-digits display, at a duty of 15/16 T=8/fOSC Frame cycle t1=1024T (t1=4096uS when fOSC=2MHz) Display timing t2=60T (t2=240uS when fOSC=2MHz) Blank timing t3=4T (t3=16uS when fOSC=2MHz) G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 AD1,2 S1~35 Rev. 1.00 9 January 18, 2012 HT16523 Segment and AD Position Positional relationship between S1~S35 and AD1 ~ AD2 - single digit C0 AD1 ADRAM written data. Corresponds to 2nd byte. C1 AD2 C0 S1 C1 S2 C2 S3 C3 S4 C4 S5 C5 S6 C6 S7 C7 S8 C8 S9 C9 S10 C10 S11 C11 S12 C12 S13 C13 S14 C14 S15 C15 S16 C16 S17 C17 S18 C18 S19 C19 S20 C20 S21 C21 S22 C22 S23 C23 S24 C24 S25 C25 S26 C26 S27 C27 S28 C28 S29 C29 S30 C30 S31 C31 S32 C32 S33 C33 S34 C34 S35 CGRAM written data. Corresponds to 2nd byte (1st column) CGRAM written data. Corresponds to 3rd byte (2nd column) CGRAM written data. Corresponds to 4th byte (3rd column) CGRAM written data. Corresponds to 5th byte (4th column) CGRAM written data. Corresponds to 6th byte (5th column) Rev. 1.00 10 January 18, 2012 HT16523 Command Table Function Byte R/W Bit7 Bit6 (MSB) Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Note Default DDRAM data write 1st W 0 0 0 * X3 X2 X1 X0 Xn: Address specification for each RAM DDRAM data 2nd W C7 C6 C5 C4 C3 C2 C1 C0 Cn: character code specification for each RAM CGRAM data write 1st W 0 0 1 * * X2 X1 X0 Xn: Address specification for each RAM CGRAM Data 2nd W * C30 C25 C20 C15 C10 C5 C0 — CGRAM Data 3rd W * C31 C26 C21 C16 C11 C6 C1 — CGRAM Data 4th W * C32 C27 C22 C17 C12 C7 C2 CGRAM Data 5th W * C33 C28 C23 C18 C13 C8 C3 — CGRAM Data 6th W * C34 C29 C24 C19 C14 C9 C4 — ADRAM data write 1st W 0 1 0 * X3 X2 X1 X0 Xn: Address specification for each RAM ADRAM Data 2nd W * * * * * * C1 C0 Cn: character code specification for each RAM General output port set 1st W 0 1 1 * * * P2 P1 Pn: General output port status specification 63H Display duty set 1st W 1 0 0 * * D2 D1 D0 Dn: display duty specification 80H Number of digits set 1st W 1 0 1 * * K2 K1 K0 Kn: Number of digits specification A0H C0H E0H Cn: character code specification for each RAM All lights ON/OFF 1st W 1 1 0 * D S H L D: display on/off instruction S: standby mode instruction H: all lights ON instruction L: all lights OFF instruction TEST mode 1st W 1 1 1 0 0 0 0 0 For HOLTEK internal testing Rev. 1.00 11 00H — 20H — 40H — January 18, 2012 HT16523 Functional Description Command and Data Transfer Methods Complete access to the VFD driver consists of display commands and the display data. The number of transmitted data bytes for a complete access depends upon the command and memory type as the Command Table shows. The display control commands and data are transmitted using a 3-wire serial interface from the host MCU. The following steps show how the operation of the serial interface circuitry. Timing Generation Circuit A timing generation circuit generates timing signals for the operation of internal circuits such as the DDRAM, CGRAM, CGROM and ADRAM. VFD Driver Circuit The VFD driver circuit consists of 16 grid signal drivers and 35 segment signal drivers. When the number of digits are selected by a corresponding command, the required grid signal drivers automatically output drive waveforms, while the other grid signal drivers continue to output non-selection waveforms. Sending serial data is latched when the display data character pattern corresponds to the last address of the display data RAM (DDRAM). • Setting the CS pin to a “Low” level will enable a data transfer. • Data is 8-bits wide and is sequentially shifted-in on the SI pin from LSB to MSB (LSB first) • Data shifted into the register is ready at the rising edge of the serial shift clock, SCK. If the 8-bit data is to be written in, then internal signals are automatically generated and the data will be written into the corresponding register and RAM. Data Display RAM - DDRAM • Setting the CS pin to “High” will disable the command and data transfer The Display Data RAM (DDRAM) stores the display data in 8-bit character codes. Its extended capacity is 16x8 bits or 16 characters. • When data is written into the RAM area including DDRAM, ADRAM and CGRAM continuously, the command used to specify the RAM area is contained in the first shifted-in command byte together with the start address. Then the RAM address will be internally incremented by 1 automatically. Therefore, it is not necessary to specify the start address of the data to be written after the command byte. DDRAM data write command Reset Function Byte R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 1st W 0 0 0 * X3 X2 X1 Bit0 X0 2nd W C7 C6 C5 C4 C3 C2 C1 C0 3rd W C7 C6 C5 C4 C3 C2 C1 C0 4th W C7 C6 C5 C4 C3 C2 C1 C0 : : : : : : : : : : *: Don’t care When the RST pin is set to “Low”, the module is initialized to the following conditions: The DDRAM data write command descriptions are shown in the following: • Address will be reset to 00H for each RAM including DDRAM, ADRAM and CGRAM • X3~X0: DDRAM address is for 16 digits addressed from 00H to 0FH • C7~C0: character code of the CGROM (internal 248 characters) or CGRAM (user-defined 8 characters) • The contents of the RAM including DDRAM, ADRAM and CGRAM are undefined. • All general output ports go “High”. • To specify the character code of the CGROM or CGRAM continuously, only the character code needs to be specified • Display duty setting will be reset to 8/16 duty (register value D2, D1, D0=0, 0, 0). • Number of digits setting will be reset to 16 digits (register value K2, K1, K0=0, 0, 0). • The addresses of the DDRAM are automatically incremented by 1. • All display lights ON/OFF settings will be switched to the “display off” mode (register value D,S,H,L=0,0,0,0) • The address will be wrapped around to the start address when the DDRAM data write function is successively executed and the DDRAM address is greater than the maximum available address • All segment outputs go “Low”. • All AD outputs go “Low”. • All grid outputs go “Low”. Note: After a power on reset, all the RAM, including DDRAM, ADRAM and CGRAM, will be cleared. Rev. 1.00 12 January 18, 2012 HT16523 • Grid positions and set DDRAM addresses Rev. 1.00 HEX X3 X2 X1 X0 Grid Position 0 0 0 0 0 G1 1 0 0 0 1 G2 2 0 0 1 0 G3 3 0 0 1 1 G4 4 0 1 0 0 G5 5 0 1 0 1 G6 6 0 1 1 0 G7 7 0 1 1 1 G8 8 1 0 0 0 G9 9 1 0 0 1 G10 A 1 0 1 0 G11 B 1 0 1 1 G12 C 1 1 0 0 G13 D 1 1 0 1 G14 E 1 1 1 0 G15 F 1 1 1 1 G16 13 January 18, 2012 HT16523 Character Generator ROM (CGROM) • The CGROM for generating character patterns of 5x7 dots from 8-bit character codes generates 248 types of character patterns • The character codes are shown on the following page • Character codes 00H to 07H are allocated to the CGRAM Character Code Table for ROM code 002 Rev. 1.00 14 January 18, 2012 HT16523 LSB MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 RAM0 0001 RAM1 (CGRAM) (CGRAM) 0010 RAM2 (CGRAM) 0011 RAM3 (CGRAM) 0100 RAM4 (CGRAM) 0101 RAM5 (CGRAM) 0110 RAM6 (CGRAM) 0111 RAM7 (CGRAM) 1000 1001 1010 1011 1100 1101 1110 1111 Character Code Table for ROM code 003 Rev. 1.00 15 January 18, 2012 HT16523 Character Generator RAM (CGRAM) • To specify character pattern data continuously, only the character pattern data needs to be specified The CGRAM stores the pixel information (1=pixel on, 0=pixel off) for the eight user-defined 5x7 characters. Valid CGRAM addresses are 00H to 07H. Character codes 00H~07H are assigned to the userdefined characters. • The addresses of the CGRAM are automatically incremented by 1 • The address will be wrapped around to the start address when the CGRAM data write function is successively executed and the CGRAM address is greater than the maximum available address CGRAM data write command Byte R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1st W 0 0 1 * * X2 X1 X0 2nd W * C30 C25 C20 C15 C10 C5 C0 3rd W * C31 C26 C21 C16 C11 C6 C1 4th W * C32 C27 C22 C17 C12 C7 5th W * C33 C28 C23 C18 C13 C8 6th W * C34 C29 C24 C19 C14 C9 C4 • CGROM addresses and set CGRAM addresses HEX X2 X1 X0 CGRAM Mapping to CGROM Address C2 00 0 0 0 RAM00 00000000B C3 01 0 0 1 RAM01 00000001B 02 0 1 0 RAM02 00000010B 03 0 1 1 RAM03 00000011B 04 1 0 0 RAM04 00000100B 05 1 0 1 RAM05 00000101B 06 1 1 0 RAM06 00000110B 07 1 1 1 RAM07 00000111B *: Don’t care The CGRAM data write command descriptions are described by the following: • X2~X0: CGRAM addresses for 8 user-defined characters • C34~C0: character pattern data, 35-bit outputs per digit. The relationship between the 35-bit character pattern data and the dot positions for each digit is shown in the accompanying diagram • Relationship between the CGRAM output data and the character dot position • A character pattern stored in the CGRAM can be displayed and addressed by the character code specified in the DDRAM C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 area that corresponds to 2nd byte (1st column) area that corresponds to 3rd byte (2nd column) area that corresponds to 4th byte (3rd column) area that corresponds to 5th byte (4th column) area that corresponds to 6th byte (5th column) Rev. 1.00 16 January 18, 2012 HT16523 Additional Symbol Display RAM (ADRAM) General Output Port Command The ADRAM stores the additional symbol information (1=symbol on, 0=symbol off) for the 16 digits. For each 5x7 digit there are two symbols displayed together with the character. The positional relationship is shown in the accompanying diagram. R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 1st W 0 1 0 * X3 X2 X1 X0 W * * * * * * C1 C0 3rd W * * * * * * C1 C0 4th W * * * * * * C1 C0 : : : : : : : : : : Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 W 0 1 1 * * * P2 P1 The general output port command descriptions are described by the following: • P2, P1: general output port data • The general output port supports 2-bit static output operation Bit0 2nd R/W 1st *: Don’t care ADRAM Data Write Command Byte Byte • Used to control other I/O devices or control LEDs • When the general output port data is set to a high level, the related pin will output a VDD voltage level while the related pin will output a GND voltage level when the general output port data is cleared to a low level *: Don’t care The ADRAM data write command descriptions are described by the following: • Relationship between the general output port data and the output pin status • X3~X0: ADRAM addresses for 16 digits • C1~C0: 2 bits Symbol data for each digit Display State of General Output Port P2 P1 • Symbol data specified by the ADRAM is directly output regardless of the CGRAM data and the CGROM code • The ADRAM can store 2 types of symbol pattern for each digit 0 0 Sets P2 to low; Sets P1 to low — 0 1 Sets P2 to low; Sets P1 to high — 1 0 Sets P2 to high; Sets P1 to low — 1 Default state when power Sets P2 to high; Sets P1 to high is applied or when the RST input is at a low level. 1 • The ADRAM contents output to the terminal can be used as a cursor for each digit Comment Display Duty Set Command • The address of the ADRAM is automatically incremented by 1 • The address will be wrapped around to the start address when the ADRAM data write function is successively executed and the ADRAM address is greater than the maximum available address Byte R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1st W 1 0 0 * * D2 D1 D0 *: Don’t care The display duty set command descriptions are described by the following: • D2~D0: Display duty selections • Grid positions and ADRAM addresses • The display duty adjusts the contrast in 8 stages using 3 selection bits to adjust the pulse width of the segment output. HEX X3 X2 X1 X0 Grid Position 0 0 0 0 0 G1 1 0 0 0 1 G2 2 0 0 1 0 G3 3 0 0 1 1 G4 4 0 1 0 0 G5 5 0 1 0 1 G6 6 0 1 1 0 G7 7 0 1 1 1 G8 8 1 0 0 0 G9 3 0 1 1 11/16 — 9 1 0 0 1 G10 4 1 0 0 12/16 — A 1 0 1 0 G11 B 1 0 1 1 G12 C 1 1 0 0 G13 D 1 1 0 1 G14 E 1 1 1 0 G15 F 1 1 1 1 G16 Rev. 1.00 • The relationship between the setup data and the grid duty is shown in the table. HEX 0 17 D2 0 D1 0 D0 0 Grid Duty Comment 8/16 Default state when power is applied or when RST input is at a low level. 1 0 0 1 9/16 — 2 0 1 0 10/16 — 5 1 0 1 13/16 — 6 1 1 0 14/16 — 7 1 1 1 15/16 — January 18, 2012 HT16523 Number of Digits Set Command Byte R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1st W 1 0 1 * * K2 K1 K0 D S H L 1 0 0 Normal display — — 0 1 0 0 1 0 1 * Sets all segments and AD to High All grids maintain scan General ports active — Display off mode (Default state when power is applied or when the RST input is at a low level.) • K2~K0: number of digit selections • The number of display digits can be from 9 to 16 digits using the 3 selection bits. • The relationship between setup data and the displayed grid is shown in the table. HEX K2 K1 K0 Number of Digits of Grid Comment 0 0 0 0 G1 to G16 1 0 0 1 G1 to G9 — 2 0 1 0 G1 to G10 — 3 0 1 1 G1 to G11 — 4 1 0 0 G1 to G12 — 5 1 0 1 G1 to G13 — 6 1 1 0 G1 to G14 — 7 1 1 1 G1 to G15 — Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 1st W 1 1 0 * D S 0 * * * 1 * * Sets all segments and AD to Low. Sets all grids to Low. Standby mode Set General ports to high. Wake-up Setting The wake-up behavior is described by the following: • The device is woken up when a CS low pulse is asserted i.e. when a CS signal falling edge occurs. • The D and S control bits described in the preceding section will be set to “0” - display off mode • The oscillator starts to oscillate after wake-up • The VFD driver does not display until the host MCU transmits commands to it. All Display Lights On/Off Set Command R/W 0 Sets all segments and AD to Low Sets all grids to Low General ports active *: Don’t care Default state when power is applied or when the RST input is at a low level. Byte Comment Sets all segments and Sets all segments and AD to Low. 1 All grids maintain scan General ports active AD to Low *: Don’t care The number of digits set command descriptions is are described by the following: Driver Output Status Bit1 Bit0 H L Wake-up CS *: Don’t care SCK The display ON/OFF set command descriptions are described by the following: SI TEST Command • S bit: S=“1” is standby mode; S=“0” is normal mode • D bit: D=“1” is display ON; D=“0” is display OFF • H bit: set all lights ON Byte R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1st W 1 1 1 0 0 0 0 0 The TEST command is described by the following: • L bit: set all lights OFF • Only when the TEST pin is high is the TEST command “E0H” is valid • When S bit = “1”, the internal oscillator stops and all outputs are set to low and the general port is set to high (P2 and P1 are all at high levels) • This command is used by HOLTEK for internal testing. • When S bit = “1”, all registers will keep their original value • After being woken up, the device will set the S and D bits to “0” • The “All display lights ON” command is used primarily for display testing • The “All display lights OFF” command is primarily used for display flashing • The command bits, including D, H and L bits, cannot control the general output port • The relationship between the control bits and display state of G1~G16, S1~S35 and AD1~AD2 pins is shown in the table. Rev. 1.00 18 January 18, 2012 HT16523 Setting Flowchart Power applied included Apply VDD Apply VH All display lights OFF Status of all outputs by RST signal input General output port setting Number of digits setting Display duty setting Select a RAM to be used DDRAM Data write mode (with address setting) Address is automatically incremented Address is automatically incremented Address is automatically incremented DDRAM Character code NO DDRAM Is character code write ended? ADRAM Data write mode (with address setting) CGRAM Data write mode (with address setting) ADRAM Character code CGRAM Character code CGRAM Is character code write ended? NO YES NO ADRAM Is character code write ended? YES YES YES Another RAM to be set? NO Releases all display lights OFF mode Display operation mode End Rev. 1.00 19 January 18, 2012 HT16523 Power-off Flowchart Display operation mode Turn off VH Turn off VDD Rev. 1.00 20 January 18, 2012 HT16523 Application Circuit RST Pin is Connected to a MCU 5x7 dot matrix fluorescent display tube CSB SCK SI RST Microcontroller VSS VDD VDD 2 35 16 AD1-2 S1-35 G1-16 VH R4 R3 VH LED VDD TEST VSS P1-2 OSCI 2 C4 ZD VDD VDD R1 C3 C1 GND RST Pin is Connected to External Resistor and Capacitor 5x7 dot matrix fluorescent display tube CSB SCK SI Microcontroller VDD 2 35 16 AD1-2 S1-35 G1-16 VH R4 R3 VH LED VSS VDD VDD RST TEST VSS P1-2 OSCI R2 VDD C3 C2 VDD 2 C4 ZD R1 C1 GND Note: 1. The VDD value depends on the power supply voltage of the microcontroller used. Adjust the values of the components R2, R4, C2, C3 and C4 according to the power supply voltage used. 2. The VH value depends on the fluorescent display tube used. Adjust the values of the components R3 and ZD according to the power supply voltage used. 3. R1=120KΩ, C1=0.1μF. Rev. 1.00 21 January 18, 2012 HT16523 Package Information Package Information LQFP Outline Dimensions 64-pin LQFP (7mm7mm) 64-pin LQFP (7mm xOutline 7mm)Dimensions Outline Dimensions Symbol Dimensions in inch Nom. Dimensions in inch Min. 0.350 Min. Nom. 0.358Max. A B 0.350 0.272 ― 0.2800.358 B C 0.272 0.350 ― 0.3580.280 C D 0.350 0.272 ― 0.2800.358 D E 0.272 ― 0.005 0.016― 0.280 0.009 ― E F F G G H H I JI KJ K α Symbol Symbol A A B B C C D D E E F F G G H H I I J J K K α 0.016 ― 0.005 0.053 0.053 ― ― ― 0.002 0.002 0.018 ― ― ― ― Dimensions in mm Dimensions in mm Nom. 0.018 0.004 0.004 0 0° Min. Min. 8.90 Nom. ― 8.90 6.90 6.90 8.90 8.90 6.90 6.90 ― 0.13 0.13 1.35 1.35 ― 0.05 0.05 0.45 0.45 0.09 0.09 0 0° ― ― ― 0.40 0.40 ― ― ― ― ― ― ― 1 Rev. 1.00 Max. Symbol A 22 0.0570.009 0.0630.057 0.0060.063 0.0300.006 0.0080.030 0.008 7 7° Max. 9.10Max. 7.10 9.10 9.10 7.10 7.10 0.23 1.45 1.60 0.15 0.75 0.20 7 9.10 7.10 ― 0.23 1.45 1.60 0.15 0.75 0.20 7° February 8, 2010 January 18, 2012 HT16523 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. (Dongguan Sales Office) Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311, 86-769-2626-1322 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright © 2012 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 23 January 18, 2012