Data Sheet

74LV4053-Q100
Triple single-pole double-throw analog switch
Rev. 1 — 25 March 2014
Product data sheet
1. General description
The 74LV4053-Q100 is a triple single-pole double-throw (SPDT) analog switch, suitable
for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS
device and is pin and function compatible with the 74HC4053-Q100 and
74HCT4053-Q100. Each switch has a digital select input (Sn), two independent
inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share
an enable input (E). A HIGH on E causes all switches into the high-impedance OFF-state,
independent of Sn.
VCC and GND are the supply voltage connections for the digital control inputs (Sn and E).
The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VCC as a positive limit and VEE as a negative limit. VCC  VEE may not
exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND
(typically ground). VEE and VSS are the supply voltage connections for the switches.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Optimized for low-voltage applications: 1.0 V to 3.6 V
 Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
 Low ON resistance:
 180  (typical) at VCC  VEE = 2.0 V
 100  (typical) at VCC  VEE = 3.0 V
 75  (typical) at VCC  VEE = 4.5 V
 Logic level translation:
 To enable 3 V logic to communicate with 3 V analog signals
 Typical ‘break before make’ built in
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Multiple package options
74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
3. Ordering information
Table 1.
Ordering information
Type number
74LV4053D-Q100
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16
plastic dual-in line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5  3.5  0.85 mm
74LV4053PW-Q100 40 C to +125 C
74LV4053BQ-Q100
40 C to +125 C
SOT763-1
4. Functional diagram
E
6
VCC
16
13 1Y1
S1 11
LOGIC
LEVEL
CONVERSION
12 1Y0
DECODER
14 1Z
1 2Y1
S2 10
LOGIC
LEVEL
CONVERSION
2 2Y0
15 2Z
3 3Y1
S3 9
LOGIC
LEVEL
CONVERSION
5 3Y0
4 3Z
8
GND
Fig 1.
7
VEE
001aak341
Functional diagram
74LV4053_Q100
Product data sheet
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Rev. 1 — 25 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
6
11
S1
1Y0
12
10
S2
1Y1
13
11
9
S3
1Z
EN
#
14
14
2Y0
2
2Y1
1
10
15
15
2Z
3Y0
5
3Y1
3
3Z
4
9
MUX/DMUX
0
×
0
1
0/1
12
13
1
#
2
1
5
#
3
4
6
E
001aae125
Fig 2.
Logic symbol
001aae126
Fig 3.
IEC logic symbol
Y
VCC
VEE
VCC
VCC
VCC
VEE
from
logic
VEE
Z
001aad544
Fig 4.
Schematic diagram (one switch)
74LV4053_Q100
Product data sheet
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Rev. 1 — 25 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 25
74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
5. Pinning information
5.1 Pinning
/94
<
=
=
<
<
<
(
6
9((
6
*1'
6
/94
<
=
<
=
<
<
9&&
<
=
=
<
=
<
=
<
(
<
<
6
9((
(
9((
6
*1'
DDD
6
9&&
=
<
9&&
6
6
6
<
WHUPLQDO
LQGH[DUHD
9&&
*1'
<
<
/94
DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin. The
substrate is attached to this pad
using conductive die attach
material. There is no electrical or
mechanical requirement to
solder this pad. However, if it is
soldered, the solder land should
remain floating or be connected
to VCC.
Fig 5.
Pin configuration
SOT109-1
Fig 6.
Pin configuration
SOT403-1
Fig 7.
Pin configuration for
SOT763-1
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
E
6
enable input (active LOW)
VEE
7
supply voltage
GND
8
ground supply voltage
S1, S2, S3
11, 10, 9
select input
1Y0, 2Y0, 3Y0
12, 2, 5
independent input or output
1Y1, 2Y1, 3Y1
13, 1, 3
independent input or output
1Z, 2Z, 3Z
14, 15, 4
common output or input
VCC
16
supply voltage
74LV4053_Q100
Product data sheet
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Rev. 1 — 25 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
6. Functional description
Table 3.
Function table [1]
Inputs
Channel on
E
Sn
L
L
nY0 to nZ
L
H
nY1 to nZ
H
X
switches off
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
Conditions
supply voltage
VCC
Min
Max
Unit
[1]
0.5
+7.0
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[2]
-
20
mA
ISK
switch clamping current
VSW < 0.5 V or VSW > VCC + 0.5 V
[2]
-
20
mA
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
source or sink current
[2]
-
25
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C
[3]
SO16 package
-
500
mW
TSSOP16 package
-
500
mW
DHVQFN16 package
-
500
mW
[1]
To avoid drawing VCC current from terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current flows out of terminals nYn. In this case, there is
no limit to the voltage drop across the switch. However, the voltages at nYn and nZ may not exceed VCC or VEE.
[2]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[3]
For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74LV4053_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 25
74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
see Figure 8
1
3.3
6
V
VI
input voltage
0
-
VCC
V
VSW
switch voltage
Tamb
ambient temperature
t/V
[1]
0
-
VCC
V
40
-
+125
C
input transition rise and fall rate VCC = 1.0 V to 2.0 V
-
-
500
ns/V
VCC = 2.0 V to 2.7 V
-
-
200
ns/V
VCC = 2.7 V to 3.6 V
-
-
100
ns/V
in free air
The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V. However, LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
001aak344
8.0
VCC - GND
(V)
6.0
operating area
4.0
2.0
0
0
Fig 8.
2.0
4.0
6.0
8.0
VCC - VEE (V)
Guaranteed operating area as a function of the supply voltages
74LV4053_Q100
Product data sheet
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Rev. 1 — 25 March 2014
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74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
input leakage current
II
IS(OFF)
IS(ON)
OFF-state leakage current
ON-state leakage current
supply current
ICC
ICC
additional supply current
CI
input capacitance
Csw
switch capacitance
[1]
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VCC = 1.2 V
0.9
-
-
0.9
-
V
VCC = 2.0 V
1.4
-
-
1.4
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V
3.15
-
-
3.15
-
V
VCC = 6.0 V
4.20
-
-
4.20
-
V
VCC = 1.2 V
-
-
0.3
-
0.3
V
VCC = 2.0 V
-
-
0.6
-
0.6
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V
-
-
1.35
-
1.35
V
VCC = 6.0 V
-
-
1.80
-
1.80
V
VCC = 3.6 V
-
-
1.0
-
1.0
A
VCC = 6.0 V
-
-
2.0
-
2.0
A
VCC = 3.6 V
-
-
1.0
-
1.0
A
VCC = 6.0 V
-
-
2.0
-
2.0
A
VCC = 3.6 V
-
-
1.0
-
1.0
A
VCC = 6.0 V
-
-
2.0
-
2.0
A
VCC = 3.6 V
-
-
20
-
40
A
VCC = 6.0 V
-
-
40
-
80
A
per input; VI = VCC  0.6 V;
VCC = 2.7 V to 3.6 V
-
-
500
-
850
A
-
3.5
-
-
-
pF
independent pins nYn
-
5
-
-
-
pF
common pins nZ
-
8
-
-
-
pF
VI = VCC or GND
VI = VIH or VIL; see Figure 9
VI = VIH or VIL; see Figure 10
VI = VCC or GND; IO = 0 A
Typical values are measured at Tamb = 25 C.
74LV4053_Q100
Product data sheet
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Rev. 1 — 25 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
Triple single-pole double-throw analog switch
9.1 Test circuits
VCC
VIH or VIL
VCC
S1 to S3
nY0
1
nZ
nY1
2
E
IS
S1 to S3
nY0
1
nZ
nY1
2
VI
VO
VI
001aak345
001aak346
VI = VCC or VEE and VO = VEE or VCC.
Fig 9.
IS
GND = VEE
GND
VO
switch
E
IS
GND = VEE
VCC
VIH or VIL
switch
VI = VCC or VEE and VO = open circuit.
Test circuit for measuring OFF-state leakage
current
Fig 10. Test circuit for measuring ON-state leakage
current
9.2 ON resistance
Table 7.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol
Parameter
RON(peak) ON resistance (peak)
40 C to +85 C
Conditions
Min
Max
Min
Max
-
-
-
-
-

VCC = 2.0 V; ISW = 1000 A
-
180
365
-
435

VCC = 2.7 V; ISW = 1000 A
-
115
225
-
270

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
100
200
-
245

VCC = 4.5 V; ISW = 1000 A
-
75
150
-
180

VCC = 6.0 V; ISW = 1000 A
-
70
140
-
165

-
-
-
-
-

-
5
-
-
-

VI = 0 V to VCC  VEE
VCC = 1.2 V; ISW = 100 A
RON
ON resistance mismatch VI = 0 V to VCC  VEE
between channels
VCC = 1.2 V; ISW = 100 A
[2]
[2]
VCC = 2.0 V; ISW = 1000 A
74LV4053_Q100
Product data sheet
40 C to +125 C Unit
Typ[1]
VCC = 2.7 V; ISW = 1000 A
-
4
-
-
-

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
4
-
-
-

VCC = 4.5 V; ISW = 1000 A
-
3
-
-
-

VCC = 6.0 V; ISW = 1000 A
-
2
-
-
-

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74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 7.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and
Figure 12.
Symbol
RON(rail)
Parameter
ON resistance (rail)
40 C to +85 C
Conditions
Min
Max
Min
Max
-
250
-
-
-

VCC = 2.0 V; ISW = 1000 A
-
120
280
-
325

VCC = 2.7 V; ISW = 1000 A
-
75
170
-
195

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
70
155
-
180

VCC = 4.5 V; ISW = 1000 A
-
50
120
-
135

VCC = 6.0 V; ISW = 1000 A
-
45
105
-
120

-
350
-
-
-

VCC = 2.0 V; ISW = 1000 A
-
170
340
-
400

VCC = 2.7 V; ISW = 1000 A
-
105
210
-
250

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
95
190
-
225

VCC = 4.5 V; ISW = 1000 A
-
70
140
-
165

VCC = 6.0 V; ISW = 1000 A
-
65
125
-
150

VI = GND
VCC = 1.2 V; ISW = 100 A
RON(rail)
ON resistance (rail)
40 C to +125 C Unit
Typ[1]
[2]
VI = VCC  VEE
VCC = 1.2 V; ISW = 100 A
[2]
[1]
Typical values are measured at Tamb = 25 C.
[2]
When supply voltages (VCC  VEE) approach 1.2 V, the analog switch ON resistance becomes extremely non-linear. Use these devices
only for transmitting digital signals, when using a supply of 1.2 V.
74LV4053_Q100
Product data sheet
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Rev. 1 — 25 March 2014
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NXP Semiconductors
Triple single-pole double-throw analog switch
9.3 On resistance waveform and test circuit
V
VSW
VCC
VIH or VIL
S1 to S3
nY0
1
nZ
nY1
2
switch
E
GND = VEE
GND
ISW
VI
001aak347
RON = VSW / ISW.
Fig 11. Test circuit for measuring RON
001aak348
200
VCC = 2.0 V
RON
(Ω)
150
VCC = 3.0 V
100
VCC = 4.5 V
50
0
0
1.2
2.4
3.6
4.8
VI (V)
Vi = 0 V to VCC  VEE
Fig 12. Typical RON as a function of input voltage
74LV4053_Q100
Product data sheet
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Rev. 1 — 25 March 2014
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10 of 25
74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 15.
Symbol Parameter
tpd
40 C to +85 C
Conditions
Min
Max
Min
Max
VCC = 1.2 V
-
25
-
-
-
ns
VCC = 2.0 V
-
9
17
-
20
ns
-
6
13
-
15
ns
propagation delay nYn, nZ to nZ, nYn; see Figure 13
VCC = 3.0 V to 3.6 V
[3]
-
5
10
-
12
ns
-
4
9
-
10
ns
-
3
7
-
8
ns
VCC = 1.2 V
-
100
-
-
-
ns
VCC = 2.0 V
-
34
65
-
77
ns
-
25
48
-
56
ns
-
16
-
-
-
ns
VCC = 4.5 V
VCC = 6.0 V
enable time
E to nYn, nZ; see Figure 14
[2]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
VCC = 3.0 V to 3.6 V
[3]
-
19
38
-
45
ns
-
17
32
-
38
ns
-
13
25
-
29
ns
VCC = 1.2 V
-
125
-
-
-
ns
VCC = 2.0 V
-
43
82
-
97
ns
-
31
60
-
71
ns
-
20
-
-
-
ns
VCC = 4.5 V
VCC = 6.0 V
Sn to nYn, nZ; see Figure 14
[2]
VCC = 2.7 V
74LV4053_Q100
Product data sheet
Unit
[2]
VCC = 2.7 V
ten
40 C to +125 C
Typ[1]
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
VCC = 3.0 V to 3.6 V
[3]
-
24
48
-
57
ns
VCC = 4.5 V
-
21
41
-
48
ns
VCC = 6.0 V
-
16
31
-
37
ns
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Rev. 1 — 25 March 2014
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74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 15.
Symbol Parameter
tdis
disable time
40 C to +85 C
Conditions
Min
VCC = 1.2 V
-
95
-
-
-
ns
VCC = 2.0 V
-
34
61
-
73
ns
-
26
46
-
54
ns
-
17
-
-
-
ns
E to nYn, nZ; see Figure 14
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
VCC = 3.0 V to 3.6 V
[3]
Max
20
37
-
44
ns
18
32
-
38
ns
-
15
25
-
30
ns
VCC = 1.2 V
-
90
-
-
-
ns
VCC = 2.0 V
-
32
59
-
70
ns
-
24
44
-
52
ns
-
16
-
-
-
ns
Sn to nYn, nZ; see Figure 14
[2]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
VCC = 3.0 V to 3.6 V
[3]
VCC = 4.5 V
VCC = 6.0 V
[2]
Min
-
VCC = 6.0 V
[1]
Max
-
VCC = 4.5 V
power dissipation
capacitance
Unit
[2]
VCC = 2.7 V
CPD
40 C to +125 C
Typ[1]
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[4]
-
19
36
-
42
ns
-
17
31
-
36
ns
-
14
24
-
28
ns
-
36
-
-
-
pF
All typical values are measured at Tamb = 25 C.
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + ((CL + CSW)  VCC2  fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
CSW = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
(CL  VCC2  fo) = sum of the outputs.
74LV4053_Q100
Product data sheet
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Triple single-pole double-throw analog switch
10.1 Waveforms
VCC
nYn or nZ
input
VM
VEE
tPLH
tPHL
VO
nZ or nYn
output
VM
VEE
001aak351
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 13. nYn, nZ to nZ, nYn propagation delays
VCC
Sn, E input
VM
VSS
tPLZ
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
tPZL
VO
90 %
10 %
VEE
tPHZ
VO
tPZH
90 %
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
10 %
VEE
switch ON
switch OFF
switch ON
001aak352
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 14. Enable and disable times
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
< 2.7 V
0.5VCC
0.5VCC
VOL + 0.1VCC
VOH  0.1VCC
2.7 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH  0.3 V
> 3.6 V
0.5VCC
0.5VCC
VOL + 0.1VCC
VOH  0.1VCC
74LV4053_Q100
Product data sheet
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74LV4053-Q100
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Triple single-pole double-throw analog switch
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
VEE
RL
CL
001aak353
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 15. Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
< 2.7 V
VCC
 6 ns
50 pF
1 k
open
VEE
2VCC
2.7 V to 3.6 V
2.7 V
 6 ns
15 pF, 50 pF
1 k
open
VEE
2VCC
> 3.6 V
VCC
 6 ns
50 pF
1 k
open
VEE
2VCC
74LV4053_Q100
Product data sheet
Load
VEXT
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NXP Semiconductors
Triple single-pole double-throw analog switch
10.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). VI = GND or VCC (unless otherwise
specified). tr = tf  6.0 ns; Tamb = 25 C.
Symbol Parameter
Conditions
THD
fi = 1 kHz; CL = 50 pF; RL = 10 k; see Figure 20
total harmonic
distortion
Min
Typ
Max
Unit
VCC = 3.0 V; VI = 2.75 V (p-p)
-
0.8
-
%
VCC = 6.0 V; VI = 5.5 V (p-p)
-
0.4
-
%
VCC = 3.0 V; VI = 2.75 V (p-p)
-
2.4
-
%
VCC = 6.0 V; VI = 5.5 V (p-p)
-
1.2
-
%
-
180
-
MHz
-
200
-
MHz
-
50
-
dB
-
50
-
dB
VCC = 3.0 V
-
0.11
-
V
VCC = 6.0 V
-
0.12
-
V
VCC = 3.0 V
-
60
-
dB
VCC = 6.0 V
-
60
-
dB
fi = 10 kHz; CL = 50 pF; RL = 10 k; see Figure 20
f(3dB)
3 dB frequency
response
CL = 50 pF; RL = 50 ; see Figure 16
isolation (OFF-state)
fi = 1 MHz; CL = 50 pF; RL = 600 ; see Figure 18
[1]
VCC = 3.0 V
VCC = 6.0 V
iso
[2]
VCC = 3.0 V
VCC = 6.0 V
crosstalk voltage
Vct
Xtalk
crosstalk
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 600 ; see Figure 21
between switches; fi = 1 MHz; CL = 50 pF;
RL = 600 ; see Figure 22
[1]
To obtain 0 dBm level at output for 1 MHz, adjust fi voltage (0 dBm = 1 mW into 50 ).
[2]
To obtain 0 dBm level at output for 1 MHz, adjust fi voltage (0 dBm = 1 mW into 600 ).
74LV4053_Q100
Product data sheet
[2]
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74LV4053-Q100
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Triple single-pole double-throw analog switch
10.2.1 Test circuits
001aak361
5
(dB)
VCC
VCC
0
VIH or VIL
S1 to S3
nY0
1
nZ
nY1
2
2RL
switch
E
0.1 μF
GND = VEE
GND
2RL
CL
dB
fi
−5
10
102
103
104
105
106
f (kHz)
001aak355
VCC = 3.0 V; GND = 0 V; VEE = 3.0 V; RL = 50 ;
RSOURCE = 1 k.
Fig 16. Test circuit for measuring frequency response
Fig 17. Typical frequency response
001aak360
0
(dB)
VCC
VCC
VIH or VIL
0.1 μF
VCC
S1 to S3
nY0
1
nZ
nY1
2
−50
2RL
switch
E
GND = VEE
2RL
CL
dB
fi
−100
10
102
103
104
105
106
f (kHz)
001aak356
VCC = 3.0 V; GND = 0 V; VEE = 3.0 V; RL = 50 ;
RSOURCE = 1 k.
Fig 18. Test circuit for measuring isolation (OFF-state)
74LV4053_Q100
Product data sheet
Fig 19. Typical isolation (OFF-state) as function of
frequency
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Triple single-pole double-throw analog switch
VCC
VCC
VIH or VIL
S1 to S3
nY0
1
nZ
nY1
2
2RL
switch
E
10 μF
GND = VEE
GND
2RL
CL
D
fi
001aak354
Fig 20. Test circuit for measuring total harmonic distortion
VCC
VCC
VCC
2RL
S1 to S3
nY0
1
nZ
nY1
2
2RL
switch
E
2RL
G
GND = VEE
VIH or VIL
2RL
CL
V
VO
001aak357
a. Test circuit
logic
input (Sn, E)
off
on
off
Vct
VO
001aaj908
b. Input and output pulse definitions
VI may be connected to Sn or E.
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
74LV4053_Q100
Product data sheet
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17 of 25
74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
VCC
VCC
VCC
2RL
VIH or VIL
RL
S1 to S3
nY0
nZ
nY1
2RL
E
0.1 μF
GND = VEE
GND
2RL
VO
CL
2RL
dB
VI
001aak358
a. Switch closed condition
VCC
VCC
VCC
2RL
VCC
2RL
VIH or VIL
S1 to S3
nY0
nZ
nY1
2RL
E
GND = VEE
GND
RL
2RL
VO
VI
2RL
CL dB
001aak359
b. Switch open condition
Fig 22. Test circuit for measuring crosstalk between switches
74LV4053_Q100
Product data sheet
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74LV4053-Q100
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Triple single-pole double-throw analog switch
11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 23. Package outline SOT109-1 (SO16)
74LV4053_Q100
Product data sheet
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19 of 25
74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 24. Package outline SOT403-1 (TSSOP16)
74LV4053_Q100
Product data sheet
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74LV4053-Q100
NXP Semiconductors
Triple single-pole double-throw analog switch
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
7
y
y1 C
v M C A B
w M C
b
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 25. Package outline SOT763-1 (DHVQFN16)
74LV4053_Q100
Product data sheet
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Triple single-pole double-throw analog switch
12. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LV4053_Q100 v.1
20140325
Product data sheet
-
-
74LV4053_Q100
Product data sheet
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Triple single-pole double-throw analog switch
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LV4053_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 March 2014
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Triple single-pole double-throw analog switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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NXP Semiconductors
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Triple single-pole double-throw analog switch
16. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
9.1
9.2
9.3
10
10.1
10.2
10.2.1
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8
On resistance waveform and test circuit. . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Additional dynamic parameters . . . . . . . . . . . 15
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 March 2014
Document identifier: 74LV4053_Q100