WINBOND W83628F

PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
GENERAL DESCRIPTION
W83628F is a PCI-to-ISA bus conversion IC. W83629D is a condensed centralizer
IC for IRQ and DMA control. W83628F and W83629D together form a complete set
for the PCI-to-ISA bridge.
For the new generation Intel chipset Camino and Whitney, featuring LPC bus, there
is no support for ISA bus and slots. However the demand of ISA devices still exist.
For such case, W83628F plus W83629D are the best companion solution for the
non-ISA chipset. Also the packages of W83628F (128-QFP) and W83629D (48LQFP) had been chosen to be the most economic solution for save the M/B board
layout size and cost.
For the new generation chipset featuring LPC interface and support no ISA bus,
W83627HF/F (Winbond LPC I/O) together with the set of W83628F and W83629D
is the complete solution.
FEATURES
PCI to ISA Bridge
•
•
•
•
•
•
•
•
•
Full ISA Bus Support including ISA Masters
5V ISA and 3.3V PCI interfaces
PC/PCI DMA protocol for Software Transparent
IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ
Supports 3 fully ISA Compatible Slots without Buffering
PCI Bus at 25MHz, 33MHz and up to 40MHz
Supports Programmable ISA Bus Divide the PCI Bus Clock into 3 or 4
All ISA Signals can be Isolate
Supports Configuration registers for programming performance
PACKAGE
• 128-pin PQFP for W83628F
• 48-pin LQFP for W83629D
-1-
Publication Release Date: Dec 1998
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
BLOCK DIAGRAM OF W83628F
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
SERR#
SA[19:0]
SD[15:0]
BALE
AEN
IOCHRDY
IOCS16#
IOCHK#
IOR#
IOW#
LA[23:17]
SBHE#
MEMCS16#
MEMR#
MEMW#
SMEMR#
SMEMW#
ZEROWS#
MASTER#
REFRESH#
ROMCS#
RSTDRV
SYSCLK
PCI
Interface
ISA
Interface
NOGO
PCIRST#
PCICLK
ISOLATE#
3.3V
5V
Signal
Isolation
Control
Power
SuppIy
Handshaking
-2-
HS[2:0]
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
BLOCK DIAGRAM OF W83629D
PCIRST#
PCI Host &
Bridge Set
Handshaking
Logic
PCICLK
NOGO
HS[2:0]
ISAREQ#
DREQ[7:5,3:0]
PCI/PCI
ISAGNT#
Interface
Serial
to
Parallel
IRQ
SERIRQ
3.3V
5V
DACK[7:5,3:0]#
TC
IRQ[15,14,12:9,7:3]
Power
SuppIy
-3-
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
PIN CONFIGURATION FOR 628F
S
Y
SS
V S S CA
CDDL1
C6 7 K9
S
A
1
8
S S
AG A
1N1
7D6
S SS
A AA
1 11
5 43
SSS
N
A A A S S S S S V S S S S SO
1 1 1 A A A A A CA A A A AG
2 1 0 9 8 7 6 5 C4 3 2 1 0 O
R
E
FR
RS
ET
SD
HR
# V
I
SP
R OC
OL I
UAR
C T S A A AAA G
S E T D D DDD N
# ## 0 1 234 D
11 1 99 9 9 99 9 9 9 9 8 8 88 8 8 88 8 877 7 7 7 7 7 7 7 7 6 6 6 6 6
00 0 98 7 6 54 3 2 1 0 9 8 76 5 4 32 1 098 7 6 5 4 3 2 1 0 9 8 7 6 5
21 0
SD5
SD4
IOCHK#
ZEROWS#
SD3
SD2
SD1
SD0
GND
HS2
HS1
HS0
VCC
IOCHRDY
SMEMR#
AEN
SMEMW#
IOR#
IOW#
BALE
MEMCS16#
IOCS16#
LA17
LA18
LA19
GND
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
W83628F
3VCC
AD5
AD6
AD7
C/BE0#
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
C/BE1#
GND
PAR
PCLK_OUT
PCICLK
3VCC
SERR#
C/BE2#
DEVSEL#
TRDY#
IRDY#
FRAME#
STOP#
1 1 1 11 1 1 1 1 1 22 22 2 22 2 2 2 3 33 3 3 33 33
1 2 34 5 67 8 90 1 2 34 5 6 7 8 9 01 23 4 56 7 8 9 0 12 3 4 56 78
VL
CA
C2
0
L LL
AAA
2 22
1 23
MM S S SS S S S S G MS A A A
E E D D DD D D D D N A B D D D
MM 8 9 1 1 1 1 1 1 D S H 3 3 2
01 2 3 4 5 T E109
RW
E#
# #
R
L
#
A
2
2
-4-
A
D
2
8
A A AA
D D DD
2 2 22
7 6 54
3 CI A
V/ DD
CBS 2
CEE 3
3 L
#
AAAA
DDDD
2 2 2 1
2 1 0 9
A AA G
D DD N
1 11 D
8 76
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
PIN CONFIGURATION FOR 629D
D
R
N Q
C 7
D
A
C
K
7
#
D
R
Q
6
D
A
C
K
6
#
D
R
Q
5
D
A
D
C
D A
K G R C
5 N Q K
# D 3 3
36
NC
NC
NC
NOGO
ISAREQ#
ISAGNT#
GND
PCICLK
NC
SERIRQ
PCIRST#
3VCC
D
R V
Q C
2 C
25
37
24
DACK2#
13
DRQ1
DACK1#
DRQ0
DACK0#
TC
GND
HS2
HS1
HS0
VCC
IRQ15
W83629D
48
1
G I
N R
D Q
3
12
I
R
Q
4
I
R
Q
5
I
R
Q
6
I V I I I
R C R R R
Q D
C Q Q Q
7
9 1 1
0 1
-5-
I
I
R R
Q Q
1 1
2 4
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O12t
I/O24t
- TTL level bi-directional pin with 12 mA source-sink capability
I/O12tp3
I/O24tp3
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
I/OD12t
- TTL level bi-directional pin open drain output with 12 mA sink capability
I/O24t
OUT12t
- TTL level output pin with 12 mA source-sink capability
OUT24t
- TTL level output pin with 24 mA source-sink capability
OUT12tp3
OUT24tp3
- 3.3V TTL level output pin with 24 mA source-sink capability
OD12
- Open-drain output pin with 12 mA sink capability
OD24
INcs
- Open-drain output pin with 24 mA sink capability
INt
- TTL level input pin
INtd
- TTL level input pin with internal pull down resistor
INts
- TTL level Schmitt-trigger input pin
INtsp3
- 3.3V TTL level Schmitt-trigger input pin
- TTL level bi-directional pin with 24 mA source-sink capability
- 3.3V TTL level bi-directional pin with 24 mA source-sink capability
- TTL level bi-directional pin with 24 mA source-sink capability
- 3.3V TTL level output pin with 12 mA source-sink capability
- CMOS level Schmitt-trigger input pin
1.1 W83628F PIN DESCRIPTION
1.1.1
PCI Interface
SYMBOL
AD[31:0]
PIN
I/O
FUNCTION
19-26
I/O24tp3
PCI Bus Address and Data Signals. The standard PCI address
and data lines. Address is driven with FRAME# assertion, data is
driven or received in following clocks.
I/O24tp3
PCI Bus Command and Byte Enables. During the address
phase of a transaction C/BE[3:0]# define the bus command.
During the data phase C/BE[3:0]# are used as Byte Enables.
30-37
52-59
61-63
66-70
C/BE[3:0]#
28,45
51,60
PCICLK
47
INt
PCLK_OUT
48
OUT12t
PCI Bus System Clock. PCICLK provides timing for all
transactions on the PCI bus. All other PCI signals are sampled
on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
PCI Bus System Clock DPLL Output. The PCLK_OUT can
reduce the PCICLK Loading and it produced from internal DPLL.
-6-
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
1.1.1 PCI Interface, continued
SYMBOL
PIN
I/O
FUNCTION
FRAME#
40
I/O24tp3
Frame Signal. FRAME# is driven by the current PCI bus master
to indicate the beginning and duration of an access.
IDSEL
29
INt
Initialization Device Select. IDSEL is used as a chip select
during configuration read and write transactions. This signal
should be externally tied to one of the upper 21 address signals.
STOP#
39
I/O12tp3
Bus Stop#. STOP# indicates the current target is requesting the
master to stop the current PCI bus transaction.
IRDY#
41
I/O12tp3
Initiator Ready. IRDY# indicates the initiating agent ability to
complete the current data phase of the PCI bus transaction.
TRDY#
42
I/O12tp3
Target Ready. TRDY# indicates the target agent’s ability to
complete the current data phase of the PCI bus transaction.
DEVSEL#
43
I/O12tp3
Device Select. W83628F drives DEVSEL# to indicate that it is
the target of the current PCI bus transaction. W83628F uses
subtractive decoding and the NOGO protocol to claim PCI
transactions.
SERR#
45
OD12
System Error. SERR# can be pulsed active by any PCI agent
that detects a system error condition.
PAR
49
I/O12tp3
Parity Signal. W83628F generates even parity across AD[31:0]
and C/BE[3:0]#.
PCIRST#
71
INt
PCI Reset. W83628F receives PCIRST# as a reset from the PCI
Bus.
1.1.2 Control Logic and Handshaking Signals
SYMBOL
PIN
HS[2:0]
I/O
FUNCTION
I/O12
Handshaking Signals. HS[2:0] connected to W83629D for PCI
to ISA SET handshaking signals.
112114
HS1 is handshaking Signal 1, this pin weak pulled-down
during PCIRST# is asserted, and apply a pull-up
resistor(4.7Kohm) to this pin disables ISA bridge
subtraction decoder.
ISOLATE#
72
INt
Isolation Control Input. Isolate# is an active low signal by user
programming to control the W83628F all output signals to
Isolation and Tri-state.
NOGO
76
INt
NOGO, This signal indicates which master initiated the current
transaction and also indicates whether or not the current bus
cycle is targeted for the ISA bus. This signal is a point-to-point
connection between PCI HOST Bridge and W83628F.
-7-
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
1.1.3 ISA Interface Signals
SYMBOL
PIN
I/O
SA[19:17]
98-96
OUT24t
SA[16:0]
94-83
I/O24t
System Address Bus. These are the bi-directional lower
address lines that define the ISA’s byte granular address space
(up to 1 Mbyte). SA[16:0] are at an unknown state upon
PCIRST#.
I/O24t
System Data. SD[15:0] provide the 16-bit data path for devices
residing on the ISA Bus. The W83628F tri-states SD[15:0] during
PCIRST#.
81-77
SD[15:0]
110107,
104,
FUNCTION
System Address Bus. These are the upper address lines that
define the ISA’s byte granular address space (up to 1 Mbyte).
SA[19:17] are at an unknown state upon PCIRST#.
103,
101,
100,
8-15
AEN
118
OUT24t
IOR#
120
I/O24t
I/O Read. IOR# is the command to an ISA I/O slave device that
the slave may drive data on to the ISA data bus (SD[15:0]).
IOW#
121
I/O24t
I/O Write. IOW# is the command to an ISA I/O slave device that
the slave may latch data from the ISA data bus (SD[15:0]).
IOCHRDY
116
I/O24t
I/O Channel Ready. Resources on the ISA Bus negate
IOCHRDY to indicate that additional time (wait states) is required
to complete the cycle.
SYSCLK
99
OUT24t
ISA System Clock. SYSCLK is the reference clock for the ISA
bus. The SYSCLK is generated by dividing PCICLK by 3 or 4.
RSTDRV
74
OUT24t
Reset Drive. W83628F asserts RSTDRV to reset devices that
reside on the ISA Bus. The W83628F asserts this signal while
the PCIRST# is asserted.
IOCS16#
124
INt
16-bit I/O Chip Select. This signal is driven by I/O devices on
the ISA Bus to indicate that they support 16-bit I/O bus cycles.
SBHE#
18
I/O24t
System Byte High Enable. SBHE# asserted indicates that a
byte is being transferred on the upper byte (SD[15:8]) of the data
bus. SBHE# is at an unknown state upon PCIRST#.
IOCHK#
105
INt
I/O Channel Check. IOCHK# can be driven by any resource on
the ISA bus during on detection of an error.
Address Enable. AEN is asserted during DMA cycles. This
signal is also driven high during W83628F initiated refresh
cycles. AEN is driven low upon PCIRST#.
-8-
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
1.1.3 ISA Interface, continued
SYMBOL
MEMR#
PIN
6
I/O
I/O24t
MEMW#
7
I/O24t
MASTER#
17
INt
LA[23:17]
5-2
127125
I/O24t
ROMCS#
73
I/O12
REFRESH#
75
I/O24t
ZEROWS#
106
INt
SMEMR#
117
OUT24t
SMEMW#
119
OUT24t
BALE
122
OUT24t
MEMCS16#
123
OD24
1.1.4 Power Signals
SYMBOL
PIN
VCC
1, 82, 102, 115
3VCC
27, 46, 64
FUNCTION
Memory Read. MEMR# asserted indicates the current ISA bus
cycle is a memory read.
Memory Write. MEMW# asserted indicates the current ISA bus
cycle is a memory write.
MASTER#. This signal is used with a DREQ line by an ISA
master to gain control of the ISA Bus.
Unlatched Address. The LA[23:17] address lines are bidirectional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs
when the W83628F owns the ISA Bus.
ROMCS# ,this pin weak pulled-down during PCIRST is
asserted, and apply a pull-up resistor (4.7 Kohm) to this pin
enable positive decoder of BIOS address range (depend on
Configure register 70 , bit 3,2). When BIOS assress range is
enabled , the PIN is BIOS ROM CS# output.
Refresh. REFRESH# asserted indicates that a refresh cycle is in
progress, or that an ISA master is requesting W83628F to
generate a refresh cycle. Upon PCIRST#, this signal is tri-stated.
Zero Wait States. An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate
that the current cycle can be executed as an ISA zero wait state
cycle. ZEROWS# has no effect during 16-bit I/O cycles.
Standard Memory Read. SMEMR# asserted indicates the
current ISA bus cycle is a memory read cycle to an address
below 1 Mbyte.
Standard Memory Write. SMEMW# asserted indicates the
current ISA bus cycle is a memory write cycle to an address
below 1 Mbyte.
Bus Address Latch Enable. BALE is an active high signal
asserted by the W83628F to indicate that the address (SA[19:0],
LA[23:17]) and SBHE# signal lines are valid.
The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master
cycles. BALE is driven low upon PCIRST#.
Memory Chip Select 16. MEMCS16# asserted indicates that the
memory slave supports 16-bit accesses.
I/O
PWR
PWR
-9-
FUNCTION
5V Supply.
3.3V Supply.
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
GND
16, 38, 50, 65, 95,
111, 128
PWR
- 10 -
Ground.
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
1.2 W83629D PIN DESCRIPTION
1.2.1 Control Logic and Handshaking Signals
SYMBOL
PIN
I/O
FUNCTION
HS[2:0]
17-15
I/O12
Handshaking Signals. HS[2:0] connected to W83628F for PCI
to ISA SET handshaking signals.
NOGO
40
INt
NO GO. This signal indicates which master initiated the current
transaction and also indicates whether or not the current bus
cycle is targeted for the ISA bus. This signal is a point-to-point
connection between PCI HOST Bridge and W83628F.
PCICLK
44
INt
PCI Bus System Clock. PCICLK provides timing for all
transactions on the PCI bus. All other PCI signals are sampled
on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
PCIRST#
47
INt
PCI Reset. W83628F receives PCIRST# as a reset from the PCI
Bus.
PIN
I/O
FUNCTION
ISAREQ#
41
OUT24t
ISA Bus Request. This signal is a point-to-point signal between
W83629D and a PCI HOST arbiter . The W83629D asserts this
signal according to the PC/PCI protocol.
ISAGNT#
42
INt
ISA Bus Grant. This signal is a point-to-point signal between
W83629D and a PCI HOST Bridge’s secondary bus
PCPCIGNT# signal. W83629D asserts this signal according to
the PC/PCI protocol.
DRQ
35,33
INt
[7:5,3:0]
31,28
DMA Request. The DREQ signal indicates that either a slave
DMA device is requesting DMA services, or an ISA bus master is
requesting use of the ISA bus.
1.2.2 PC/PCI Interface
SYMBOL
26,23
21
DACK
34,32
[7:5,3:0]#
30,27
OUT24t
DMA Acknowledge. The DACK# signal indicates that either a
DMA channel or an ISA bus master has been granted the ISA
bus.
OUT24t
Terminal Count. The W83628F asserts TC to DMA slaves as a
terminal count indicator.
24,22
20
TC
19
- 11 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
1.2.3 IRQ Serializer Interface
SYMBOL
PIN
I/O
SERIRQ
46
I/OD12t
IRQ
2-6
INt
[3:7,9:12,14,
15]
8-13
FUNCTION
Serial Interrupt Requested Signals. This signal is for transfer
IRQ mode between parallel IRQ to serial IRQ.
Parallel Interrupt Requested Input.
1.2.4 Power Signals
SYMBOL
PIN
I/O
FUNCTION
VCC
7, 14, 25
PWR
5V Supply.
3VCC
48
PWR
3.3V Supply.
GND
1, 18, 29, 43
PWR
Ground.
PIN
I/O
1.2.5 NC Pins
SYMBOL
NC
36, 37,38, 39, 45
FUNCTION
No Connection.
- 12 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2. PCI CONFIGURATION REGISTERS
2.1 VID-VENDOR IDENTIFICATION REGISTER
Address Offset:
00-01h
Default Value:
1050h
Attribute:
Read only
This register is read-only and contains Winbond vendor identification number(1050h).
2.2 DID-DEVICE IDENTIFICATION REGISTER
Address Offset:
02-03h
Default Value:
0628h
Attribute:
Read only
This register is read-only and contains the device identification number(0628h).
2.3 PCICMD-PCI COMMAND REGISTER
Address Offset:
04-05h
Default Value:
0007h
Attribute:
Read/Write
This register provides control over ISA bridge to generate and response to PCI cycles properly. When
a 0 is written to this register, ISA bridge is to be disconnected from PCI bus for all accesses except
configuration accesses.
Bit 15:10
Reserved.
Bit 9
Fast Back to Back. This bit always returns a zero.
Bit 8
SERR# Enable.
Bit 7
=1
Enable.
=0
Disable.
Wait Cycle Control(Not supported).
Hardwired to zero.
Bit 6
Parity Error Response(Not supported).
Hardwired to zero.
Bit 5
VGA Palette Snoop Enable(Not supported).
Hardwired to zero.
Bit 4
Memory Write and Invalidate Enable(Not supported).
Hardwired to zero.
- 13 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Bit 3
Parity Error Response(Not supported).
Hardwired to zero.
Bit 2
Bus Master Enable.
Hardwired to one. The ISA bridge Bus Masters are always supported to generate a
PCI Bus master cycle.
Bit 1
Memory Space Enable.
Hardwired to one. The ISA bridge Memory space is always enabled.
Bit 0
I/O Space Enable.
Hardwired to one. The ISA bridge I/O space is always enabled.
2.4 PCISTS-PCI STATUS REGISTER
Address Offset:
06-07h
Default Value:
0200h
Attribute:
Read/Write
This register shows status information for PCI bus related events.
Bit 15
Detected Parity Error.
Hardwired to zero. The ISA bridge does not check bus parity.
Bit 14
Signaled System Error.
This bit is set when ISA bridge asserts SERR# on PCI bus.
Bit 13
Received Master Abort Status.
This bit is set when the ISA bridge is target aborted as a master on the PCI bus.
Software sets this bit to 0 by writing a 1 to it.
Bit 12
Received Target Abort Status.
This bit is set when the ISA bridge target aborts a PCI transaction as a target.
Software sets this bit to 0 by writing a 1 to it.
Bit 11
Signaled Target Abort Status.
This bit is set when the ISA bridge signals a target abort for a PCI transaction.
Software sets this bit to 0 by writing a 1 to it.
Bit 10:9
DEVSEL# Timing. This 2 bits always return a 01b(medium decode).
Bit 8
Data Parity Detected(Not supported).
Hardwired to zero.
Bit 7
Fast Back-to-Back(Not supported).
Hardwired to zero.
- 14 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Bit 6
66 MHz/ 33 MHz(Only support 33 MHz).
Hardwired to zero.
Bit 5
User Defineable Features(Not supported).
Hardwired to zero.
Bit 4:0
Reserved.
Reserved and will returns zero when reading this register.
2.5 REVID-REVISION IDENTIFICATION REGISTER
Address Offset:
08h
Default Value:
See lastest stepping information
Attribute:
Read Only
This register shows status information for PCI bus related events.
Bit 7:0
Revision Identification Number.
2.6 CCODE-CALSS CODE REGISTER
Address Offset:
09-0Bh
Default Value:
060100h
Attribute:
Read Only
The class code register is a read-only register and used to identify the ISA bridge.
Bit 23:16
Base Class Code.
06h = Bus Bridge
Bit 15:8
Sub-Class Code.
01h = PCI to ISA Bridge
Bit 7:0
Programming Interface.
00h
2.7 HEADT-HEAD TYPE REGISTER
Address Offset:
0Eh
Default Value:
00h
Attribute:
Read Only
The register is a read-only register and used to indicate that the ISA bridge configuration space
adheres to PCI local bus specification. It also indicates that ISA bridge is not a multifunction device.
Bit 7
Multifunction Indicator.
0 = Not a multifunction device.
Bit 6:0
Layout Code.
00h = PCI layout type.
- 15 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2.8 IO_RCVR-IO RECOVERY REGISTER
Address Offset:
40h
Default Value:
4Dh
Attribute:
Read/Write
Bit 7
SYSCLK Divider.
0 = SYSCLK is equal to PCICLK divided by 4.
1 = SYSCLK is equal to PCICLK divided by 3.
Bit 6
8-bit I/O Recovery Enable
0 = Disable bits 5:3 setting and uses 3.5 SYSCLKs for 8 bit I/O recovery time.
1 = Enable bits 5:3 setting.
Bit 5:3
8-bit I/O RecoveryTimes.
When bit 6=1 ,this 3-bit field defines the additional number of SYSCLKs added
to standard 3.5 SYSCLK recovery time for 8 bit I/O
000 =0 SYSCLK
001 =1 SYSCLK
010 =2 SYSCLKs
011 =3 SYSCLKs
100 =4 SYSCLKs
101 =5 SYSCLKs
110 =6 SYSCLKs
111 = 7 SYSCLKs
Bit 2
16-bit I/O Recovery Enable.
= 0 Ignore bits 1:0 setting and uses 3.5 SYSCLKs for 16-bit I/O recovery time.
= 1 The 16-bit I/O recovery time is decided by bits 1:0.
Bit 1:0
16-bit I/O Recovery Times.
When bit 2=1 ,this 2-bit field defines the additional number of SYSCLKs added
to standard 3.5 SYSCLK recovery time for 16 bit I/O
= 01
1 SYSCLK
= 10
2 SYSCLKs
= 11
3 SYSCLKs
= 00
4 SYSCLKs
2.9 WISA_STS-ISA BRIDGE ERROR STATUS REGISTER
Address Offset:
42h
Default Value:
00h
- 16 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Attribute:
Read/Write
Bit 7:3
Reserved.
Bit 2
IOCHK# Pin State.
This bit reflects the inverse state of IOCHK# pin on the ISA bus.
Bit 1
Reserved.
Bit 0
Byte Lane Error.
This bit is set if the ISA bridge detects an illegal byte lane combination for a
PCI I/O cycles.
2.10 WISA_FADC-ISA BRIDGE FAST DECODERS CONTROL REGISTER
Address Offset:
50h
Default Value:
00h
Attribute:
Read/Write
Bit 7
Enable/Disable Fast I/O Address Decoder # 7.
Bit 6
Enable/Disable Fast I/O Address Decoder # 6.
Bit 5
Enable/Disable Fast I/O Address Decoder # 5.
Bit 4
Enable/Disable Fast I/O Address Decoder # 4.
Bit 3
Enable/Disable Fast I/O Address Decoder # 3.
Bit 2
Enable/Disable Fast I/O Address Decoder # 2.
Bit 1
Enable/Disable Fast I/O Address Decoder # 1.
Bit 0
Enable/Disable Fast I/O Address Decoder # 0.
2.11 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 0 MASK CONTROL
REGISTER
Address Offset:
58h
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 0, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 0.
- 17 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2.12 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL
REGISTER
Address Offset:
59h
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 1, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 1.
2.13 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 2 MASK CONTROL
REGISTER
Address Offset:
5Ah
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 2, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 2.
2.14 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 3 MASK CONTROL
REGISTER
Address Offset:
5Bh
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 3, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 3.
2.15 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 4 MASK CONTROL
REGISTER
Address Offset:
5Ch
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 4, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 4.
- 18 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2.16 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 5 MASK CONTROL
REGISTER
Address Offset:
5Dh
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 5, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 5.
2.17 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 6 MASK CONTROL
REGISTER
Address Offset:
5Eh
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 6, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 6.
2.18 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 7 MASK CONTROL
REGISTER
Address Offset:
5Fh
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 7, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 7.
2.19 WISA_FADCB0-ISA BRIDGE FAST DECODERS # 0 BASE ADDRESS
REGISTER
Address Offset:
60-61h**
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 0.A
**Note: 60h is lower byte and 61h is upper byte.
- 19 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2.20 WISA_FADCB1-ISA BRIDGE FAST DECODERS # 1 BASE ADDRESS
REGISTER
Address Offset:
62-63h
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 1.
2.21 WISA_FADCB2-ISA BRIDGE FAST DECODERS # 2 BASE ADDRESS
REGISTER
Address Offset:
64-65h
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 2.
2.22 WISA_FADCB3-ISA BRIDGE FAST DECODERS # 3 BASE ADDRESS
REGISTER
Address Offset:
66-67h
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 3.
2.23 WISA_FADCB4-ISA BRIDGE FAST DECODERS # 4 BASE ADDRESS
REGISTER
Address Offset:
68-69h
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 4.
2.24 WISA_FADCB5-ISA BRIDGE FAST DECODERS # 5 BASE ADDRESS
REGISTER
Address Offset:
6A-6Bh
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 5.
- 20 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2.25 WISA_FADCB6-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS
REGISTER
Address Offset:
6C-6Dh
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 6.
2.26 WISA_FADCB7-ISA BRIDGE FAST DECODERS # 6 BASE ADDRESS
REGISTER
Address Offset:
6E-6Fh
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 0.
2.27 WISA_CTRLREG1-ISA BRIDGE CONTROL REGISTER 1
Address Offset:
70h
Default Value:
000001ssb
Attribute:
Read/Write
Power-on setting bits
bit 1:0 are power-on set by ROMCS# and HS1.
Bit 7-6
Reserved.
Bit 5-4
= 00 Send AD Bus with no STEP
= 01 Send AD Bus with 2 STEP
= 10 Send AD Bus with 4 STEP
= 11 Reverse
Bit 3-2
= 00 1MB BIOS ROM positive decode.
= 01 2MB BIOS ROM positive decode.
= 10 4MB BIOS ROM positive decode.
= 11 8MB BIOS ROM positive decode.
Bit 1
=0 Disable High-Address BIOS ROM decoder.
=1 Enable High-Address BIOS ROM decoder.
This bit can be set/reset by ROMCS# power-on setting during PCIRST# assert.
Bit 0
=0 Normal mode.
=1 Disable ISA Bridge subtraction decoder.
This bit can be set/reset by HS1 power-on setting during PCIRST# assert.
- 21 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2.28 WISA_CTRLREG2-ISA BRIDGE CONTROL REGISTER 2
Address Offset:
71h
Default Value:
00h
Attribute:
Read/Write
Bit7
=0 Enable IRQ11.
=1 Disable IRQ11.
Bit 6
=0 Enable IRQ10.
=1 Disable IRQ10.
Bit 5
=0 Enable IRQ9.
=1 Disable IRQ9.
Bit 4
=0 Enable IRQ7.
=1 Disable IRQ7.
Bit 3
=0 Enable IRQ6.
=1 Disable IRQ6.
Bit 2
=0 Enable IRQ5.
=1 Disable IRQ5.
Bit 1
=0 Enable IRQ4.
=1 Disable IRQ4.
Bit 0
=0 Enable IRQ3.
=1 Disable IRQ3.
2.29 WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3
Address Offset:
72h
Default Value:
00h
Attribute:
Read/Write
Bit 7-3
Reserved.
Bit 2
=0 Enable IRQ15.
=1 Disable IRQ15.
Bit 1
=0 Enable IRQ14.
=1 Disable IRQ14.
Bit 0
=0 Enable IRQ12.
=1 Disable IRQ12.
- 22 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
2.30 WISA_CTRLREG4-ISA BRIDGE CONTROL REGISTER 4
Address Offset:
73h
Default Value:
00h
Attribute:
Read/Write
Bit7
=0 Enable DRQ 7.
=1 Disable DRQ 7.
Bit 6
=0 Enable DRQ6.
=1 Disable DRQ6.
Bit 5
=0 Enable DRQ5.
=1 Disable DRQ5.
Bit 4
Reserved.
Bit 3
=0 Enable DRQ 3.
=1 Disable DRQ 3.
Bit 2
=0 Enable DRQ 2.
=1 Disable DRQ 2.
Bit 1
=0 Enable DRQ 1.
=1 Disable DRQ 1.
Bit 0
=0 Enable DRQ 0.
=1 Disable DRQ 0.
2.31 WISA_TSTREG-ISA BRIDGE TEST REGISTER
Address Offset:
80h
Default Value:
04h
Attribute:
Read/Write
Bit 7-5
Reserved and should not write data to this register.
Bit 4
=0 80h port decoding on subtrastive cycles of LPC I/F.
=1 80h port decoding on positive cycles of LPC I/F.
This Bit must be set 1when LPC I/F is only decoding on positive cycles,but
when the bridge is used in PIIX4 for test set the bit to 0 .
Bit 3
Bit 2-0
Reserved and should not write data to this register.
000
- 0.8 nS.
001
- 0.6 nS.
For Winbond Internal Reference only.
- 23 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
010
- 0.4 nS.
011
- 0.2 nS.
100
0
nS.
101
+0.2 nS.
110
+0.4 nS.
111
+0.6 nS.
- 24 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
3. PACKAGE DIMENSIONS 1 FOR W83628F (128-PIN PQFP)
HE
Min
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
0
65
102
64
103
D
HD
39
128
1
e
38
b
c
A
A1
y
Nom
Dimension in inch
Max
Min
Nom Max
0.25
0.35
0.45
0.010
0.014
2.57
2.72
2.87
0.101
0.107
0.113
0.10
0.20
0.30
0.004
0.008
0.012
0.018
0.10
0.15
0.20
0.004
0.006
0.008
13.90
14.00
14.10
0.547
0.551
0.555
19.90
20.00
20.10
0.783
0.787
0.791
0.50
0.020
17.00
17.20
17.40
0.669
0.677
0.685
23.00
23.20
23.40
0.905
0.913
0.921
0.65
0.80
0.95
0.025
0.031
0.037
1.60
0.063
0.08
0
7
0.003
0
7
Note:
A2
See Detail F
Seating Plane
Dimension in mm
Symbol
E
L
L1
- 25 -
Detail F
1.Dimension D & E do not include interlead
flash.
2.Dimension b does not include dambar
protrusion/intrusion .
3.Controlling dimension : Millimeter
4.General appearance spec. should be based
on final visual inspection spec.
5. PCB layout please use the "mm".
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
4. PACKAGE DIMENSIONS 2 FOR W83629D (48-PIN LQFP)
HD
D
25
36
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
24
37
E
48
HE
13
1
e
b
12
0
Dimension in inch
Dimension in mm
Min.
Min.
Nom.
Max.
---
---
1.60
0.05
---
0.15
1.35
1.40
1.45
0.17
0.20
0.27
0.09
---
0.20
Nom.
Max.
7.00
7.00
0.50
9.00
9.00
0.45
0.60
0.75
1.00
---
0.08
---
0
3.5
7
Notes:
c
A2
Seating Plane
See Detail F
A1
y
A
L
L1
Detail F
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks
of products and companies mentioned in this data sheet belong to their original owners
- 26 -
Publication Release Date: Jan 1999
Revision 0.32
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
5. REVISION NOTICES.
1998.11.16
Add High-Address BIOS ROM decoder function(CS#/HS3). (Page 7 & Page 20)
1998.11.19
Change decode range to #FFF00000~#FFFFFFFF & #000E0000~#000FFFFF.
1999.01.17
Supports 3 fully ISA Compatible Slots without Buffering
Rename HS3. it is renamed to ROMCS# in W83628F,and NC in W83629D.
1999.04.21
when
Indicate the Bit 4 of offset address 80h is used to enable 80h port decoding
only positive decoding switched of LPC I/F.
- 27 -
Publication Release Date: Jan 1999
Revision 0.32