ACS139MS Radiation Hardened Dual 2-to-4 Line Decoder/Demultiplexer November 1997 Features Description • QML Qualified Per MIL-PRF-38535 Requirements The Radiation Hardened ACS139MS contains two independent binary to one-of-four decoders, each with a single active low enable input. Data on the select inputs cause one of the four normally high outputs to go low. • 1.25Micron Radiation Hardened SOS CMOS • Radiation Environment - Latch-up Free Under any Conditions - Total Dose . . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si) - SEU Immunity . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day - SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm2) If the enable input is high, all four outputs remain high. During demultiplexer operation the enable input acts as the data input. The enable input also functions as a chip select when the devices are cascaded. • Input Logic Levels . . .VIL = (0.3)(VCC), VIH = (0.7)(VCC) The ACS139MS is fabricated on a CMOS Silicon on Sapphire (SOS) process, which provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. These devices offer significant power reduction and faster performance when compared to ALSTTL types. • Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8mA • Quiescent Supply Current. . . . . . . . . . . . . . . . . . .400µA • Propagation Delay - Enable to Output . . . . . . . . . . . . . . . . . . . . . . . . . 13ns - Address to Output . . . . . . . . . . . . . . . . . . . . . . . . 15ns Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Applications Detailed Electrical Specifications for the ACS139 are contained in SMD 5962-97639. A “hot-link” is provided on our homepage with instructions for downloading. http://www.semi.Intersil.com/data/sm/index.htm • Memory Decoding • Data Routing • Code conversion Ordering Information SMD PART NUMBER TEMP. RANGE (oC) INTERSIL PART NUMBER 5962F9763901VEC ACS139DMSR-02 N/A ACS139D/Sample-02 PACKAGE CASE OUTLINE -55 to 125 16 Ld SBDIP CDIP2-T16 25 16 Ld SBDIP CDIP2-T16 5962F9763901VXC ACS139KMSR-02 -55 to 125 16 Ld Flatpack CDFP4-F16 N/A ACS139K/Sample-02 25 16 Ld Flatpack CDFP4-F16 N/A ACS139HMSR-02 25 Die N/A Pinouts ACS139 (SBDIP) TOP VIEW 1E 1 ACS139 (FLATPACK) TOP VIEW 16 VCC 1E 1 16 VCC 1A0 2 15 2E 1A0 2 15 2E 1A1 3 14 2A0 1A1 3 14 2A0 1Y0 4 13 2A1 1Y0 4 13 2A1 1Y1 5 12 2Y0 1Y1 5 12 2Y0 11 2Y1 1Y2 6 11 2Y1 1Y3 7 10 2Y2 GND 8 9 2Y3 1Y2 6 1Y3 7 10 2Y2 GND 8 9 2Y3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 4431 ACS139MS Die Characteristics SUBSTRATE POTENTIAL: DIE DIMENSIONS: Unbiased Insulator Size: 2390µm x 2390µm (94 mils x 94 mils) Thickness: 525µm ±25µm (20.6 mils ±1 mil) Bond Pad: 110µm x 110µm (4.3 mils x 4.3 mils) BACKSIDE FINISH: Sapphire METALLIZATION: PASSIVATION Type: Al Metal 1 Thickness: 0.7µm ±0.1µm Metal 2 Thickness: 1.0µm ±0.1µm Type: Phosphorous Silicon Glass (PSG) Thickness: 1.30µm ±0.15µm SUBSTRATE: SPECIAL INSTRUCTIONS: Silicon on Sapphire (SOS) Bond VCC First ADDITIONAL INFORMATION: Worst Case Density: <2.0 x 105 A/cm2 Transistor Count: 190 Metallization Mask Layout ACS139MS. 1A0 1E VCC 2E 1A1 2A0 1Y0 2A1 1Y1 2Y0 1Y2 2Y1 1Y3 GND 2Y3 2Y2 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 2