ISL6144 ® Data Sheet February 2004 FN9131 High Voltage ORing MOSFET Controller Features The ISL6144 ORing MOSFET Controller and a suitably sized N-channel power MOSFET(s) increases power distribution efficiency and availability when replacing a power ORing diode in high current applications. • Wide Supply Voltage Range +10V to +75V In a multiple supply, fault tolerant, redundant power distribution system, paralleled power supplies contribute equally to the load current through various power sharing schemes. Regardless of the scheme, a common design practice is to include discrete ORing power diodes to protect against reverse current flow should one of the power supplies develop a catastrophic output short to ground. In addition, reverse current can occur if the current sharing scheme fails and an individual power supply voltage falls significantly below the others. • Internal Charge Pump allows the use of N-channel MOSFET • Transient Rating to +100V • Reverse Current Fault Isolation Although the discrete ORing diode solution has been used for some time and is inexpensive to implement, it has some drawbacks. The primary downside is the increased power dissipation loss in the ORing diodes as power requirements for systems increase. Another disadvantage when using an ORing diode would be failure to detect a shorted or open ORing diode, jeopardizing power system reliability. An open diode reduces the system to single point of failure while a diode short might pose a hazard to technical personnel servicing the system while unaware of this failure. • HS Comparator Provides Very Fast <0.3µs Response Time to Dead Shorts on Sourcing Supply. HS Comparator also has resistor-adjustable trip level • HR Amplifier allows Quiet, <100µs MOSFET Turn Off for Power Supply Slow Shut Down • Open Drain, Active Low Fault Output with 120µs Delay • Provided in Packages Compliant to UL60950 (UL1950) Creepage Requirements • QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile • Lead-Free Available as an Option Applications • ORing MOSFET Control in Power Distribution Systems The ISL6144 can be used in 10V to 75V systems and has an internal charge pump to provide a floating gate drive for the N-channel ORing MOSFET. The High Speed (HS) Comparator protects the common bus from individual power supply shorts by turning off the shorted feed’s ORing MOSFET in less than 300ns and ensuring low reverse current. An external resistor-programmable detection level for the HS Comparator allows users to set the N-channel MOSFET “VOUT - VIN” trip point to adjust control sensitivity to power supply noise. The Hysteretic Regulating (HR) Amplifier provides a slow turn off of the ORing MOSFET. This turn off is achieved in less than 100µs when one of the sourcing power supplies is shutdown slowly for system diagnostics, ensuring zero reverse current. This slow turn off mechanism also reacts to output voltage droop, degradation, or power down. An open drain FAULT pin will indicate that a fault has occurred. The fault detection circuitry covers different types of failures; including dead short in the sourcing supply, a short of any two ORing MOSFET terminals, or a blown fuse in the power distribution path. 1 • N+1 Redundant Distributed Power Systems • File and Network Servers (12V and 48V) • Telecom/Datacom Systems Ordering Information TEMP. RANGE (°C) PACKAGE ISL6144IV -40 to +105 16 Ld TSSOP M16.173 ISL6144IVZA (See Note) 40 to +105 16 Ld TSSOP (Lead-Free) M16.173 ISL6144IR -40 to +105 20 Ld 5x5 QFN L20.5x5 ISL6144IRZA (See Note) -40 to +105 20 Ld 5x5 QFN L20.5x5 (Lead-Free) PART # PKG. DWG. # NOTE: Intersil Lead-Free products employ special lead-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and lead-free soldering operations. Intersil Lead-Free products are MSL classified at lead-free peak reflow temperatures that meet or exceed the lead-free requirements of IPC/JEDEC J Std-020B. Tape and Reel available. Add “T” suffix for Tape and Reel Packing Option. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6144 Pinouts HVREF 3 14 VSET NC 4 13 NC NC 5 12 NC NC 6 11 NC NC 7 10 NC GND 8 9 NC COMP 20 19 18 17 16 1 15 VOUT 2 14 COMP NC 3 13 VSET NC 4 12 NC NC 5 11 NC VIN HVREF FAULT 6 7 8 9 10 NC 15 NC 2 FAULT VIN NC VOUT NC 16 GND 1 NC GATE GATE ISL6144 (20 LEAD 5x5 QFN) TOP VIEW NC ISL6144 (16 LEAD TSSOP) TOP VIEW Pin Descriptions TSSOP PIN # QFN PIN # SYMBOL 1 19 GATE External FET Gate Drive Allows active control of external N-channel FET gate to perform ORing function. 2 1 VIN Power supply connection Chip bias input. Also provides a sensing node for external FET control. 3 2 HVREF Chip high voltage reference Low side of floating high voltage reference for all of the HV chip circuitry. 8 7 GND Chip ground reference Chip ground reference point. 9 9 FAULT Fault Output Provides an open drain active low output as an indication that a fault has occurred: GATE is OFF (GATE < VIN+0.37V) or other types of faults resulting in VIN-VOUT > 0.41V. 14 13 VSET Low side connection for trip level Resistor connected to COMP provides adjustable “Vd-Vs” trip level along with pin COMP. 15 14 COMP High side connection for HS Comparator trip level Resistor connected to VOUT provides sense point for the adjustable Vd-Vs trip level along with pin VSET. 16 15 VOUT Chip bias and Load connection Provides the second sensing node for external FET control and chip output bias. 4-7, 10-13 3-6, 8, 10-12, 16-18, 20 NC FUNCTION No Connection 2 DESCRIPTION ISL6144 + LOAD “+48V” General Application Circuit - DC/DC 1 AC/DC 1 GATE VOUT ISL6144 COMP HVREF 5V GATE VOUT ISL6144 HVREF COMP VIN VIN 5V FAULT FAULT VSET GND VSET AC/DC N+1 +12VDC BUS +48VDC BUS AC POWER LOAD “+12V” GND DC/DC N+1 GATE VOUT ISL6144 COMP HVREF VIN 5V FAULT VSET GND GATE VOUT ISL6144 COMP HVREF VIN 5V FAULT VSET GND NOTES: 1. AC/DC 1 through (N+1) are multistage AC/DC converters which include AC/DC rectification stage and a DC/DC Converter with a + 48VDC output (also might include a Power Factor Correction stage). 2. DC/DC Converter 1 through (N+1) are DC/DC converters to provide additional Intermediate Bus 3. Load “+12V” and Load “+48V” might include other DC/DC converter stages to provide lower voltages such as ±15V, ±5V, +3.3V, +2.5V, +1.8V etc. 4. Fuse location might vary depending on power system architecture. FIGURE 1. ISL6144 GENERAL APPLICATION CIRCUIT IN A DISTRIBUTED POWER SYSTEM 3 ISL6144 Simplified Block Diagram D2* Source 2 F2** 10 - 75V C1 VIN GATE HVREF VOUT R1 ISL6144 FAULT C2 * D1,D2 Parasitic diodes **F1,F2 Fuses could also be placed on the input side before the VIN pin. This placement depends on power system architecture. COMP GND R2 VSET D1* F1** Source 1 10 - 75V VIN GATE LOAD VOUT Gate Logic & Charge Pump C1 FAULT DETECTION 5.5V 20mV + Level Shift R1 High Voltage Pass and Clamping 5.3V 0.1mA REG AMPLIFIER 2A* 5mA COMP + R2 HS COMP HVREF VSET Delay 100us UV COMP FAULT + 0.6V BIAS & REF 0.2 mA 1.5mA 1.5mA GND FIGURE 2. SIMPLIFIED BLOCK DIAGRAM 4 C2 ISL6144 Absolute Maximum Ratings TA = 25oC Thermal Information VIN, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +100V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+12V HVREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN- 5V COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT VSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT-5V FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLASS 2 Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W) TSSOP Package (Note 1) . . . . . . . . . . 90 N/A QFN Package (Notes 3, 4). . . . . . . . . . 35 5 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Operating Conditions Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . +10 to +75V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40°C to +105°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for details.) 2. All voltages are relative to GND, unless otherwise specified. 3. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside. 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “die attach” features. (See Tech Brief, #TB379 for details.) VIN = 48V, TA = -40oC to 105oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS BIAS “VIN” POR Rising PORL2H VIN Rising to VGATE > VIN+7.5V 10 - - V 12V Bias Current I12V VIN = 12V, VGATE = VIN + VGQP - 3.5 - mA 48V Bias Current I48V VIN = 48V, VGATE = VIN + VGQP - 4.5 - mA 75V Bias Current I75V VIN = 75V, VGATE = VIN + VGQP - 5 - mA GATE Charge Pump Voltage VGQP VIN = 12V to 75V VIN+9 VIN+10.5 VIN+12 V Gate Low Voltage Level VGL VIN - VOUT < 0V -0.3 VIN VIN+0.5 V Low Pull Down Current IPDL * Cgs = 39nF, IPDL = Cgs*dVgs/Ttofs - 5 - mA High Pull Down Current IPDH * Cgs = 39nF, IPDH = Cgs*dVgs/Ttoff - 2 - A Slow Turn-off Time Ttoffs Cgs = 39nF - - 100 µs Fast Turn-off Time Ttoff Turn-off from VGATE = VIN+VGQP to VIN+1V with Cgs = 39nF (includes HS Comparator delay time) - 250 300 ns Start up “Turn-On” Time TON Turn-on from VGATE = VIN to VIN+ 7.5V into 39nF - 1 - ms GATE Turn-On Current ION VIN = 10V to 75V - 1 - mA ISL6144 controls voltage across FET Vds to VFWD_HR during static forward operation at loads resulting in I*rDS(ON)< VFWD_HR 10 20 30 mV Externally programmable threshold for noise sensitivity (System Dependant), typical 0.05 to 0.3V 0 0.05 5.3 V * CONTROL AND REGULATION I/O HR Amplifier Forward Voltage Regulation VFWD_HR * HS COMP Externally Programmable Threshold VTH(HS) HS Comparator Offset Voltage VOS(HS) -40 0 25 mV ICOMP - 1.1 - µA COMP Input Current (bias current) 5 ISL6144 VIN = 48V, TA = -40oC to 105oC, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS HVREF Voltage (VIN-HVREF) HVREF(VZ) VIN = 10V to 75V - 5.5 - V VSET Voltage (VOUT-VSET) VREF(VSET) VIN = 10V to 75V - 5.3 - V VIN - VOUT < 0V, VGATE = VGL - - 0.5 V Fault Low Output Voltage VFLT_L Fault Sink Current IFLT_SINK FAULT = VFLT_L, VIN < VOUT, VGATE = VGL 4 - - mA Fault Leakage Current IFLT_LEAK FAULT = ”VFLT_H”, VIN >VOUT, VGATE = VIN + VGQP - - 10 µA GATE = VGL to FAULT = VFLT_L - 120 - µs Fault Delay -Low to High TFLT NOTES: 5. The * denotes parameters which are guaranteed by design and not production tested. 6. Specifications to +105°C and -40°C are guaranteed by design and not production tested. Functional Pin Description GATE This is the Gate Drive output of the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn on time is typically 1ms. VIN Input bias pin connected to the sourcing supply side (ORing MOSFET Source). Also serves as the sense pin to determine the sourcing supply voltage. The ORing MOSFET will be turned off when VIN becomes lower than VOUT by a value more than the externally set threshold. VOUT Connected to the Load side (ORing MOSFET Drain). This is the VOUT sense pin connected to the load. This is the common connection point for multiple paralleled supplies. VOUT is compared to VIN to determine when the ORing FET has to be turned off. HVREF Low side of the internal IC High Voltage Reference used by internal circuitry, also available as an external pin for additional external capacitor connection. COMP This is the high side connection for the HS Comparator trip level setting (VTH(HS)). A resistor R1 connected between COMP and VOUT along with resistor R2 provides adjustable VOUT-VIN trip level (0 to 5V). This provides flexibility to externally set the desired level depending on particular system requirement. VSET Low side connection for the HS Comparator trip level setting A second resistor R2 connected between VSET and COMP provides adjustable “VIN - VOUT” level along with R1. 6 FAULT Open-Drain pull-down FAULT Output with internal on chip filtering (TFLT). The ISL6144 fault detection circuitry will pull down this pin to GND as soon as it detects a fault. Different types of faults and their detection mechanisms are discussed in more detail in the Block Diagram Description section. GND IC ground reference Detailed Description The ISL6144 and a suitably sized N-Channel power MOSFET(s) increases power distribution efficiency and availability when replacing a power ORing diode in high current applications. Refer to the Application Consideration section for power saving when using ISL6144 with an N-channel ORing MOSFET compared to a typical ORing diode. Functional Block Description REG. AMPLIFIER - Slow (Quiet) Turn Off A Hysteretic Regulating (HR) Amplifier is used for a Quiet/ Slow turn off mechanism. This slow turn off is initiated when the sourcing power supply is turned off slowly for system diagnostics. Under normal operating conditions as VOUT pulls up to 20mV below VIN (VIN-20mV > VOUT), the HR Amplifier regulates the gate voltage to keep the 20mV (VFWD_HR) forward voltage drop across the ORing MOSFET (Vs-Vd). This will continue until the load current exceeds the MOSFET ability to deliver the current with Vsd of 20mV. In this case Gate will be charged to the full charge pump voltage (VGQP) to fully enhance the MOSFET. At this point the MOSFET will be fully enhanced and behave as a constant resistor valued at the rDS(ON). Once VIN starts to drop below VOUT, regulation cannot be maintained and the output of the HR Amp is pulled high and the gate is pulled down to VIN slowly in less than a 100µs. As a result, the ORing FET is turned off, avoiding reverse current as well as voltage and current stresses on supply components. ISL6144 The slow turn off is achieved in two stages. The first stage starts with a slow turn off action and lasts for up to 20µs. The gate pull down current for the first stage is 2mA. The second slow turn off stage completes the gate turn off with a 10mA pull down current. The 20µs delay filters out any false trip off due to noise or glitches that might be present on the supply line. The fault can be detected and isolated by using the ISL6144 and an N-channel ORing MOSFET. VIN is compared to VCOMP, and whenever: V IN < V COMP ; where V COMP = V OUT – V TH ( HS ); (EQ. 2) VTH(HS) is defined below The gate turn on and gate turn off drivers have a 50kHz filter to reduce the variation in FET forward voltage drop (and FET gate voltage) due to normal SMPS system switching noises (typically higher than 50kHz). These filters do not affect the total turn on or slow turn off times. Special system design precautions must be taken to insure that no AC mains related low frequency noise will be present at the input or output of ISL6144. Filters and multiple power conversion stages, which are part of any distributed dc power system, normally filter out all such noise. HS Comparator - Fast Turn Off There is a High Speed (HS) Comparator used for fast turnoff of the ORing MOSFET to protect the common bus against hard short faults at a sourcing power supply output (refer to Figure 3). During normal operation the gate of the ORing MOSFET is charge pumped to a voltage that depends on whether it is in the 20mV regulation mode or fully enhanced. In this case: V OUT = V IN – I OUT • r DS(ON ) (EQ. 1) If a dead short fault occurs in the sourcing supply, it causes VIN to drop very quickly while VOUT is not affected as more than one supply are paralleled. In the absence of the ISL6144 functionality, a very high reverse current will flow from Output to the Input supply pulling down the common DC Bus, resulting in an overall “catastrophic” system failure. FROM SOURCING SUPPLY VIN TO SHARED LOAD GATE VOUT VIN 2A* VTH(HS) HV PASS & CLAMP + HS DRIVER COMP COMP R1 C2 R2 5.3V VSET BIAS R1 + R2 = 50kΩ The fast turn off mechanism will be activated and the MOSFET(s) will be turned off very quickly. The speed of this turn off depends on the amount of equivalent gate loading capacitance. For an equivalent Cgs = 39nF. The gate turn off time is <300ns and gate pull down current is 2A. The level of VTH(HS) (HS Comparator trip level) is adjustable by means of external resistors R1 and R2 to a value theoretically ranging from 0-5.3V. Typical values are 0.05V to 0.3V. This is done in order to avoid false turn off due to noise or minor glitches present in the DC switching power supply. The threshold voltage is calculated as: R1 V TH ( HS ) = --------------------------- V REF ( VSET ) ( R1 + R2 ) (EQ. 3) Where VREF(VSET) is an internal zener reference (5.3V typical) between VOUT and VSET pins. R1 and R2 must be chosen such that their sum is about 50kΩ. An external capacitor C2 is needed between VOUT and COMP pins to provide high frequency decoupling. The HS comparator has an internal delay time on the order of 50ns which is part of the <300ns overall turn off time specification (with Cgs=39nF). Gate Logic and Charge Pump The IC has two charge pumps: The first charge pump generates the floating gate drive for the N-channel MOSFET. The second charge pump output current opposes the pull down current of the slow turn off transistor to provide regulation of the GATE voltage. The presence of the charge pump allows the use of an N-channel MOSFET with a floating gate drive. The N-channel MOSFETs normally have lower rDS(ON) (not to mention cost saving) compared to P-Channel MOSFETs, allowing further reduction of conduction losses. BIAS & REF Bias currents for the two internal zener supplies (HVREF and VSET) is provided by this block. This block also provides a 0.6V band-gap reference used in the UV detection circuit. Undervoltage Comparator FIGURE 3. HS COMPARATOR 7 The undervoltage comparator compares HVREF to 0.6V internal reference. Once it falls below this level the UV circuitry pulls and holds down the gate pin as long as the HVREF UV condition is present. Voltage at both VIN and HVREF pins track each other. ISL6144 Application Considerations High Voltage Pass and Clamp A high voltage pass and clamping circuit prevents the high output voltage from damaging the comparators in case of quick drop in VIN. The comparators are running from the 5V supply between HVREF and VIN. These devices are rated for 5V and will be damaged if VOUT is allowed to be present (as the output is powered from other parallel supplies), and does not fall when VIN is falling. For example, if VIN falls to 30V, VOUT remains at 48V and the differential Voltage between the “-” and “+” terminals of the comparator would be 18V, exceeding the rating of the devices and causing permanent damage to the IC. Fault Detection Block The fault detection block has two monitoring circuits (refer to Figure 4): 1. Gate monitoring detects when the GATE < VIN+0.37V 2. VOUT monitoring detects when VIN-0.41V > VOUT ORing MOSFET Selection Using an ORing MOSFET instead of an ORing diode results in increased overall power system efficiency as losses across the ORing elements are reduced. The use of ORing MOSFETs becomes more important at higher current levels, as power loss across the traditionally used ORing diode is very high. The high power dissipation across these diodes requires special thermal design precautions such as heat sinks and forced airflow. For example, in a 48V, 40A (1+1) redundant system with current sharing, using a Schottky diode as the ORing (auctioneering) device (refer to Figure 5), the forward voltage drop is in the 0.4-0.7V range, let us assume it is 0.5V. Power loss across each diode: I OUT P loss ( D1 ) = P loss ( D2 ) = --------------- ⋅ V F = 20A ⋅ 0.5V = 10W 2 These two outputs are ORed, inverted, level shifted, and delayed using an internal filter (TFLT ) Total power loss across the two ORing diodes is 20W. The following failures can be detected by the fault detection circuitry: INPUT BUS 1 36 TO 75 VDC 1. ORing FET off due to dead short in the sourcing supply, leading to VIN < VOUT DC/DC #1 +IN +OUT CIN1 100µF 2. Shorted Terminals of the ORing FET Cd1 220nF Ccs1 1nF +S PC PR -IN 4. Open Gate terminal VOUT (40A) -OUT DC/DC #2 INPUT BUS 2 36 TO 75 VDC Rpb1 10 -S 5. HVREF UV SECONDARY GROUND +OUT2 = 48V +IN +OUT CIN2 100µF Cd2 220nF +S PC SC Ccs2 1nF PR GATE -IN D1 0.5V@ 20A Note 8 Figure 16 SC 3. Blown fuse in the power path of the sourcing supply The FAULT pin is not latched off and the pull down will shut off as soon as the fault is removed and the pin becomes high impedance. Typically, an external pull-up resistor is connected to an external voltage source (for example 5V, 3.3V) to pull the pin high, an LED can be used to indicate the presence of a fault. +OUT1 = 48V Rpb2 10 D2 0.5V@ 20A Note 8 Figure 16 -S -OUT + - PRIMARY GROUND 0.37V +- FAULT VIN FIGURE 5. 1+1 REDUNDANT SYSTEM WITH DIODE ORing + DELAY 120µs 0.41V LEVEL SHIFT + - VOUT If a 5mΩ single MOSFET per feed is used, the Power loss across each MOSFET is: I OUT 2 P loss ( M 1 ) = P loss ( M 2 ) = --------------- ⋅ r DS ( ON ) 2 (EQ. 4) FIGURE 4. FAULT DETECTION BLOCK 2 P loss ( M 1 ) = ( 20A ) ⋅ 5mΩ = 2W Total power loss across the two ORing MOSFETs is 4W. In case of failure of current sharing scheme, or failure of DC/DC #1, the full load will be supplied by DC/DC #2. ORing 8 ISL6144 MOSFET M2 or ORing Diode D2 will be conducting the full load current. Power loss across the ORing devices is: P loss ( D 2 ) = I OUT ⋅ V F = 40A ⋅ 0.5V = 20W 2 (EQ. 5) 2 P loss ( M2 ) = ( I OUT ) ⋅ R dson = ( 40A ) ⋅ 5mΩ = 8W This shows that worst-case failure scenario has to be accounted for when choosing the ORing MOSFET. In this case we need to use two MOSFETs in parallel per feed to reduce overall power dissipation and prevent excessive temperature rise of any single MOSFET. Another alternative would be to choose a MOSFET with lower rDS(ON). The final choice of the N-Channel ORing MOSFET depends on the following aspects: 1. Voltage Rating: The drain-source breakdown voltage VDSS has to be higher than the maximum input voltage including transients and spikes. Also the gate to source voltage rating has to be considered, The ISL6144 maximum Gate charge voltage is 12V, make sure the used MOSFET has a maximum VGS rating >12V. 2. Power Losses: In this application the ORing MOSFET is used as a series pass element, which is normally fully enhanced at high load currents, switching losses are negligible. The major losses are conduction losses, which depend on the value of the on-state resistance of the MOSFET rDS(ON), and the per feed load current. For an N+1 redundant system with perfect current sharing, the per feed MOSFET losses are: I LOAD 2 P loss ( FET ) = ----------------- ⋅ r DS ( ON ) N+1 (EQ. 6) The rDS(ON) value also depends on junction temperature; a curve showing this relationship is usually part of any MOSFET’s data sheet. The increase in the value of the rDS(ON) over temperature has to be taken into account. 3. Current handling capability, steady state and peak, are also two important parameters that must be considered. The limitation on the maximum allowable drain current comes from limitation on the maximum allowable device junction temperature. The thermal board design has to be able to dissipate the resulting heat without exceeding the MOSFET’s allowable junction temperature. Another important consideration when choosing the ORing MOSFET is the forward voltage drop across it, if this drop approaches the 0.41V limit, which is used in the VOUT fault monitoring mechanism then this will result in a permanent fault indication. Normally the voltage drop would be chosen not to exceed a value around 100mV. “ISL6144+ORing FET” vs “ORing Diode” Solution “ISL6144+ORing FET“ solution is more efficient, which will result in simplified PCB and thermal design. It will also eliminate the need for a heat sink for the ORing diode. This will result in cost savings. In addition is the fact that the ISL6144 solution provides a more flexible, reliable and 9 controllable ORing functionality and protecting against system fault scenarios (refer to fault detection block description). On the other hand the most common failures caused by diode ORing include open circuit and short circuit failures. If one of these diodes (Feed A) has failed open, then the other Feed B will provide all of the power demand. The system will continue to operate without any notification of this failure reducing the system to a single point of failure. A much more dangerous failure is where the diode has failed short. The system will continue to operate without notification that the short has occurred. With this failure transients and failures on Feed B propagate to Feed A. Also this silent short failure could pose a significant safety hazard for technical personnel servicing these feeds. “ISL6144 + ORing FET” vs “Discrete ORing FET” Solution If we compare the ISL6144 integrated solution to discrete ORing MOSFET solutions, the ISL6144 wins in all aspects, the main ones being PCB real estate saving, cost savings, and reduction in the MTBF of this section of the circuit as the overall number of components is reduced. In brief the solution offered by this IC enhances power system performance and protection while not adding any considerable cost, on the contrary saving PCB board real estate and providing simple to implement integrated solution. Setting the External HS Comparator Threshold Voltage In general, paralleled modules in a redundant power system have some form of active current sharing, to realize the full benefit of this scheme including lower operating temperatures, lower system failure rate, as well as better transient response when load step is shared. Current sharing is realized using different techniques; all of these techniques will lead to similar modules operating under similar conditions in terms of switching frequency, duty cycle, output voltage and current. When paralleled modules are current sharing, their individual output ripple will be similar in amplitude and frequency and the common bus will have the same ripple as these individual modules and will not cause any of the turn off mechanisms to be activated as the same ripple will be present on both sensing nodes (VIN and VOUT). This would allow setting the high speed comparator threshold (VTH(HS)) to a very low value. As a starting point a VTH(HS) of 50mV could be used, the final value of this TH will be system dependant and has to be finalized in the system prototype stage. If the gate experiences false turn-off due to system noise, the VTH(HS) has to be increased. ISL6144 The reverse current peak can be estimated as: V TH ( HS ) + V SD + V OS ( HS ) I reverseP = ------------------------------------------------------------------------- ; where r DS ( ON ) (EQ. 7) Reducing the value of VTH(HS) results in lower reverse current amplitude and reduces transients on the common bus output voltage. HVREF and COMP Capacitor Values VSD is the MOSFET forward voltage drop VOS(HS) is the voltage offset of HS Comparator The duration of the reverse current pulse is few hundred nanoseconds and is normally kept well below current rating of the ORing MOSFET. HVREF Capacitor (C1): this capacitor is necessary to stabilize the HVREF(VZ) supply and a value of 150nF is sufficient. Increasing this value will result in gate turn on time increase. COMP Capacitor (C2):Placed between VOUT and COMP pins to provide filtering and decoupling. A 10nF capacitor is adequate for most cases. . Typical Performance Curves and Waveforms CHARGE PUMP VOLTAGE (V) 75V 11 48V 12V 10 9 10V 8 7 -40 -20 0 20 40 60 80 100 120 REG AMP FORWARD REGULATION (mV) 12 32 75V 28 48V 24 10 & 12V 20 16 12 -40 -20 0 TEMPERATURE (oC) 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 6. CHARGE PUMP VOLTAGE (VGQP) vs TEMPERATURE FIGURE 7. REG. AMP FORWARD REGULATION 5.4 6 75V 5 VSET VOLTAGE (V) BIAS CURRENT (mA) 5.5 48V 4.5 4 12V 12V 3.5 10V 3 75V 5.3 48V 10 & 12V 5.2 5.1 2.5 2 -40 -20 0 20 40 60 80 100 TEMPERATURE (oC) FIGURE 8. I BIAS CURRENT vs TEMPERATURE 10 120 5 -40 -20 0 20 40 60 TEMPERATURE (oC) FIGURE 9. VSET VOLTAGE 80 100 120 ISL6144 Typical Performance Curves and Waveforms (Continued) HVREF(VZ) 6 1V/DIV 75V HVREF VOLTAGE (V) 5.875 48V 10V/DIV VG VIN 5.75 10V/DIV 10 & 12V 5.625 IIN 5.5 10A/DIV 5.375 5.25 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 10. HVREF VOLTAGE FIGURE 11. FIRST SUPPLY START UP rDS(ON) = 19mΩ, QTOT = 70nC, EXTERNAL CGS = 33nF, VTH(HS) = 55mV rDS(ON) = 19mΩ, QTOT = 70nC, EXTERNAL CGS = 33nF, VTH(HS) = 55mV IIN2 VOUT 5A/DIV 10V/DIV IIN2 VOUT 10V/DIV 10V/DIV 5V/DIV FIGURE 12. HIGH SPEED TURN OFF, VIN = 48V, COMMON LOAD IS SMPS (CLOAD = 100µF) WITH EQUIVALENT 4A LOAD 11 10V/DIV VIN2 VIN2 VGS2 5A/DIV VGS2 5V/DIV FIGURE 13. HIGH SPEED TURN OFF, VIN = 48V, COMMON LOAD IS SMPS (CLOAD = 100µF) WITH EQUIVALENT 1.3A LOAD ISL6144 Typical Performance Curves and Waveforms IIN2 (Continued) 2A/DIV VOUT VOUT 10V/DIV VIN2 VGS2 10V/DIV VIN2 2V/DIV 5V/DIV VGS2 5V/DIV IIN2 2A/DIV FIGURE 15. SLOW SPEED TURN OFF, VIN = 12V, COMMON LOAD IS SMPS (CLOAD = 100µF) WITH EQUIVALENT 4A LOAD FIGURE 14. SLOW SPEED TURN OFF, VIN = 48V, COMMON LOAD IS SMPS (CLOAD = 100µF) WITH EQUIVALENT 4A LOAD Application Circuit DC/DC #1 INPUT BUS 1 36 TO 75VDC +IN +OUT CIN1 100µF PC Ccs1 1nF Cd1 220nF +S SC PR -IN Rpb1 Sa Sb 10 FROM CB -S D1 (NOTE 7) F1 15A +OUT1 = 48V Q1 FDB3632 Cpb1 22µF 5V -OUT R3 4.99K DC/DC #2 INPUT BUS 2 36 TO 75VDC +IN +OUT CIN2 100µF PC Cd2 220nF +S SC PR Ccs2 1nF -IN -S Rpb2 Sa Sb 10 FROM CB C2 10nF COMMON BUS “CB” 10A R2 47.5K Q2 FDB3632 VIN C3 150nF 5V R4 4.99K PRIMARY R1 499 D2 (NOTE 7) Cpb2 22µF -OUT VOUT HVREF U1 COMP ISL6144 VSET FAULT GND F2 15A +OUT2 = 48V GATE VIN C1 150nF GATE VOUT U1 COMP HVREF ISL6144 FAULT GND VSET R5 499 C4 10nF R6 47.5K SECONDARY NOTES: 7. D1, D2 are parasitic MOSFET diodes. 8. Remote Sense pin (+S) on both DC/DC converters has to be connected either directly at the module output (Sa closed) or to the CB point (Sb closed). Connecting to CB is not recommended as it might cause Fault propagation in case of short circuit on a PS output. 9. F1, F2 are optional and can be eliminated depending on power system configuration and requirements. 10. DC/DC #1, 2 configuration is based on Vicor V48B48C250AN3. FIGURE 16. APPLICATION CIRCUIT FOR A 1+1 REDUNDANT 48V SYSTEM 12 ISL6144 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M 2 INCHES E1 GAUGE PLANE -B1 B M L 0.05(0.002) -A- SYMBOL MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - A1 3 A D -C- e α c 0.10(0.004) C A M 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - B S 0.002 D 0.193 0.201 4.90 5.10 3 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 N α NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 13 0.006 E1 e A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 0.70 6 16 8o 0o - 6.50 7 8o Rev. 1 2/02 ISL6144 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.5x5 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHC ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 A3 b 0.23 D 0.28 9 0.38 5, 8 5.00 BSC D1 D2 9 0.20 REF - 4.75 BSC 2.95 3.10 9 3.25 7, 8 E 5.00 BSC - E1 4.75 BSC 9 E2 2.95 e 3.10 3.25 7, 8 0.65 BSC - k 0.25 - - - L 0.35 0.60 0.75 8 L1 - - 0.15 10 N 20 2 Nd 5 3 Ne 5 3 P - - 0.60 9 θ - - 12 9 Rev. 3 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14