austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: [email protected] Please visit our website at www.ams.com AS3543 Data Sheet 1 General Description 2 Key Features The AS3543 is an ultra low power stereo audio codec and is designed for Portable Digital Audio Applications. Audio It allows high-end quality playback with up to 100dBA SNR and recording in FM quality. With one microphone (including pre-amplifier and supply for an electret microphone) and two line inputs, it allows connecting a variety of audio inputs. The different audio signals can be mixed via a 6-channel mixer and fed to either a headphone output for 16 /32 headsets or a line output. Both outputs have a ground noise cancellation to use it e.g. in car docking stations. The audio outputs have also an auto fading implemented which performs the fade-in, fadeout as well as the transition between specific volume levels automatically with an selectable timing. Audio power consumption: - 5mW: 96dB DAC to Headphone @ 1.8V, 32Ω - 7mW: 100dB DAC to Headphone @ 2.9V, 32Ω Sigma Delta Converters DAC lv al id H i g h E n d Ste r eo A ud i o C o d ec w i th S y st em P M U - 85dB SNR ('A' weighted) @ 1.7V Sampling Frequency am lc s on A te G nt st il - 98dB SNR ('A' weighted) @ 1.7V - 102dB SNR ('A' weighted) @ 2.9V ADC Further the device offers advanced power management functions. All necessary ICs and peripherals in a Digital Audio Player are supplied by the AS3543. It features 2 DCDC converters for core and memory/periphery supply as well as 4 LDOs. Both DCDC converter feature DVM (dynamic voltage management) with an selectable timing for the voltage stepping. The different regulated supply voltages are programmable via the serial control interface. ca The step-up converter for the backlight can operate up to 15V (with an external transistor even higher) in voltage and current control mode. An internal voltage protection is limiting the output voltage in the case of external component failures. 2 high voltage current sinks can be used to operate two, if needed also unbalanced, LED strings. An automatic dimming function allows a logarithmic on/off of the backlight with selectable timing. ch ni AS3543 also contains a Li-Ion battery charger with constant current, constant voltage and trickle charging. The maximum charging current is 460mA. An integrated battery switch is separating the battery during charging or whenever an external power supply is present. With this switch it is also possible to operate with no or deeply discharged batteries. High Efficiency Headphone Amplifier volume control via serial interface 32 steps @1.5dB and MUTE 2x12mW @16Ω driver capability@ 1.8V supply THD -74dB @16Ω; 1.8V 2x40mW @16Ω driver capability@ 3.6V supply THD -77dB @16Ω; 3.6V headphone and over-current detection phantom ground eliminates large capacitors ground noise cancellation Line Output volume control via serial interface 32 steps @1.5dB and MUTE 0.6Vp @10kΩ, 1.8V ground noise cancellation Te The AS3543 has an on-chip, phase locked loop (PLL) which generates the needed internal CODEC master clock. I2S Frame and shift-clock have to be applied from the processor for playback and recording. - DAC: 8-96kHz - ADC: 8-24kHz Further the AS3543 has an independent 32kHz real time clock (RTC) on chip which allows a complete power down of the system CPU while only consuming less than 1µA. An internal switch automatically switches between the RTC backup-battery and main battery supply. The single supply voltage may vary from 2.7V to 5.5V. www.austriamicrosystems.com Revision 1.11 1 - 91 AS3543 3v2 Data Sheet - A p p l i c a t i o n s General Microphone Input 3 gain pre-setting (30dB/36dB/42dB) and AGC 32 gain steps @1.5dB and MUTE supply for electret microphone microphone detection remote control by switch Supervisor automatic battery monitoring with interrupt generation and selectable warning level automatic temperature monitoring with interrupt generation and selectable warning and shutdown levels 2 Line Inputs volume control via serial interface 32 steps @1.5dB and MUTE stereo or 2x mono Real Time Clock Audio Mixer 8 channel input/output mixer with AGC mixes line inputs, microphone and ADC with DAC left and right channels independent Power Management Voltage Generation ultra low power 32kHz oscillator 32bit RTC sec counter, 96 days auto wake-up selectable interrupt (seconds or minutes) 128bit free SRAM for random settings 32kHz clock output to peripheral voltage generation trim able oscillator <1uA total power consumption am lc s on A te G nt st il lv Auxiliary Oscillator (system clock generation) step down for CPU core (0.61V-3.35V, 250mA) low power 12-24MHz oscillator step down for peripheral (0.61V-3.35V, 250mA) clock output LDO1 for AFE supply (1.7V (1.65-3.2V), 50mA) LDO2 for AFE supply (2.7V (2.3-3.5V), 200mA) 10bit resolution LDO3 for peripherals (1.2V-3.5V, 100/200mA) 22 inputs analog multiplexer LDO4 for peripherals (1.2V-3.5V, 100/200mA) VBUS comparator separate input for LDO3 power supply supervision & hibernation modes 5sec and 10sec emergency shut-down ca Backlight Driver al id General Purpose ADC Interfaces 2 wire serial control interface reset pin with selectable delay, power good pin 64bit unique ID (OTP) 26 different interrupts Package CTBGA68 [6.0x6.0x1.1mm] 0.5mm pitch step up for backlight (15V (25V)) current control mode (1.2-37.2mA) voltage control mode Portable Digital Audio/Video Player and Recorder 2 HV current sinks PDA, Smartphone ni automatic dimming over-voltage protection ch 3 Applications Te Battery Charger automatic trickle charge (55mA) prog. constant current charging (55-460mA) prog. constant voltage charging (3.9V-4.25V) current limitation for USB mode integrated battery switch www.austriamicrosystems.com Revision 1.11 2 - 91 AS3543 3v2 Data Sheet - A p p l i c a t i o n s Te ch ni ca am lc s on A te G nt st il lv al id Figure 1. Block Diagram www.austriamicrosystems.com Revision 1.11 3 - 91 AS3543 3v2 Data Sheet - A p p l i c a t i o n s Contents 1 General Description ............................................................................................................................ 1 2 Key Features .......................................................................................................................................1 3 Applications ........................................................................................................................................ 2 4 Pinout ................................................................................................................................................... 6 ..............................................................................................................................................6 4.2 Pin Description ...............................................................................................................................................6 5 Absolute Maximum Ratings ............................................................................................................... 9 ................................................................................................................. 11 7 Typical Operating Characteristics ................................................................................................... 13 8 Detailed Description - Audio Functions 8.1 Audio Line Inputs (2x) 8.2 Microphone Input ..................................................................................................................................14 .........................................................................................................................................15 ..................................................................................................................................................17 am lc s on A te G nt st il 8.3 Line Output .......................................................................................... 14 lv 6 Electrical Characteristics al id 4.1 Pin Assingment 8.4 Headphone Output .......................................................................................................................................18 8.5 DAC, ADC and I2S Digital Audio Interface 8.6 Audio Output Mixer ..................................................................................................21 ......................................................................................................................................24 8.7 2-Wire-Serial Control Interface ....................................................................................................................25 9 Detailed Description - Power Management Functions 9.1 Low Drop Out Regulators ............................................................................................................................28 9.2 DCDC Step-Down Converter (2x) 9.3 15V Step-Up DCDC Converter 9.4 Charger .................................................................. 28 ................................................................................................................31 ....................................................................................................................35 ........................................................................................................................................................37 9.5 Battery Switch ..............................................................................................................................................40 10 Detailed Description - SYSTEM Functions 10.1 SYSTEM 10.2 Hibernation 10.3 Supervisor ....................................................................................................................................................41 ................................................................................................................................................43 ..................................................................................................................................................44 10.4 Interrupt Generation 10.7 GPIO Pins ...................................................................................................................................44 .........................................................................................................................................46 ca 10.5 Real Time Clock 10.6 10-Bit ADC ................................................................................... 41 .................................................................................................................................................47 ..................................................................................................................................................48 ..................................................................................................................................49 ni 10.8 12-24MHz Oscillator 10.9 Unique ID Code (64 bit OTP ROM) 11 Register Definition ...........................................................................................................50 .......................................................................................................................... 51 ch 12 Application Information .................................................................................................................. 88 13 Package Drawings and Markings .................................................................................................. 89 ...................................................................................................................... 90 Te 14 Ordering Information www.austriamicrosystems.com Revision 1.11 4 - 91 AS3543 3v2 Data Sheet - A p p l i c a t i o n s Revision History Table 1. Revision History Revision Date Owner 1.01 17.4.2009 pkm official release Description 5.2009 pkm added audio characterisation data 1.11 12.2012 pkm typo and register bit description corrections Te ch ni ca am lc s on A te G nt st il lv al id 1.10 www.austriamicrosystems.com Revision 1.11 5 - 91 AS3543 3v2 Data Sheet - P i n o u t 4 Pinout 4.1 Pin Assignment Figure 2. Pin Assignments (Top View) 3 A CHGOUT BVDDBSW PVDD1 B CHGIN BATTEMP BVDDP1 C VSS15V SW15V D 4 E BVDDC2 ISINK1 F LXC2 CVDD2 G FVDD VSS HPCM VDD17IN HPGND VBUS LIN2R HPVDD 8 9 10 HPR HPVSS HPL LOGND LOUTR LOUTL LIN1R LIN1L LIN2L MICS VPROG3 MICN MICP SCLK VPROG2 AGND AVSS VPROG1 VREF CVDD1 J LXC1 PWRUP XRES XIN24M XOUT24M XIRQ SDI SDO PWGD Q24M DVSS DVDD ca CVSS12 4.2 PVDD2 7 MCLK LRCK H K BVDDC1 6 am lc s on A te G nt st il ISINK2 BVDD 5 al id 2 lv 1 AVDD27 AVDD17 CSCL RVDD XIN32K CSDA BVDDR XOUT32K Q32K Pin Description Table 2. Pin Description for AS3543 K2 Type Description XIN24M ANA IO 24MHz Crystal Input (ext. 22pF C needed) XOUT24M ANA IO 24MHz Crystal Output (ext. 22pF C needed) ch K3 Pin Name ni Pin Number PWRUP DIG IN Power Up Input G2 FVDD SUP IN Digital Pos. Supply (e.g. DAC, …) J3 XRES DIG OUT Reset Output J4 XIRQ DIG OUT Interrupt Request Output J5 PWGD DIG IO PowerUp Sequence Complete Output E4 MCLK DIG IN MCLK input F4 SCLK DIG IN I2S Shift Clock Input G4 LRCK DIG IN I2S Frame Clock Input G5 SDI DIG IN I2S Data Input to DAC Te J2 www.austriamicrosystems.com Revision 1.11 6 - 91 AS3543 3v2 Data Sheet - P i n o u t Table 2. Pin Description for AS3543 Pin Number Pin Name Type K5 DVSS GND Digital Circuit Neg. Supply Terminal Digital Periphery Pos. Supply K6 DVDD G6 SDO J6 Q24M DIG IO 24MHz clock digital output J7 Q32K DIG IO 32kHz clock digital output J8 CSCL DIG IN 2 wire SERIF Clock Input K8 CSDA DIG IO 2 wire SERIF Data I/O K9 BVDDR SUP IN Secondary RTC Supply - Supercap K10 XOUT32K ANA IO 32KHz Crystal Output XIN J10 XIN32K ANA IO 32kHz Crystal Input XOUT J9 RVDD ANA IO RTC LDO output, RTC supply input G9 VREF ANA IO DAC Reference Pin G7 VPRG1 ANA IN Core Supply Voltage Definition Pin F7 VPRG2 ANA IN Memory Supply Voltage Definition Pin E7 VPRG3 ANA IN PowerUp Sequence Definition Pin F10 AVSS GND F9 AGND ANA IO Analog Common Mode Voltage Pin E10 MICP ANA IN Microphone Input P E9 MICN ANA IN Microphone Input N D9 MICS ANA IO Microphone Supply Output / Remote Control input D6 LIN2R ANA IN Analog Line Input 2 Right Channel D7 LIN2L ANA IN Analog Line Input 2 Left Channel B8 LOGND ANA IO Line Output Common Mode Voltage Pin C9 LIN1R ANA IO Analog Line Input 1 Right Channel B9 LOUTR ANA OUT Analog Line Output Right Channel B10 LOUTL ANA OUT Analog Line Output Left Channel C10 LIN1L ANA IO Analog Line Input 1 Right Channel B7 HPVDD SUP IN Headphone Supply default 1.8V (max. 3.6V) A10 HPL ANA OUT Headphone Output Left Channel HPR ANA OUT Headphone Output Right Channel al id lv am lc s on A te G nt st il Ground (analog) ca HPCM ch A6 DIG OUT I2S Data Output from ADC ni A8 SUP IN Description ANA OUT Headphone Common Mode Buffer Pin Headphone Ground HPVSS GND B6 HPGND ANA IO Headphone Common Mode Voltage Pin H10 AVDD17 SUP IO LDO1 Output default 1.7V B5 VDD17IN SUP IN LDO1 Pos. Supply Terminal H9 AVDD27 SUP IO LDO2 Output default 2.7V B4 BVDD SUP IN Main Battery Supply Input (2.7-5.5V) D5 VBUS ANA IN VBUS Detection Input A5 PVDD2 ANA OUT LDO4 Output (PVDD2) A3 PVDD1 ANA OUT LDO3 Output (PVDD1) Te A9 www.austriamicrosystems.com Revision 1.11 7 - 91 AS3543 3v2 Data Sheet - P i n o u t Table 2. Pin Description for AS3543 Type Description B3 BVDDP1 SUP IN LDO3 Pos. Supply Terminal A2 BVDDBSW SUP IO Battery Switch output to be connected against BVDD A1 CHGOUT SUP IO Li-Ion Charger Output (battery switch input) B1 CHGIN SUP IN Li-Ion Charger Input B2 BATTEMP ANA IO Li-Ion Charger Battery Temp. Sensor Input D4 VSS GND Power Management Neg. Reference Supply C1 VSS15V GND DCDC15V & Current Sinks Neg. Supply Terminal C2 SW15V D2 ISINK2 ANA IO DCDC15V Load Current Sink2 Terminal E2 ISINK1 ANA IO DCDC15V Load Current Sink1 Terminal E1 BVDDC2 SUP IN CVDD2 Step Down Pos. Supply Terminal F1 LXC2 F2 CVDD2 ANA IN H1 CVSS12 GND H2 CVDD1 ANA IN J1 LXC1 K1 BVDDC1 am lc s on A te G nt st il DIG OUT DCDC15V Switch Output to Coil al id Pin Name lv Pin Number DIG OUT CVDD2 Step Down Switch Output to Coil CVDD2 and Feedback Pin DCDC12 Substrate Pin CVDD1 and Feedback Pin DIG OUT CVDD1 Step Down Switch Output to Coil CVDD1 Step Down Pos. Supply Terminal Te ch ni ca SUP IN www.austriamicrosystems.com Revision 1.11 8 - 91 AS3543 3v2 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 11 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions. Table 3. Absolute Maximum Ratings Min Max Units Comments al id Parameter -0.5 7.0 V 3V pins -0.5 5.0 V Applicable for pins DVDD, HPVDD, FVDD, VDD17IN, RVDD, VPRG1, VPRG2, VPRG3 15V pins -0.5 17 V Applicable for pin SW15V, ISINK1/2 Voltage difference at VSS terminals -0.5 0.5 V Applicable for pins VSS, VSS15V, CVSS12, HPVSS, AVSS, DVSS 3.3V pins with protection to AVDD27 -0.5 5.0 AVDD27 V Applicable for pins BATTEMP, HPGND 3.3V pins with protection to DVDD -0.5 5.0 DVDD+0.5 V Applicable for pins MCLK, LRCK, SCLK, SDI, SDO, XIRQ, XRES, PWGD, Q32K, Q24M, XIN24M, XOUT24M 3.3V pins with protection to RVDD -0.5 5.0 RVDD+0.5 V Applicable for pins XIN32K, XOUT32K 3.3V pins with protection to AVDD17 -0.5 5.0 AVDD17+0.5 V Applicable for pins LOUTL/R, LOGND, VREF, AGND, LIN1L/R, LIN2L/R, MICP/ N,MICS 3.3V pins with protection to HPVDD -0.5 5.0 HPVDD+0.5 V Applicable for pins HPCM, HPR/L voltage regulator pins with protection to BVDD -0.5 5.0 BVDD+0.5 V Applicable for pins AVDD27, PVDD1/2, CVDD1, LXC1, CVDD2, LXC2 voltage regulator pins with protection to AVDD17IN -0.5 5.0 AVDD17IN +0.5 V Applicable for pins AVDD17 Input Current (latch-up immunity) -100 100 mA Norm: JEDEC 17 500 mW PT for CTBGA68 package +/-1 kV Norm: JEDEC JESD22-A114C -20 +85 ºC +110 ºC -50 +125 ºC 5 85 % am lc s on A te G nt st il lv 5V pins Applicable for pins BVDD, BVDDC1, BVDDC2, BVDDR, BVDDP1, BVDDBSW, CHGIN, CHGOUT, VBUS, CSCL, CSDA, PWRUP ca Continuous Power Dissipation (TA = +70ºC) Continuous power dissipation 1 ni Electrostatic Discharge Electrostatic Discharge HBM ch Temperature Ranges and Storage Conditions Operating Temperature Range Junction Temperature Te Storage Temperature Range Humidity non-condensing www.austriamicrosystems.com Revision 1.11 9 - 91 AS3543 3v2 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s Table 3. Absolute Maximum Ratings Parameter Min Max Units Comments 260 °C Norm IPC/JEDEC J-STD-020C, reflects moisture sensitivity level only 235 245 °C peak temperature 30 45 s well time above 217 °C 1 Represents a max. floor live time of 168h Package Body Temperature Solder Profile Moisture Sensitive Level 3 Te ch ni ca am lc s on A te G nt st il lv 1. Depending on actual PCB layout and PCB used al id Bump Temperature (soldering) www.austriamicrosystems.com Revision 1.11 10 - 91 AS3543 3v2 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics BVDD=+2.7V...+5.5V, TA =-20ºC...+85ºC. Typical values are at BVDD=+3.6V, TA=+25ºC, unless otherwise specified. Table 4. Electrical Characteristics Symbol Parameter Condition Min Typ BVDDx Battery Supply Voltage BVDD, BVDDBSW, BVDDC1, BVDDC2, BVDDP1 2.7 3.6 BVDDR RTC secondary Supply Voltage 1.2 VBUS USB VBUS Voltage CHGIN Charger Supply Voltage 4.5 HPVDD HP Supply Voltage 1.8 DVDD Digital Periphery Supply Voltage 1.8 VDD17IN LDO1 Input Voltage 1.8 FVDD Digital Supply Voltage 1.75 AVDD27 Analogue Supply Voltage AVDD17 Analogue Supply Voltage AGND Analog Ground Voltage Internally generated VDELTA- Difference of Negative Supplies CVSS12, VSS15V, HPVSS, AVSS, DVSS, VSS To achieve good performance, the negative supply terminals should be connected to low impedance ground plane. Max Unit 5.5 V 5.5 V lv V V 3.6 V am lc s on A te G nt st il POR & Watchdog 5.5 5.5 3.6 V 3.6 V 1.8 3.5 V 2.6 2.7 3.5 V 1.7 1.7 3.5 V Difference of Positive Supplies VDELTA+ 5.0 al id Supply Voltages 2.9 AVDD17 /2 -0.1 V 0.1 V RVDD-AVDD27; AVDD17-AVDD27; FVDD-AVDD27 0 V AVDD27-HPVDD 0.3 V BVDD-AVDD27 0.1 V Power-on Reset Activation Level Power-on Reset activation level when DVDD decreases 2.15 V VPOR_OFF Power-on Reset Release Level Power-on Reset release when DVDD increases 2.0 V 100 mV fLRCLK_WD Power-on Hysteresis LRCLK Watchdog ch PWRUP ni VPOR_HY ca VPOR_ON 2 Delay Time of pin PWRUP Minimum key press time VPWRUP_L Input Level LOW, Pin PWRUP, BVDD>3V Te tON_DELAY VPWRUP_H IPWRUP Input Level HIGH Internal Pull-down Current Source www.austriamicrosystems.com 4.1 8 30 kHz ms 0.5 V Pin PWRUP, BVDD>3V BVDD/ 3 V Pin PWRUP, BVDD<=3V 1 V Pin PWRUP; @2.9V 2.5 Revision 1.11 7 19 uA 11 - 91 AS3543 3v2 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 4. Electrical Characteristics (Continued) Symbol Parameter Condition Min Typ Max Unit 10% DVDD V Digital Inputs/Outputs VDO_DL Digital Output Driver Capability (drive LOW) Pins XRES, XIRQ, PWGD @ 8mA, SDO VDO_DH Digital Output Driver Capability (drive HIGH) Pins XRES, XIRQ @ 8mA, push/pull mode only, SDO IPU Internal Pull-up Current Source Pins XRES, XIRQ, PWGD, Q32K, Q24M; @0V 10 VDI_L Digital Input Level LOW Pin SDI, SCLK, MCLK, LRCK 30% DVDD VDI_H Digital Input Level HIGH Pin SDI, SCLK, MCLK, LRCK 70% DVDD fCLK Audio Clock Frequency LRCK according to streamed audio data al id µA V V lv 8 V 96 am lc s on A te G nt st il Block Power Requirements 90% DVDD IREF Reference supply current IBIAS kHz 330 uA Audio Bias current 32 uA ISUM Summing stage current 174 uA ILIN Line input stage current no signal 146 uA IMIC Mic input stage current no signal 643 uA IMICS Mic Supply stage current no load 201 uA ILOUT Line output stage current no load 436 uA IDAC_GS DAC gain stage current no signal 214 uA IADC_GS ADC gain stage current no signal 1,36 mA 1.8V, no load 1,94 Bias reduction on, no load 1,48 CM buffer off, no load 1,47 Bias reduction on, CM buffer off, no load 0,94 Headphone stage current ca IHPH all blocks off, only LDO2 on IDAC ch ni DAC supply current IADC Te ADC supply current LRCK=48kHz 1,48 LRCK=44.1kHz 1,41 LRCK=32kHz 1,19 LRCK=16kHz 0,91 LRCK=8kHz 0,76 LRCK=24kHz 1,7 LRCK=22.05kHz 1,69 LRCK=16kHz 1,64 LRCK=8kHz 1,58 LRCK=4kHz 1,55 mA mA mA IDAC->HP DAC playback current no load, 44.1kHz, including PMU mA ILine->HP Line Input playback current no load, including PMU mA IRTC RTC supply current www.austriamicrosystems.com 600 Revision 1.11 nA 12 - 91 AS3543 3v2 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.1 Audio Specification BVDD=+3.6V, VDD27=HPVDD=FVDD=+3V, VDD17=+2.9V, fS=48kHz, TA=+25ºC, unless otherwise specified. Table 5. Electrical Characteristics Symbol Parameter Condition Min Typ Max Unit DAC Input to Line Output Full Scale Output RL= 10kΩ, f=1kHz, 1VRMS input 0,960 SNR Signal to Noise Ratio A-weighted, no load, silence input 100 Dynamic Range A-weighted, no load, -60dB FS, f=1kHz 94 Total Harmonic Distortion 1kHz -1dB FS input, RL=10kΩ -82 CS Channel Separation RL=10kΩ 62 Line Input to Line Output dB dB dB dB lv DR THD VRMS al id FS FS Full Scale Output RL= 10kΩ, f=1kHz, 1VRMS input SNR Signal to Noise Ratio A-weighted, no load, silence input THD Total Harmonic Distortion 1kHz 1VRMS (-1dB FS) input, RL=10kΩ -72 dB CS Channel Separation RL=10kΩ 100 dB RL=32Ω 0,800 VRMS RL=16Ω 0,793 VRMS VRMS 101 dB am lc s on A te G nt st il 0,754 DAC Input to HP Output FS Full Scale Output SNR Signal to Noise Ratio A-weighted, no load, silence input 100 dB DR Dynamic Range A-weighted, no load, -60dB FS, f=1kHz 89 dB no load, f=1kHz, -1dB FS input -80 dB THD Total Harmonic Distortion POUT=20mW, RL=32Ω, f=1kHz, -1dB FS -79 dB POUT=40mW, RL=16Ω, f=1kHz, -1dB FS -78 RL=32Ω -61 dB RL= 16Ω -60 dB RL= 32Ω, f=1kHz, 1VRMS(FS) input 0,834 VRMS RL= 16Ω, f=1kHz, 1VRMS(FS) input 0,827 VRMS 101 dB CS Channel Separation -60 dB Line Input to HP Output Full Scale Output SNR Signal to Noise Ratio A-weighted, no load, silence input no load, f=1kHz, 1VRMS -72 dB THD Total Harmonic Distortion POUT=20mW, RL=32Ω, f=1kHz, 1VRMS -72 dB POUT=40mW, RL=16Ω, f=1kHz, 1VRMS -72 RL = 32Ω 84 dB RL = 16Ω 72 dB ni Channel Separation ch CS ca FS -60 dB Mic Input to Line Output Full Scale Output f=1kHz, 27mVRMS FS input 0,950 VRMS SNR Signal to Noise Ratio A-weighted, no load, silence input 80 dB THD Total Harmonic Distortion 1kHz 27mVRMS FS input -77 dB Te FS Mic Input to ADC Output SNR Signal to Noise Ratio A-weighted, no load, silence input 81 dB DR Dynamic Range A-weighted, no load, -60dB FS, f=1kHz 84 dB THD Total Harmonic Distortion 1kHz 27mVVRMS FS input -65 dB www.austriamicrosystems.com Revision 1.11 13 - 91 AS3543 3v2 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s BVDD=+3.6V, VDD27=+2.7V, HPVDD=FVDD=1.8V, VDD17=+1.7V, fS=48kHz, TA=+25ºC, unless otherwise specified. Table 6. Electrical Characteristics Symbol Parameter Condition Min Typ Max Unit DAC Input to Line Output Full Scale Output RL= 10kΩ, f=1kHz, 1VRMS input 0,568 VRMS SNR Signal to Noise Ratio A-weighted, no load, silence input 96 dB dB DR Dynamic Range A-weighted, no load, -60dB FS, f=1kHz 95 THD Total Harmonic Distortion 1kHz -1dB FS input, RL=10kΩ -90 CS Channel Separation RL=10kΩ 62 RL= 10kΩ, f=1kHz, 545mVRMS input 0,545 FS Full Scale Output Signal to Noise Ratio A-weighted, no load, silence input THD Total Harmonic Distortion 1kHz 1VRMS (-1dB FS) input, RL=10kΩ CS Channel Separation RL=10kΩ dB VRMS 97 dB -81 dB 100 dB RL=32Ω 0,560 VRMS RL=16Ω 0,550 VRMS am lc s on A te G nt st il SNR dB lv Line Input to Line Output al id FS DAC Input to HP Output FS Full Scale Output SNR Signal to Noise Ratio A-weighted, no load, silence input 97 dB DR Dynamic Range A-weighted, no load, -60dB FS, f=1kHz 88 dB no load, f=1kHz, FS input -87 dB THD Total Harmonic Distortion CS POUT=6mW, RL=32Ω, f=1kHz, -1dB FS -81 POUT=12mW, RL=16Ω, f=1kHz, -1dB FS -78 RL=32Ω 63 dB RL= 16Ω 60 dB RL= 32Ω, f=1kHz, 545mVRMS(FS) input 0,450 VRMS RL= 16Ω, f=1kHz, 545mVRMS(FS) input 0,447 VRMS A-weighted, no load, silence input 97 dB no load, f=1kHz, 545mVRMS -77 dB Channel Separation -60 dB dB Line Input to HP Output Full Scale Output SNR Signal to Noise Ratio CS Total Harmonic Distortion POUT=6mW, RL=32Ω, f=1kHz, 545mVRMS -75 POUT=12mW, RL=16Ω, f=1kHz, 545mVRMS -75 RL = 32Ω 77 dB RL = 16Ω 66 dB ni THD ca FS Channel Separation dB -60 dB ch Mic Input to Line Output Full Scale Output f=1kHz, 27mVRMS FS input 0,512 VRMS SNR Signal to Noise Ratio A-weighted, no load, silence input 75 dB THD Total Harmonic Distortion 1kHz 27mVRMS FS input 77 dB Te FS Mic Input to ADC Output SNR Signal to Noise Ratio A-weighted, no load, silence input 77 dB DR Dynamic Range A-weighted, no load, -60dB FS, f=1kHz 84 dB Total Harmonic Distortion 1kHz 27mVVRMS FS input -64 dB THD www.austriamicrosystems.com Revision 1.11 14 - 91 AS3543 3v2 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics Te ch ni ca am lc s on A te G nt st il lv al id BVDD = +3.6V, TA = +25ºC, unless otherwise specified. www.austriamicrosystems.com Revision 1.11 15 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8 Detailed Description - Audio Functions 8.1 Audio Line Inputs (2x) 8.1.1 General The chip features two identical line inputs. The blocks can work in 2x mono single ended or in stereo single ended mode. al id The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each and MUTE. The gain can be set from –40.5dB to +6dB. The stage is set to mute by default. If the line input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input. Line Input 1 and 2 are sharing one gain stage. Parameter am lc s on A te G nt st il 8.1.2 lv Figure 3. Line Inputs o AVDD17=1.7V, AVDD27=2.7V, TA= 25 C, unless otherwise mentioned Table 7. Line Input Parameter Parameter Condition VLIN Input Signal Level Pls observe gain settings. Max. peak levels at any node within the circuit shall not exceed AVDD RLIN Input Impedance ∆RLIN CLIN Min Typ Max Unit AVDD17 AVDD17 V PEAK /3 /2 8-25 kΩ Input Impedance Tolerance ±30 % Input Capacitance 5 pF ni ALIN ca Symbol Programmable Gain -40.5 dB dB Gain Step Accuracy ±0.25 dB Mute Attenuation 100 dB Te discrete logarithmic gain steps +6 1.5 ch Gain Steps ALINMUTE depending on gain setting www.austriamicrosystems.com Revision 1.11 16 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.1.3 Register Description Table 8. Line Input Related Register Base Offset Description LINE_IN_R 2-wire serial 0Ah Right Line Input 1/2 settings, Line Input 2 selection LINE_IN_L 2-wire serial 0Bh Left Line Input 1/2 settings AudioSet1 2-wire serial 14h Enable/disable driver stage AudioSet3 2-wire serial 16h Enable/disable mixer input al id Name Line input has to be enabled in register 14h first before other settings in register 0Ah and 0Bh can be programmed. Microphone Input 8.2.1 General lv 8.2 am lc s on A te G nt st il The AFE offers one microphone input and one low noise microphone voltage supply (microphone bias), voice activation, microphone connect detection and push button remote control. Figure 4. Microphone Input 8.2.2 Gain Stage & Limiter ca The integrated pre-amplifier allows 3 preset gain settings. There is also a limiter which attenuates high input signals from e.g. electret microphones signal to 1Vp. The AGC has 128 steps with 0.375dB with a dynamic range of the full pre-amplifier level. The AGC is ON by default but can be disabled by a microphone register bit. ni Apart from the microphone pre-amplifier the microphone input signal can further be amplified with 32 @1.5dB programmable logarithmic gain steps and MUTE. All gains and MUTE are independently programmable. The gain can be set from –40.5dB to +6dB. ch The stage features a soft-start function. Pre-amplifier and gain-stage settings can be set before enabling the microphone stage. After enabling the stage to gain is automatically set to the defined value by using the 128 steps of the AGC. 8.2.3 Supply & Detection Te Each microphone input generates a supply voltage of 1.5V above HPCM. The supply is designed for ≤2mA and has a 6.5mA current limit. In OFF mode the MICS terminal is pulled to AVDD with 20kOhm. A current of typically 50uA generates an interrupt to inform the CPU, that a circuit is connected. When using HPCM as headset ground the HP–stage gives the interrupt. After enabling the HP-stage through the CPU the microphone detection interrupt will follow. When using the MICS terminal as ADC-10 input to monitor external voltages the 20kOhm pull-up has to be disabled by disabling the interrupt for microphone detection. www.austriamicrosystems.com Revision 1.11 17 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.2.4 Remote Control Fast changes of the supply current of typically 500uA are detected as a remote button press, and an interrupt is generated. Then the CPU can start the measurement of the microphone supply current with the internal 10-bit ADC to distinguish which button was pressed. As the current measurement is done via an internal resistor, only two buttons generating a current of about 0.5mA and 1mA can be detected. With this, 1mA as microphone bias is still available. 8.2.5 Voice Activation 8.2.6 al id Further a built-in voice activation comparator can actuate an interrupt if microphone input voltage of about 5mVRMS is detected. Parameter o AVDD17=1.7V, AVDD27=2.7V, TA= 25 C unless otherwise mentioned Symbol Parameter Condition VMICIN0 Input Signal Level AMICPRE = 30dB; AMIC = 0dB Typ Max mVP 10 mVP AMICPRE = 42dB; AMIC = 0dB 5 mVP MICP, MICN to AGND 7.5 kΩ % AMICPRE = 36dB; AMIC = 0dB VMICIN2 RMICIN Input Impedance Unit 20 am lc s on A te G nt st il VMICIN1 Min lv Table 9. Microphone Input Parameter ∆MICIN Input Impedance Tolerance -7 +33 CMICIN Input Capacitance 5 pF AMICPRE Microphone Preamplifier Gain 30 36 42 dB AMIC Programmable Gain Preamplifier has 3 selectable (fixed) gain settings -40.5 Gain Steps discrete logarithmic gain steps +6 dB 1.5 dB Gain Step Precision ±0.25 dB VATTACK Limiter Activation Level 0.57 VPEAK VDECAY Limiter Release Level 0.47 VPEAK AMICLIMIT Limiter Gain Overdrive 30 36 42 dB tATTACK Limiter Attack Time 50 µs/6dB tDECAY Limiter Decay Time 120 ms/ 6dB AMICMUTE Mute Attenuation 100 dB ni ca 128 @ 0.375dB Microphone Supply Voltage depending on V_MICS setting 2 1.55 1.26 1.06 V IMICMAX Max. Microphone Supply Current microphones nominally need a bias current of 0.5mA-1mA 6.5 mA VNOISE Microphone Supply Voltage Noise 5 µV IMICDET Microphone Detection Current 50 µA IREMDET Max. Remote Detection Current 500 µA Te ch VMICSUP www.austriamicrosystems.com Revision 1.11 18 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.2.7 Register Description Table 10. Microphone Input Related Register Base Offset Description MIC_R 2-wire serial 06h Right Microphone Input volume settings, AGC control MIC_L 2-wire serial 07h Left Microphone Input volume settings, MIC supply control AudioSet1 2-wire serial 14h Enable/disable driver stage AudioSet3 2-wire serial 16h Enable/disable mixer input IRQENRD_1 2-wire serial 24h Interrupt settings for microphone voice activation al id Name 2-wire serial 26h IRQENRD_4 2-wire serial 27h Interrupt settings for remote button press detection Line Output 8.3.1 General am lc s on A te G nt st il 8.3 lv IRQENRD_3 Interrupt settings for microphone detection The line output is designed to provide the audio signal with a typical VPEAK level at a load of minimum 10kΩ, which is a minimum value for line inputs. If the limiters (N20/N21) are deactivated the peak output voltage is AVDD17/2 Vp. This AFE has a combined output stage for headphone and line output with an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from -40.5dB to +6dB. If the line output is not enabled, the volume settings are set to their default values. Changing of volume and mute control can only be done after enabling the output. 8.3.2 ni ca Figure 5. Line Output Auto Fading ch By setting a new output volume level, the stage does a automatic fading from the current gain setting to the new target. Changing the input multiplexer from one source to another will be done by fadeing out to mute, source changing and fading in of the new source to the target volume. Change from HPH-out to LINE-out is done by fading out of HPH-out to mute and fading in of the LINE-out to the target volume. Te The fading speed can be programmed to 3 different speed levels. The immediate response can be selected as 4th state. 8.3.3 Ground Noise Cancelation A separate ground input allows to connect a ground sense line direct from the dock connector ground or line out jack shield to make the audio output independent from PCB ground noise. www.austriamicrosystems.com Revision 1.11 19 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.3.4 Parameter o AVDD17=1.7, AVDD27=2.7, TA= 25 C, unless otherwise mentioned Table 11. Line Output Parameter Parameter Condition Min RL_LO Load Impedance (Stereo Mode) line inputs nominally have 10kΩ 5 CL_LO Load Capacitance (Stereo Mode) ALO Programmable Gain Typ discrete logarithmic gain steps 1.5 8.3.5 ±0.25 Mute Attenuation OUT_L AudioSet2 AudioSet3 8.4 +6 dB dB dB dB am lc s on A te G nt st il Table 12. Line Output Related Register OUT_R pF 100 Register Description Name 100 lv Gain Step Accuracy ALOMUTE Unit kΩ -40.5 Gain Steps Max al id Symbol Base Offset Description 2-wire serial 00h Right Line Output volume settings, MUX control 2-wire serial 01h Left Line Output volume settings 2-wire serial 15h Auto fading timing settings 2-wire serial 16h Enable/disable mixer input Headphone Output The headphone output is designed to provide the audio signal with 2x40mW @ 16Ω or 2x20mW @32Ω, which are typical values for headphones. This AFE has a combined output stage for headphone and line output with an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from -40.5dB to +6dB. Te ch ni ca Figure 6. Headphone Output www.austriamicrosystems.com Revision 1.11 20 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.4.1 Phantom Ground There are 2 ways to connect a headphone to the AFE. In order to spare the bulky ac/dc de-coupling capacitors at pins HPR/HPL a buffered ground (Phantom Ground) is provided. This Common Mode Buffer needs to be switched on if utilized. If form factor considerations are less stringent, the headphones can be conventionally connected via 2x200µF capacitors. 8.4.2 am lc s on A te G nt st il lv al id Figure 7. Headphone Output using Common Mode Buffer No-Pop Function The output is automatically set to mute when the output stage is disabled. To avoid Pop-Click noise during power-up and shut-down of the headphone amplifier, a charge/discharge control of HPGND (0V-HPVDD/2-0V) at pins HPR/HPL is incorporated into the AFE. The 470nF capacitor at pin HPGND is used to form the charge/discharge slope. Pls observe that pin HPGND is a high impedance node which must not be connected to any other external device than the 470nF buffer capacitor. To avoid Pop-Click noise one has to wait for 750ms in between a power-down (switch-off) and a power-up (switch-on) of the headphone amplifier. 8.4.3 Auto Fading ca By setting a new output volume level, the stage does a automatic fading from the current gain setting to the new target. Changing the input multiplexer from one source to another will be done by fading out to mute, source changing and fading in of the new source to the target volume. Change from HPH-out to LINE-out is done by fading out of HPH-out to mute and fading in of the LINE-out to the target volume. The fading speed can be programmed to 3 different speed levels. The immediate response can be selected as 4th state. Te ch ni Figure 8. Headphone Startup with MaxGain Settings www.austriamicrosystems.com Revision 1.11 21 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s Headphone Detection lv 8.4.4 al id Figure 9. Headphone Change Gain Settings 8.4.5 am lc s on A te G nt st il When the headphone amplifier is powered down, one can detect the connection of a headset. It only work if the headset is connected between pins HPR/HPL and HPCM. As long as the headphone amplifier is powered down, HPCM is biased to 150mV and acting as the sense pin. There is a corresponding interrupt available to be enabled. Over-current Protection The headphone amplifier has an over-current protection (e.g. HPR/HPL is shorted). This over-current protection will power down the headphone amplifier for a programmable time-out period (512ms, 0ms). There is a corresponding interrupt available to be enabled. Figure 10. Headphone Overcurrent OFF-ON Sequence 8.4.6 Ground Noise Cancelation As separate ground input allows to connect a ground sense line direct from the dock connector ground or headphone jack shield to make the audio output independent from PCB ground noise. Power Options ca 8.4.7 To save power, especially when driving 32 Ohm loads, a reduction of the bias current is selected. For 16Ohm loads the bias current can be increased. Parameter ni 8.4.8 o AVDD17=1.7, AVDD27=2.7, HPVDD = 2.7V, TA= 25 C, unless otherwise mentioned ch Table 13. Headphone Output Parameter Parameter Condition Min RL_HP Load Impedance stereo mode 16 CL_HP Load Capacitance stereo mode PHP Nominal Output Power RL=16Ω, limiter enabled RL=32Ω, limiter enabled AHP Programmable Gain Te Symbol Gain Steps discrete logarithmic gain steps Revision 1.11 Max Unit Ω 100 40 20 -40.5 Gain Step Accuracy www.austriamicrosystems.com Typ pF mW +6 dB 1.5 dB ±0.25 dB 22 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s Table 13. Headphone Output Parameter (Continued) Parameter Condition Over current limit HPR/HPL pins HPCM pin, @1.8V 70mA 110mA mA mA Over current limit HPR/HPL pins HPCM pin, @2.7V 140mA 220mA mA mA PSRRHP Power Supply Rejection Ratio 200Hz-20kHz, 720mVpp, RL=16Ω 90 dB AHPMUTE Mute Attenuation 8.4.9 Min Typ 100 Register Description Unit dB lv Table 14. Headphone Related Register Max al id Symbol Base Offset OUT_R 2-wire serial 02h Right HP Output volume and over-current settings OUT_L 2-wire serial 03h Left HP Output volume settings, enable and detection control AudioSet2 AudioSet3 IRQENRD_3 Description am lc s on A te G nt st il Name 2-wire serial 15h Auto fading timing settings 2-wire serial 16h Power options, common mode buffer enable 2-wire serial 26h Interrupt settings for over current and HP detection 8.5 DAC, ADC and I2S Digital Audio Interface 8.5.1 Input The AFE receives serialized audio data for the DAC via pin SDI. The output of the DAC is fed through a volume control to the mixer stage and to the multiplexers of line output and headphone amplifiers or direct to these output stages. This serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. Via pin LRCK the alignment clock is input to the DAC digital filters. LRCK (Left Right Clock) indicates whether the serial bit-stream received via pin SDI, represents right channel or left channel audio data. Via pin SCLK the bit clock for the serial bit-stream is signalled. SDI and LRCK are synchronous with SCLK. SDI, LRCK and SCLK are inputs; SDO is not used. 8.5.2 Output ca The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input. This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a volume control to the audio ADC. The digital output is done via an I2S interface. ch ni The AFE sends serialized audio data from the ADC via pin SDO. This serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. Via pin LRCK the alignment clock is signalled to the connected devices (e.g. CPU). LRCLK (Left Right Clock) indicates whether the serial bit-stream sent via pin SDI, presents right channel or left channel audio data. Via pin SCLK the bit clock for the serial bit-stream is signalled. SDO and LRCK are synchronous with SCLK. SDO is an output; LRCK and SCK are inputs; SDI is not used. Te The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input. The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate. The exact ratio can be set in register 11h. The SDO output can be configured to operate in push/pull (3 different driver strengths) or to be tri-state. For a more detailed description of the GPIO functionality of this pin please refer to chapter GPIO Pins on page 50. www.austriamicrosystems.com Revision 1.11 23 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.5.3 I2S Modes The AFE can be operated either in Slave Mode or in Slave Mode with the master clock directly signalled via pin MCLK. The master clock (MCLK) is the necessary internal over-sampling clock for the DAC and ADC (e.g. 128*fs, fs=audio sampling frequency) al id In Slave Mode the PLL generates the master clock based on LRCK. Thus the PLL needs to be preset to the expected sampling frequency. The ranges are 8kS-23kS (8kHz-23kHz) and 24kS-48kS (24kHz-48kHz). Please refer to register 1A-7h. 8.5.4 am lc s on A te G nt st il lv Figure 11. I2S Modes Clock Supervision The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK input changes. A bit in the interrupt register represents the actual state (present or not present) of the LRCK. 8.5.5 Signal Description The digital audio interface uses the standard I2S format: left justified MSB first one additional leading bit The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than 18 bits sampled, the data sample is completed with “0”s. In I2S direct mode the data length has to be minimum 18 bits. The ADC output is always 14 bit. If more SCLK pulses are provided, only the first 14 will be significant. All following bits will be “0”. SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges. The LRCK signal has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always in correct phase lock condition to the external LRCK. Te ch ni ca Please observe that LRCK has to be activated before enabling the ADC. www.austriamicrosystems.com Revision 1.11 24 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.5.6 Parameter am lc s on A te G nt st il lv al id Figure 12. I2S left justified mode DVDD=2.9V, TA=25°C, Slave Mode, f S=48kHz, MCLK = 128*fS, unless otherwise specified Table 15. I2S Timing Parameter tSCLK Condition SCLK Cycle Time 160 ns tSCLKH SCLK Pulse Width High 80 ns tSCLKL SCLK Pulse Width Low 80 ns TLRSU LRCK Setup Time before SCLK rising edge 80 ns TLRHD LRCK Hold Time after SCLK rising edge 80 ns tSDSU SDI setup time before SCLK rising edge 25 ns tSDHD SDI hold time after SCLK rising edge 25 ns tSDOD SDO Delay from SCLK falling edge tJITTER Jitter of LRCK ca Symbol Min Typ Max Unit ns -20 20 ns SCLK delay after MCLK rising edge 0.5 1.5 ns LRLCK delay after SCLK rising edge 0.5 1.5 ns t SDSU SDI setup time before SCLK rising edge 5 ns t SDHD SDI hold time after SCLK rising edge 5 ns t SDOD SDO Delay from SCLK falling edge ni 25 internal PLL generates MCLK from LRCK I2S direct mode ch T SCD Te T LRD www.austriamicrosystems.com 15 Revision 1.11 ns 25 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.5.7 Register Description Table 16. Audio Converter Related Register Base Offset Description DAC_R 2-wire serial 0Eh DAC input volume settings DAC_L 2-wire serial 0Fh DAC input volume settings ADC_R 2-wire serial 10h ADC output volume settings, source multiplexer settings ADC_L 2-wire serial 11h ADC output volume settings, sampling rate settings DAC_IF 2-wire serial 11h DAC input digital volume settings AudioSet1 2-wire serial 14h Enable/disable DAC, DAC gain stage & ADC AudioSet3 2-wire serial 16h Enable/disable mixer input Out_Cntr3 2-wire serial 1A-3h Control of SDO signal and drive PLL 2-wire serial 1A-7h PLL sample rate settings PMU_Enable 2-wire serial 1Ch Enables writings to extended registers 1Ah-3 and 1Ah-7 IRQENRD_1 2-wire serial 25h Interrupt settings for LRCK changes am lc s on A te G nt st il lv al id Name DAC and ADC have to be enabled in register 14h first before other settings in register 0Eh to 11h can be programmed. 8.6 Audio Output Mixer 8.6.1 General The mixer stage sums up the audio signals of the following stages Microphone Input 1 Line Input 1/2 DAC Output ADC Input The mixing ratios have to be set within the volume registers of the corresponding input stages. Please be sure that the peak voltage of input signals for the mixer stage is less than AVDD17/3. If summing up several signals, each individual signal has of course to be accordingly lower. This shall insure that the output signal is also not higher than AVDD17/3 peak to get a proper signal for the output amplifier. This stage features an automatic gain control (AGC), which automatically avoids clipping. Register Description ca 8.6.2 Table 17. Audio Mixer Related Register Name Offset 2-wire serial 15h Enable/disable mixer stage and AGC 2-wire serial 16h Enable/disable DAC, MIC or Line Inputs to mixer stage ni AudioSet2 Base Te ch AudioSet3 Description www.austriamicrosystems.com Revision 1.11 26 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.7 2-Wire-Serial Control Interface 8.7.1 General There is an I2C slave block implemented to have access to 64 byte of setting information. 8Ch_write 8Dh_read 8.7.2 Protocol Table 18. 2-Wire Serial Symbol Definition al id The I2C address is: Adr_Group8 - audio processors Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R DW Device address for write R 1000 1100b (8Ch) DR Device address for read R 1000 1101b 8Dh) Word address R 8 bit Acknowledge W 1 bit No Acknowledge R 1 bit Register data/write R 8 bit Register data/read W 8 bit Stop condition R 1 bit Increment word address internally R during acknowledge lv Symbol am lc s on A te G nt st il 1 bit WA A N reg_data data (n) P WA++ AS3543 (=slave) receives data AS3543 (=slave) transmits data ca Figure 13. Byte Write Te ch ni Figure 14. Page Write Byte Write and Page Write formats are used to write data to the slave. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. www.austriamicrosystems.com Revision 1.11 27 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. lv al id Figure 15. Random Read Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. am lc s on A te G nt st il The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. Figure 16. Sequential Read ca Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. ch ni Figure 17. Current Address Read Te To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a notacknowledge following the last data byte and a subsequent STOP condition. www.austriamicrosystems.com Revision 1.11 28 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s 8.7.3 Parameter DVDD =2.9V, Tamb=25ºC; unless otherwise specified Table 19. 2-Wire Serial Parameter Symbol Parameter Min Typ Max VCSL CSCL, CSDA Low Input Level (max 30%DVDD) 0 - 0.87 V VCSH CSCL, CSDA High Input Level CSCL, CSDA (min 70%DVDD) 2.03 - 5.5 V HYST CSCL, CSDA Input Hysteresis 200 450 800 mV VOL CSDA Low Output Level - - 0.4 V Tsp Spike insensitivity 50 100 - ns TH Clock high time max. 400kHz clock speed 500 ns TL Clock low time max. 400kHz clock speed 500 ns CSDA has to change Tsetup before rising edge of CSCL 250 - - ns No hold time needed for CSDA relative to rising edge of CSCL 0 - - ns CSDA H hold time relative to CSDA edge for start/stop/rep_start 200 - - ns am lc s on A te G nt st il Condition lv al id Figure 18. 2-Wire Serial Timing TSU THD TS at 3mA CSDA prop delay relative to lowgoing edge of CSCL 50 ns Te ch ni ca TPD Unit www.austriamicrosystems.com Revision 1.11 29 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9 Detailed Description - Power Management Functions 9.1 Low Drop Out Regulators 9.1.1 General al id These LDOs are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, micro-controller and other peripheral devices. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices. lv Stability is guaranteed with ceramic output capacitors of 1µF +/-20% (X5R) or 2.2µF +100/-50% (Z5U). The low ESR of these caps ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance. 9.1.2 LDO1 am lc s on A te G nt st il Figure 19. LDO Block Diagram This LDO generates the audio supply voltage used for the AFE itself. Input voltage is VDD17IN Output voltage is AVDD17 (typ. 1.7V) Driver strength: 50mA ca LDO2 ch 9.1.3 ni It is set to a default output voltage of 1.7V, 50mAmax. It supplies the analog audio blocks of the AFE. Additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. Further the external load must not induce noise to the sensitive AVDD17 supply pin. This LDO generates the digital and audio supply voltage used for the AFE itself. Input Voltage is BVDD Output Voltage is AVDD27 (typ. 2.7V) Te Driver strength: 100mA, can be programmed to 200mA It is set to a default output voltage of 2.7V, 100mAmax. It supplies the digital part of the AFE as well as all audio switches and multiplexers. Additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. Further the external load must not induce noise to the AVDD27 supply pin but is not as critical as AVDD17. www.austriamicrosystems.com Revision 1.11 30 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.1.4 LDO3 & LDO4 These LDOs can be used to generate the periphery voltage for the digital processor or other external components (e.g. ext. DAC, USB-PHY, SD-Cards, NAND-Flashes, FM-Tuner …) Input Voltage BVDDP1 or BVDD Output Voltage is PVDD1 & PVDD2 (1.2 to 3.5V) Default value at start-up is defined by VPRG2 pin Driver strength: 100mA, can be programmed to 200mA 9.1.5 al id LDO3 has a separate input pin (BVDDP1) which can be connected to either the battery or a DCDC converter output. Parameter o Table 20. LDO Parameter Parameter R ON On resistance PSRR Power supply rejection ratio I OFF Shut down current I VDD Supply current Noise Output noise t start Startup time V out_tol Output voltage tolerance V LineReg Line regulation V LoadReg Load regulation Condition Min Typ Max Unit 1 Ω am lc s on A te G nt st il Symbol lv BVDD=3.6V, TA= 25 C, unless otherwise mentioned I LIMIT 70 f=100kHz 40 dB 100 nA without load 50 µA 10Hz < f < 100kHz 50 µV rms 200 µs minimum +/- 50mV -2.5% 2.5% LDO2, Static <1 LDO2, Transient; Slope: t r =10µs <10 LDO2, Static <1 LDO2, Transient; Slope: t r =10µs <10 LDO1 100 LDO2, LDO3, LDO4 200 LDO2, LDO3 and LDO4, has to be enabled via register 18h-1, 18h-2, 18h-3 350 mV mV mV mA Te ch ni ca Current limitation f=1kHz www.austriamicrosystems.com Revision 1.11 31 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Figure 20. LDO Block Diagram Output noise am lc s on A te G nt st il lv al id Load regulation transient load: 1mA – 100mA slope: 1µs Load Regulation Output load: 150mA Load Regulation output load: 150mA transient input voltage ripple: 500mV 9.1.6 ca output load: 10mA transient input voltage ripple: 500mV Register Description ni Table 21. LDO Related Register Base Offset 2-wire serial 18h-1 PVDD1 (LDO3) control and voltage settings Description PVDD2 2-wire serial 18h-2 PVDD2 (LDO4) control and voltage settings AVDD27 2-wire serial 18h-6 AVDD27 (LDO2) control and voltage settings AVDD17 2-wire serial 18h-7 AVDD17 (LDO1) control and voltage settings Te ch Name PVDD1 2-wire serial 1Ch PMU_Enable www.austriamicrosystems.com Enables writings to extended registers 18h-1 to 18h-7 Revision 1.11 32 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.2 DCDC Step-Down Converter (2x) 9.2.1 General input Voltage BVDDC1/2 (usually connected to the battery) output Voltage CVDD1 & CVDD2 output voltage levels can be programmed independently form 0.61V to 3.35V the default value at start-up is defined by VPRG1 and VPRG2 pin DVM for both outputs with selectable timings driver strength 250mA under- and over-voltage detection lv al id These converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for microprocessors. ch ni ca am lc s on A te G nt st il Figure 21. DCDC Step-Down Block Diagram Functional Description Te 9.2.2 The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 97% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 250mA, with an output capacitor of only 10µF. The implemented current limitation protects the DCDC and the coil during overload condition. To achieve optimized performance in different applications, adjustable settings allow to compromise between high efficiency and low input, output ripple: www.austriamicrosystems.com Revision 1.11 33 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Low ripple, low noise operation: In this mode there is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the PMOS will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. In the case of an inverted coil current the regulator will not operate in pulse skip mode. am lc s on A te G nt st il lv al id Figure 22. DCDC buck with disabled current force / pulse skip mode 1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage High efficiency operation: In this mode there is a minimum coil current necessary before switching off the PMOS. As result, fewer pulses at low output loads are necessary, and therefore the efficiency at low output load is increased. On the other hand the output voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current. Te ch ni ca Figure 23. DCDC buck with enabled current force / pulse skip mode 1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage It’s also possible to switch between these two modes dynamically during operation: 100% PMOS ON mode for low dropout regulation: For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is than in LDO mode. This feature is enabled if the output voltage drops by more than 4%. www.austriamicrosystems.com Revision 1.11 34 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.2.3 Parameter o BVDD=3.6, TA= 25 C, unless otherwise mentioned Table 22. DCDC Parameter Parameter Condition Min Max Unit VIN Input voltage BVDD 2.7 5.5 V VOUT Regulated output voltage 0.65 3.4 V VOUT_tol Output voltage tolerance Iload Maximum Load current 250 ILIMIT Current limit 450 minimum +/- 50mV Typ -3% al id Symbol 3% P-Switch ON resistance BVDD=3.0V 0.5 N-Switch ON resistance BVDD=3.0V 0.5 fSW Switching frequency depending on DCDC_Cntr settings fSWsc Switching frequency in shortcut case Cout Output capacitor Ceramic, +/- 10% tolerance mA mA 0.7 Ω 0.7 Ω lv RPSW RNSW mV MHz 0.6 MHz 10 µF am lc s on A te G nt st il 1/2 Inductor +/- 10% tolerance Efficiency Iout=100mA, Vout=3.0V 97 % IVDD Current consumption Operating current without load Low power mode current Shutdown current 220 100 0.1 µA tMIN_ON Minimum on time 80 ns tMIN_OFF Minimum off time 40 ns VLineReg Line regulation Static 2 mV Transient; Slope: tr=10µs, 100mV step, 200mA load 10 Load regulation VLoadReg 2.2 4.7 µH Lx ηeff Static 5 Transient; Slope: tr=10µs, 100mA step 50 mV Figure 24. DCDC Step-down Performance Characteristics ca Efficiency vs. Output Current 100 VOUT=3.0V ni 90 VOUT=1.8V VOUT=1.2V ch EFFICIENCY [%] 95 85 Te 80 75 VIN=3.6V 70 0,1 1 10 100 1000 OUTPUT CURRENT [mA] www.austriamicrosystems.com Revision 1.11 35 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Output voltage vs. Output Current Line Regulation 1,225 1,215 1,215 1,205 1,195 IOUT =0mA al id OUTPUT VOLTAGE [V] OUTPUT VOLTAGE [V] 1,21 1,205 IOUT =125mA IOUT =250mA 1,2 1,185 VIN=3.6V 1,195 0 50 100 150 200 250 3 OUTPUT CURRENT [mA] 3,8 4,2 4,6 5 INPUT VOLTAGE [V] am lc s on A te G nt st il 9.2.4 3,4 lv VOUT =1.2V 1,175 Register Description Table 23. DCDC Buck Related Register CVDD1 CVDD2 Offset 2-wire serial 17h-1 CVDD1 (DCDC1) voltage settings 2-wire serial 17h-2 CVDD2 (DCDC2) voltage settings Description 2-wire serial 17h-6 Hibernation control DCDC_Cntr 2-wire serial 17h-7 DCDC frequency and DVM settings PMU_Enable 2-wire serial 1Ch Enables writings to extended registers 17h-1 to 17h-7 Te ch ni Hibernation Base ca Name www.austriamicrosystems.com Revision 1.11 36 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.3 15V Step-Up DCDC Converter 9.3.1 General The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 15V. A constant switching-frequency results in a low noise on supply and output voltages. It has two programable high voltage current sinks (1.2 to 37.2mA) for driving e.g. white LEDs as back-light. It can drive also unbalanced strings due to the internal automatic feedback selection. al id A voltage feedback mode allows generating constant supply voltages for e.g. OLEDs by using an external Zener diode. To bias the diode ISINK1 is sinking about 50uA in this voltage feedback mode. An internal protection circuit will shut down the regulator if the voltage on SW15 exceeds 15V. No more external protection has to be used to avoid an exceeding of the operation conditions in a no load situation. Dimming lv 9.3.2 9.3.3 am lc s on A te G nt st il The DCDC booster together with the current sinks has an adjustable automatic logarithmic dimming for a smooth ON/ OFF transition. It is also possible to control the dimming with an external signal via a GPIO pin. PWGD, Q24M or Q32K pin can be selected as input for the external dimming signal. Current Sink Only Mode The current sinks are normally only working when the DCDC booster is switched on, but can also be activated separately. To do so reg. 1Bh-1 has to be set to 08h (select external dimming), and reg. 1Ah-4 has to be set to xxxx xx00b (no ext. dimming source selected). Te ch ni ca Figure 25. DCDC15 Block Diagram www.austriamicrosystems.com Revision 1.11 37 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.3.4 Parameter o BVDD=3.6V, TA= 25 C, unless otherwise mentioned Table 24. DCDC Parameter Condition V SW High Voltage Pin Pin SW15 I VDD Quiescent Current Pulse Skipping mode V FB Feedback Voltage, Transient Pin ISINK1 or ISINK2 V FB Feedback Voltage, during Regulation Pin ISINK1 or ISINK2 I SW_MAX Current Limit V15_ON = 1 R SW Switch Resistance V15_ON = 0 I LOAD Load Current I FB Current into ISINK1 during voltage feedback mode V PULSESKIP Pulse-skip Threshold F IN Fixed Switching Frequency C OUT Output Capacitor L (Inductor) I LOAD > 20mA t MIN_ON MDC @ 15V output voltage Min Typ 0 Max Unit 15 V 140 0 5.5 0.63 350 510 0.85 0 µA al id Parameter V 750 Ω 45 mA am lc s on A te G nt st il uA Voltage at pin ISINK1 or ISINK2, pulse skips are introduces when load current becomes too low 0.96 0.45 0.66 0.85 1 Use inductors with small C PARASITIC (<100pF) for high efficiency 17 22 27 8 10 27 Minimum On-Time Guaranteed per design 90 Maximum Duty Cycle Guaranteed per design 84 I LOAD < 20mA mA 1.54 50 Ceramic V lv Symbol 91 V MHz µF µH 200 ns 98 % Figure 26. 15V Step-Up Performance Characteristics Efficiency vs. output current ca 95 ni 85 80 ch EFFICIENCY [%] 90 Te 75 VIN=3.6V Load = 3 LEDs 70 1 10 100 OUTPUT CURRENT [mA] www.austriamicrosystems.com Revision 1.11 38 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.3.5 Register Description Table 25. DCDC15 Related Register Base Offset In_Cntr 2-wire serial 1Ah-4 Selection of external dimming input DCDC15 2-wire serial 1Bh-1 DCDC15 on/off and dimming control ISINK1 2-wire serial 1Bh-2 ISINK1 current settings ISINK2 2-wire serial 1Bh-3 ISINK2 current settings PMU_Enable 2-wire serial 1Ch Charger 9.4.1 General Enables writings to extended registers 1Ah1, 1Bh-1 to 1Bh-3 lv 9.4 Description al id Name This block can be used to charge a 4V Li-Ion accumulator. It supports constant current and constant voltage charging modes with adjustable charging currents (55 to 460mA) and maximum charging voltage (3.9 to 4.25V). am lc s on A te G nt st il An internal protection circuit will limit the charging current when a CHGIN voltage drop is detected. For the end of charge current four levels can be selected while the battery temperature shutdown has two temperature levels to choose from. The current battery voltage as well as the actual charging current can be measured with the general purpose ADC. Te ch ni ca Figure 27. Charger Block Diagram www.austriamicrosystems.com Revision 1.11 39 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.4.2 Soft Charge am lc s on A te G nt st il lv al id Figure 28. Charger States If the battery and therefore CHGOUT is below 3V the charger is working in a fixed soft charge mode with the smallest possible charging current of 55mA and 3.9V charger end voltage. After reaching the 3V level the charger switches to the register defined mode and sets the programmed charging current and voltage. 9.4.3 End of Charge Detection For the EOC level 4 presets can be selected. This makes it possible to monitor the charging progress also during constant voltage mode. If the EOC level is reached an interrupt can be generated, but it is also possible to poll the charger status bits at any time. 9.4.4 Temperature Supervision ca This charger block also features a 15uA supply for an external 100k NTC resistor to measure the battery temperature while charging. If the temperature is too high, an interrupt can be generated. If the battery temperature drops the charger will start charging again. The levels for switching off/on the charger (45/42°C or 55/50°C) can be selected via register settings. If the NTC resistor does not have 100kΩ its value can be corrected with a resistor in series or in parallel. Parameter ni 9.4.5 o AVDD27=2.7, TA= 25 C, unless otherwise mentioned ch Table 26. Charger Parameter Parameter Condition Min Typ Max Unit ICHG (0-7) Charging Current BVDD > 2.7V, ICHG > 60mA INOM -8% INOM INOM +8% mA VCHG (0-7) Charging Voltage BVDD > 2.7V, end of charge is true VNOM -50mV VNOM VNOM +30mV V VON_ABS Charger On Voltage IRQ CHGOUT>3V 3.1 4.0 V VON_REL Charger On Voltage IRQ CHGIN-CHGOUT 170 240 mV VOFF_REL Charger Off Voltage IRQ CHGIN-CHGOUT Te Symbol www.austriamicrosystems.com Revision 1.11 40 77 mV 40 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Table 26. Charger Parameter Symbol Parameter Condition VBATEMP_ON Battery Temp. high level (45 or 55°C) BVDD >3V 610 or 400 mV VBATEMP_OFF Battery Temp. low level (42 or 50°C) BVDD >3V 700 or 500 mV ICHG_OFF End Of Charge current level BVDD >3V IREV_OFF Reverse current shut down BVDD = 5V, CHGIN open 5% INOM 10% 30% 50% 70% INOM <1 Register Description Max 15% INOM Unit mA al id Typ uA lv 9.4.6 Min Table 27. Charger Related Register Base Offset CHGVBUS1 2-wire serial 19h-1h Charger voltage, current and temp. supervision control 2-wire serial 19h-2h Charger temperature and EOC level settings 2-wire serial 1Ch Enables writings to extended registers 19h-1 to 19h-2 2-wire serial 25h Enable/disable EOC and battery over-temperature interrupt Read out charger status 2-wire serial 27h Set CHGIN debounce time 2-wire serial 2Eh ADC source selection, ADC result<9:8> 2-wire serial 2Fh ADC result <7:0> CHGVBUS2 PMU_Enable IRQENRD_2 IRQENRD_4 ADC10_0 Te ch ni ca ADC10_1 Description am lc s on A te G nt st il Name www.austriamicrosystems.com Revision 1.11 41 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 9.5 Battery Switch 9.5.1 General An integrated battery switch provides a battery separation during charging. In normal battery operation the switch is closed. With an ideal diode function a smooth transition between the different modes are guaranteed. Te ch ni ca am lc s on A te G nt st il lv al id Figure 29. Battery Switch Modes www.austriamicrosystems.com Revision 1.11 42 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10 Detailed Description - SYSTEM Functions 10.1 SYSTEM 10.1.1 General The system block handles the power up, power down and regulator voltage settings of the AFE. al id The PWGD and XRES outputs can be configured to operate in push/pull (2 different driver strengths) open-drain mode or to be tri-state. For a more detailed description of the GPIO functionality of these pins please refer to chapter GPIO Pins on page 50. 10.1.2 Power Up/Down Conditions # Source Description PWRUP PwUp 2 CHGIN PwUp Charger Plug-In … High level at CHGIN pin of >= 4.0V 3 VBUS PwUp USB Plug-In …. High level at VBUS pin of >= 4.5V 4 WAKEUP PwUp 4 MCLK PwUp am lc s on A te G nt st il 1 ON_KEY High Level at PRWUP pin of >= 1/3 BVDD lv The chip powers up when one of the following condition is true: Table 28. Power UP Conditions Wake-Up Timer power-up on RTC clock ON_KEY High Level at MCLK pin of >= 1/3 BVDD The chip automatically shuts off if one of the following conditions arises: Table 29. Power DOWN Conditions # Source Description Power-Down by SERIF writing 0h to register 20h This Power-Down clears wake-up as well. 1 SERIF MAJOR PwDn 2 Emergency PwDn 3 Wake-Up PwDn write 4h to reg. 1Ch and 0h to reg. 1Ah … disable heartbeat source Write 3 times to reg.22h to define wake-up time; Power-Down by heartbeat without source by writing 9h to reg. 20h 4 Heartbeat PwDn write 4h to reg. 1Ch and 4h/8h or Ch to reg. 1Ah … select HBT source write 9h to reg. 20h … enable heartbeat with source Power-Down if no edge on the selected HBT source is seen for 500ms. 5 SERIF Watch-Dog PwDn ca write 3h to reg. 20h … enable SERIF watch-dog Power-Down if no SERIF read is seen for 500ms. Power-Down if junction temperature rises up to 140degC. This threshold can be lowered with bits <4:0> in reg 21h. This supervisor can be disabled with bit 2 in reg. 20h. ni 6 Power-Down if PWRUP pin is HIGH for 10sec. This time can be reduced to 5sec with bit 7 in register 21h. Junction-Temp PwDn BVDD LOW PwDn Power-Down if AVDD27 LDO has 10% under-voltage for more than 680us. This supervisor can get disabled with bit 6 in reg. 21h. 8 PVDD1 LOW PwDn Power-Down if enabled with bit 1 in reg. 23h and PVDD1 LDO has 10% under-voltage for more than 680us. Te ch 7 9 PVDD2 LOW PwDn Power-Down if enabled with bit 3 in reg. 23h and PVDD2 LDO has 10% under-voltage for more than 680us. 10 CVDD1 LOW PwDn Power-Down if enabled with bit 7 in reg. 23h and CVDD1 DCDC has 10% under-voltage for more than 680us. 11 CVDD2 LOW PwDn Power-Down if enabled with bit 1 in reg. 24h and CVDD2 DCDC has 10% under-voltage for more than 680us. www.austriamicrosystems.com Revision 1.11 43 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10.1.3 Start-up Sequence The AFE offers different power-up sequences. While VPRG1 and VPRG2 pins are defining the regulator voltages VPRG3 is setting the sequence of powering on the regulators during the start-up. These pins detect 5 logical input states which shall come from an external resistor divider network. At first, LDO2 (AVDD27) and LDO1 (AVDD17) are powered up. This cannot be influenced with the selection of specific sequences below. LDO2 is necessary for the internal supply of the AFE, LDO1 could be turned off later if no audio functionality is needed. CVDD1 CVDD2 PVDD1 PVDD2 vdd lv VPRG1 (core) 0.8V 150k PU 1.5V open 1.2V 2 150k PD vss am lc s on A te G nt st il 1 al id After power-up sequence all voltage settings and power on/off conditions of the described regulators can be programmed via the serial interface Table 30. Start-Up Sequence 1.0V VPRG2 (peri) vdd 150k PU open 150k PD vss VPRG3 (sequence) vdd 1 150k PU open 1 3 150k PD vss 3.3V 3.3V 2.8V 1.8V 3.3V 1.8V 3.3V 3.3V 3.3V 3.3V 3.3V st st rd rd nd rd 2 3 nd rd 2 3 nd 2 1 nd 2 1 st st off rd 3 1 st off ca 3 2.5V ni 1. pull ups (PU) must be connected to AVDD27 2. pull downs (PD) shall be connected to DVSS 10.1.4 XRES delay with PWGD pin Te ch With using an exteral capacitor on PWGD, the XRES signal can be delayed. This delay can be calculated with the 10uA pull-up current and a comparator threshold of ~1V. Using a 100nF capacitance will give a delay of 10ms. www.austriamicrosystems.com Revision 1.11 44 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10.1.5 Register Description Table 31. System Related Register Base Offset Out_Cntr1 2-wire serial 1A-1h Control of PWGD and XRES signal and drive In_Cntr 2-wire serial 1A-4h Selection of HBT input pin PMU_Enable 2-wire serial 1Ch Enables writings to extended registers 1Ah-1 and 1Ah-5 SYSTEM 2-wire serial 20h Watchdog and Over-temperature control, Power down enable SUPERVISOR 2-wire serial 21h Set emergency shutdown time IRQENRD_0 2-wire serial 23h Enable/disable PMU interrupts IRQENRD_1 2-wire serial 24h Enable/disable wake-up, voice and PMU interrupts IRQENRD_2 2-wire serial 25h Enable/disable charger, USB and supervisor interrupts IRQENRD_3 2-wire serial 26h Enable/disable junction temperature interrupt lv Hibernation 10.2.1 General am lc s on A te G nt st il 10.2 Description al id Name Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible interrupt of the AFE. E.g. one can use the RTC for a time triggered wake-up. The interrupt has to be enabled before going to hibernation.: Table 32. Hibernation Enter Hibernation VDD27 chip supply is kept ON All other regulators are switched OFF dependent on the KEEP-Bits XRES goes active and PWGD goes inactive. The chip will come out of Hibernation with IRQ activation. Start-Up sequence is provided defined by the VPRG state latched on the previous Start-Up. (VPRG state does not get latched again by leaving hibernation) ni Leave Description To enter hibernation mode the following settings have to be done: - Enable just these IRQ sources which should lead to leave hibernation mode. - Make sure that IRQ is inactive (IRQ flags get cleared by Reg0x23-27 readings. - Define which regulators should be kept powered and enter hibernation by writing to Reg 1Ch_0x06 + Reg 17h_0xXX Note that hibernation will shutdown regulators which are not in the keep list of the mentioned Reg 17h writing and which are powered by the selected power-up sequence. (e.g. PVDD2 will not go hibernation with VPRG3 is vss or vdd) ca State 10.2.2 Register Description ch Table 33. Hibernation Related Register Base Offset Hibernation 2-wire serial 17h-6 PMU_Enable 2-wire serial 1Ch Description Hibernation control Enables writings to extended register 17h-6 Te Name www.austriamicrosystems.com Revision 1.11 45 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10.3 Supervisor 10.3.1 General This supervisor function can be used for automatic detection of BVDD brown out or junction over-temperature condition. 10.3.2 BVDD Supervision al id The BVDD supervision interrupt level is set to 175mV above regulator output AVDD27. When BVDD reaches this level an interrupt can be generated. If AVDD27 reaches the “programmed level of AVDD27” -10% for more than 680us, the AFE shuts down automatically, if the shutdown is not disabled. 10.3.3 Junction Temperature Supervision lv The temperature supervision level can also be set by 5 bits (120 to –15ºC). If the temperature reaches this level, an interrupt can be generated. The over-temperature shutdown level is always 20ºC higher. am lc s on A te G nt st il 10.3.4 Power Rail Monitoring The 4 main regulators as well as the DCDC15 booster and the system supply AVDD27 have an extra monitor which observes the output voltage of the regulators. This power rail monitors are independent from the 10bit ADC. To activate these please see related registers. For a shut down the voltage of the regulator has to be 10% or more below the programmed value for more than 680us. 10.3.5 Register Description Table 34. Supervisor Related Register Name SUPERVISOR IRQENRD_0 IRQENRD_1 IRQENRD_2 IRQENRD_3 IRQENRD_4 Offset Description 2-wire serial 21h Low battery shutdown disable and junction temperature supervision threshold levels 2-wire serial 23h Enable/disable PVDD/CVDD monitoring interrupt and shutdown 2-wire serial 24h Enable/disable PVDD/CVDD monitoring interrupt and shutdown 2-wire serial 25h Enable/disable battery brown out interrupt 2-wire serial 26h Enable/disable junction temperature interrupt 2-wire serial 27h Enable/disable AVDD27 and DCDC15 monitoring interrupt Interrupt Generation 10.4.1 General ca 10.4 Base ni All interrupt sources can get enabled or disabled by corresponding bits in the 5 IRQ-bytes. By default no interrupt source is enabled. ch The XIRQ output can be configured to operate in push/pull (2 different driver strengths), open-drain mode or to be tristate. The signal polarity can be defined as active-low or active-high. Default state is open-drain active-low. For a more detailed description of the GPIO functionality of this pin please refer to chapter GPIO Pins on page 50. 10.4.2 IRQ Source Interpretation Te There are 3 different modules to process interrupt sources: LEVEL The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled EDGE The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read. www.austriamicrosystems.com Revision 1.11 46 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s STATUS CHANGE The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source. The IRQ stays active until the corresponding interrupt register gets read. 10.4.3 De-bouncer al id There is a de-bounce function implemented for USB and CHARGER. Since these 2 signals can be unstable for the phase of plug-in or unplug, a de-bounce time of 512ms/256ms/128ms/8ms can be selected by 2 bits in the IRQ_ENRD_4 register (27h). 10.4.4 Interrupt Sources 26 IRQ events will activate the XIRQ pin: Headphone connected Headphone over-current Microphone connected Microphone remote control Voice activation threshold reached RTC sec/min elapsed 10bit ADC end of conversion I²S changed (active/inactive) USB changed (connect/disconnect) Charger changed (end of charge or connect/disconnect) Battery temperature high (at 45ºC or 55ºC with 100kΩ NTC) Junction temperature high RTC watchdog (e.g. after battery was changed) Battery low (Brown-out voltage reached) Wake-up from hibernation Power-up key (pin PWRUP) pressed Power rail monitor: over-voltage PVDD1, PVDD2, CVDD1, CVDD2, DCDC15 Power rail monitor: under-voltage PVDD1, PVDD2, CVDD1, CVDD2, AVDD27 am lc s on A te G nt st il lv ca 10.4.5 Register Description Table 35. Interrupt Related Register Name Offset 2-wire serial 1A-3h ni Out_Cntr3 Base Description Control of XIRQ signal, polarity and drive 2-wire serial 1Ch Enables writings to extended register 1Ah-3 and 1Ah-5 IRQENRD_0 2-wire serial 23h Enable/disable PMU interrupts ch PMU_Enable 2-wire serial 24h Enable/disable wake-up, voice and PMU interrupts IRQENRD_2 2-wire serial 25h Enable/disable charger, USB and supervisor interrupts IRQENRD_3 2-wire serial 26h Enable/disable junction temperature, headphone, microphone and I2S interrupt 2-wire serial 27h Enable/disable PMU, RTC, ADC10 and microphone interrupt, set VBUS and CHGIN debounce time Te IRQENRD_1 IRQENRD_4 www.austriamicrosystems.com Revision 1.11 47 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10.5 Real Time Clock 10.5.1 General The real time clock block is an independent block, which is still working even when the chip is shut down. The only condition for this operation is that BVDDR has a voltage of above 1.0V. The block uses a standard 32kHz crystal that is connected to a low power oscillator. The total power consumption is typ. 650nA. (Q32K clock buffer not operating) al id An internal supply switch will supply the RTC as long as possible form the Li-Ion battery and only switch to BVDDR if the main battery is empty or has been removed. The RTC seconds counter is 32bit wide and can be programmed via the 2-wire serial interface. The RTC can deliver a second or minute interrupt. Another 23bit wide counter allows auto wake-up (max. after 96 days). This counter is internally connected to the power-up and hibernation control block. lv The RTC voltage regulator (RVDD) further supplies a 128bit SRAM. It can be used to store settings or data before shutdown. am lc s on A te G nt st il The Q32K output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. For a more detailed description of the GPIO functionality of this pin please refer to chapter GPIO Pins on page 50. 10.5.2 Clock Adjustment The RTC clock is adjustable in steps of 7.6ppm which allows the use of inexpensive 32kHz crystals. The nominal frequency shall be 32.768Hz. This frequency is divided down to 0.25Hz: f = 32.768 / (4*32*1024) At the input of this divider one can add corrective counts, which allow to correct an inaccurate crystal in a range from – 64 counts (=-488ppm) to +63 counts (=+480ppm): fcorrected = fcrystal / [(4*32*1024)-64+RTC_TBC] 10.5.3 Register Description Table 36. RTC Related Register Out_Cntr2 PMU_Enable IRQENRD_2 IRQENRD_4 RTC_Cntr RTC_Time Offset 19h Description 2-wire serial 1A-2h 2-wire serial 1Ch Enables writings to extended register 1Ah-2 2-wire serial 25h Interrupt settings for RVDD under-voltage detection 2-wire serial 27h Interrupt settings for getting a second or minute interrupt RTC wake-up settings and SDRAM access Control of Q32K signal and drive 2-wire serial 28h RTC oscillator and counter enable, free usable bits 2-wire serial 29h RTC interrupt and time correction settings 2-wire serial 2Ah to 2Dh RTC time-base seconds registers Te ch ni RTC_0 to RTC_3 Base 2-wire serial ca Name RAM & WakeUp www.austriamicrosystems.com Revision 1.11 48 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10.6 10-Bit ADC 10.6.1 General This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, button press detection, etc. 10.6.2 Input Sources # Source Range LSB al id Table 37. ADC10 Input Sources Description BVDD 5.120V 5mV check main system input voltage 1 BVDDR 5.120V 5mV check RTC backup battery voltage 2 CHGIN 5.120V 5mV check charger input voltage 3 CHGOUT 5.120V 5mV check battery voltage of 4V Li-Ion accumulator 4 VBUS 5.120V 5mV check USB input voltage 5.120V 5mV Source defined by DC_TEST in register 18h 6 BatTemp 7 8 2.048V 2mV check battery charging temperature 2.048V 2mV check voltage on MICS for remote control or external voltage measurement reserved MICS 9 A am lc s on A te G nt st il 5 lv 0 reserved I_MICS 1.024mA typ. B 2uA check current of MICS for remote control detection reserved VBE_1uA D VBE_2uA E I_CHGact F I_CHGref 10.6.3 Parameter 1.024 1mV measuring basis-emitter voltage of temperature sense transistor; Tj = (674 - ADC10<9:0>) / 2 1.024 1mV measuring basis-emitter voltage of temperature sense transistor; Tj = (694 - ADC10<9:0>) / 2 1.024V 1mV check active charger current 1.024V 1mV check reference charger current ca C o Symbol ADCFS Parameter Condition Typ Max 2.16 Unit V Conversion Time - 34 50 µs I_MICS Full Scale Range 0.7 1.0 1.4 mA Te I_MICFS Min ADC Full Scale Range ch TCON ni AVDD27=2.7, TA= 25 C, unless otherwise mentioned Table 38. ADC10 Parameter www.austriamicrosystems.com Revision 1.11 49 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10.6.4 Register Description Table 39. ADC10 Related Register Base Offset PMU_Enable 2-wire serial 1Ch Extended ADC source selection IRQENRD_4 2-wire serial 27h Interrupt settings for end of conversion interrupt ADC10_0 2-wire serial 2Eh ADC source selection, ADC result<9:8> ADC10_1 2 wire serial 2Fh ADC result <7:0> 10.7 Description GPIO Pins 10.7.1 General al id Name lv PWGD, XRES, Q24M, Q32K, SDO, XIRQ are so called GPIO (general purpose inputs/outputs) as they can feature auxiliary functionality. am lc s on A te G nt st il If the main pin function is not needed all pins can provide internal clocks or can drive a static HIGH or LOW. Four different clock lines (CLKINT1, CLKINT2, CLK24M, CLK32K) can be selected. Each of these clock lines can drive different frequencies which can be set by register options. In addition some pins can provide a PWM signal. The duty cycle of the PWM output can also be set in the registers. PWGD, XRES and XIRQ can be configured also as open drain outputs. For all pins the driver strength of the push/pull output mode can be selected. PWGD, Q24M, Q32K can also be used as inputs for a heartbeat signal or an external dimming signal for the DCDC15 booster. 10.7.2 Internal Source Signals CLKINT1 Signal This is an internal signal line which can drive pre defined frequencies of 125Hz, 1kHz, 667kHz or 2MHz. This signal line can be selected as source for the XRES, Q24M, Q32K, XIRQ and SDO GPIO output pins. CLKINT2 Signal This is an internal signal line which can drive the PLL clock, the clock for the logarithmic dimming of DCDC15 or can be set to static HIGH/LOW. This signal line can be selected as source for the PWGD, Q24M, Q32K and XIRQ output pins. CLK24M Signal CLK32K Signal ca This is an internal signal line which is driving the 12-24MHz oscillator output clock per default, but can be set to drive this clock divided by 2 or 4. The forth option is to deactivate the 12-24MHz oscillator. ni This is an internal signal line which is driving the 32kHz oscillator output clock per default, but can be set to drive also a 1Hz signal as well as a a static HIGH/LOW. PWM Signal ch The duty cycle of the PWM signal can be set in 128 steps plus an option to invert the signal. It ca be used as source for all GPIO outputs other than XIRQ. Te 10.7.3 Pin Functions PWGD Pin Can drive CLK24M, CLKINT2 or the PWM signal as auxiliary function. The output can be configured to operate in push/pull (2 different driver strength) open-drain mode or to be trie-state. It can be used as an input for a heartbeat, external dimming signal or as additional source for the 10-bit general purpose ADC. Using a capacitor on this pin will delay the XRES signal. Please refer to chapter XRES delay with PWGD pin on page 44. When usig the pin as an ADC input the voltage to be measurted has to be higher than 1V, the XRES delay functionality is than no longer avilable. www.austriamicrosystems.com Revision 1.11 50 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s XRES Pin Can drive CLK32K, CLKINT1 or the PWM signal as auxiliary function. The output can be configured to operate in push/ pull (2 different driver strengths) open-drain mode or to be trie-state. The XRES signal can be delayed by using a capacitor on PWGD pin. Please refer to chapter XRES delay with PWGD pin on page 44. Q24M Pin al id Can drive CLKINT1, CLKINT2 or the PWM signal as auxiliary function. The output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. It can be used as an input for a heartbeat or external dimming signal. Q32K Pin lv Can drive CLKINT1, CLKINT2 or the PWM signal as auxiliary function. The output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. It can be used as an input for a heartbeat or external dimming signal. XIRQ Pin SDO Pin am lc s on A te G nt st il Can drive CLKINT1, CLKINT2 signal as auxiliary function. The output can be configured to operate in push/pull (2 different driver strengths) open-drain mode or to be trie-state. The interrupt signal polarity can be defined as active-low or active-high. Can drive CLK24M, CLKINT1 or the PWM signal as auxiliary function. The output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. 10.7.4 Register Description Table 40. GPIO Related Register Out_Cntr1 Out_Cntr2 Out_Cntr3 In_Cntr Clk_Cntr PWM_Cntr PMU_Enable 10.8 Base Offset Description 2-wire serial 1A-1h Control of PWGD and XRES signal and drive 2-wire serial 1A-2h Control of Q32K signal and drive 2-wire serial 1A-3h Control of XIRQ signal, polarity and drive 2-wire serial 1A-4h Selection of HBT and DCDC 15 dimming input pin 2-wire serial 1A-5h Selection of clock source or drive level for GPIO pins 2-wire serial 1A-6h PWM duty cycle and polarity settings 2-wire serial 1Ch Enables writings to extended registers 1Ah-1 to 1Ah-6 ca Name 12-24MHz Oscillator ni 10.8.1 General ch This oscillator can be used to generate a system clock for e.g. a microprocessor if needed. It is not needed for any other AFE function. As the oscillator is default ON, it has to be disabled if not needed. 10.8.2 Register Description Table 41. 12-24MHz Oscillator Related Register Base Offset Clk_Cntr 2-wire serial 1A-5h PMU_Enable 2-wire serial 1Ch Te Name www.austriamicrosystems.com Description Enable/disable oscillator and clock divider settings Enables writings to extended registers A1Ah-5 Revision 1.11 51 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s 10.9 Unique ID Code (64 bit OTP ROM) 10.9.1 General This fuse array is used to store a unique identification number, which can be used for DRM issues. The number is generated and programmed during the production process. Table 42. UID Related Register Base UID_0 to UID_7 2-wire serial Offset Description 38h to 3Fh Unique ID register 0 to 7 Te ch ni ca am lc s on A te G nt st il lv Name al id 10.9.2 Register Description www.austriamicrosystems.com Revision 1.11 52 - 91 b7 b6 b5 0: HP; 1: LOUT 0: SUM; 1: DAC; 2: LIN1(2); 3: MIC 03h OUT_L MUTE_K_ON STAGE_ON 04h 05h reserved reserved MIC_MODE PRE_GAIN<1:0> 06h MIC_R 0: MonoDiff 1: SingleEnd 0: 30dB; 1: 36dB; 2: 42dB; 3: reserved 07h MIC_L MSUP_OFF MUTE_D_ON 08h 09h reserved reserved LI_HIQ MUX_E 0Ah LINE_IN_R 0: LowPwr 1: HiQuality 0: LIN1 1: LIN2 0Bh LINE_IN_L 0Ch 0Dh reserved reserved 0Eh b3 b2 OUTR_VOL<4:0> Gain from MUX_C to HPR/LOUTR= -40.5dB...+6dB HPDET_ON OUTL_VOL<4:0> Gain from MUX_C to HPL/LOUTL= -40.5dB…+6dB am lc s on A te G nt st il MUX_C<1:0> OUT_R MICR_VOL<4:0> Gain from MicAmp (N4) to Mixer (N12) = -40.5dB...+6dB - MICL_VOL<4:0> Gain from MicAmp (N4) to Mixer (N13) = -40.5dB...+6dB MUTE_B_OFF LIR_VOL<4:0> Gain from MUX_E (N27) to Mixer (N10) = -40.5dB...+6dB LO_DISCHG_O LI_MODE 0: stereo FF 1: mono MUTE_G_OFF LIL_VOL<4:0> Gain from MUX_E (N28) to Mixer (N17) = -40.5dB...+6dB DAC_R - - - 0Fh DAC_L - - 10h ADC_R 0: MIC; 1: LIN1; 2: LIN2; 3: SUM 11h ADC_L 0: Fdac/2; 1: Fdac/4; 2,3: Fdac/1 MUTE_H_OFF ADR_VOL<4:0> Gain from MUX_A to ADC/Mixer (N9) = -34.5dB...+12dB MUTE_A_OFF ADL_VOL<4:0> Gain from MUX_A to ADC/Mixer (N18) = -34.5dB...+12dB 53 - 91 ch ADC_MODE<1:0> Te DAR_VOL<4:0> Gain from DAC (N19) to Mixer (N23) = -40.5dB…+6dB DAL_VOL<4:0> Gain from DAC (N22) to Mixer (N26) = -40.5dB…+6dB - ni MUX_A<1:0> ca Revision 1.11 LOUT 02h b4 al id Name b1 lv Addr Audio Registers 00h reserved 01h reserved b0 AS3543 3v2 Table 43. I2C Register Overview Data Sheet - R e g i s t e r D e f i n i t i o n www.austriamicrosystems.com 11 Register Definition b6 b5 I2S_ATTEN b4 b3 b2 SDI_ATTEN<4:0> Attenuation of I2S input data = -48dB...-1.5dB 12h DAC_IF I2S_DIRECT I2S_LOOP 0: NoAtten 1: AttenON 13h 14h reserved AudioSet1 ADC_ON DAC_ON DAC_GST_ON - 15h AudioSet2 BIAS_OFF SUM_OFF SUM_AGC_OF SUM_HP_HIQ F 16h AudioSet3 - MICMIX_OFF - 0: 2ms; 1: 4ms; 2: 8ms; 3: no control LINMIX_OFF VMICS<1:0> PMU Register b0 MIC_ON 0: VDD17*20/17, 1: VDD17*20/22 2: VDD17*20/27, 3: VDD17*20/32 HP_FASTSTAR HP_BIAS 0: *1 T 1: *1.5 am lc s on A te G nt st il ADCMIX_ON LIN_ON GAIN_STEP<1:0> b1 al id b7 lv Name HPCM_ON VSEL_CVDD1>6:0> 17h-1 CVDD1 PROG_CVDD1 0 … OFF 0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V) 0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V) 0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V) Revision 1.11 VSEL_CVDD2<6:0> 0 … OFF 0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V) 0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V) 0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V) 17h-2 CVDD2 PROG_CVDD2 17h-3 17h-4 17h-5 17h-6 - KEEP_PVDD2 KEEP_PVDD1 - reserved reserved reserved Hibernation CVDD2_fast CVDD1_fast CVDD2_freq CVDD1_freq 17h-7 DCDC_Cntr 0: Cext=10uF 1: Cext=22uF 0: Cext=10uF 1: Cext=22uF 0: 2MHz 1: 1MHz 0: 2MHz 1: 1MHz 18h-1 PVDD1 PVDD1_OFF 18h-2 PVDD2 PVDD2_OFF ca ILIM_H_PVDD1 0: 100mA 1: 200mA PRG_PVDD1 ILIM_H_PVDD2 PRG_PVDD2 ni ch Te 54 - 91 18h-3 reserved 18h-4 reserved 18h-5 reserved 0: 100mA 1: 200mA DVM_CVDD2<1:0> KEEP_CVDD2 KEEP_CVDD1 DVM_CVDD1<1:0> 0: immediate; 1: 42us/step; 2: 166us/step; 3: 666us/step 0: immediate; 1: 42us/step; 2: 166us/step; 3: 666us/step VSEL_PVDD1<4:0> 0x00 – 0x0F: 1.2V + VSEL * 50mV -> (1.2V – 1.95V) 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV ->(2.0V – 3.5V) VSEL_PVDD2<4:0> 0x00 – 0x0F: 1.2V + VSEL * 50mV -> (1.2V – 1.95V) 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV ->(2.0V – 3.5V) AS3543 3v2 Addr Data Sheet - R e g i s t e r D e f i n i t i o n www.austriamicrosystems.com Table 43. I2C Register Overview b6 ILIM_H_VDD27 b5 18h-6 AVDD27 - 0: 100mA 1: 200mA PRG_AVDD27 18h-7 AVDD17 AVDD17_OFF - PRG_AVDD17 19h-1 CHGVBUS1 BAT_TEMP_OF CHG_I<2:0> 0..3: 55, 70, 140, 210mA F 4..7: 280, 350, 420, 460mA b4 - b3 VSEL_AVDD27<3:0> VSEL_AVDD17<4:0> 0x00 – 0x1F: 1.65V + VSEL * 50mV -> (1.65V – 3.2V) CHG_V<2:0> 3.9V + CHG_V * 50mV -> (3.9V – 4.25V) DRIVE_PWGD<1:0> 1Ah-1 Out_Cntr1 0: 6mA OD; 1: 6mA PP; 2: 1mA PP; 3: HiZ DRIVE_Q24M<1:0> 1Ah-2 Out_Cntr2 0: 6mA PP; 1: HiZ; 2: 2mA PP; 3: 1mA PP DRIVE_SDO<1:0> Revision 1.11 1Ah-3 Out_Cntr3 0: 6mA PP; 1: HiZ; 2: 2mA PP; 3: 1mA PP 1Ah-4 In_Cntr - - CLKINT2<1:0> 1Ah-5 Clk_Cntr 0: CLKPLL; 1: CLKlogdim; 2: LOW; 3: HIGH 1Ah-6 PWM_Cntr PWM_INVERT - b0 - CHG_OFF BAT_TEMP CHG_EOC_TH<1:0> 0: 0.4/0.5V; 1: 0.6/0.7V 0: 10% CC; 1: 30% CC; 2: 50% CC; 3: 70% CC am lc s on A te G nt st il - 0: 4.5V; 1: 3.18V; 2: 1.5V; 3: 0.6V b1 0x0 – 0x2: 2.3V 0x3 – 0xF: 2.0V + VSEL* 100mV ->(2.3V – 3.5V) VBUS_COMP_TH <1:0> 19h-2 CHGVBUS2 b2 al id b7 lv Name MUX_PWGD<1:0> DRIVE_XRES<1:0> MUX_XRES<1:0> 0: PWGD; 1: CLK24M; 2: CLKINT2; 3: PWM 0: 6mA OD; 1: 6mA PP; 2: 1mA PP; 3: HiZ 0: XRES; 1: CLK32K; 2: CLKINT1; 3: PWM MUX_Q24M<1:0> DRIVE_Q32k<1:0> MUX_Q32k<1:0> 0: CLK24M; 1: CLKINT1; 2: CLKINT2; 3: PWM 0: 6mA PP; 1: HiZ; 2: 2mA PP; 3: 1mA PP 0: CLK32K; 1: CLKINT1; 2: CLKINT2; 3: PWM MUX_SDO<1:0> DRIVE_XIRQ<1:0> MUX_XIRQ<1:0> 0: SDO; 1: CLK24M; 2: CLKINT1; 3: PWM 0: 6mA OD; 1: 6mA PP; 2: 1mA PP; 3: HiZ 0: XIRQ; 1: CLKINT1; 2: CLKINT2; 3: IRQ MUX_HBT<1:0> MUX_ExtDim<1:0> 0: OFF; 1: PWGD; 2: Q24M; 3: Q32K 0: OFF; 1: PWGD; 2: Q24M; Q32K CLKINT1<1:0> CLK24M<1:0> CLK32k<1:0> 0: 2MHz; 1: 667kHz; 2: 1kHz; 3: 125Hz 0: OSC24M; 1: OSC24M_div2; 2: OSC24M_div4; 3: OSC24M_PD 0: OSC32k; 1: 1Hz; 2: LOW; 3: HIGH VCO_MODE<1:0> PLL_MODE<1:0> 0: 24-48kHz; 1: 8-23kHz; 2: 49-96kHz; 3: n/a 0: automatic; 1: ON; 2: OFF; 3: auto_inv - - PWM_CYCLE<6:0> 0: no pulses; 1-127: duty cycle = PWM_CYCLE * 0.39% OSR<3:0> DIM_UP_XDO WN I_SINK1<4:0> 1Bh-2 ISINK1 DIM_RATE<1:0> 0: 0ms; 1: 300ms; 2: 600ms; 3: 1200ms 0: OFF; 1-31: 1.2mA *I;_ISINK1 -> (1.2mA...37.2mA) 0: OFF; 1-31: 1.2mA *I;_ISINK2 -> (1.2mA...37.2mA) Te 55 - 91 ch I_SINK2<4:0> 1Bh-3 ISINK2 ca 1Bh-1 DCDC15 0x0: 128; 0x1-0xF: n/a ni 1Ah-7 PLL VFB_ON ExtDim_ON - - - AS3543 3v2 Addr Data Sheet - R e g i s t e r D e f i n i t i o n www.austriamicrosystems.com Table 43. I2C Register Overview b6 b5 b4 b3 DC_TEST_MUX <3:0> 1Ch PMU_Enable 0: open; 1: AVDD27; 2: AVDD17; 3: PVDD1; 4: PVDD2; 5: CVDD1; 6: CVDD2; 7: RVDD; 8: FVDD; 9: PWGD; A-F: not defined PMU_GATE System Register 20h SYSTEM 1: 5s VDD27-10% 1st write/read: WAKE_UP_BYTE_0 128s 64s 2nd write/read: WAKE_UP_BYTE_1 RAM & WakeUp 32ks 16ks 3rd write/read: WAKE_UP_BYTE_2 WAKEUP_ ON 4Ms 8s 4s 2s 1s 8ks 4ks 2ks 1ks 512s 256s 2Ms 1Ms 512ks 256ks 128ks 64ks PVDD2_SD PVDD2_under - PVDD2_IRQ PVDD2_over - USB_CON I2S_IRQ I2S_changed - USB_IRQ USB_changed VOXM_IRQ PVDD1_SD PVDD1_under CVDD2_SD CVDD2_under RTC_WD PVDD1_IRQ PVDD1_over CVDD2_IRQ CVDD2_over BVDD_LOW MIC_CON HPH_CON RTC_UPDATE ADC_EOC RTC_ON OSC_ON IRQENRD_0 24h IRQENRD_1 25h IRQENRD_2 26h IRQENRD_3 27h IRQENRD_4 0: 512ms; 1: 256ms; 2: 128ms; 3: 8ms 28h 29h 2Ah RTC_Cntr RTC_Time RTC_0 Free_Bits<3:0> to be used for application purpose IRQ_MIN TRTC<6:0> QRTC<7:0> CHG_CON HP_OVC ca BATTEMP_IRQ CHG_EOC JTEMP_HIGH - 56 - 91 ch PWR_HOLD 16s 23h Te I2C_WD_ON Temp_ShutDown = 140°C - JTEMP_SUP*5°C -> (140°C...- 15°C) TEmp_IRQ = 120°C - JTEMP_SUP*5°C -> (120°C...-35°C) 4th to 19th write/read: non volatile memory bytes<0:15> SRAM_128<0:15> CVDD1_SD CVDD1_IRQ CVDD1_under CVDD1_over PWRUP_IRQ WAKEUP_IRQ MCLK_IRQ - T_DEB<1:0> JTEMP_OFF JTEMP_SUP<4:0> 32s AVDD27_IRQ ni Revision 1.11 22h HB_WD_ON b0 SubRegister addresses for registers: 0x17: DCDC regulators 0x18: LDOs regulators 0x19: Charger 0x1A: IO_clock_control 0x1B: BackLight_DCDC am lc s on A te G nt st il 21h Design_Version<3:0> BVDDlow_SD_ SD_TIME SUPERVISOR 0: 10s; OFF b2 b1 PMU_WR_ENABLE <2:0> al id b7 lv Name CHG_IRQ CHG_changed I2S_status DCDC15_IRQ REM_DET AVDD27_under DCDC15_over - AS3543 3v2 Addr Data Sheet - R e g i s t e r D e f i n i t i o n www.austriamicrosystems.com Table 43. I2C Register Overview ADC10_0 0: BVDD; 1: BVDDR; 2: CHGIN; 3: CHGOUT; 4: VBUS 5: DC_TEST; 6: BATTEMP; 7: MCLK; 8: MICS; A: I_MICS; C: VBE_1uA; D: VBE_2uA; E: I_CHGact; F: I_CHGref 2Fh ADC10_1 ADC10<7:0> b4 b3 - b2 - b1 Te 57 - 91 ch ni ca Revision 1.11 ID<7:0> ID<15:8> ID<23:16> ID<31:24> ID<39:32> ID<47:40> ID<55:48> ID<63:56> b0 al id b5 ADC10<9:8> lv 2Eh UID Register 38h UID_0 39h UID_1 3Ah UID_2 3Bh UID_3 3Ch UID_4 3Dh UID_5 3Eh UID_6 3Fh UID_7 b6 am lc s on A te G nt st il b7 QRTC<15:8> QRTC<23:16> QRTC<31:24> ADC10_MUX<3:0> AS3543 3v2 Addr Name 2Bh RTC_1 2Ch RTC_2 2Dh RTC_3 Data Sheet - R e g i s t e r D e f i n i t i o n www.austriamicrosystems.com Table 43. I2C Register Overview AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 44. OUT_R Register Name Base Default OUT_R 2-wire serial 00h Right HP/Line Output Register Bit Bit Name Default Access 7 LOUT 0 R/W Switches between headphone and line output 00: headphone enabled 01: line out enabled 6:5 MUX_C<1:0> 00 R/W Multiplexes the analog audio inputs to MUX_C output for HPR/L and LOUTR/L 00: Mixer: ΣR to HPR/LOUTR and ΣL to HPL/LOUTL 01: DAC direct : (N19/ N22), DAC gain stage and mixer are bypassed 10: LineIn direct (N10/N17) 11: Mic direct (N12/N13) 4:0 OUTR_VOL<4:0> am lc s on A te G nt st il lv Bit Description al id Configures MUX_C and the audio gain from MUX_C output to HPR/LOUTR output and switches between the headphone and line output. This register is reset when the block is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled. Offset: 02h 00000 R/W volume settings for right headphone/line output, adjustable in 32 steps @ 1.5dB; gain from MUX_C to HPR/LOUTR 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain Table 45. OUT_L Register Name Base Default OUT_L 2-wire serial 00h Left HP/Line Output Register Configures the audio gain from MUX_C output to HPL/LOUTL output and controls MUTE switch K as well as on/off of the stage. This register is reset when the stage is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled ca Offset: 03h Bit Name Default Access 7 MUTE_K_ON 0 R/W Control of MUTE switch K 0: HP/line output set to mute 1: normal operation 6 STAGE_ON 0 R/W 0: HP/line stage not powered 1: normal operation 5 HPDET_ON 0 R/W Enables the detection when a headset gets connected. HPCM is used as a sense pin and is biased to 150mV 0: no headphone detection 1: enable headphone detection 00000 R/W volume settings for left headphone/line output, adjustable in 32 steps @ 1.5dB; gain from MUX_C to HPL/LOUTRL 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain Te ch ni Bit 4:0 OUTL_VOL<4:0> www.austriamicrosystems.com Bit Description Revision 1.11 58 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 46. MIC_R Register Name Base Default MIC_R 2-wire serial 00h Right Microphone Input Register al id Configures MUX_C and the audio gain from MUX_C output to HPR/LOUTR output and switches between the headphone and line output. This register is reset at a AVDD27-POR. Offset: 06h Bit Name Default Access Bit Description 7 MIC_MODE 0 R/W Selects the microphone input mode 0: mono differential mode 1: single ended mode 6:5 PRE_GAIN<1:0> 00 R/W Sets the gain of the microphone preamplifier (gain from microphone inputs to N3) 00: gain set to 30 dB 01: gain set to 36 dB 10: gain set to 42 dB 11: reserved, do not use. 4:0 MICR_VOL<4:0> am lc s on A te G nt st il lv Bit 00000 R/W volume settings for right microphone input, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N4) to mixer input (N12) 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain Table 47. MIC_L Register Name Base Default MIC_L 2-wire serial 00h Left Microphone Input Register Configures the gain from microphone amplifier output up to mixer input (Σ) and controls MUTE switch D. This register is reset at a AVDD27-POR. Offset: 07h Bit Name Default Access 7 MSUP_OFF 0 R/W 0: microphone supply enabled 1: microphone supply disabled 6 MUTE_D_ON 0 R/W Control of MUTE switch D 0: normal operation 1: microphone input set to mute 5 - 0 n/a MICL_VOL<4:0> 00000 R/W ch ni ca Bit Te 4:0 www.austriamicrosystems.com Bit Description volume settings for left microphone input, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N4) to mixer input (N13) 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain Revision 1.11 59 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 48. LINE_IN_R Register Name Base Default LINE_IN_R 2-wire serial 00h Right Line Input Register al id Configures the gain from right analog line input MUX E to mixer input (Σ) and controls MUTE switch B. This register is reset when the block is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled. Offset: 0Ah Bit Name Default Access 7 LI_HIQ 0 R/W 0: line input set to low power mode 1: line input set to high quality mode Bit Description 6 MUX_E 0 R/W Selects the line input 0: MUX_E output connected to Line Input 1 1: MUX_E output connected to Line Input 2 5 MUTE_B_OFF 0 R/W Control of MUTE switch B 0: right line input is set to mute 1: normal operation 4:0 LIR_VOL<4:0> 00000 R/W volume settings for right line input, adjustable in 32 steps @ 1.5dB; gain from MUX output (N27) to mixer input (N10) 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain am lc s on A te G nt st il lv Bit Table 49. LINE_IN_L Register Name Base Default LINE_IN_L 2-wire serial 00h Left Line Input Register Configures the gain from analog left line input MUX E to mixer input (Σ) and controls MUTE switch G. This register is reset when the block is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled. ca Offset: 0Bh Bit Name Default Access Bit Description 7 LO_DISCHG_OFF 0 R/W 0: normal operation 1: disables discharge resitors. Need if the line ouptut is directly connected to the line input for useing the same connector. 0 R/W Selects the line input mode 0: stereo 1: 2x mono single ended 0 R/W Control of MUTE switch G 0: left line input is set to mute 1: normal operation 00000 R/W volume settings for left line input, adjustable in 32 steps @ 1.5dB; gain from MUX output (N28) to mixer input (N17) 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain LI_MODE ch 6 ni Bit MUTE_G_OFF Te 5 4:0 LIL_VOL<4:0> www.austriamicrosystems.com Revision 1.11 60 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 50. DAC_R Register Name Base Default DAC_R 2-wire serial 00h Right DAC Output Register Bit Bit Name Default Access - 000 n/a 4:0 DAR_VOL<4:0> 00000 R/W Bit Description volume settings for right DAC output, adjustable in 32 steps @ 1.5dB; gain from DAC output (N19) to mixer input (N23) 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain am lc s on A te G nt st il lv 7:5 al id Configures the gain from DAC output to mixer input (Σ). This register is reset when the block is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled. Offset: 0Eh Table 51. DAC_L Register Name Base Default DAC_L 2-wire serial 00h Left DAC Output Register Configures the gain from DAC output to mixer input (Σ) and controls MUTE switch H. This register is reset when the block is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled. Offset: 0Fh Bit Bit Name Default Access Bit Description - 00 n/a 5 MUTE_H_OFF 0 R/W Control of MUTE switch H 0: DAC output is set to mute 1: normal operation 4:0 DAL_VOL<4:0> 00000 R/W volume settings for left DAC output, adjustable in 32 steps @ 1.5dB; gain from DAC output (N22) to mixer input (N26) 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain Te ch ni ca 7:6 www.austriamicrosystems.com Revision 1.11 61 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 52. ADC_R Register Name Base Default ADC_R 2-wire serial 00h Right ADC Input Register Default Access 7:6 MUX_A<1:0> 00 R/W 5 - 0 n/a 4:0 ADR_VOL<4:0> Bit Description Connect MUX A output to following inputs 00: Microphone (N4/N4) 01: Line_In1 (N1/N8) 10: Line_IN2 (N2/N7) 11: Mixer output (N24/N25) lv Bit Name am lc s on A te G nt st il Bit al id Configures MUX_A and the gain from MUX_A output to the ADC/mixer input (Σ). This register is reset when the block is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled. Offset: 10h 00000 R/W volume settings for right ADC input, adjustable in 32 steps @ 1.5dB; gain from MUX A output to ADC/mixer input (Σ) (N9) 11111: 12 dB gain 11110: 10.5 dB gain .. 00001: -33 dB gain 00000: -34.5 dB gain Table 53. ADC_L Register Name Base Default ADC_L 2-wire serial 00h Left ADC Input Register Configures the ADC mode, gain from MUX_A output to the ADC/mixer input (Σ) input and controls MUTE switch A. This register is reset when the block is disabled in AudioSet1 register (14h) or at a AVDD27-POR. The register cannot be written when the block is disabled. Offset: 0Fh Bit Name Default Access 7:6 ADC_MODE<1:0> 00 R/W 5 MUTE_A_OFF 0 R/W Control of MUTE switch A 0: ADC input is set to mute 1: normal operation 4:0 ADL_VOL<4:0> 00000 R/W volume settings for left ADC input, adjustable in 32 steps @ 1.5dB; gain from MUX A output to ADC/mixer input (Σ) (N18) 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 00000: -40.5 dB gain Te ch ni ca Bit www.austriamicrosystems.com Bit Description Devider setting for ADC sampling frequency 00: I2S LRCK / 2 01: I2S LRCK / 4 10: I2S LRCK 11: I2S LRCK Revision 1.11 62 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 54. DAC_IF Register Name Base Default DAC_IF 2-wire serial 00h Offset: 12h Configures the DAC interface and digital gain on the I2S input stream. This register is reset at a AVDD27-POR. Bit Bit Name Default Access 7 I2S_DIRECT 0 R/W 0: I2S master clock is generated by the internal PLL 1: signal on MCLK is used as I2S master clock 6 I2S_LOOP 0 R/W 0: normal operation 1: ADC output is connected to DAC input 5 I2S_ATTEN 0 R/W 0: normal operation 1: digital attenuation on I2S input data (SDI) enabled 4:0 SDI_ATTEN<4:0> 00000 R/W digital volume settings I2S input data (SDI), adjustable in 32 steps @ 1.5dB; gain from SDI pin to DAC input 11111: -1.5 dB gain 11110: -3 dB gain .. 00001: -46.5 dB gain 00000: -48.0 dB gain am lc s on A te G nt st il lv Bit Description al id DAC Interface Register Table 55. AudioSet1 Register Name Base Default AudioSet1 2-wire serial 00h First Audio Set Register Powers the various audio inputs and outputs UP or DOWN. Caution: This control register resets and holds LineIn, DAC, and ADC related registers in reset. After activation the required register settings need to be reprogrammed. This register is reset at a AVDD27-POR. Offset: 14h Bit Name Default Access 7 ADC_ON 0 R/W 6 DAC_ON 0 R/W 0: DAC powered down 1: DAC enabled for playback 5 DAC_GST_ON 0 R/W 0: DAC gainstage powered down 1: DAC gainstage enabled (needed for playback via mixer) 4:3 - 00 n/a ch ni ca Bit LIN_ON 0 R/W 1 - 0 n/a 0 MIC_ON 0 R/W Te 2 www.austriamicrosystems.com Bit Description 0: ADC powered down 1: ADC enabled for recording 0: Line Input powered down 1: Line Input enabled 0: Microphone Input powered down 1: Microphone Input enabled Revision 1.11 63 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 56. AudioSet2 Register Name Base Default AudioSet2 2-wire serial 00h Second Audio Set Register Offset: 15h al id Control of various audio blocks. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 7 BIAS_OFF 0 R/W Power-down of the AGND bias if only digital data transfer and PMU functions are used. 0: bias enabled 1: bias disabled, for power saving in non audio mode 6 SUM_OFF 0 R/W 0: Mixer stage enabled 1: Mixer stage powered down 5 SUM_AGC_OFF 0 R/W Switches the signal limiter OFF (N20/N21) 0: automatic gain control for summing stage enabled 1: automatic gain control for summing stage disabled 4 SUM_HP_HIQ 0 R/W 0: mixer and headphone stage in low power mode 1: mixer and headphone stage in high quality mode 3:2 GAIN_STEP<1:0> 00 R/W Sets the transition time of the auto fading for the output stage 00: 2ms/step 01: 4ms/step 10: 8ms/step 11: auto fading off 1:0 VMICS<1:0> 00 R/W Sets the microphone supply output voltage 00: AVDD17*20/17 01: AVDD17*20/22 10: AVDD17*20/27 11: AVDD17*20/32 am lc s on A te G nt st il lv Bit Table 57. AudioSet3 Register Name Base Default AudioSet3 2-wire serial 00h Third Audio Set Register Bit Control of mixer stage inputs and headphone. This register is reset at a AVDD27-POR. ca Offset: 16h Bit Name Default Access - 0 n/a 6 MICMIX_OFF 0 R/W 5 - 0 n/a ch ni 7 Bit Description 0: microphone input to ΣR and ΣL (N12/N13) on 1: microphone input to mixer disabled ADCMIX_ON 0 R/W 0: ADC input to mixer disabled 1: ADC input to ΣR and ΣL (N12/N13) on 3 LINMIX_OFF 0 R/W 0: line input to ΣR and ΣL (N12/N13) on 1: line input to mixer disabled Te 4 2 HP_FASTSTART 0 R/W 0: normal operation 1: shortens delay for start-up when using 220nF on HPGND 1 HP_BIAS 0 R/W 0: 100% 1: 150%, increased bisas for lower noise and THD 0 HPCM_ON 0 R/W 0: headphone common mode buffer is switched off 1: headphone common mode buffer is powerd up www.austriamicrosystems.com Revision 1.11 64 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 58. CVDD1 Register Name Base Default CVDD1 2-wire serial 00h CVDD1 DC/DC Buck Regulator Control Register Offset: 17h-1 al id This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 7 PROG_CVDD1 0 R/W Selects the control mode for CVDD1 0: CVDD1 is in default mode controlled by pin VPRG1 1: CVDD1 is register controlled (Reg. 17-1h) 6:0 VSEL_CVDD1>6:0> 000000 R/W The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. 00h: DC/DC powered down 01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV 41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV 71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV am lc s on A te G nt st il lv Bit Table 59. CVDD2 Register Name CVDD2 Base Default 2-wire serial 00h CVDD2 DC/DC Buck Regulator Control Register Offset: 17h-2 This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access 7 PROG_CVDD2 0 R/W Selects the control mode for CVDD2 0: CVDD2 is in default mode controlled by pin VPRG2 1: CVDD2 is register controlled (Reg. 17-1h) 6:0 VSEL_CVDD2<6:0> 000000 R/W The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. 00h: DC/DC powered down 01h-40h: CVDD1=0.6V+VSEL_CVDD2*12.5mV 41h-70h: CVDD1=1.4V+(VSEL_CVDD2-40h)*25mV 71h-7Fh: CVDD1=2.6V+(VSEL_CVDD2-70h)*50mV Bit Description Te ch ni ca Bit www.austriamicrosystems.com Revision 1.11 65 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 60. Hibernation Register Name Hibernation Base Default 2-wire serial 00h PMU Hibernation Control Register Bit Bit Name Default Access al id Hibernation starts when writing this register. This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Offset: 17h-6 Bit Description - 0 n/a 6 KEEP_PVDD2 0 R/W Keeps the programmed PVDD2 level during hibernation. 0: power down PVDD2 1: keep PVDD2 5 KEEP_PVDD1 0 R/W Keeps the programmed PVDD1 level during hibernation. 0: power down PVDD1 1: keep PVDD1 4:2 - 1 0 am lc s on A te G nt st il lv 7 000 n/a KEEP_CVDD2 0 R/W Keeps the programmed CVDD2 level during hibernation. 0: power down CVDD2 1: keep CVDD2 KEEP_CVDD1 0 R/W Keeps the programmed PVDD1 level during hibernation. 0: power down CVDD1 1: keep CVDD1 Table 61. DCDC_Cntr Register Name Base Default DCDC_Cntr 2-wire serial 00h DC/DC Step Down Control Register Offset: 17h-7 This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name 7 CVDD2_fast 6 CVDD1_fast Default Access Bit Description 0 R/W Selects a faster regulation mode for CVDD2 suitable for larger load changes. 0: normal mode, Cext=10uF 1: fast mode, Cext=22uF required ca Bit R/W Selects a faster regulation mode for CVDD1 suitable for larger load changes. 0: normal mode, Cext=10uF 1: fast mode, Cext=22uF required ch ni 0 CVDD2_freq 0 R/W Selects the switching frequency for DCDC2 0: 2MHz 1: 1MHz 4 CVDD1_freq 0 R/W Selects the switching frequency for DCDC2 0: 2MHz 1: 1MHz Te 5 www.austriamicrosystems.com Revision 1.11 66 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 61. DCDC_Cntr Register Name Base Default DCDC_Cntr 2-wire serial 00h DC/DC Step Down Control Register Offset: 17h-7 This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 3:2 DVM_CVDD2<1:0> 00 R/W Configures the dynamic voltage management (output voltage slope) for CVDD2 00: immediate change of the output voltage 01: 42us/step 02:166us/step 03: 666us/step 1:0 DVM_CVDD1<1:0> 00 R/W Configures the dynamic voltage management (output voltage slope) for CVDD1 00: immediate change of the output voltage 01: 42us/step 02:166us/step 03: 666us/step am lc s on A te G nt st il lv al id Bit Table 62. PVDD1 Register Name Base Default PVDD1 2-wire serial 00h PVDD1 Control Register Offset: 18h-1 This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access 7 PVDD1_OFF 0 R/W Switches off PVDD1 regulator 0: normal mode 1: PVDD1 switched off 6 ILIM_H_PVDD1 0 R/W Selects the higher current limit for PVDD1 0: default mode, 100mA 1: 200mA mode 5 PRG_PVDD1 0 R/W Selects the output voltage control mode for PVDD1 0: PVDD1 is in default mode controlled by pin VPRG2 1: PVDD1 is register controlled (Reg. 18-1h) 4:0 VSEL_PVDD1<4:0> 00000 R/W Sets the LDO output voltage in register control mode (default voltage of the regulator is selcted by pin VPROG2) 0x00-0x0F: 1.2V+VSEL*50mV ->(1.2V - 1.95V) 0x10-0x1F: 2.0V + (VSEL-0x10)*100mV -> (2.0V-3.5V) Bit Description Te ch ni ca Bit www.austriamicrosystems.com Revision 1.11 67 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 63. PVDD2 Register Name Base Default PVDD2 2-wire serial 00h PVDD2 Control Register Offset: 18h-2 Bit Bit Name Default Access 7 PVDD2_OFF 0 R/W Switches off PVDD2 regulator 0: normal mode 1: PVDD1 switched off 6 ILIM_H_PVDD2 0 R/W Selects the higher current limit for PVDD2 0: default mode, 100mA 1: 200mA mode 5 PRG_PVDD2 0 R/W Selects the output voltage control mode for PVDD2 0: PVDD2 is in default mode controlled by pin VPRG2 1: PVDD2 is register controlled (Reg. 18-2h) 4:0 VSEL_PVDD2<4:0> am lc s on A te G nt st il lv Bit Description al id This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a AVDD27-POR. 00000 R/W Sets the LDO output voltage in register control mode (default voltage of the regulator is selcted by pin VPRG2) 0x00-0x0F: 1.2V+VSEL*50mV ->(1.2V - 1.95V) 0x10-0x1F: 2.0V + (VSEL-0x10)*100mV -> (2.0V-3.5V) Table 64. AVDD27 Register Name Base Default AVDD27 2-wire serial 00h AVDD27 Control Register Offset: 18h-6 This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name 7 - 6 ILIM_H_VDD27 5 PRG_AVDD27 0 R/W 5 - 0 n/a 0000 R/W Access 0 n/a 0 R/W ni VSEL_AVDD27<3:0> Bit Description Selects the higher current limit for AVDD27 0: default mode, 100mA 1: 200mA mode Selects the output voltage control mode for AVDD27 0: AVDD27 is in default mode (2.7V) 1: AVDD27 is register controlled (Reg. 18-6h) Sets the LDO output voltage in register control mode (default voltage of the regulator is 2.7V) 0x0-0x2: 2.3V 0x3-0xF: 2.0V + VSEL*100mV -> (2.3V-3.5V) Te ch 3:0 Default ca Bit www.austriamicrosystems.com Revision 1.11 68 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 65. AVDD17 Register Name Base Default AVDD17 2-wire serial 00h AVDD17 Control Register Offset: 18h-7 Bit Name Default Access 7 AVDD17_OFF 0 R/W - 0 n/a 5 PRG_AVDD17 0 R/W 4:0 VSEL_AVDD17<4:0> Switches off AVDD17 regulator 0: normal mode 1: AVDD17 switched off, no audio functions possible Selects the output voltage control mode for AVDD17 0: AVDD17 is in default mode (1.7V) 1: AVDD17 is register controlled (Reg. 18-7h) am lc s on A te G nt st il 6 Bit Description lv Bit al id This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first. This register is reset at a AVDD27-POR. 0000 R/W Sets the LDO output voltage in register control mode (default voltage of the regulator is 1.7V) 0x00-0x1F: 1.65V + VSEL*100mV -> (1.65V-3.2V) Table 66. CHGVBUS1 Register Name Base Default CHGVBUS1 2-wire serial 00h Charger / VBUS 1 Control Register Offset: 19h-1 This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access 7 BAT_TEMP_OFF 0 R/W 0: enables 15uA supply for external 100k NTC resistor 1: disables supply 6:4 CHG_I<2:0> 000 R/W set maximum charging current during constant current charging 111: 460 mA 110: 420 mA 101: 350 mA 100: 280 mA 011: 210 mA 010: 140 mA 001: 70 mA 000: 55 mA 3:1 CHG_V<2:0> ni ca Bit 000 R/W set maximum charger voltage in 50mV steps for the constant voltage charging 111: 4.25 V 110: 4.2 V .. 001: 3.95 V 000: 3.9 V 0 R/W 0: enables Charger 1: disables Charger ch Te 0 CHG_OFF www.austriamicrosystems.com Bit Description Revision 1.11 69 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 67. CHGVBUS2 Register Name CHGVBUS2 Base Default 2-wire serial 00h Charger / VBUS 2 Control Register Offset: 19h-2 al id This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 7:6 VBUS_COMP_TH <1:0> 00 R/W Sets the threshold for the VBUS comparator. The output can be read in register 25h. 00: 4.5V 01: 3.18V 10: 1.5V 11: 0.6V 5:3 - 000 n/a - 2 BAT_TEMP 0 R/W Selects the battery temperature supervision level 0: 0.4/0.5V equal to 55/50°C with 100k NTC 1: 0.6/0.7V equal to 45/42°C with 100k NTC 1:0 CHG_EOC_TH<1:0> 00 R/W Setes the threshold for the charger EOC (end of charge) interrupt as a ratio of the constant current (CC) setting. 00: 10% CC 01: 30% CC 10: 50% CC 11: 70% CC am lc s on A te G nt st il lv Bit Table 68. Out_Cntr1 Register Name Base Default Out_Cntr1 2-wire serial 00h PWGD and XRES Output Control Register Offset: 1Ah-1 Bit Name 7:6 DRIVE_PWGD<1:0> 5:4 MUX_PWGD<1:0> Default Access Bit Description 00 R/W Sets the PWGD output pin to open-drain, push-pull or tri-state and sets various driving strengths 00: 6mA open-drain output 01: 6mA push-pull output 10: 1mA push-pull output 11: HiZ, stri-state 00 R/W Multiplexes various digital signals to the PWGD output pin 00: PWGD, PowerGood control signal 01: CLK24M, 24MHz oszillator output 10: CLKINT2, internal clock signal, see Clk_Cntr regsiter 11: PWM, PMW_Cntr register Te ch ni ca Bit This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a AVDD27-POR. www.austriamicrosystems.com Revision 1.11 70 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 68. Out_Cntr1 Register Name Base Default Out_Cntr1 2-wire serial 00h PWGD and XRES Output Control Register Offset: 1Ah-1 This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 3:2 DRIVE_XRES<1:0> 00 R/W Sets the XRES output pin to open-drain, push-pull or tri-state and sets various driving strengths 00: 6mA open-drain output 01: 6mA push-pull output 10: 1mA push-pull output 11: HiZ, stri-state 1:0 MUX_XRES<1:0> 00 R/W Multiplexes various digital signals to the XRES output pin 00: XRES, active low reset signal 01: CLK32k, 32kHz RTC oszillator output 10: CLKINT1, internal clock signal, see Clk_Cntr regsiter 11: PWM, PMW_Cntr register am lc s on A te G nt st il lv al id Bit Table 69. Out_Cntr2 Register Name Base Default Out_Cntr2 2-wire serial 00h Q24M and Q32k Output Control Register Offset: 1Ah-2 Bit Name Default Access 7:6 DRIVE_Q24M<1:0> 00 R/W Sets the PWGD output pin to push-pull or tri-state and sets various driving strengths 00: 6mA push-pull output 01: HiZ, stri-state 10: 2mA push-pull output 11: 1mA push-pull output 5:4 MUX_Q24M<1:0> 00 R/W Multiplexes various digital signals to the PWGD output pin 00: CLK24M, 24MHz oszillator output signal 01: CLKINT1, internal clock signal, see Clk_Cntr regsiter 10: CLKINT2, internal clock signal, see Clk_Cntr regsiter 11: PWM, PMW_Cntr register 3:2 DRIVE_Q32k<1:0> ca Bit This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a AVDD27-POR. R/W Sets the XRES output pin to push-pull or tri-state and sets various driving strengths 00: 6mA push-pull output 01: HiZ, stri-state 10: 2mA push-pull output 11: 1mA push-pull output R/W Multiplexes various digital signals to the XRES output pin 00: CLK32k, 32kHz RTC oszillator output signal 01: CLKINT1, internal clock signal, see Clk_Cntr regsiter 10: CLKINT2, internal clock signal, see Clk_Cntr regsiter 11: PWM, PMW_Cntr register ch ni 00 MUX_Q32k<1:0> Te 1:0 www.austriamicrosystems.com 00 Bit Description Revision 1.11 71 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 70. Out_Cntr3 Register Name Out_Cntr3 Base Default 2-wire serial 00h SDO and XIRQ Output Control Register Offset: 1Ah-3 al id This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 7:6 DRIVE_SDO<1:0> 00 R/W Sets the SDO output pin to push-pull or tri-state and sets various driving strengths 00: 6mA push-pull output 01: HiZ, stri-state 10: 2mA push-pull output 11: 1mA push-pull output 5:4 MUX_SDO<1:0> 00 R/W Multiplexes various digital signals to theSDO output pin 00: SDO, serial data output of the audio ADC 01: CLK24M, 24MHz oszillator output 10: CLKINT1, internal clock signal, see Clk_Cntr regsiter 11: PWM, PMW_Cntr register 3:2 DRIVE_XIRQ<1:0> 00 R/W Sets the XIRQ output pin to open-drain, push-pull or tri-state and sets various driving strengths 00: 6mA open-drain output 01: 6mA push-pull output 10: 1mA push-pull output 11: HiZ, stri-state 1:0 MUX_XIRQ<1:0> 00 R/W Multiplexes various digital signals to the XRES output pin 00: XIRQ, active low interrupt request signal 01: CLKINT1, internal clock signal, see Clk_Cntr regsiter 10: CLKINT2, internal clock signal, see Clk_Cntr regsiter 11: IRQ, active low reset signal am lc s on A te G nt st il lv Bit Table 71. In_Cntr Register Name In_Cntr Base Default 2-wire serial 00h ca HBT and Dimming Input Control Register Offset: 1Ah-4 7:4 Access Bit Description 0000 n/a MUX_HBT<1:0> 00 R/W Selects the HBT (heartbeat) input pin 00: OFF, heartbeat input deactivated 01: PWGD pin 10: Q24M pin 11: Q32k pin 00 R/W Selects the input pin for external dimming of the DCDC15 00: OFF, no pin selected In this mode the current sinks can be used without enabling the DCDC15. ExtDim_ON bit has to be set in DCDC15 register. 01: PWGD pin 10: Q24M pin 11: Q32k pin MUX_ExtDim<1:0> Te 1:0 Default - ch 3:2 Bit Name ni Bit This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first. This register is reset at a AVDD27-POR. www.austriamicrosystems.com Revision 1.11 72 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 72. Clk_Cntr Register Name Base Default Clk_Cntr 2-wire serial 00h Clock Control Register Offset: 1Ah-5 al id This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 7:6 CLKINT2<1:0> 00 R/W Selects the CLKINT2 input source. Note, this is an internal clock, which can be multiplexed to one of the GPIO ouptus. 00: CLKPLL, internal PLL clock 01: CLKlogdim, clock used for dimming the DCDC15 10: LOW, drives the signal to logic “0” 11: HIGH, drives the signal to logic “1” 5:4 CLKINT1<1:0> 00 R/W Selects the CLKINT1 frequency. Note, this is an internal clock, which can be multiplexed to one of the GPIO ouptus. 00: 2MHz 01: 887kHz 10: 1kHz 11: 125Hz 3:2 CLK24M<1:0> 00 R/W Selects the CLK24M frequency, clock of 24MHz oszillator 00: OSC24MHz, oszillator frequency 01: OSC24MHz_div2, oszillator frequency divided by 2 10: OSC24MHz_div4, oszillator frequency divided by 4 11: OSC24MHz_PD, OSC24M is set to power down 1:0 CLK32k<1:0> 00 R/W Selects the CLK32k frequnecy, clock of 32kHz RTC oszillator 00: OSC32kHz, RTC oszillator frequency 01: 1Hz 10: LOW, drives the signal to logic “0” 11: HIGH, drives the signal to logic “1” am lc s on A te G nt st il lv Bit Table 73. PWM_Cntr Register Name Base Default PWM_Cntr 2-wire serial 00h ca PWM Control Register Offset: 1Ah-6 Bit Name 7 PWM_INVERT ch PWM_CYCLE<6:0> Access Bit Description 0 R/W PWM output polarity 0: not inverted 1: inverted 0000000 R/W Sets the PWM duty cycle 0: no pulses 1-127: duty cycle = PWM_CYCLE * 0,39% Te 6:0 Default ni Bit This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first. This register is reset at a AVDD27-POR. www.austriamicrosystems.com Revision 1.11 73 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 74. PLL Register Name Base Default PLL 2-wire serial 00h PLL Register Offset: 1Ah-7 al id This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Bit Name Default Access Bit Description 7:4 OSR<3:0> 0000 R/W Sets the oversampling rate when using the internal PLL 0x0: 128 0x1-0xF: n/a 3:2 VCO_MODE<1:0> 00 R/W Selects the speed of the PLL VCO according to the audio sampling frequency. 00: normal: 24-48kHz 01: low: 8-23kHz 10: high: 49-96kHz 11: n/a 1:0 PLL_MODE<1:0> am lc s on A te G nt st il lv Bit 00 R/W Selects the PLL mode and master clock frequency source 00: automatic turns PLL on, PLL clock is used as master clock if freq(LRCK) >8kHz and freq(MCLK)<32*freq(LRCK) 01: ON; turns PLL on, PLL clock is used as master clock 10: OFF; turns the PLL off, MCLK is used as master clock 11: auto_inv; like automatic but with inverted clock Table 75. DCDC15 Register Name Base Default DCDC15 2-wire serial 00h DCDC15 Register Offset: 1Bh-1 Bit Name 7 DIM_UP_XDOWN 6:5 DIM_RATE<1:0> Default Access 0 R/W ca Bit This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first. This register is reset at a AVDD27-POR. 0: disables the step-up converter and dims it down 1: enables the step-up converter and dims it up R/W Selects the dimming speed when enabling or disablilng the DCDC15 00: 0ms 01: 300ms 10: 600ms 11: 1200ms VFB_ON 0 R/W 0: current feedback selected via ISINK1 and ISINK2 1: voltage feedback selected, ISINK1 is sinking 50uA to define the voltage via an external zener diode 3 ExtDim_ON 0 R/W 0: selects internal clock for dimming 1: selects external clock for dimming 000 n/a Te ch 4 ni 00 Bit Description 2:0 - www.austriamicrosystems.com Revision 1.11 74 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 76. ISINK1 Register Name Base Default ISINK1 2-wire serial 00h ISINK1 Register Offset: 1Bh-2 Bit Name Default Access 7:3 I_SINK1<4:0> 00000 R/W 2:0 - 000 n/a Bit Description sets the current into current sink 1in 1.2mA steps 0: OFF, current sink 1 disabled 1-31 1.2mA * I_SINK1 -> (1.2mA...37.2mA) lv Bit al id This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first. This register is reset at a AVDD27-POR. Table 77. ISINK2 Register Base ISINK2 2-wire serial Default am lc s on A te G nt st il Name 00h ISINK2 Register Offset: 1Bh-3 Bit Name Default Access 7:3 I_SINK2<4:0> 00000 R/W 2:0 - 000 n/a Bit Description sets the current into current sink 2in 1.2mA steps 0: OFF, current sink 2 disabled 1-31 1.2mA * I_SINK2 -> (1.2mA...37.2mA) Te ch ni ca Bit This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first. This register is reset at a AVDD27-POR. www.austriamicrosystems.com Revision 1.11 75 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 78. PMU_Enable Register Name Base Default PMU_Enable 2-wire serial 00h PMU_Enable Register Bit Description al id Selects the extended register on address 17h to 1Bh and enables writng to these PMU register. It also sets the ADC10 multiplexer to measure various regulator voltages This register is reset at a AVDD27-POR. Offset: 1Ch-2 Bit Bit Name Default Access 7:4 DC_TEST_MUX <3:0> 0000 R/W 3 PMU_GATE 000 R/W Enables all settings made in registers 17h to 1Bh at once. If this bit is set, changes are activated as soon as they are written to the related register. 0: no change 1: change at once 2:0 PMU_WR_ENABLE <2:0> 000 R/W Selects extended registers 17h to 1Bh for the next write 0: no register selected 1: 17h-1 to 1Bh-1 selected 2: 17h-2 to 1Bh-2 selected ... 7: 17h-7 to 1Bh-7 selected Te ch ni ca am lc s on A te G nt st il lv Allows multiplexing internal and external supply voltages to one DC test node which can be further multiplexed to the ADC10. The accuracy is 5mV/LSB (see reg. 2Eh) 0x0: open 0x1: AVDD27 0x2: AVDD17 0x3: PVDD1 0x4: PVDD2 0x5: CVDD1 0x6: CVDD2 0x7: RVDD 0x8: FVDD 0x9: PWGD 0xA-0xF: n/a www.austriamicrosystems.com Revision 1.11 76 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 79. SYSTEM Register Name Base Default SYSTEM 2-wire serial 41h SYSTEM Register Offset: 20h Bit Description al id This register is reset at a AVDD27-POR. Bit Bit Name Default Access 7:4 Design_Version<3:0> 0100 R 3 HB_WD_ON 0 R/W Heartbeat (HBT) Watchdog The watchdog counter will be reset by a rising edge at the HBT input pin which has to occur at least every 500ms. If the watchdog counter is not reset, the AFE will be powered down. 0: HBT watchdog is disabled 1: HBT watchdog is enabled 2 JTEMP_OFF 0 R/W Junction temperature supervision (level can be set in register 21h) 0: temperature supervision enabled 1: temperature supervision disabled 1 I2C_WD_ON 0 R/W 2-wire serial interface watchdog To reset the watchdog counter a 2-wire serial read operation has to be performed at least every 500ms. If the watchdog counter is not reset, the AFE will be powered down. 0: watchdog is disabled 1: watchdog is enabled 0 PWR_HOLD 0 R/W 0: power up hold is cleared and AFE will power down 1: is automatically set to on after power on am lc s on A te G nt st il lv AFE number to identify the design version 0100: for chip version 3v0 Table 80. SUPERVISOR Register Name Base Default SUPERVISOR 2-wire serial 00h SUPERVISOR Register Offset: 21h This register is reset at a AVDD27-POR. Bit Name 7 SD_TIME 0100 R/W Sets the emergency shut-down time invoked by PWRUP. 0: 5.4sec 1: 10.9sec 6 BVDDlow_SD_OFF 0 R/W 0: BVDDlow shut down enalbed 1: BVDDlow shut down disabled 5 - 0 n/a 0 R/W Access ni ch JTEMP_SUP<4:0> Bit Description Sets the threshold for junction temperature emergency shutdown and junction temperature interrupt Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5°C Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5°C Te 4:0 Default ca Bit www.austriamicrosystems.com Revision 1.11 77 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 81. RAM & WakeUp Register Name Base Default RAM & WakeUp 2-wire serial 00h RAM & WakeUp Register Offset: 22h rd al id Sets and enables the RTC wake-up counter and programs the 128bit SRAM. 3 bytes need to be written in a sequence to set the counter. The MSB of the 3 byte enables the wake-up counter. Byte 4 …19 will program the static 128bit SRAM which is supplied by RVDD. This register keeps its content during normal shut-down and is only reset at a RVDD-POR. Byte Name Default Access 7:0 WAKE_UP_BYTE_0 00h R/W st 7:0 WAKE_UP_BYTE_1 (2 7:0 nd 00h R/W 0000 0001b: 256sec 0000 0010b: 512sec 0000 0100b: 1 024sec 0000 1000b: 2 048sec 0001 0000b: 4 096sec 0010 0000b: 8 192sec 0100 0000b: 16 384sec 1000 0000b: 32 768sec 00h n/a 000 0001b: 65 536sec 000 0010b: 131 072sec 000 0100b: 262 144sec 000 1000b: 524 288sec 001 0000b: 1 048 576sec 010 0000b: 2 097 152sec 100 0000b: 4 194 304sec 0xxx xxxxxb = wake-up disabled 1xxx xxxxxb = wake-up enabled 00h R/W xxxx xxxxb = byte 0 : xxxx xxxxb = byte 15 write to 0x19 is byte 1) WAKE_UP_BYTE_2 rd (3 write to 0x19 is byte 2) 7:0 SRAM_128<0:15> th th 0000 0001b: 1sec 0000 0010b: 2sec 0000 0100b: 4sec 0000 1000b: 8sec 0001 0000b: 16sec 0010 0000b: 32sec 0100 0000b: 64sec 1000 0000b: 128sec am lc s on A te G nt st il (1 write to 0x19 is byte 0) Bit Description lv Bit Te ch ni ca (4 … 19 write to 0x22 programs the 128bit static SRAM) www.austriamicrosystems.com Revision 1.11 78 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 82. First Interrupt Register Name Base Default IRQENRD_0 2-wire serial 00h First Interrupt Register al id Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a AVDD27-POR. Offset: 23h Bit Name Default Access Bit Description 7 CVDD1_SD 0 W Invokes shut-down of AFE when a –10% under-voltage spike at CVDD1 occurs 0: disable 1: enable CVDD1_under x R This bit is set when a –5% under-voltage at CVDD1 occurs CVDD1_IRQ 0 W Enables interrupt for over-voltage/under-voltage supervision of CVDD1 0: disable 1: enable This bit is set when a +8% over-voltage at CVDD1 occurs am lc s on A te G nt st il 6 lv Bit CVDD1_over x R 5:4 - 00 n/a 3 PVDD2_SD 0 W Invokes shut-down of AFE when a –10% under-voltage spike at PVDD2 occurs 0: disable 1: enable PVDD2_under x R This bit is set when a –5% under-voltage at PVDD2 occurs PVDD2_IRQ 0 W Enables interrupt for over-voltage/under-voltage supervision of PVDD2 0: disable 1: enable 1 x R This bit is set when a +5% over-voltage at PVDD2 occurs PVDD1_SD 0 W Invokes shut-down of AFE when a –10% under-voltage spike at PVDD1 occurs 0: disable 1: enable PVDD1_under x R This bit is set when a –5% under-voltage at PVDD1 occurs PVDD1_IRQ 0 W Enables interrupt for over-voltage/under-voltage supervision of PVDD1 0: disable 1: enable R This bit is set when a +5% over-voltage at PVDD1 occurs ni 0 PVDD2_over ca 2 x Te ch PVDD1_over www.austriamicrosystems.com Revision 1.11 79 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 83. Second Interrupt Register Name Base Default IRQENRD_1 2-wire serial 00h Second Interrupt Register Bit Name Default Access 7 PWRUP_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the PWRUP input pin occurs 0: disable 1: enable x R This bit is set whenever a high level of min. BVDD/3 at the PWRUP input pin occurs (PWRUP pin is commonly connected to the power-up button) am lc s on A te G nt st il 5 lv Bit 6 Bit Description al id Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a AVDD27-POR. Offset: 24h WAKEUP_IRQ MCLK_IRQ 0 W Enables interrupt which is invoked whenever a wake-up from RTC wake-up counter occurs 0: disable 1: enable x R This bit is set when a wake-up has been invoked by the RTC wake-up counter. 0 W Enables interrupt which is invoked whenever a high signal at the MCLK input pin occurs 0: disable 1: enable x R This bit is set whenever a high level of min. BVDD/3 at the MCLK input pin occurs (MCLK pin can be used as alternative power-up button) 0 n/a - 1 CVDD2_SD 0 W Invokes shut-down of AFE when a –10% under-voltage spike at CVDD2 occurs 0: disable 1: enable CVDD2_under x R This bit is set when a –5% under-voltage at CVDD2 occurs CVDD2_IRQ 0 W Enables interrupt for over-voltage/under-voltage supervision of CVDD2 0: disable 1: enable R This bit is set when a +8% over-voltage at CVDD2 occurs ni 0 ca 4:2 x Te ch CVDD2_over www.austriamicrosystems.com Revision 1.11 80 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 84. Thrid Interrupt Register Name Base Default IRQENRD_2 2-wire serial 00h Third Interrupt Register Bit Bit Name Default Access 7 BATTEMP_IRQ 0 W Battery over-temperature interrupt setting. 0: disable 1: enable interrupt if battery temperature exceeds 45/55°C The interrupt must not be enabled if the charger block and battery temperature supervision is disabled x R Battery over-temperature interrupt reading 0: battery temperature below 45/55°C 1: battery temperature was too high and the charger was turned off. The charger will be turned on again, when the temperature gets below 42/50°C am lc s on A te G nt st il lv Bit Description al id Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a AVDD27-POR. Offset: 25h CHG_EOC x R Battery end of charge interrupt reading 0: battery charging in progress 1: charging is complete, charging current is below 10% of nominal current, turn off charger 5 CHG_CON x R 0: no charger input source connected 1: charger input source connected, also valid if charger is connected during wakeup 4 CHG_IRQ 0 W Charger status change interrupt setting 0: disable 1: enables an interrupt on a low to high or high to low change of CHGIN pin or on an EOC condition CHG_changed (status change) x R Charger input status change interrupt reading 0: charger status not changed 1: charger status changed, check CHG_CON, CHG_EOC 3 USB_CON 0 n/a 0: no USB input connected 1: USB input connected, also valid if USB is connected during wakeup. The threshold can be set in the USB_UTIL register (1Ah) 2 USB_IRQ W USB input status change interrupt setting 0: disable 1: enables an interrupt on a low to high or high to low change of VBUS pin. The threshold can be set in the USB_UTIL register (1Ah) R USB input status change interrupt reading 0: USB input status not changed 1: USB input status changed, check USB_CON ca 6 ch ni 0 x Te USB_changed (status change) www.austriamicrosystems.com Revision 1.11 81 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 84. Thrid Interrupt Register Name Base Default IRQENRD_2 2-wire serial 00h Third Interrupt Register Offset: 25h Bit Name Default Access 1 RTC_WD (level) 0 W Real time clock watchdog interrupt setting 0: disable 1: enable x R Real time clock watchdog interrupt reading 0: RTC o.k. 1: RTC oszillator was stopped, RTC not longer valid The interrupt gets set in hibernation or during power-up even if the interrupt is not enabled thus allowing to recognise a change of the battery connected to BVDDR during hibernation or shutdown. For a valid reading, the interrupt has to be enabled first. am lc s on A te G nt st il lv Bit 0 Bit Description al id Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a AVDD27-POR. BVDD_LOW (level) 0 W BVDD under-voltage supervisor interrupt setting 0: disable 1: enable x R BVDD supervisor interrupt reading 0: BVDD is above brown out level 1: BVDD has reached brown out level The threshold can be set in the SUPERVISOR register (21h) Table 85. Fourth Interrupt Register Name Base Default IRQENRD_3 2-wire serial 00h Fourth Interrupt Register Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a AVDD27-POR. ca Offset: 26h Bit Name Default Access 7 JTEMP_HIGH (level) 0 W Supervisor junction over-temperature interrupt setting 0: disable 1: enable x R Supervisor junction over-temperature interrupt reading 0: chip temperature below threshold 1: chip temperature has reached the threshold The threshold can be set in the SUPERVISOR register (21h) 0 n/a ch ni Bit - Te 6 Bit Description www.austriamicrosystems.com Revision 1.11 82 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 85. Fourth Interrupt Register Name Base Default IRQENRD_3 2-wire serial 00h Fourth Interrupt Register Offset: 26h Bit Bit Name Default Access 5 HP_OVC (level) 0 W Headphone over-current interrupt setting 0: disable 1: enable The interrupt must not be enabled if the headphone block is disabled x R Headphone over-current interrupt reading 0: no over-current detected 1: headphone over-current detected, headphone amplifier was shut down. The current thresholds are 150mA at HPR / HPL pin or 300mA at HPCM pin. am lc s on A te G nt st il lv Bit Description al id Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a AVDD27-POR. 4 I2S_status x R 0: no LRCK on I2S interface detected 1: LRCK on I2S interface present 3 I2S_IRQ 0 W I2S input status change interrupt setting 0: disable 1: enable I2S_changed (status change) x R I2S input status change interrupt reading 0: I2S input status not changed 1: I2S input status changed, check I2S_status VOXM_IRQ 0 W Enables interrupt which is invoked by reaching a voltage threshold at the MIC input (voice activation) 0: disable 1: enable x R This bit is set when a voltage threshold of 5mVRMS (unfiltered) at the MIC has been reached (voice activation) 0 W Microphone connect detection interrupt setting 0: disable 1: enable R Microphone connect detection interrupt reading 0: no microphone connected to MIC input 1: microphone connected at MIC input. This interrupt is only invoked when the microphone stage is powered down. The IRQ will be released after enabling the microphone stage. Detecting a microphone during operation has to be done by measuring the supply current 0 W Headphone connect detection interrupt setting 0: disable 1: enable x R Headphone connect detection interrupt reading 0: no headphone connected 1: headphone connected This interrupt is only invoked when the headphone stage is powered down. The IRQ will be released after enabling the headphone stage. Detecting a headphone during operation is not possible. 2 MIC_CON (level) ca 1 ch ni x HPH_CON (level) Te 0 www.austriamicrosystems.com Revision 1.11 83 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 86. Fifth Interrupt Register Name Base Default IRQENRD_4 2-wire serial 00h Fifth Interrupt Register Bit Bit Name Default Access 7:6 T_DEB<1:0> 00 R/W 5 AVDD27_IRQ 0 W Enables interrupt for under-voltage supervision of AVDD27 0: disable 1: enable AVDD27_under x R This bit is set when a -5% under-voltage at AVDD27 occurs DCDC15_IRQ 0 W Enables interrupt for over-voltage supervision of SW15 0: disable 1: enable DCDC15_over x R This bit is set when SW15 exceeds 15V. 3 - 0 n/a 2 REM_DET (edge) 0 W Microphone remote key press detection interrupt setting 0: disable 1: enable x R Microphone remote key press detection interrupt reading 0: no key press detected 1: Microphone supply current got increased, remote key press detected -> measure MICS supply current 0 W RTC timer interrupt setting 0: disable 1: enable R RTC timer interrupt reading 0: no RTC interrupt occurred 1: RTC timer interrupt occurred. Selecting minute or second interrupt can be done via RTCT register (29h) 0 W ADC end of conversion interrupt setting 0: disable 1: enable x R ADC end of conversion interrupt reading 0: ADC conversion not finished 1: ADC conversion finished. Read out ADC_0 and ADC_1 register to get the result (2Eh & 2Fh) RTC_UPDATE (edge) ca 1 ni x ADC_EOC (edge) lv Te ch 0 Sets the USB and Charger connect de-bounce time: 00: 512ms 01: 256ms 10: 128ms 11: 0ms am lc s on A te G nt st il 4 Bit Description al id Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a AVDD27-POR. Offset: 27h www.austriamicrosystems.com Revision 1.11 84 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 87. RTC_Cntr Register Name Base Default RTC_Cntr 2-wire serial 03h RTC Control Register Offset: 28h Bit Bit Name Default Access Bit Description 7:4 Free_Bits<3:0> 0000 R/W 3:2 - 00 n/a 1 RTC_ON 1 R/W RTC counter clock control: 0: Disable clock for RTC counter 1: Enables clock for RTC counter 0 OSC_ON 1 RW RTC oscillator control: 0: Disable RTC oscillator 1: Enable RTC oscillator am lc s on A te G nt st il lv Free Bits to be used for application purpose al id This register is reset at a RVDD-POR. Table 88. RTC_Time Register Name Base Default RTC_time 2-wire serial 03h RTC Timing Register Offset: 29h This register is reset at a RVDD-POR. Bit Name 7 IRQ_MIN 6:0 TRTC<6:0> Default Access 0 R/W 0: generates an interrupt every second 1: generates an interrupt every minute The interrupt has to be enable in IRQENRD_4 (27h) 1000000 R/W These bits are used to correct the inaccuracy of the used 32kHz crystal. Bit Description Trimming register for RTC, 128 steps @ 7.6ppm 000000: 1 (7.6ppm) 000001: 2 (15.2ppm) … 100000: 64 (488ppm) … 111110: 126 (960.8ppm) 111111: 127 (968.4ppm) ni ca Bit Table 89. RTC_0 to RTC_3 Register Base Default 2-wire serial 03h ch Name RTC_0 to RTC_3 RTC Counter Seconds Register This register is reset at a RVDD-POR. Te Offset: 2Ah to 2Dh Adr. Byte Name Default Access 2Ah RTC_0 00h R/W QRTC<7:0>; RTC seconds bits 0 to 7 2Bh RTC_1 00h R/W QRTC<15:8>; RTC seconds bits 8 to 15 2Ch RTC_2 00h R/W QRTC<23:9>; RTC seconds bits 9 to 23 2Dh RTC_3 00h R/W QRTC<31:24>; RTC seconds bits 24 to 31 www.austriamicrosystems.com Bit Description Revision 1.11 85 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 90. ADC10_0 Register Name Base Default ADC10_0 2-wire serial 0000 00xxb First 10-bit ADC Register Offset: 2Eh Bit Bit Name Default Access 7:4 ADC10_MUX<3:0> 0000 R/W 3:2 - 1:0 ADC10<9:8> Bit Description am lc s on A te G nt st il lv Selects ADC input source 0000: BVDD 0001: BVDDR 0010: CHGIN 0011: CHGOUT 0100: VBUS 0101: defined by DC_TEST in register 0x1C 0110: BATTEMP 0111: reserved 1000: MICS 1001: reserved 1010: I_MICS 1011: reserved 1100: VBE_1uA 1101: VBE_2uA 1110: I_CHGact 1101: I_CHGref al id Writing to this register will start the measurement of the selected source. This register is reset at a AVDD27-POR, exception are bit 0 and 1 00 n/a xx R ADC result bit 9 to 8 Table 91. ADC10_1 Register Name Base Default ADC10_1 2-wire serial xxh Second 10-bit ADC Register Offset: 2Fh This register is reset at a AVDD27-POR. Bit Name ADC10<7:0> Default Access ca Bit 7:0 R Bit Description ADC results bits 7 to 0 Te ch ni 00h www.austriamicrosystems.com Revision 1.11 86 - 91 AS3543 3v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 92. UID_0 to UID_7 Register Name Base Default UID_0 to UID7 2-wire serial n/a Byte Name Default Access Bit Description 38h UID_0 n/a R Unique ID byte 0 39h UID_1 n/a R Unique ID byte 1 3Ah UID_2 n/a R Unique ID byte 2 3Bh UID_3 n/a R Unique ID byte 3 3Ch UID_4 n/a R Unique ID byte 4 3Dh UID_5 n/a R Unique ID byte 5 3Eh UID_6 n/a R Unique ID byte 6 3Fh UID_7 n/a R Unique ID byte 7 Te ch ni ca am lc s on A te G nt st il Adr. al id This is a read only register and gets not reset. lv Offset: 38h to 3Fh UNIQUE ID Register www.austriamicrosystems.com Revision 1.11 87 - 91 A B C Backlight Cathode Backlight Anode 5 VDDMEM / 1.8V VDDCORE / 1.2V 1uF C14 10uF C21 10uF C20 D9 22uH C22 L3 L2 C19 C11 3.3uF 4.7uH 4.7uH 3.3uF BVDD BVDD L1 2.2uF IOVDD / 3.3V AS3543 BVDDC2 LXC2 CVDD2 CVSS12 CVDD1 LXC1 BVDDC1 ISINK2 ISINK1 VSS15V SW15V PVDD2 PVDD1 U1 4 R10 10k DVDD E1 F1 F2 H1 H2 J1 K1 D2 E2 C1 C2 A5 A3 2.2uF 2.2uF VDDMEM / 1.8V D4 D2 IOVDD / 3.3V BVDD D5 C3 C8 A10 A8 A6 2 C2 C1 R11 10k DVDD B4 BVDD B3 BVDDP1 I2S Interface 100nF Digital Supply Digital Filter Start - Up Sequence Power Up Reset Out S1 AS3543 Charger I2C Int. System Supply C6 C4 3 Power Up BVDD 24MHz Output RTC 100uF AGND VREF HPGND LOGND HPVSS AVSS AVDD17 AVDD27 AVDD17IN HPVDD LIN1R LIN1L LIN2L LIN2R MICS MICP MICN LOUTL LOUTR HPL HPR HPCM 47nF F9 G9 B6 B8 A9 F10 H10 H9 B5 B7 C9 C10 D7 D6 D9 E10 E9 B10 B9 2 10uF 10uF D7 2.2uF C27 2.2uF C28 220nF R7 1k 22nF 220nF AVDD27 R6 1k C13 C18 100nF 100nF 47k R4 C17 C15 C12 47k R3 D8 2 1 3 R8 47k 1 R GND L MIC1 R9 47k MICROPHONE 1 2 Line Out Right Line Out Left U2 Headphone Output 1 al id lv 470nF 470nF C25 C26 10uF C16 10uF 100R 10uF C10 47k 47k C9 R2 R1 VDDMEM / 1.8V C24 R5 100uF - 220uF 100uF - 220uF C23 am lc s on A te G nt st il C5 BVDDBSW BVDD ca ni BATTEMP D6 C29 U3 Li-Ion Battery BVDD DC 5V A1 CHGOUT 33nF CSDA CSCL XIRQ K8 J8 J4 Two Wire Interface DATA Two Wire Interface CLOCK AS3543 Interrupt C7 32kHz Y1 BATTERY D3 B1 CHGIN USB SDI SDO SCLK LRCK MCLK G5 G6 F4 G4 E4 I2S SDI I2S SDO I2S SCLK I2S LRCK VBUS Q32k PWGD XRES PWRUP VSS D5 J7 J5 J3 J2 D4 1 2 DCDC Buck Converter CPU Reset# ch USB 5V B2 BATTEMP G2 FVDD K6 DVDD D 2.2uF D1 K5 DVSS VPROG1 VPROG2 VPROG3 G7 F7 E7 Te A2 3 J6 . . 4 K9 J9 BVDDR RVDD J10 K10 XIN32k XOUT32k Q24M Revision 1.11 XOUT24M XIN24M 15VDCDC BL-Booster K3 K2 Audio Outputs Audio Inputs www.austriamicrosystems.com PRG LDOs Audio Supplies 5 Line Input Left Line Input Right A B C D AS3543 3v2 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 12 Application Information Figure 30. Typical Application Schematic 88 - 91 AS3543 3v2 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 13 Package Drawings and Markings Table 93. Package Code AYWWZZZ lv al id Figure 31. CTBGA67 Marking Y WW ZZZ year working week assembly / packaging free choice am lc s on A te G nt st il A B ... for Green Te ch ni ca Figure 32. CTBGA68 6x6 0.5mm pitch www.austriamicrosystems.com Revision 1.11 89 - 91 AS3543 3v2 Data Sheet - O r d e r i n g I n f o r m a t i o n 14 Ordering Information Table 94. Ordering Information Description AS3543-ECTP E CT P High End Stereo Audio Codec with System PMU Temperature Range: -20ºC - 85ºC Package: CTBGA Delivery Form: Tape & Reel dry pack Package 68-ball CTBGA 0.5mm pitch (6.0mm x 6.0mm) Te ch ni ca am lc s on A te G nt st il lv Note: Delivery Form Tape & Reel dry pack al id Model www.austriamicrosystems.com Revision 1.11 90 - 91 AS3543 3v2 Data Sheet - O r d e r i n g I n f o r m a t i o n Copyrights Copyright © 1997-2011, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. al id Disclaimer am lc s on A te G nt st il lv Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. ni ca The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. ch Contact Information Te Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.11 91 - 91