CD4020BMS, CD4024BMS, CD4040BMS CMOS Ripple-Carry Binary Counter/Dividers October 1996 Features Pinouts • High Voltage Types (20V Rating) CD4020BMS TOP VIEW • Medium Speed Operation • Fully Static Operation • Buffered Inputs and Outputs Q12 1 16 VDD • 100% Tested for Quiescent Current at 20V Q13 2 15 Q11 • Standardized Symmetrical Output Characteristics Q14 3 14 Q10 • Common Reset Q6 4 13 Q8 • 5V, 10V and 15V Parametric Ratings Q5 5 12 Q9 • Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC Q7 6 11 RESET Q4 7 10 θ • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications For Description Of ‘B’ Series CMOS Devices” Applications 9 Q1 VSS 8 CD4024BMS TOP VIEW θ 1 14 VDD RESET 2 13 NC Q7 3 12 Q1 • Control Counters • Timers Q6 4 11 Q2 Q5 5 10 NC Q4 6 9 Q3 VSS 7 8 NC • Frequency Dividers • Time-Delay Circuits Description NC = NO CONNECTION CD4020BMS - 14 Stage CD4024BMS - 7 Stage CD4040BMS TOP VIEW CD4040BMS - 12 Stage CD4020BMS, CD4024BMS, and CD4040BMS are ripplecarry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4020BMS, CD4024BMS and the CD4040BMS is supplied in these 14 lead outline packages: CD4020B CD4024B CD4040B Braze Seal DIP H4W H4Q H4X Frit Seal DIP H1F H1B H1F Ceramic Flatpack H6W H3W H6W Q12 1 16 VDD Q6 2 15 Q11 Q5 3 14 Q10 Q7 4 13 Q8 Q4 5 12 Q9 Q3 6 11 R Q2 7 10 θ VSS 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-359 9 Q1 File Number 3300.1 Specifications CD4020BMS, CD4024BMS, CD4040BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND GROUP A SUBGROUPS LIMITS TEMPERATURE 1 VDD = 18V, VIN = VDD or GND Input Leakage Current Input Leakage Current IIL IIH VIN = VDD or GND VIN = VDD or GND Output Voltage Output Current (Sink) Output Current (Sink) VOL15 VOH15 IOL5 IOL10 UNITS 10 µA - 1000 µA oC - 10 µA +125 C 3 -55 1 +25o C -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC VDD = 20 VDD = 18V Output Voltage MAX - +25 C 2 MIN o o VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V 1 +25oC 0.53 - mA 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH10 IOH15 VNTH VPTH F VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 7-360 V -55oC +25oC, NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay 0 To Q1 SYMBOL TPHL1 TPLH1 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Reset To Q TPLH3 TPHL3 VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency 9 10, 11 Propagation Delay Qn To Qn + 1 Transition Time Q1 GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 360 ns - 486 ns - 330 ns - 446 ns - 280 ns - 378 ns - 200 ns - 270 ns 9 +25oC 3.5 - MHz 10, 11 +125oC, -55oC 2.22 - MHz MIN MAX UNITS µA NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 7-361 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage Low SYMBOL VIL CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, - 3 V -55oC Input Voltage High VIH Propagation Delay Input To Q1 TPHL1 TPLH1 Propagation Delay QN To QN + 1 Propagation Delay Reset To Q Transition Time Maximum Clock Input Frequency Minimum Reset Pulse Width TPHL2 TPLH2 TPHL3 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V - V 1, 2, 3 +25oC 160 ns 1, 2, 3 +25 C - 130 ns VDD = 10V 1, 2, 3 +25 oC - 80 ns VDD = 15V 1, 2, 3 +25oC - 60 ns o - 120 ns o VDD = 15V VDD = 10V 1, 2, 3 +25 C VDD = 15V 1, 2, 3 +25 C - 100 ns TTHL TTLH VDD = 10V 2, 3 +25oC - 100 ns VDD = 15V 2, 3 +25oC - 80 ns FCL VDD = 10V 1, 2, 3 +25oC 8 - MHz VDD = 15V 1, 2, 3 +25oC 12 - MHz TW TREM TW CIN o VDD = 5V 1, 2, 3 +25 C - 200 ns VDD = 10V 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC - 60 ns VDD = 5V 1, 2, 3 +25 oC - 350 ns VDD = 10V 1, 2, 3 +25oC - 150 ns 1, 2, 3 o +25 C - 100 ns VDD = 5V 1, 2, 3 +25 oC - 140 ns VDD = 10V 1, 2, 3 +25oC - 60 ns 1, 2, 3 oC - 40 ns +25oC - 7.5 pF VDD = 15V Input Capacitance 7 - VDD = 15V Minimum Input Pulse Width +25oC, +125oC, -55oC o VDD = 15V Reset Removal Time 1, 2 Any Input 1, 2 +25 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTND P Threshold Voltage VTP P Threshold Voltage Delta ∆VTPD Functional F CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VSS = 0V, IDD = 10µA 1, 4 VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND MAX UNITS - 25 µA -2.8 -0.2 V - ±1 V +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 7-362 MIN Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 1 - 7, 9, 12 - 15 10 PART NUMBER CD4020BMS Static Burn-In 1 Note 1 1 - 7, 9, 12 - 15 8, 10, 11 16 Static Burn-In 2 Note 1 1 - 7, 9, 12 - 15 8 10, 11, 16 Dynamic BurnIn Note 1 - 8, 11 16 1 - 7, 9, 12 - 15 8 10, 11, 16 1, 2, 7 14 Irradiation Note 2 PART NUMBER CD4024BMS Static Burn-In 1 Note 1 3 - 6, 8 - 13 7-363 25kHz Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued) OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 2 Note 1 3 - 6, 8 - 13 7 1, 2, 14 Dynamic BurnIn Note 1 8, 10, 13 2, 7 14 3 - 6, 8 - 13 7 1, 2, 14 Irradiation Note 2 9V ± -0.5V 50kHz 3 - 6, 9, 11, 12 1 1 - 7, 9, 12 - 15 10 25kHz PART NUMBER CD4040BMS Static Burn-In 1 Note 1 1 - 7, 9, 12 - 15 8, 10, 11 16 Static Burn-In 2 Note 1 1 - 7, 9, 12 - 15 8 10, 11, 16 Dynamic BurnIn Note 1 - 8, 11 16 1 - 7, 9, 12 - 15 8 10, 11, 16 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Functional Diagrams VDD 14 VDD 16 9 Q1 14 STAGE RIPPLE COUNTER 4 Q6 6 Q7 13 Q8 12 Q9 14 Q10 15 Q11 1 Q12 2 Q13 3 Q14 11 12 BUFFERED OUTPUTS 5 Q5 9 Q1 10 12 7 Q4 Q1 11 1 7 STAGE RIPPLE COUNTER INPUT PULSES RESET Q2 9 Q3 6 2 Q4 5 Q5 4 Q6 7 BUFFERED OUTPUTS 10 INPUT PULSES 7 Q2 INPUT PULSES 6 Q3 12 STAGE RIPPLE COUNTER RESET VSS CD4020BMS NC = 8, 10, 13 11 7 8 VSS VSS CD4024BMS 7-364 2 Q6 13 Q8 12 Q9 14 Q10 15 Q11 1 Q12 RESET 8 3 Q5 4 Q7 3 Q7 5 Q4 CD4040BMS 12 BUFFERED OUTPUTS VDD 16 CD4020BMS, CD4024BMS, CD4040BMS Logic Diagrams Ø1 Q1 Ø2 FF1 Ø* Ø1 R* Q2 Ø3 Q13 FF2 Q1 Ø2 R Q1 Ø14 Q14 FF14 Q2 Ø3 Q13 R Ø14 Q14 R FF3 - FF13 VDD *INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK Q1 Q4 Q13 Q14 VSS FIGURE 1. LOGIC DIAGRAM FOR CD4020BMS Ø1 Q1 Ø2 FF1 Ø* Ø1 R* Q2 Ø3 Q6 FF2 Q1 Ø2 R Q1 Ø7 Q7 FF14 Q2 Ø3 Q6 Ø7 R Q7 R FF3 - FF6 VDD *INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK Q2 Q1 Q3 Q6 Q7 VSS FIGURE 2. LOGIC DIAGRAM FOR CD4024BMS Ø1 Q1 Ø2 FF1 Ø* Ø1 R* Q2 Ø3 Q11 FF2 Q1 Ø2 R Q1 Ø7 Q12 FF12 Q2 Ø3 Q11 R Ø7 Q12 R FF3 - FF11 VDD *INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK Q1 Q2 Q3 VSS FIGURE 3. LOGIC DIAGRAM FOR CD4040BMS 7-365 Q11 Q12 CD4020BMS, CD4024BMS, CD4040BMS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 -5 -10V 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 -10 -15V -15 FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (φ TO Q1) TRANSITION TIME (tTHL, tTLH) (ns) 200 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 100 FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (φ TO Q1)) 7-366 CD4020BMS, CD4024BMS, CD4040BMS Typical Performance Characteristics POWER DISSIPATION (PD) (µW) 105 104 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC 2 SUPPLY VOLTAGE (VDD) = 5V (Continued) 8 6 4 ∅ ∅ p p n 10V R 2 103 ∅ 10V 8 6 4 5V 2 102 CD = 15pF CL = 50pF 8 6 4 ∅ n ∅ R * Q1 Q R ∅ p p n n ∅ ∅ Q 2 10 2 1 4 68 2 4 68 2 4 68 2 4 68 2 * ON FIRST STAGE ONLY 4 68 10 102 103 104 INPUT PULSE FREQUENCY (fφ) (kHz) 105 FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT PULSE FREQUENCY FOR CD4020BMS FIGURE 11. DETAIL OF TYPICAL FLIP-FLOP STAGES Chip Dimensions and Pad Layouts Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) DIMENSIONS AND PAD LAYOUT FOR CD4020BMS. DIMENSIONS AND PAD LAYOUT FOR CD4040BMS ARE IDENTICAL METALLIZATION: PASSIVATION: BOND PADS: DIMENSIONS AND PAD LAYOUT FOR CD4024BMSH Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-367 CD4020BMS, CD4024BMS, CD4040BMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 File Number 368