CD4508BMS CMOS Dual 4-Bit Latch December 1992 Features Pinout • High-Voltage Types (20-Volt Rating) CD4508BMS TOP VIEW • Two Independent 4-Bit Latches • Individual Master Reset for Each 4-Bit Latch • 3-State Outputs with High-Impedance State for Bus Line Applications RESET A 1 24 VDD STROBE A 2 23 Q3B OUTPUT DISABLE A 3 22 D3B D0A 4 21 Q2B Q0A 5 20 D2B • Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.) at VDD = 10V and CL = 50pF D1A 6 19 Q1B Q1A 7 18 D1B • 5V, 10V, and 15V Parametric Ratings D2A 8 17 Q0B • Standardized, Symmetrical Output Characteristics Q2A 9 16 D0B D3A 10 15 OUTPUT DISABLE B Q3A 11 14 STROBE B VSS 12 13 RESET B • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC • Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Functional Diagram • Meets all Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ‘B’ Series CMOS Devices" OUTPUT DISABLE Q0A D0A Applications D1A • Buffer Storage D2A 4-BIT LATCH Q1A 3-STATE OUTUTS Q3A D3A • Holding Registers Q2A STROBE • Data Storage and Multiplexing RESET OUTPUT DISABLE Description D0B CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input. Q0B Q1B D1B D2B D3B 4-BIT LATCH 3-STATE OUTUTS Q2B Q3B STROBE RESET The CD4508BMS is supplied in these 24 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4V H1Z H4P CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1148 File Number 3337 Specifications CD4508BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125 C - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -0.4 - µA Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1149 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4508BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Strobe In to Data Out Transition Time SYMBOL TPHL1 TPLH1 TTHL TTLH GROUP A SUBGROUPS TEMPERATURE CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 260 ns - 351 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 -55oC, +25oC - 10 +125oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V 1, 2 1, 2 +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V VDD = 10V 1, 2, 3 +25oC - 140 ns VDD = 15V 1, 2, 3 +25oC - 100 ns Propagation Delay Strobe In to Data Out TPHL1 TPLH1 7-1150 Specifications CD4508BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Propagation Delay Data In to Data Out TPHL2 TPLH2 Propagation Delay Reset to Data Out TPHL3 TPLH3 Propagation Delay 3-State TPHZ TPZH Transition Time 3-State TPLZ TPZL Transition Time Minimum Strobe Pulse Width Minimum Data Setup Time Minimum Reset Pulse Width Input Capacitance NOTES TEMPERATURE MIN MAX UNITS VDD = 5V 1, 2, 3 +25oC - 210 ns VDD = 10V 1, 2, 3 +25oC - 120 ns VDD = 15V 1, 2, 3 +25oC - 90 ns VDD = 5V 1, 2, 3 +25oC - 180 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 5V 1, 2, 4 +25oC - 180 ns VDD = 10V 1, 2, 4 +25oC - 100 ns VDD = 15V 1, 2, 4 +25oC - 70 ns VDD = 5V 1, 2, 4 +25oC - 180 ns VDD = 10V 1, 2, 4 +25oC - 100 ns o VDD = 15V 1, 2, 4 +25 C - 70 ns TTHL TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns TWS VDD = 5V 1, 2, 3 +25oC - 140 ns VDD = 10V 1, 2, 3 +25oC - 80 ns VDD = 15V 1, 2, 3 +25oC - 70 ns TS Minimum Data Hold Time CONDITIONS TH TWR CIN o VDD = 5V 1, 2, 3 +25 C - 50 ns VDD = 10V 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 20 ns VDD = 5V 1, 2, 3 +25oC - 0 ns VDD = 10V 1, 2, 3 +25oC - 0 ns VDD = 15V 1, 2, 3 +25oC - 0 ns VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 140 ns VDD = 15V 1, 2, 3 +25oC - 100 ns 1, 2 +25oC - 7.5 pF Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage SYMBOL IDD VNTH CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC MIN MAX UNITS - 25 µA -2.8 -0.2 V All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 1151 Specifications CD4508BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D READ AND RECORD IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-1152 Specifications CD4508BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 5, 7, 9, 11, 17, 19, 21, 23 1-4, 6, 8, 10, 12-16, 18, 20, 22 24 Static Burn-In 2 Note 1 5, 7, 9, 11, 17, 19, 21, 23 12 1-4, 6, 8, 10, 1316, 18, 20, 22, 24 Dynamic BurnIn Note 1 - 1, 3, 12, 13, 15 2, 14, 24 5, 7, 9, 11, 17, 19, 21, 23 12 1-4, 6, 8, 10, 1316, 18, 20, 22, 24 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 5, 7, 9, 11, 17, 19, 21, 23 4, 6, 8, 10, 16, 18, 20, 22 - NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram OUTPUT DISABLE TYPICAL LATCH * OUTPUT DISABLE 3 OUTPUT DISABLE - A 1 VDD * RESET - A Qn-A 5(7, 9, 11) OUTPUT ST * 4(6, 8, 10) p Dn - A n VDD VSS ST ST ST p 2 * n ST STROBE - A ST VSS * All inputs protected by CMOS protection network. FIGURE 1. LOGIC DIAGRAM (A-SECTION), 1 OF 4 IDENTICAL LATCHES WITH COMMON OUTPUT DISABLE, RESET AND STROBE TRUTH TABLE RESET DISABLE STROBE D INPUT Q OUTPUT 0 0 1 1 1 0 0 1 0 0 0 0 0 X LATCHED 1 0 X X 0 X 1 X X Z 1 = HIGH LEVEL 0 = LOW LEVEL X = DON’T CARE Z = HIGH IMPEDANCE 7-1153 CD4508BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 15 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10 -15 -10V -20 -25 -15V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -30 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -5 -10V -15V PROPAGATION DELAY TIME (tPHL, tPLH) - ns TRANSITION TIME (fTHL, fTLH) (ns) 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 0 0 15V 20 -10 -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 50 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 150 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 175 150 SUPPLY VOLTAGE (VDD) = 5V 125 100 75 10V 50 15V 25 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 100 FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (STROBE TO DATA OUT) 7-1154 CD4508BMS Typical Performance Characteristics 105 POWER DISSIPATION PER 4-BIT LATCH (PD) - µW 8 6 4 2 104 8 6 4 103 (Continued) AMBIENT TEMPERATURE (TA) = +25oC, tr, tf = 20ns RL = 200kΩ SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V 2 8 6 4 2 102 8 6 4 CL = 50pF 2 CL = 15pF 10 2 4 68 2 4 6 8 2 2 4 6 8 4 6 8 101 103 102 INPUT FREQUENCY (fIN) (kHz) 10 104 FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY Waveforms and Test Circuits tW(st) STROBE INPUT tSU tH Dn INPUT tW(R) RESET OUTPUT DISABLE tPHL tPHL tPLH tPLH Qn OUTPUT tTLH tTHL FIIGURE 9. TEST WAVEFORMS VDD VDD 50% 50% VSS OUTPUT DISABLE tPLZ PULSE GEN D STROBE DISABLE D0 D1 D2 D3 RESET Q1 10% Q OUTPUT Q0 Q OUTPUT TEST ANY OUTPUT 1kΩ tPLZ 90% VOL VOH 90% 10% Q Q2 tPZH tPHZ 50pF Q3 TEST VOLT. VSS CHAR. AT D tPHZ VDD VSS tPLZ VSS VDD tPZL VSS VDD tPZH VDD VSS FIGURE 10. OUTPUT DISABLE TEST CIRCUIT AND WAVEFORMS 7-1155 VDD AT Q VSS CD4508BMS Bus Registers CD4508BMS CD4508BMS 3-STATE 4 BIT LATCH 3-STATE 4 BIT LATCH DATA BUS 4-LINE DATA BUS RESET CLOCK SERIAL DATA 4 BIT SHIFT REGISTER 4 BIT SHIFT REGISTER CD4019BMS 4-LINE DATA BUS CD4015BMS 3-STATE 4 BIT LATCH 3-STATE 4 BIT LATCH A B STROBE DISABLE QUAD LATCH (3 STATE) QUAD LATCH (3 STATE) FUNCTON SELECT CD4508BMS DISABLE 4-LINE DATA BUS FIGURE 11. BUS REGISTER A B 0 0 Inhibit (All 0) 1 0 Select A Bus 0 1 Select B Bus 1 1 AI + BI FIGURE 12. DUAL MULTIPLEXED BUS REGISTER WITH FUNCTION SELECT Chip Dimensions and Pad Layouts 0 10 FUNCTION 20 30 40 50 60 70 80 90 96 94 90 80 70 60 50 91-99 (2.311-2.515) 40 30 20 10 0 4-10 (0.102-0.254) 93-101 (2.362-2.565) Dimensions in parentheses are in milimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch.) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1156