Advanced Single Universal Pulse-Width Modulation (PWM) Controller ISL8130 Features The ISL8130 is a versatile controller that integrates control, output adjustment, monitoring and protection functions into a single package for synchronous buck, standard boost, SEPIC and flyback topologies. • Universal controller for multiple DC/DC converters • Wide input range - 4.5V to 5.5V - 5.5V to 28V The ISL8130 provides simple, single feedback loop, voltage mode control with fast transient response. The output voltage of the converter can be precisely regulated to as low as 0.6V. The switching frequency is adjustable from 100kHz to 1.4MHz. • Programmable soft-start • Supports pre-biased load applications • Resistor-selectable switching frequency - 100kHz to 1.4MHz The error amplifier features a 15MHz gain-bandwidth product and 6V/µs slew rate that enables fast transient response. The PWM duty cycle ranges from 0% to 100% in transient conditions. The capacitor from the ENSS pin to ground sets soft-start slew rate. • External reference tracking mode • Fast transient response - High-bandwidth error amplifier • Extensive circuit protection functions - Overvoltage, overcurrent, shutdown The ISL8130 monitors the output voltage and generates a PGOOD (power-good) signal when soft-start sequence is complete and the output is within regulation. A built-in overvoltage protection circuit prevents the output voltage from going typically above 115% of the set point. For a buck and buck-boost configuration, protection from overcurrent conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit the PWM operation appropriately. This approach improves efficiency by eliminating the need for a current sensing resistor. For other topologies, overcurrent protection is achieved using a current sensing resistor. • Pb-free (RoHS compliant) Applications • Power supplies for microprocessors/ASICs • Ethernet routers and switchers • Medical instrument power supplies Related Literature • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages” 5.6V to 16V C1 C3 C2 VIN VCC5 C4 R1 499Ω PVCC MONITOR AND PROTECTION ENSS OSC R3 10kΩ R6 C15 470pF L1 10µH 32V BOOT REF + + - FB 3.32kΩ LGATE C11 COMP 470pF R5 C12 PGND C7 0.1µF Rcs 5mΩ OCSET ISEN RT 47.5kΩ PGOOD R2 CDEL 0.1µF C8 SGND C6 C5 D1 UGATE PHASE REFOUT C14 2.2µF Q1 C9 C10 220µF x 2 REFIN 12.1kΩ 47nF R4 174kΩ FIGURE 1. BOOST CONVERTER October 5, 2012 FN7954.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL8130 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL8130IAZ 8130 IAZ -40 to +85 20 Ld QSOP M20.15 ISL8130IRZ 81 30IRZ -40 to +85 20 Ld 4x4 QFN L20.4x4 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8130 For more information on MSL please see techbrief TB363. Pin Configurations ISL8130 (20 LD QSOP) TOP VIEW BOOT UGATE PHASE PVCC LGATE ISL8130 (20 LD QFN) TOP VIEW 20 19 18 17 16 ISEN 1 15 PGND REFIN 2 14 CDEL OCSET 3 13 PGOOD REFOUT 4 12 ENSS 6 7 8 9 10 SGND RT FB 11 COMP VIN 5 VCC5 NC CDEL 1 PGND 2 19 ENSS LGATE 3 18 COMP PVCC 4 17 FB PHASE 5 20 PGOOD EP 16 RT UGATE 6 BOOT 7 14 VIN ISEN 8 13 VCC5 REFIN 9 12 NC OCSET 10 15 SGND 11 REFOUT Pin Descriptions PIN # QFN, QSOP SYMBOL DESCRIPTION 1, 8 ISEN Input to overcurrent protection comparator. Voltage on this pin is compared with voltage on OCSET pin to detect an overcurrent condition. Connect this pin to the junction of the inductor and a current sensing resistor in a boost, sepic and flyback configuration. Connect this pin to the phase node for sensing the voltage drop across the upper MOSFET in a buck configuration. See ‘Overcurrent Protection” on Page 13 for details. 2, 9 REFIN To use REFIN as input reference, connect the desired reference voltage to the REFIN pin in the range of 0.6V to 1.25V. To use internal reference voltage, tie this pin to VCC5. Do not leave the REFIN pin floating. 3, 10 OCSET An internal current source draws 100µA through a resistor connected between the supply and this pin. Voltage at this pin is compared with voltage at the ISEN pin for detecting an overcurrent condition. 4, 11 REFOUT This pin provides buffered reference output for REFIN. Connect 2.2µF decoupling capacitor to this pin. 5, 12 NC 6, 13 VCC5 This pin is the output of the internal 5V LDO. Connect a minimum of 4.7µF ceramic decoupling capacitor as close to the IC as possible at this pin. Refer to Table 1. 7, 14 VIN This pin powers the controller and must be decoupled to ground using a ceramic capacitor as close as possible to the VIN pin. 8, 15 SGND No Connect. This pin provides the signal ground for the IC. Tie this pin to the ground plane through the lowest impedance connection. 2 FN7954.3 October 5, 2012 ISL8130 Pin Descriptions (Continued) SYMBOL DESCRIPTION 9, 16 RT This is the oscillator frequency selection pin. Connecting this pin directly to VCC5 will select the oscillator free running frequency of 300kHz. By placing a resistor from this pin to GND, the oscillator frequency can be programmed from 100kHz to 1.4MHz. Figure 2 shows the oscillator frequency vs RT resistance. FREQUENCY (kHz) PIN # QFN, QSOP 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 25 50 75 RT (kΩ) 100 125 150 FIGURE 2. OSCILLATOR FREQUENCY vs RT 10, 17 FB This pin is connected to the feedback resistor divider and provides the voltage feedback signal for the controller. This pin sets the output voltage of the converter. 11, 18 COMP This pin is the error amplifier output pin. It is used as the compensation point for the PWM error amplifier. 12, 19 ENSS This pin provides enable/disable function and soft-start for the PWM output. The output drivers are turned off when this pin is held below 1V. 13, 20 PGOOD This pin provides a power-good status. It is an open collector output used to indicate the status of the output voltage. 14, 1 CDEL The PGOOD signal can be delayed by a time proportional to a CDEL current of 2µA and the value of the capacitor connected between this pin and ground. A 0.1µF will typically provide 125ms delay. 15, 2 PGND This pin provides the power ground for the IC. Tie this pin to the ground plane through the lowest impedance connection. 16, 3 LGATE This pin provides the PWM-controlled gate drive for the lower MOSFET in buck and buck/boost configuration. 17, 4 PVCC This pin is the power connection for the gate drivers. Connect this pin to the VCC5 pin. Connect a minimum of 1.0µF ceramic decoupling capacitor as close to the IC as possible at this pin. 18, 5 PHASE This pin also provides a return path for the upper gate driver. In a buck configuration it is the junction point of the inductor, the upper MOSFET source and the lower MOSFET drain. For boost, sepic and flyback configurations, this pin is tied to the power ground. 19, 6 UGATE This pin provides the PWM-controlled gate drive for the main switching MOSFET in all configurations. 20, 7 BOOT This pin is used to generate level shifted gate drive signals on the UGATE pin. Connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode in a buck or buck/boost configuration. For other topologies, connect this pin to PVCC. Please refer to typical application circuits beginning on page 5 for details. 21 (QSOP only) EP This pad is electrically isolated. Connect this pad to the signal ground plane using at least five vias for a robust thermal conduction path. 3 FN7954.3 October 5, 2012 Block Diagram VCC5 ENSS VIN OCSET 10µA ENSS 4 INTERNAL 0.6V 100µA LINEAR REGULATOR POWER-ON RESET (POR) ISEN OTP SSDONE BOOT REFIN OVERCURRENT COMP SSDONE REFOUT VOLTAGE CONTROL UGATE FAULT LOGIC SSDONE MODE PHASE CDEL PWM COMP SS PVCC VREF FB EA LGATE COMP PGND OSCILLATOR PGOOD PGOOD COMP OV/UV COMP FN7954.3 October 5, 2012 SGND RT EP (QFN ONLY) ISL8130 GATE CONTROL LOGIC ISL8130 Typical Step Down DC/DC Application Schematic 5.5V to 27V C6 C1 VIN PVCC C3 VCC5 C2 BOOT RT Q1 PGOOD R2 CDEL C8 L1 PHASE REF C11 Q2 LGATE -+ + + - FB VOUT ISEN SGND R3 C9 UGATE OSC C10 PGND REFIN COMP C7 0.1µF D1 R1 OCSET MONITOR AND PROTECTION ENSS C5 C4 REFOUT C12 R5 R4 Typical Standard Boost DC/DC Application Schematic 5.6V TO 16V C6 C1 C3 C2 VIN C4 R1 PVCC VCC5 MONITOR AND PROTECTION ENSS C5 RT R2 CDEL C8 L1 BOOT REF -+ + SGND UGATE PHASE 32V D1 C9 C10 Q1 + - FB R3 LGATE OSC C11 R5 COMP PGND C7 0.1µF PGOOD Rcs OCSET ISEN C12 REFOUT C14 REFIN R4 5 FN7954.3 October 5, 2012 ISL8130 Typical SEPIC DC/DC Application Schematic 8.4V TO 19V C6 C1 C3 C2 VIN VCC5 C4 R1 PVCC MONITOR AND PROTECTION ENSS C5 ISEN PGOOD R2 LGATE OSC REF -+ + SGND UGATE PHASE C11 R5 COMP C12 PGND + - FB R3 C13 BOOT CDEL C8 COUPLED INDUCTOR L1 RT C7 0.1µF Rcs OCSET REFOUT C14 C9 D1 12V C10 Q1 REFIN R4 6 FN7954.3 October 5, 2012 ISL8130 Absolute Maximum Ratings Thermal Information VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V PHASE, BOOT, and UGATE Pins to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V PVCC, VCC5, PGOOD, REFIN, and CDEL to GND . . . . . . . . . . . . . . . -0.3V to +6V LGATE, ENSS, COMP, FB and RT to GND . . . . . . . . . . . . . . .-0.3V to VCC5 + 0.3V OCSET and ISEN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V OCSET to ISEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +27V ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 150V Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV Latch Up (Tested per JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) QFN Package (Notes 4, 6) . . . . . . . . . . . . . . 43 6.5 QSOP Package (Notes 5, 7). . . . . . . . . . . . . 90 52 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature Range . . . . . . . . . . . . -40°C to +85°C (for “I” suffix) Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Recommended Operating Conditions VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to +24V OCSET to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.4V to +0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside. 7. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications Operating Conditions: VIN = 12V, PVCC shorted with VCC5, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 13) TYP MAX (Note 13) UNITS - 1.4 - mA - 2.0 3.0 mA VIN SUPPLY CURRENT Shutdown Current (Note 8) IVIN_SHDN Operating Current (Notes 8, 9) IVIN_OP EN/SS = GND VCC5 SUPPLY (Notes 9, 10) Input Voltage Range VIN = VCC5 for 5V configuration 4.5 5.0 5.5 V Output Voltage VIN = 5.6V to 28V, IL = 3mA to 50mA 4.5 5.0 5.5 V Maximum Output Current VIN = 12V 50 - - mA 4.310 4.400 4.475 V 4.090 4.100 4.250 V 0.16 - - V POWER-ON RESET Rising VCC5 Threshold VIN connected to VCC5, 5V input operation Falling VCC5 Threshold UVLO Threshold Hysteresis PWM CONVERTERS Maximum Duty Cycle fSW = 300kHz 90 96 - % Minimum Duty Cycle fSW = 300kHz - - 0 % - 80 - nA FB Pin Bias Current Undervoltage Protection VUV Fraction of the set point; ~3µs noise filter 75 - 85 % Overvoltage Protection VOVP Fraction of the set point; ~1µs noise filter 112 - 120 % Free Running Frequency RT = VCC5, TA = -40°C to +85°C 270 300 330 kHz Total Variation TA = -40°C to +85°C, with frequency set by external resistor at RT - ±10% - % Frequency Range (Set by RT) VIN = 12V 100 - 1400 kHz OSCILLATOR 7 FN7954.3 October 5, 2012 ISL8130 Electrical Specifications Operating Conditions: VIN = 12V, PVCC shorted with VCC5, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) MIN (Note 13) TYP MAX (Note 13) UNITS ΔVOSC - 1.25 - VP-P VREF 0.594 - 0.606 V ISS - 10 - µA VSOFT 1.0 - - V - - 1.0 V Gate Drive Pull Down Resistance - 2.0 - Ω Gate Drive Pull Up Resistance - 2.6 - Ω PARAMETER SYMBOL Ramp Amplitude (Note 11) TEST CONDITIONS REFERENCE AND SOFT-START/ENABLE Internal Reference Voltage Soft-Start Current Soft-Start Threshold Enable Low (Converter Disabled) PWM CONTROLLER GATE DRIVERS Rise Time Co = 3300pF - 25 - ns Fall Time Co = 3300pF - 25 - ns - 20 - ns - 88 - dB GBW - 15 - MHz SR - 6 - V/µs Dead Time Between Drivers ERROR AMPLIFIER DC Gain (Note 11) Gain-Bandwidth Product (Note 11) Slew Rate (Note 11) COMP Source/Sink Current (Note 11) ±0.4 mA OVERCURRENT PROTECTION OCSET Current Source IOCSET VOCSET = 4.5V 80 100 120 µA POWER-GOOD AND CONTROL FUNCTIONS Power-Good Lower Threshold VPG- Fraction of the set point; ~3µs noise filter -14 -10 -8 % Power-Good Higher Threshold VPG+ Fraction of the set point; ~3µs noise filter 9 - 16 % VPULLUP = 5.0V (Note 12) - - 1 µA PGOOD Voltage Low IPGOOD = 4mA - - 0.5 V PGOOD Delay CDEL = 0.1µF - 125 - ms CDEL Current for PGOOD CDEL threshold = 2.5V - 2 - µA - 2.5 - V Min External Reference Input at REFIN - 0.600 - V Max External Reference Input at REFIN - - 1.250 V PGOOD Leakage Current IPGLKG CDEL Threshold EXTERNAL REFERENCE REFERENCE BUFFER Buffered Output Voltage - Internal Reference VREFOUT IREFOUT = 1mA, CREFOUT = 2.2µF, TA = -40°C to +85°C 0.583 0.595 0.607 V Buffered Output Voltage - Internal Reference VREFOUT IREFOUT = 20mA, CREFOUT = 2.2µF, TA = -40°C to +85°C 0.575 0.587 0.599 V Buffered Output Voltage - External Reference VREFOUT VREFOUT= 1.25V, IREFOUT = 1mA, CREFOUT = 2.2µF, TA = -40°C to +85°C 1.227 1.246 1.265 V 8 FN7954.3 October 5, 2012 ISL8130 Electrical Specifications Operating Conditions: VIN = 12V, PVCC shorted with VCC5, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) MIN (Note 13) TYP MAX (Note 13) UNITS 1.219 1.238 1.257 V 20 - - mA Shutdown Temperature (Note 11) - 150 - °C Thermal Shutdown Hysteresis (Note 11) - 20 - °C PARAMETER SYMBOL Buffered Output Voltage - External Reference Current Drive Capability VREFOUT TEST CONDITIONS VREFOUT= 1.25V, IREFOUT = 20mA, CREFOUT = 2.2µF, TA = -40°C to +85°C CREFOUT = 2.2µF THERMAL SHUTDOWN NOTES: 8. The operating supply current and shutdown current specifications for 5V input are the same as VIN supply current specifications, i.e., 5.6V to 28V input conditions. These should also be tested with part configured for 5V input configuration, i.e., VIN = VCC5 = PVCC = 5V. 9. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current. 10. When the input voltage is 5.6V to 28V at VIN pin, the VCC5 pin provides a 5V output capable of 50mA (max) total from the internal LDO. When the input voltage is 5V, VCC5 pin will be used as a 5V input, the internal LDO regulator is disabled and the VIN must be connected to the VCC5. In both cases the PVCC pin should always be connected to VCC5 pin (refer to “Functional Description” on page 15 for more details). 11. Limits established by characterization and are not production tested. 12. It is recommended to use VCC5 as the pull-up source. 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9 FN7954.3 October 5, 2012 ISL8130 2.00 2.00 1.75 1.75 IVIN_SHDN(mA) IVIN_SHDN (mA) Typical Performance Curves Oscilloscope plots are taken using the ISL8130EVAL1Z Evaluation Board for buck converter or ISL8130EVAL2Z for boost converter, VIN = 12V, VOUT = 5V for buck converter or VOUT = 32V for boost converter unless otherwise noted. 1.50 1.25 1.00 -40 -15 10 35 60 1.50 1.25 1.00 4 85 8 12 16 TEMPERATURE (°C) 24 28 FIGURE 4. SHUTDOWN CURRENT, IVIN_SHDN vs VIN 3.00 4 2.50 3 IVIN_OP(mA) IVIN_OP (mA) FIGURE 3. SHUTDOWN CURRENT, IVIN_SHDN vs TEMPERATURE 2.00 2 1 1.50 1.00 -40 20 VIN (V) -15 10 35 60 0 85 4 8 12 16 TEMPERATURE (°C) 20 24 28 VIN (V) FIGURE 5. OPERATING CURRENT IVIN_OP vs TEMPERATURE FIGURE 6. OPERATING CURRENT IVIN_OP vs VIN 5.10 5.5 5.4 5.3 5.2 VVCC (V) VVCC (V) 5.05 5.00 5.1 5.0 4.9 4.8 4.95 4.7 4.6 4.90 -40 -15 10 35 TEMPERATURE (°C) FIGURE 7. VVCC vs TEMPERATURE 10 60 85 4.5 0 0.01 0.02 0.03 0.04 0.05 IVCC (A) FIGURE 8. VVCC vs IVCC FN7954.3 October 5, 2012 ISL8130 Typical Performance Curves Oscilloscope plots are taken using the ISL8130EVAL1Z Evaluation Board for buck converter or ISL8130EVAL2Z for boost converter, VIN = 12V, VOUT = 5V for buck converter or VOUT = 32V for boost converter unless otherwise noted. (Continued) 0.610 320 310 FSW (kHz) VREF (V) 0.605 0.600 0.595 0.590 -40 300 290 280 -15 10 35 60 270 -40 85 -15 TEMPERATURE (°C) FIGURE 9. VREF vs TEMPERATURE 60 85 60 85 12 11 1.05 ISS (µA) IOCSET NORMALIZED 35 FIGURE 10. FSW vs TEMPERATURE 1.15 10 0.95 9 0.85 -40 -15 10 35 TEMPERATURE (°C) 60 8 -40 85 10 35 FIGURE 12. SOFT-START CURRENT, ISS vs TEMPERATURE 2.2 1.25 1.10 2.1 ICDEL(µA) 0.95 0.80 2.0 1.9 0.65 0.50 0.50 -15 TEMPERATURE (°C) FIGURE 11. IOCSET vs TEMPERATURE VFB (V) 10 TEMPERATURE (°C) 0.65 0.80 0.95 VREFIN (V) FIGURE 13. VFB vs VREFIN 11 1.10 1.25 1.8 -40 -15 10 35 60 85 TEMPERATURE (°C) FIGURE 14. CDEL CURRENT FOR PGOOD, ICDEL vs TEMPERATURE FN7954.3 October 5, 2012 ISL8130 Typical Performance Curves Oscilloscope plots are taken using the ISL8130EVAL1Z Evaluation Board for buck converter or ISL8130EVAL2Z for boost converter, VIN = 12V, VOUT = 5V for buck converter or VOUT = 32V for boost converter unless otherwise noted. (Continued) VIN VIN EN/SS EN/SS VOUT VOUT PHASE PHASE FIGURE 15. SOFT-START WAVEFORM, NO PREBIASED, BUCK CONVERTER VOUT FIGURE 16. SOFT-START WAVEFORM, PREBIASED, BUCK CONVERTER VOUT PGOOD PGOOD EN/SS EN/SS CDEL CDEL = 0.1µF FIGURE 17. PGOOD PULL-UP DELAY AT START UP, BUCK CONVERTER CDEL CDEL = 0.1µF FIGURE 18. PGOOD PULL-DOWN AT SHUTDOWN, BUCK CONVERTER VOUT VOUT VIN PHASE EN/SS FIGURE 19. SOFT-START WAVEFORM, NO PREBIASED, BOOST CONVERTER 12 VIN PHASE EN/SS FIGURE 20. SOFT-START WAVEFORM, PREBIASED, BOOST CONVERTER FN7954.3 October 5, 2012 ISL8130 Typical Performance Curves Oscilloscope plots are taken using the ISL8130EVAL1Z Evaluation Board for buck converter or ISL8130EVAL2Z for boost converter, VIN = 12V, VOUT = 5V for buck converter or VOUT = 32V for boost converter unless otherwise noted. (Continued) VOUT VOUT IINDUCTOR EN/SS VIN IINDUCTOR EN/SS PGOOD FIGURE 22. OVERCURRENT PROTECTION, BOOST CONVERTER FIGURE 21. OVERCURRENT PROTECTION, BUCK CONVERTER EN/SS VOUT IOUT EN/SS VIN PGOOD VOUT IINDUCTOR FIGURE 23. OCP ENTRY AND RECOVERY, BUCK CONVERTER FIGURE 24. OCP ENTRY AND RECOVERY, BOOST CONVERTER 1.00 1.00 VIN = 12V, VOUT = 5V VIN = 12V, VOUT = 32V 0.95 EFFICIENCY EFFICIENCY 0.95 0.90 0.85 VIN = 6V, VOUT = 32V 0.90 0.85 FSW = 280kHz 0.80 0 5 10 15 20 LOAD CURRENT (A) FIGURE 25. EFFICIENCY VS LOAD CURRENT, BUCK CONVERTER, UPPER AND LOWER MOSFET: BSC057N03LS X 2; INDUCTOR: SER2010-901 13 25 0.80 FSW = 320kHz 0 0.25 0.50 0.75 1.00 1.25 LOAD CURRENT (A) FIGURE 26. EFFICIENCY VS LOAD CURRENT, BOOST CONVERTER, MOSFET: BSC100N06LS; INDUCTOR: WE 74477110 FN7954.3 October 5, 2012 ISL8130 Typical Performance Curves Oscilloscope plots are taken using the ISL8130EVAL1Z Evaluation Board for buck converter or ISL8130EVAL2Z for boost converter, VIN = 12V, VOUT = 5V for buck converter or VOUT = 32V for boost converter unless otherwise noted. (Continued) VIN = 12V, VOUT = 5V IOUT, 10A/DIV VIN = 12V, VOUT = 32V IOUT, 0.5A/DIV VOUT, AC, 50mV/DIV VOUT, AC, 500mV/DIV ISTEP: 0A to 25A 3A/µs ISTEP: 0.5A to 1.25A 3A/µs FIGURE 27. LOAD TRANSIENT, BUCK CONVERTER, INDUCTOR: SER2010-901; COUT: 2*16SEPC180MX FIGURE 28. LOAD TRANSIENT, BOOST CONVERTER, INDUCTOR: WE 74477110; COUT: 2*220µF 50V, 42mΩ ESR 14 FN7954.3 October 5, 2012 ISL8130 Functional Description Initialization If the REFIN is connected to an external voltage source between 0.6V to 1.25V, then this external voltage is used as the reference voltage at the positive input of the error amplifier. The ISL8130 automatically initializes upon receipt of power. The Power-On Reset (POR) function monitors the internal bias voltage generated from LDO output (VCC5) and the ENSS pin. The POR function initiates the soft-start operation after the VCC5 exceeds the POR threshold. The POR function inhibits operation with the chip disabled (ENSS pin <1V). Power-Good The device can operate from an input supply voltage of 5.5V to 24V connected directly to the VIN pin using the internal 5V linear regulator to bias the chip and supply the gate drivers. For 5V ±10% applications, connect VIN to VCC5 to bypass the linear regulator. Refer to Table 1. The CDEL is used to set the PGOOD active delay after soft-start. After the ENSS pin completes its soft-start ramp, a 2µA current begins charging the CDEL capacitor to 2.5V. The capacitor will be quickly discharged before PGOOD goes high. The programmable delay can be used to sequence multiple converters or as a LOW-true reset signal. TABLE 1. INPUT SUPPLY CONFIGURATION INPUT PIN CONFIGURATION 5.5V to 24V Connect the input to the VIN pin. The VCC5 pin will provide a 5V output from the internal LDO. Connect PVCC to VCC5. 5V ±10% Connect the input to the VCC5 pin. Connect the PVCC and VIN pins to VCC5. Shutdown When ENSS pin is below 1V, the regulator is disabled with the PWM output drivers tri-stated. When disabled, the IC power will be reduced. The PGOOD pin can be used to monitor the status of the output voltage. PGOOD will be true (open drain) when the FB pin is within ±10% of the reference and the ENSS pin has completed the soft-start ramp. If the voltage on the FB pin exceeds ±10% of the reference, the PGOOD will go low after 1µs of noise filtering. Overcurrent Protection The Overcurrent Protection (OCP) function protects the converter from an overcurrent condition. The OCP circuit compares voltages at the OCSET and the ISEN pin and signals an overcurrent condition when ISEN drops below OCSET. Voltage at the OCSET pin acts as a reference and is established by a resistor connected to this pin from the input supply rail. An internal current source draws a current IOCSET (typically 100µA) from the OCSET pin resulting in a voltage at the pin given by Equation 1. (EQ. 1) Soft-Start/Enable V OCSET = V IN – R OCSET xI OCSET The ISL8130 soft-start function uses an internal current source and an external capacitor to reduce stresses and surge current during start-up. The ISEN pin is connected to a current sensing resistor that senses the current drawn from the input supply. This current sensing resistor could be the rDS(ON) of the upper MOSFET if the ISL8130 is used in a buck configuration. Please refer to the “Block Diagram” on page 4 for more details. Voltage at the ISEN pin is given by Equation 2. When the output of the internal linear regulator reaches the POR threshold, the POR function initiates the soft-start sequence. An internal 10µA current source charges an external capacitor on the ENSS pin linearly from 0V to 3.3V. When the ENSS pin voltage reaches 1V typically, the internal 0.6V reference begins to charge following the dv/dt of the ENSS voltage. As the soft-start pin charges from 1V to 1.6V, the reference voltage charges from 0V to 0.6V. Figure 15 shows a typical soft-start sequence. Start-up into Pre-Biased Load The ISL8130 is designed to power-up into a pre-biased load. During the soft starting, the error amplifier compares the voltage of the FB pin and the rising reference voltage given by the ENSS pin. The COMP pin is hold down if the VFB is greater than the rising reference voltage thus inhibiting switching. The ISL8130 starts switching when the rising reference voltage exceeds the FB pin voltage. ISL8130 operates in CCM afterwards. The waveform for this condition is shown in Figure 19. External Reference/Tracking If REFIN pin is tied to VCC5, then the internal 0.6V reference is used as the error amplifier non-inverting input. 15 V ISEN = V IN – R CS xI IN (EQ. 2) Combining Equations 1 and 2 gives the overcurrent trip point as given in Equation 3. R OCSET xI OCSET I OC = ------------------------------------------------R CS (EQ. 3) When UGATE is high, current through the sense resistor increases. If it increases enough to make VISEN smaller than VOCSET, an overcurrent event is registered for that clock cycle, a counter is incremented and the UGATE pulse is immediately terminated. If an overcurrent condition is registered for 8 consecutive cycles, the ISL8130 enters into a soft-start hiccup mode. During hiccup, the external capacitor on the ENSS pin is discharged. After the capacitor is discharged, it is released and a soft-start cycle is initiated. There are three dummy soft-start delay cycles to allow the power devices to cool down and to alleviate the thermal stress in overload or short circuit conditions. At the fourth soft-start cycle, the output starts a normal soft-start cycle, and the output tries to ramp. It is important to connect the OCSET and ISEN traces right across the current sensing resistor for good accuracy of the OCP FN7954.3 October 5, 2012 ISL8130 threshold. A Kelvin connection is recommended to avoid noise coupling. In a buck configuration, the OC trip point varies mainly due to the upper MOSFETs rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from Equation 1 with: 1. The maximum rDS(ON) at the highest junction temperature. 2. Determine I OC for I OC > I OUT ( MAX ) + ( ΔI ) ⁄ 2 , where ΔI is the output inductor ripple current. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Both the ROCSET and the filtering cap should be placed close to the ISL8130. The OCP function is active once the ENSs reaches the enable threshold voltage. Over-Temperature Protection The ISL8130 is protected against over-temperature conditions. When the junction temperature exceeds +150°C, the PWM shuts off. Normal operation is resumed when the junction temperature decreases to 130°C. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. Figure 29 shows the critical power components of the buck converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 29 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL8130 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL8130 must be sized to handle up to 1A peak current. VIN Undervoltage ISL8130 UGATE Overvoltage Protection If the voltage on the FB pin exceeds the reference voltage by 15%, the lower gate driver is turned on continuously to discharge the output voltage. If the overvoltage condition continues for 32 consecutive PWM cycles, then the chip is turned off with the gate drivers tri-stated. The voltage on the FB pin will fall and reach the 15% undervoltage threshold. After 8 clock cycles, the chip will enter soft-start hiccup mode. This mode is identical to the overcurrent hiccup mode. This overvoltage protection is disabled if the ENSS does not reach 3.3V. Gate Control Logic The gate control logic translates PWM control signals into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operational conditions. Q1 LO VOUT PHASE LGATE Q2 D2 CIN LOAD If the voltage on the FB pin is less than 85% of the reference voltage for 8 consecutive PWM cycles, then the circuit enters into soft-start hiccup mode. This mode is identical to the overcurrent hiccup mode. This undervoltage protection is disabled if the ENSS does not reach 3.3V. CO GND RETURN FIGURE 29. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS Figure 30 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, Css close to the SS pin because the internal current source is only 10µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. In a boost converter configuration, the LGATE signal may be left floating. 16 FN7954.3 October 5, 2012 ISL8130 D1 CBOOT Q1 OSC LO PHASE ENSS +5V Q2 CO DRIVER PWM COMPARATOR VOUT LOAD ISL8130 VIN +VIN BOOT + DVOSC CVCC DRIVER CO ZFB ZIN + All control traces, such as feedback resistor divider connection, compensation network connection should be placed away from the high dv/dt node. Use Kelvin sensing connection for current sensing. PHASE VE/A GND FIGURE 30. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES VOUT ESR (PARASITIC) VCC CSS LO REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS ZFB C2 General PowerPAD Design Considerations C1 Figure 31 is an example of how to use vias to remove heat from the IC. VOUT ZIN C3 R2 R3 R1 COMP FB + R4 ISL8130 REF R 1⎞ ⎛ V OUT = V REF x ⎜ 1 + -------⎟ R ⎠ ⎝ 4 FIGURE 31. PCB VIA PATTERN We recommend you fill the thermal pad area with vias. A typical via array would be to fill the thermal pad footprint with space, such that they are center on center 3x the radius apart from each other. Keep the Vias small but not so small that their inside diameter prevents solder wicking through the holes during reflow. Connect all vias to the ground plane. It is important the vias have a low thermal resistance for efficient heat transfer. It is important to have a complete connection of the plated through-hole to each plane. Feedback Compensation Figure 32 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. 17 FIGURE 32. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ΔVOSC. Modulator Break Frequency Equations 1 F LC = --------------------------------------2π • L O • C O (EQ. 4) 1 F ESR = --------------------------------------------2π • ( ESR • C O ) (EQ. 5) The compensation network consists of the error amplifier (internal to the ISL8130) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180°. The following equations relate to the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 32. Use the following guidelines for locating the poles and zeros of the compensation network. FN7954.3 October 5, 2012 ISL8130 Compensation Break Frequency Equations Component Selection Guidelines 1 F Z1 = ---------------------------------2π • R 2 • C1 (EQ. 6) Buck Converter Component 1 F P1 = ------------------------------------------------------C1 • C2 2π • R2 • ⎛ ----------------------⎞ ⎝ C1 + C2⎠ (EQ. 7) 1 F Z2 = -----------------------------------------------------2π • ( R1 + R3 ) • C3 (EQ. 8) 1 F P2 = ---------------------------------2π • R3 • C3 (EQ. 9) 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Figure 33 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 33. Using the previously mentioned guidelines should give a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Loop Gain is constructed on the log-log graph of Figure 33 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. 100 FZ1 FZ2 FP1 FP2 GAIN (dB) 40 20 OPEN LOOP ERROR AMP GAIN 20LOG (R2/R1) 20LOG (VIN/DVOSC) 0 -40 -60 COMPENSATION GAIN MODULATOR GAIN -20 LOOP GAIN FLC 10 100 1k FESR 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 33. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. 18 The logic level MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements, two N-Channel MOSFETs for the Buck converter. These MOSFETs should be selected based upon rDS(ON), gate supply requirements, and thermal management considerations. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see Equations 10 and 11). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses since the lower device turns on and off into near zero voltage. The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET’s body diode. 2 ( I O ) ( r DS ( ON ) ) ( V OUT ) ( I O ) ( V IN ) ( t SW ) ( F SW ) P UPPER = --------------------------------------------------------------- + -----------------------------------------------------------V IN 2 (EQ. 10) 2 ( I O ) ( r DS ( ON ) ) ( V IN – V OUT ) P LOWER = ------------------------------------------------------------------------------V IN (EQ. 11) A large gate-charge increases the switching time, tSW , which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. OUTPUT INDUCTOR SELECTION 80 60 MOSFET CONSIDERATIONS The PWM converters require output inductors. The output inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by Equation 12: ( V IN – V OUT ) ( V OUT ) ΔI L = ---------------------------------------------------------( f S ) ( L ) ( V IN ) (EQ. 12) OUTPUT CAPACITOR SELECTION The output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the output inductor, thus some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to its new level. The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can FN7954.3 October 5, 2012 ISL8130 The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is shown in Equation 13: Boost Converter Layout Considerations VIN LBST 2 ( L O ) ( I TRAN ) C OUT = ----------------------------------------------------------2 ( V IN – V O ) ( DV OUT ) (EQ. 13) D2 where COUT is the output capacitor(s) required, LO is the output inductor, ITRAN is the transient load current step, VIN is the input voltage, VO is output voltage, and DVOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Equivalent Series Resistance) and voltage rating requirements as well as actual capacitance requirements. The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by Equation 14: V RIPPLE = ΔI L ( ESR ) CIN RCS ISL8130 (EQ. 14) Q1 UGATE VOUT LOAD minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor. CO PHASE RETURN FIGURE 34. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS Figure 34 shows the critical power components of the boost converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 34 should be located as close together as possible. where, IL is calculated in the “Output Inductor Selection” on page 18. Boost Converter Component Selection High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. MOSFET CONSIDERATIONS Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. In most cases, multiple small-case electrolytic capacitors perform better than a single large-case capacitor. The important parameters for the bulk input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25x greater than the maximum input voltage and 1.5x is a conservative guideline. The AC RMS Input current varies with the load. The total RMS current supplied by the input capacitance is given by Equation 15: 2 DC – DC ⋅ I O (EQ. 15) where, DC is duty cycle of the buck converter. Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. 19 2 ( I OUT ) ( V OUT ) ( t SWON + t SWOFF ) ( F SW ) P FET = P COND + -----------------------------------------------------------------------------------------------------------------2 • V IN (EQ. 16) The conduction Loss PCOND is given by Equation 17: 2 P COND = ( I RMSFET ) • r DS ( ON ) (EQ. 17) Where IRMSFET is the MOSFET RMS drain current (Equation 18). INPUT CAPACITOR SELECTION I RMSx = The boost converter MOSFET has both conduction loss and switching losses (Equation 16). 2 I OUT • V OUT Δi PP ⎞ ⎛ I RMSFET = ----------------------------------- • DC • ⎜ 1 + ----------------⎟ V IN 12 ⎠ ⎝ (EQ. 18) DC is duty cycle of the boost converter. The switching loss is shown by Equation 19: 2 ( I OUT ) ( V OUT ) ( t SWON + t SWOFF ) ( F SW ) P SW = -----------------------------------------------------------------------------------------------------------------2 • V IN (EQ. 19) tSWON and tSWOFF are the MOSFET turn on and turn off time respectively and Vm is the plateau voltage during the MOSFET turn on and turn off (Equations 20, 21): Q gd • ( 2Ω + R GFET ) t SWON = -------------------------------------------------------( PVCC – V m ) (EQ. 20) Q gd • ( 2Ω + R GFET ) t SWOFF = -------------------------------------------------------Vm (EQ. 21) FN7954.3 October 5, 2012 ISL8130 The optimum MOSFET is usually that the conduction loss equals the switching loss. The worst case for the MOSFET is at the minimum VIN, when the inductor average current is the maximum. The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the Schottky diode. INDUCTOR SELECTION For a boost converter, the output ripple is not a strong function of the boost inductor. The inductor is selected to meet the efficiency, size and thermal requirement. Usually a smaller inductor is preferred for cost, size and easy compensation. When a small inductor is used, the inductor ripple current is large incurring larger core loss. The ripple ration is usually from 30% to 50% (Equation 22). V OUT 2 L BST = ------------------------------------- DC ( 1 – DC ) F SW ΔI R I OUT (EQ. 22) Where is ΔIR the desired ripple ratio. DC is the boost converter duty cycle. The DC inductor current is the maximum at the minimum VIN (Equation 23). Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the MOSFET and diode to suppress the voltage induced in the parasitic circuit impedances. CURRENT SENSING RESISTOR SELECTION A small current sensing resistor is preferred for high efficiency conversion. A too small RCS might not render an accurate overcurrent protection threshold. The current sensing resistor should be selected so that the voltage across the current sensing resistor at OCP be greater than 500mV for accurate OCP trip threshold (Equation 27). 500mV R CS = -----------------------------------------------------------I PKIND • ( 1 + M arg in ) (EQ. 27) Where IPKIND is the maximum inductor peak current. It is recommended to have 25% margin for load transient and variation. Then the resistor should be sized to survive the maximum stress at OCP (Equation 28). P RCS = R CS ( I PKIND • ( 1 + M arg in ) ) 2 (EQ. 28) 2 I OUT • V OUT Δi PP I RMSIND = ----------------------------------- • 1 + ---------------V IN 12 (EQ. 23) The maximum peak inductor current occurs at the minimum input (Equation 24). V INMIN⎞ 1 V INMIN ⎛ I PKIND = I RMSIND + --- --------------------------- ⎜ 1 – --------------------⎟ V OUT ⎠ 2 L BST F SW ⎝ (EQ. 24) Select the inductor using Equation 22. with saturation current higher than that calculated with Equation 24. Make sure the inductor can handle the thermal stress. OUTPUT CAPACITORS SELECTION The important parameters for the bulk output capacitor(s) are the voltage rating, the RMS current rating and output ripple. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum output voltage, which should be the OVP threshold and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25x greater than the maximum output voltage and 1.5x is a conservative guideline. The AC RMS output current varies with the load and VIN. The total RMS current filtered by the output capacitance is given by Equation 25: V OUT I RMSOUT = I OUT • ---------------- – 1 V IN (EQ. 25) INPUT CAPACITOR SELECTION The input current ripple for a boost converter is much smaller than the output ripple. The input capacitor of the boost converter is to filter out the inductor ripple current and to stabilize the power supply and the boost converter. The input capacitor should take the input RMS current (Equation 29). I RMSIN = ⎞ 1 ⎛ V OUT ------ • ⎜ ------------------------------- • DC ( 1 – DC )⎟ 12 ⎝ L BST ⋅ F SW ⎠ (EQ. 29) If the boost converter is powered by another DC/DC converter with sufficient output capacitors, a small ceramic capacitor can be used for the input capacitor. Boost Converter Compensation MODULATOR BREAK FREQUENCY EQUATIONS The modulator DC gain is (Equation 30): V OUT G DC = --------------------------------------------V OSC • ( 1 – DC ) (EQ. 30) VOSC is the internal oscillator output amplitude, which is 1.25V, DC is the boost converter duty cycle. The Boost converter double pole is a function of the duty cycle, inductor and output capacitor (Equation 31). The worst case is at full load and minimum VIN. When the maximum AC ripple current is as shown in Equation 26: 1 – DC F LC = ---------------------------------------------2π • ( L BST • C O ) V OUT I RMSOUT = I OUTMAX • -------------------- – 1 V INMIN The output capacitor ESR adds a zero to the loop gain (Equation 32). (EQ. 26) 1 F ESR = --------------------------------------------2π • ( ESR • C O ) 20 (EQ. 31) (EQ. 32) FN7954.3 October 5, 2012 ISL8130 The right-half-plane zero is a function of load current, VIN and the boost inductance. The RHP zero causes phase lag decreasing phase margin. It is recommended to have the closed loop gain cross 0dB at 1/3 of the FRHP (Equation 33). V IN • ( 1 – DC ) F RHP = --------------------------------------------------2π • ( I OUT • L BST ) (EQ. 33) Compensation Break Frequency Equations 1 F Z1 = ---------------------------------2π • R 2 • C1 (EQ. 34) Figure 35 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the right half plane zero, FRHP 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain (EQ. 35) 1 F Z2 = -----------------------------------------------------2π • ( R1 + R3 ) • C3 (EQ. 36) 1 F P2 = ---------------------------------2π • R3 • C3 (EQ. 37) The compensation network consists of the error amplifier (internal to the ISL8130) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180°. The following equations relate to the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 32. Use the following guidelines for locating the poles and zeros of the compensation network. Figure 35 shows an asymptotic plot of the Boost converter’s gain vs frequency. Using the previously mentioned guidelines should give a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Loop Gain is constructed on the log-log graph of 21 Estimate Phase Margin - Repeat if Necessary In applications when the RHP zero makes the stabilizing the converter very difficult, it is recommended to increase the output capacitor. 100 FZ1 FZ2 FP1 FP2 80 OPEN LOOP ERROR AMP GAIN 60 GAIN (dB) 1 F P1 = ------------------------------------------------------C1 • C2 2π • R2 • ⎛ ----------------------⎞ ⎝ C1 + C2⎠ 40 20 0 20LOG (R2/R1) 20LOG (VO/(DVOSC*(1-D))) -40 -60 COMPENSATION GAIN MODULATOR GAIN -20 LOOP GAIN FLC 10 100 1k FRHP FESR 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 35. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN FN7954.3 October 5, 2012 ISL8130 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE September 26, 2012 FN7954.3 “Overcurrent Protection” on page 15 - Changed VOCSET to IOCSET Equation 22 on page 20 -- Added IOUT to the equation. “Output Capacitors Selection” on page 20 - Changed “input ” to “output” - Deletetd “use a mix of input capacitors to control the voltage ripple across MOSFETs.” February 22, 2012 FN7954.2 Correction to “Typical Step Down DC/DC Application Schematic” on page 5. Connections corrected for VIN and PVCC. Removed capacitor C14 and GND from REFOUT. February 13, 2012 FN7954.1 Made correction to units for Shutdown and Operating Currents on page 7 from µA to mA. “PWM CONTROLLER GATE DRIVERS” on page 8 - changed Typical value in pull-down resistance from 2.6 to 2.0 and changed Typical value in pull-up resistance from 2.0 to 2.6 Load Transient Figures 27 and 28 on page 14 replaced to show a clearer description of the waveforms. February 9, 2012 FN7954.0 Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page. Also, please check the product information page to ensure that you have the most updated datasheet: ISL8130 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 FN7954.3 October 5, 2012 ISL8130 Package Outline Drawing M20.15 20 LEAD QUARTER SIZE OUTLINE PLASTIC PACKAGE (QSOP) Rev 2, 1/11 20 INDEX AREA 1 2 0.244 (6.19) 0.157 (3.98) 0.228 (5.80) 0.150 (3.81) 4 3 GAUGE PLANE TOP VIEW 6 0.050 (1.27) 0.25 0.010 SEATING PLANE 3 0.069 (1.75) 0.053 (1.35) 0.344 (8.74) 0.337 (8.56) 0.016 (0.41) 0.0196 (0.49) 5 0.0099 (0.26) 8° 0° 0.012 (0.30) 0.008 (0.20) 0.025 (0.635 BSC) 8 0.010 (0.25) 0.004 (0.10) 0.061 MAX (1.54 MIL) SIDE VIEW 0.010 (0.25) 0.007 (0.18) DETAIL "X" NOTES: 0.015 (0.38) x 20 0.025 (0.64) x 18 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 20 0.060 (1.52) x 20 3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 0.220(5.59) 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. Length of terminal for soldering to a substrate. 7. Terminal numbers are shown for reference only. 1 2 3 TYPICAL RECOMMENDED LAND PATTERN 8. Dimension does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of dimension at maximum material condition. 9. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. 23 FN7954.3 October 5, 2012 ISL8130 Package Outline Drawing L20.4x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 11/06 4X 4.00 2.0 16X 0.50 A B 16 6 PIN #1 INDEX AREA 20 6 PIN 1 INDEX AREA 1 15 4.00 2 . 10 ± 0 . 15 11 5 0.15 (4X) 6 10 0.10 M C A B 4 0.25 +0.05 / -0.07 TOP VIEW 20X 0.6 +0.15 / -0.25 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 C BASE PLANE ( 3. 6 TYP ) ( SEATING PLANE 0.08 C ( 20X 0 . 5 ) 2. 10 ) SIDE VIEW ( 20X 0 . 25 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. ( 20X 0 . 8) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 24 FN7954.3 October 5, 2012