INTERSIL KAD5512P-50

KAD5512P-50
®
Data Sheet
December 5, 2008
FN6805.0
12-Bit, 500MSPS A/D Converter
Features
General Description
• Programmable Gain, Offset and Skew control
The KAD5512P-50 is a low-power, high-performance, 12-bit,
500MSPS analog-to-digital converter designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process. The KAD5512P-50 is part of a
pin-compatible portfolio of 10, 12 and 14-bit A/Ds with
sample rates ranging from 125MSPS to 500MSPS.
• 1.3GHz Analog Input Bandwidth
The device utilizes two time-interleaved 12-bit, 250MSPS
A/D cores to achieve the ultimate sample rate of 500MSPS.
A single 500MHz conversion clock is presented to the
converter, and all interleave clocking is managed internally.
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider: ÷1 or ÷2
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of matching
characteristics (gain, offset, skew) between the two
converter cores. These adjustments allow the user to
minimize spurs associated with the interleaving process.
• Programmable Built-in Test Patterns
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512P-50 is available in a 72-contact QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
• Broadband Communications
• Single-Supply 1.8V Operation
Applications
• Radar and Satellite Antenna Array Processing
• High-Performance Data Acquisition
Key Specifications
• SNR = 64.0dBFS for fIN = 250MHz (-1dBFS)
KAD5514P-25
14
250
KAD5514P-21
14
210
KAD5514P-17
14
170
KAD5514P-12
14
125
KAD5512P-50
12
500
KAD5512P-25, KAD5512HP-25
12
250
KAD5512P-21, KAD5512HP-21
12
210
KAD5512P-17, KAD5512HP-17
12
170
• SFDR = 78dBc for fIN = 250MHz (-1dBFS)
• Power Consumption = 407mW
CLKP
12
125
KAD5510P-50
10
500
CLKOUTP
Clock Generation
&
Interleave Control
CLKN
SHA
KAD5512P-12, KAD5512HP-12
OVDD
SPEED
(MSPS)
CLKDIV
RESOLUTION
MODEL
AVDD
Pin-Compatible Family
CLKOUTN
12-bit
250 MSPS
ADC
D[11:0]N
ORP
VREF
VINP
Digital
Error
Correction
VINN
Ordering Information
D[11:0]P
ORN
OUTFMT
OUTMODE
72 Ld QFN L72.10X10D
1
VREF
1.25 V
+
–
SPI
Control
OGND
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
12-bit
250 MSPS
ADC
CSB
SCLK
SDIO
SDO
-40 to +85
SHA
AGND
500
VCM
NAPSLP
KAD5512P-50Q72
PKG.
DWG. #
RESET
PART NUMBER SPEED TEMP. RANGE PACKAGE
(Note)
(MSPS)
(°C)
(Pb-Free)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD5512P-50
Table of Contents
Absolute Maximum Ratings ......................................... 3
Serial Peripheral Interface ........................................... 18
Thermal Information...................................................... 3
SPI Physical Interface................................................
SPI Configuration.......................................................
Device Information .....................................................
Indexed Device Configuration/Control .......................
Global Device Configuration/Control..........................
Device Test ................................................................
SPI Memory Map .......................................................
Electrical Specifications ............................................... 3
Digital Specifications .................................................... 5
Timing Diagrams ........................................................... 5
Switching Specifications .............................................. 6
Thermal Impedance....................................................... 6
ESD ................................................................................. 6
Pinout/Package Information......................................... 7
Pin Descriptions.......................................................... 7
Pin Configuration ........................................................ 8
Typical Performance Curves ........................................ 9
Theory of Operation ...................................................... 12
Functional Description ................................................
Power-On Calibration .................................................
User Initiated Reset ....................................................
Analog Input ...............................................................
Clock Input .................................................................
Jitter............................................................................
Voltage Reference......................................................
Digital Outputs ............................................................
Over Range Indicator .................................................
Power Dissipation.......................................................
Nap/Sleep...................................................................
Data Format ...............................................................
2
12
12
13
13
14
15
15
15
15
15
15
16
18
18
19
19
20
21
22
Equivalent Circuits ....................................................... 23
Layout Considerations................................................. 24
Split Ground and Power Planes.................................
Clock Input Considerations ........................................
Exposed Paddle.........................................................
Bypass and Filtering ..................................................
LVDS Outputs ............................................................
LVCMOS Outputs ......................................................
Unused Inputs............................................................
24
24
24
24
24
24
24
Definitions ..................................................................... 24
Revision History ........................................................... 25
Package Outline Drawing............................................. 26
L72.10x10D .................................................................... 26
FN6805.0
December 5, 2008
KAD5512P-50
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 500MSPS.
KAD5512P-50
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.40
1.47
1.54
VP-P
DC SPECIFICATIONS (Note 1)
Analog Input
Full-Scale Analog Input Range
VFS
Differential
Input Resistance
RIN
Differential
500
Ω
Input Capacitance
CIN
Differential
1.9
pF
Full Scale Range Temp. Drift
AVTC
Full Temp
90
ppm/°C
Input Offset Voltage
VOS
Gain Error
Common-Mode Output Voltage
-10
±2
10
mV
EG
±2
%
VCM
0.535
V
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.7
1.8V Digital Supply Voltage
OVDD
1.7
1.8V Analog Supply Current
IAVDD
1.8V Digital Supply Current (Note 1)
IOVDD
Power Supply Rejection Ratio
PSRR
1.8
1.9
V
1.8
1.9
V
158
167
mA
3mA LVDS
68
76
mA
30MHz, 200mVP-P
-36
3mA LVDS
407
438
mW
dB
Power Dissipation
Normal Mode
PD
Nap Mode
PD
135
157
mW
Sleep Mode
PD
15
18
mW
AC SPECIFICATIONS
Differential Nonlinearity
DNL
Integral Nonlinearity
INL
Minimum Conversion Rate (Note 3)
fS MIN
Maximum Conversion Rate
fS MAX
Signal-to-Noise Ratio
SNR
-1.0
LSB
±1.4
LSB
160
500
MSPS
MSPS
fIN = 10MHz
64.3
dBFS
fIN = 70MHz
64.3
dBFS
64.2
dBFS
fIN = 230MHz
64.0
dBFS
fIN = 400MHz
63.2
dBFS
fIN = 995MHz
58.0
dBFS
fIN = 105MHz
3
±0.7
62.0
FN6805.0
December 5, 2008
KAD5512P-50
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 500MSPS. (Continued)
KAD5512P-50
PARAMETER
SYMBOL
Signal-to-Noise and Distortion (Note 2)
SINAD
CONDITIONS
ENOB
SFDR
IMD
UNITS
dBFS
fIN = 70MHz
63.1
dBFS
63.0
dBFS
fIN = 230MHz
62.8
dBFS
fIN = 400MHz
61.3
dBFS
fIN = 995MHz
51.9
dBFS
fIN = 10MHz
10.2
Bits
fIN = 70MHz
10.2
Bits
10.2
Bits
fIN = 230MHz
10.1
Bits
fIN = 400MHz
9.9
Bits
fIN = 995MHz
8.3
Bits
fIN = 10MHz
81
dBc
fIN = 70MHz
81
dBc
fIN = 105MHz
Intermodulation Distortion
MAX
63.1
fIN = 105MHz
Spurious-Free Dynamic Range (Note 2)
TYP
fIN = 10MHz
fIN = 105MHz
Effective Number of Bits (Note 2)
MIN
61.5
9.9
79
dBc
fIN = 230MHz
70
78
dBc
fIN = 400MHz
70
dBc
fIN = 995MHz
55
dBc
fIN = 70MHz
-90.5
dBc
fIN = 170MHz
-86.0
dBc
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
1.3
GHz
NOTES:
1. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital
output.
2. SFDR, SINAD and ENOB specifications apply after gain error and timing skew between ADC cores have been minimized through external
calibration.
3. The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 18 for more detail.
4
FN6805.0
December 5, 2008
KAD5512P-50
Digital Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT)
Input Current Low (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT)
Input Capacitance
0
1
10
µA
-25
-12
-5
µA
IIH
15
25
40
µA
IIL
-40
25
-15
µA
CDI
3
pF
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
620
950
mVP-P
965
980
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
Timing Diagrams
Sample N
Sample N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
Latency = L Cycles
t CPD
CLKOUTN
CLKOUTP
D[11:0]P
D[11:0]N
Latency = L Cycles
CLKOUTN
CLKOUTP
tDC
tPD
Data
N-L
Data
N-L+1
Data
N-L+2
Data
N-L+3
Data
N-L+4
FIGURE 1. LVDS TIMING DIAGRAM
5
Data
N
D[11:0]P
D[11:0]N
tD C
tPD
Data
N-L
Data
N-L+1
Dat a
N-L+ 2
Dat a
N-L+ 3
Dat a
N-L+ 4
Data
N
FIGURE 2. CMOS TIMING DIAGRAM
FN6805.0
December 5, 2008
KAD5512P-50
Switching Specifications
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
ADC OUTPUT
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
Output Clock to Data Propagation Delay,
LVDS Mode
Rising Edge
tDC
-260
-50
120
ps
Falling Edge
tDC
-160
10
230
ps
Output Clock to Data Propagation Delay,
CMOS Mode
Rising Edge
tDC
-220
-10
200
ps
Falling Edge
tDC
-310
-90
110
ps
Latency (Pipeline Delay)
Overvoltage Recovery
L
15
cycles
tOVR
1
cycles
SPI INTERFACE (Notes 4, 5)
SCLK Period
Write Operation
t
CLK
64
ns
Read Operation
tCLK
264
ns
SCLK Duty Cycle (tHI/tCLK or tLO/tCLK)
Read or Write
SCLK↑ to CSB↓ Setup Time
Read or Write
tS
-4
ns
SCLK↑ to CSB↑ Hold Time
Read or Write
tH
-12
ns
SCLK↑ to Data Setup Time
Read or Write
tDS
-4
ns
SCLK↑ to Data Hold Time
Read or Write
tDH
-12
ns
25
50
75
%
NOTES:
4. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be
scaled proportionally for lower sample rates.
5. The SPI may operate asynchronously with respect to the ADC sample clock.
Thermal Impedance
PARAMETER
SYMBOL
TYP
UNIT
θJA
27
°C/W
Junction to Ambient (Note 6)
NOTE:
6. Paddle soldered to ground plane.
ESD
Electrostatic charge accumulates on humans, tools and
equipment and may discharge through any metallic package
contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been
utilized in the design of this product. However, reasonable
care must be taken in the storage and handling of ESD
sensitive products. Contact Intersil for the specific ESD
sensitivity rating of this product.
6
FN6805.0
December 5, 2008
KAD5512P-50
Pinout/Package Information
Pin Descriptions
PIN #
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
1, 6, 12, 19, 24, 71
AVDD
1.8V Analog Supply
2-5, 13, 14, 17, 18, 28-31
DNC
Do Not Connect
7, 8, 11, 72
AVSS
Analog Ground
9, 10
VINN, VINP
15
VCM
16
CLKDIV
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
Output Mode (LVDS, LVCMOS)
23
NAPSLP
Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
32, 33
D0N, D0P [NC, D0]
LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0]
34, 35
D1N, D1P [NC, D1]
LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1]
37, 38
D2N, D2P [NC, D2]
LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2]
39, 40
D3N, D3P [NC, D3]
LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3]
41, 42
D4N, D4P [NC, D4]
LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4]
43, 44
D5N, D5P [NC, D5]
LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5]
46
RLVDS
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
47, 48
CLKOUTN, CLKOUTP
[NC, CLKOUT]
LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT]
49, 50
D6N, D6P [NC, D6]
LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6]
51, 52
D7N, D7P [NC, D7]
LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7]
53, 54
D8N, D8P [NC, D8]
LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8]
57, 58
D9N, D9P [NC, D9]
LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9]
59, 60
D10N, D10P [NC, D10]
LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10]
61, 62
D11N, D11P [NC, D11]
LVDS Bit 11 (MSB) Output Complement, True [NC, LVCMOS Bit 11]
63, 64
ORN, ORP [NC, OR]
LVDS Over Range Complement, True [NC, LVCMOS Over Range]
66
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
Exposed Paddle
AVSS
Analog Input Negative, Positive
Common Mode Output
Clock Divider Control
Output Data Format (Two’s Comp., Gray Code, Offset Binary)
Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
7
FN6805.0
December 5, 2008
KAD5512P-50
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVSS
AVDD
OUTFMT
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D11P
D11N
D10P
D10N
D9P
D9N
OVDD
OVSS
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
KAD5512-50
72 QFN
Top View
Not to Scale
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
D8P
D8N
D7P
D7N
D6P
D6N
CLKOUTP
CLKOUTN
RLVDS
OVSS
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
AVDD
CLKP
CLKN
OUTMODE
NAPSLP
AVDD
RESETN
OVSS
OVDD
DNC
DNC
DNC
DNC
D0N
D0P
D1N
D1P
OVDD
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
DNC
DNC
DNC
DNC
AVDD
AVSS
AVSS
VINN
VINP
AVSS
AVDD
DNC
DNC
VCM
CLKDIV
DNC
DNC
FIGURE 3. PIN CONFIGURATION
8
FN6805.0
December 5, 2008
KAD5512P-50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise
noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS.
-50
HD2 & HD3 MAGNITUDE (dBc)
SNR (dBFS) & SFDR (dBc)
90
85
SFDR
80
75
70
65
SNR
60
55
-55
-60
HD3
-65
-70
-75
-80
HD2
-85
-90
-95
50
0
200
400
600
800
0
1000
200
400
-20
SFDRFS (dBFS)
90
HD2 & HD3 MAGNITUDE
SNR & SFDR
80
70
SNRFS (dBFS)
50
SFDR (dBc)
40
30
SNR (dBc)
20
-40
-50
-60
-80
-90
-110
-120
-50
-40
-30
-20
-10
HD2 (dBFS)
-100
0
-60
HD3 (dBc)
-70
10
-70
0
HD3 (dBFS)
-70
-60
INPUT AMPLITUDE (dBFS)
-40
-30
-20
-10
0
FIGURE 7. HD2 AND HD3 vs AIN
-60
HD2 and HD3 MAGNITUDE (dBc)
95
SNR (dBFS) & SFDR (dBc)
-50
INPUT AMPLITUDE (dBFS)
FIGURE 6. SNR AND SFDR vs AIN
90
85
SFDR
80
75
70
SNR
65
60
300
1000
HD2 (dBc)
-30
60
800
FIGURE 5. HD2 AND HD3 vs fIN
FIGURE 4. SNR AND SFDR vs fIN
100
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
325
350
375
400
425
450
SAMPLE RATE (MSPS)
FIGURE 8. SNR AND SFDR vs fSAMPLE
9
475
500
-70
HD3
-80
-90
HD2
-100
-110
-120
300
325
350
375
400
425
450
475
500
SAMPLE RATE (MSPS)
FIGURE 9. HD2 AND HD3 vs fSAMPLE
FN6805.0
December 5, 2008
KAD5512P-50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise
noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS.
(Continued)
1 .5
450
1
350
300
0 .5
D N L (L SBs)
TOTAL POWER (mW)
400
250
200
150
0
-0 .5
100
-1
50
0
80
140
200
260
320
380
440
-1 .5
500
0
51 2
1 02 4
1 5 36
SAMPLE RATE (MSPS)
90
1 .5
85
SNR (dBFS) & SFDR (dBc)
2
IN L (LS Bs)
1
0 .5
0
-0 .5
-1
35 8 4
4 09 6
SFDR
80
75
70
SNR
65
60
55
-1 .5
0
51 2
1 02 4
1 5 36
20 48 2 56 0
CO DE
3 0 72
35 8 4
50
300
4 09 6
400
500
600
700
800
INPUT COMMON MODE (mV)
FIGURE 12. INTEGRAL NONLINEARITY
FIGURE 13. SNR AND SFDR vs VCM
5 0 00 0
0
4 5 00 0
A in = -1.0 dBFS
S NR = 64. 8 d BFS
S FDR = 80. 5 dBc
S INA D = 6 4.7 dB FS
-20
A M PLITU D E (d BF S )
4 0 00 0
N UM BER O F H IT S
3 0 72
FIGURE 11. DIFFERENTIAL NONLINEARITY
FIGURE 10. POWER vs fSAMPLE IN 3mA LVDS MODE
-2
20 48 2 56 0
CO DE
3 5 00 0
3 0 00 0
2 5 00 0
2 0 00 0
1 5 00 0
1 0 00 0
-40
-60
-80
-1 00
5 00 0
0
20 48 20 4 9 20 5 0 2 05 1 2 05 2 20 5 3 2 05 4 2 05 5 2 05 6 2 05 7
C OD E
FIGURE 14. NOISE HISTOGRAM
10
-1 20
0
50
100
1 50
FR EQ U EN CY ( M Hz)
2 00
2 50
FIGURE 15. SINGLE-TONE SPECTRUM @ 105MHz
FN6805.0
December 5, 2008
KAD5512P-50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise
noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS.
(Continued)
0
0
Ain = -1. 0 dBFS
SNR = 6 4. 6 d B FS
SFDR = 81. 3 d B c
SINAD = 64.5 dBFS
-40
-60
-80
-40
-60
-80
-1 00
-1 00
-1 20
0
50
100
1 50
FR EQ U EN CY ( M Hz)
2 00
-1 20
2 50
0
50
100
1 50
FR EQ U EN CY ( M Hz)
2 00
2 50
0
A in = -1.0 dBFS
S NR = 61. 8 d BFS
S FDR = 51. 7 dBc
S INA D = 5 1.7 dB FS
-40
IM D = -90. 7dB FS
-20
A M PLITU D E (d BF S )
-20
-60
-80
-1 00
-40
-60
-80
-1 00
0
50
100
1 50
FR EQ U EN CY ( M Hz)
2 00
FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz
2 50
-1 20
0
50
100
1 50
FR EQ U EN CY ( M Hz)
2 00
2 50
FIGURE 19. SINGLE-TONE SPECTRUM @ 70MHz
0
IMD = -8 3. 5dBFS
-20
A M PLITU D E (d BF S )
A M PLITU D E (d BF S )
0
FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz
FIGURE 16. SINGLE-TONE SPECTRUM @ 190MHz
-1 20
A in = -1.0 dBFS
S NR = 63. 9 d BFS
S FDR = 73. 9 dBc
S INA D = 6 3.5 dB FS
-20
A M PLIT U D E (d BF S )
A M PLIT U D E (d BF S )
-20
-40
-60
-80
-1 00
-1 20
0
50
100
1 50
F R EQ U EN CY ( M Hz)
2 00
2 50
FIGURE 20. TWO-TONE SPECTRUM @ 170MHz
11
FN6805.0
December 5, 2008
KAD5512P-50
Theory of Operation
Functional Description
The KAD5512P-50 is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 21). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted to
a unit of charge. Proprietary charge-domain techniques are
used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each
input value. The converter pipeline requires twelve samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of fifteen clock cycles. This is
evident to the user as a latency between the start of a
conversion and the data being available on the digital outputs.
The device contains two units A/D converters with carefully
matched transfer characteristics. The cores are clocked on
alternate clock edges, resulting in a doubling of the sample
rate. The gain, offset and skew errors between the two unit
ADCs can be adjusted via the SPI port to minimize spurs
associated with the interleaving process.
Time–interleaved ADC systems can exhibit non–ideal
artifacts in the frequency domain if the individual unit ADC
characteristics are not well matched. Gain, offset and timing
skew mismatches are of primary concern.
Main mismatch results in fundamental image spurs at
fNYQUIST ± fIN. Mismatches in timing skew, which shift the
sampling instances for the two unit ADCs, will result in spurs
in the same locations. Offset mismatches create spurs at DC
and multiples of fNYQUIST.
The design of the KAD5512P-50 minimizes the effect of
process, voltage and temperature variations on the matching
characteristics of the two unit ADCs. The gain and offset of
the two unit ADCs are adjusted after power-on calibration to
minimize the mismatch between the channels. All calibration
is performed using internally generated signals, with the
analog input signal disconnected from the sample and hold
amplifier (SHA).
The KAD5512P-50 does not have the ability to adjust timing
skew mismatches as part of the internal calibration sequence.
Clock routing to each unit ADC is carefully matched, however
some timing skew will exist that may result in a detectable
fundamental image spur at fNYQUIST ± fIN.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration
at start-up. An internal power-on-reset (POR) circuit detects
the supply voltage ramps and initiates the calibration when
the analog and digital supply voltages are above a threshold.
The following conditions must be adhered to for the
power-on calibration to execute successfully:
• A frequency-stable conversion clock must be applied to
the CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled up or
down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at power-up.
Clock
Generation
INP
SHA
INN
1.25V
+
–
2.5-bit
Flash
6-Stage
1.5-bit/stage
3-Stage
1-bit/stage
3-bit
Flash
Digital
Error
Correction
LVDS/LVCMOS
Outputs
FIGURE 21. ADC CORE BLOCK DIAGRAM
12
FN6805.0
December 5, 2008
KAD5512P-50
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.5dBFS and SFDR
change of less than 3dBc.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should be
connected to an open-drain driver with a drive strength of
less than 0.5mA.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less than
80MSPS will typically result in an SNR change of less than
0.5dBFS and an SFDR change of less than 3dBc.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 500MSPS
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
Figures 25 and 26 show the effect of temperature on SNR
and SFDR performance without recalibration. In each plot
the ADC is calibrated at +25°C and temperature is varied
over the operating range without recalibrating. The average
change in SNR/SFDR is shown, relative to the +25°C value.
4
3
SNR CHANGE (dBFS)
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 22. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output returns
to normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range
condition the OR pin will stay high, and it will not be possible
to detect the end of the calibration cycle.
2
1
0
-1
-2
-3
-4
-40
CLKN
CLKP
-15
10
35
60
85
TEMPERATURE (°C)
Calibration Time
FIGURE 23. SNR PERFORMANCE vs TEMPERATURE AFTER
+25°C CALIBRATION
RESETN
Calibration Begins
15
Calibration Complete
CLKOUTP
FIGURE 22. CALIBRATION TIMING
User Initiated Reset
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength of less than
0.5mA is recommended. As is the case during power-on
reset, the SDO, RESETN and DNC pins must be in the
proper state for the calibration to successfully execute.
The performance of the KAD5512P-50 changes with
variations in temperature, supply voltage or sample rate. The
extent of these changes may necessitate recalibration,
depending on system performance requirements. Best
performance will be achieved by recalibrating the ADC under
the environmental conditions at which it will operate.
13
SFDR CHANGE (dBc)
ORP
10
5
0
-5
-10
-15
-40
-15
10
35
60
85
TEMPERATURE (° C)
FIGURE 24. SFDR PERFORMANCE vs TEMPERATURE AFTER
+25°C CALIBRATION
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 1.45V, centered at the VCM voltage
of 0.535V as shown in Figure 25.
FN6805.0
December 5, 2008
KAD5512P-50
Ω
348O
1.8
Ω
69.8O
1.4
1.0
Ω
25O
Ω
100O
INN
INP
0.725V
Ω
217O
VCM
0.6
Ω
49.9O
Ω
25O
Ω
69.8O
0.2
Ω
348O
0.1µF
FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT
FIGURE 25. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 26 through 28. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 26 and 27.
ADT1-1WT
1000pF
VCM
Ω
100O
0.22µF
0.535V
ADT1-1WT
KAD5512P
CM
KAD5512P
VCM
0.1µF
A differential amplifier, as shown in Figure 28, can be used in
applications that require DC-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 42).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 29. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
1kO
Ω
FIGURE 26. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
1kO
Ω
AVDD
200pF
TC4-1W
ADTL1-12
ADTL1-12
1000pF
200pF
0.1µF
1000pF
KAD5512P
1000pF
CLKP
200O
Ω
VCM
CLKN
200pF
FIGURE 27. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5512P-50 is 500Ω.
The SHA design uses a switched capacitor input stage (see
Figure 41), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes
a disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
14
FIGURE 29. RECOMMENDED CLOCK DRIVE
A selectable 2X frequency divider is provided in series with
the clock input. The divider can be used in the 2X mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
Not Allowed
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 18.
FN6805.0
December 5, 2008
KAD5512P-50
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and
is illustrated in Figure 30.
1
SNR = 20 log 10 ⎛ --------------------⎞
⎝ 2πf t ⎠
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
(EQ. 1)
IN J
10 0
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 18.
95
tj=0.1p s
90
1 4 Bits
SNR - dB
85
80
tj=1 ps
1 2 Bits
75
An external resistor creates the bias for the LVDS drivers. A
10kΩ, 1% resistor must be connected from the RLVDS pin to
OVSS.
70
tj=1 0p s
65
60
10 Bits
tj=1 00p s
Over Range Indicator
55
50
1
10
100
10 00
Input Frequency - MHz
FIGURE 30. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The nominal value of the voltage
reference is 1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figures 1 and 2 show the
timing relationships for LVDS and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
15
The over range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary
mode). The output code does not wrap around during an
over-range condition. The OR bit is updated at the sample
rate.
Power Dissipation
The power dissipated by the KAD5512P-50 is primarily
dependent on the sample rate and the output modes: LVDS
vs. CMOS and DDR vs. SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the ADC is not required. Two
power saving modes are available: Nap, and Sleep. Nap
mode reduces power dissipation to less than 134mW and
recovers to normal operation in approximately 1µs. Sleep
mode reduces power dissipation to less than 14mW but
requires 1ms to recover.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input clock
should remain running and at a fixed frequency during Nap
or Sleep. Recovery time from Nap mode will increase if the
clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
FN6805.0
December 5, 2008
KAD5512P-50
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
Gray Code
11
10
9
••••
1
0
TABLE 3. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
••••
The power-down mode can also be controlled through the
SPI port, which overrides the NAPSLP pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 18. This is an indexed function when controlled from
the SPI, but a global function when driven from the pin.
••••
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format is
selected via the OUTFMT pin as shown in Table 4.
Binary
11
10
9
••••
1
0
FIGURE 32. GRAY CODE TO BINARY CONVERSION
TABLE 4. OUTFMT PIN SETTINGS
Mapping of the input voltage to the various data formats is
shown in Table 5.
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
TWO’S
VOLTAGE OFFSET BINARY COMPLEMENT
The data format can also be controlled through the SPI port,
which overrides the OUTFMT pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 18.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF
(all ones). Two’s complement coding simply complements
the MSB of the offset binary representation.
GRAY CODE
–Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00
–Full Scale 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01
+ 1LSB
Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00
+Full Scale
– 1LSB
111 11 111 11 10
011 11 111 11 10 100 00 000 00 01
+Full Scale
111 11 111 11 11
011 11 111 111 1 100 00 000 00 00
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 31 shows
this operation.
Binary
11
10
9
••••
1
0
••••
Gray Code
11
10
9
••••
1
0
FIGURE 31. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 32.
16
FN6805.0
December 5, 2008
KAD5512P-50
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D2
D3
D4
D5
D6
D7
FIGURE 33. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
FIGURE 34. LSB-FIRST ADDRESSING
tS
tH
t CLK
tDS
t HI
t DH
CSB
t LO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
FIGURE 35. INSTRUCTION/ADDRESS PHASE
CSB Stalling
CSB
SCLK
SDIO
Instruction/Address
Data Word 1
Data Word 2
FIGURE 36. 2-BYTE TRANSFER
Last Legal
CSB Stalling
CSB
SCLK
SDIO
Instruction/Address
Data Word 1
Data Word N
FIGURE 37. N-BYTE TRANSFER
17
FN6805.0
December 5, 2008
KAD5512P-50
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK)
serial data input (SDI), and serial data input/output (SDIO).
The maximum SCLK rate is equal to the ADC sample rate
(fSAMPLE) divided by 32 for write operations and fSAMPLE
divided by 132 for reads. At fSAMPLE = 250MHz, maximum
SCLK is 15.63MHz for writing and 3.79MHz for write
operations. There is no minimum SCLK rate.
The following sections describe various registers that are
used to configure the SPI or adjust performance or
functional parameters. Many registers in the available
address space (0x00 to 0xFF) are not defined in this
document. Additionally, within a defined register there may
be certain bits or bit combinations that are reserved.
Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting
any reserved register or value may produce indeterminate
results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the
data transfer. By default, all data is presented on the serial
data input/output (SDIO) pin in three-wire mode. The state of
the SDIO pin is set automatically in the communication
protocol (described below). A dedicated serial data output
pin (SDO) can be activated by setting 0x00[7] high to allow
operation in four-wire mode.
or written (see Table 6). The lower 13 bits contain the first
address for the data transfer. This relationship is illustrated in
Figure 35, and timing values are given in “Switching
Specifications” on page 6.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from
the ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active.
Stalling of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or
more, CSB is allowed stall in the middle of the
instruction/address bytes or before the first data byte. If CSB
transitions to a high state after that point the state machine
will reset and terminate the data transfer.
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
Figures 36 and 37 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
The SPI port operates in a half duplex master/slave
configuration, with the KAD5512P-50 functioning as a slave.
Multiple slave devices can interface to a single master in
four-wire mode only, since the SDIO output of an
unaddressed device is asserted in three wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in four-wire mode). If
multiple slave devices are selected for reading at the same
time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command.
Data can be presented in MSB-first order or LSB-first order.
The default is MSB-first, but this can be changed by setting
0x00[6] high. Figures 33 and 34 show the appropriate bit
ordering for the MSB-first and LSB-first modes, respectively.
In MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits,
W1 and W0, determine the number of data bytes to be read
18
Bit ordering and SPI reset are controlled by this register. Bit
order can be selected as MSB to LSB (MSB first) or LSB to
MSB (LSB first) to accommodate various microcontrollers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial
data as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default
values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode
can improve throughput by eliminating redundant
addressing. In 3-wire SPI mode the burst is ended by pulling
the CSB pin high. If the device is operated in 2-wire mode
the CSB pin is not available. In that case, setting the
burst_end address determines the end of the transfer.
FN6805.0
December 5, 2008
KAD5512P-50
During a write operation, the user must be cautious to
transmit the correct number of bytes based on the starting
and ending addresses.
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Bits 7:0 Burst End Address
This register value determines the ending address of the
burst data.
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Gain of the ADC core can be adjusted in coarse, medium
and fine steps. Coarse gain is a 4-bit adjustment while
medium and fine are 8-bit.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
TABLE 8. COARSE GAIN ADJUSTMENT
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
Bits 1:0 ADC01, ADC00
Determines which ADC is addressed. Valid states for this
register are 0x01 or 0x10. The two ADC cores cannot be
adjusted concurrently.
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil ADC products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed on a
per-converter basis. This register determines which
converter is being addressed for an Indexed command. It is
important to note that only a single converter can be
addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Error code ‘AD’ is returned if any indexed
register is read from without properly setting
device_index_A.
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
1100
4.2
1000
2.8
0100
1.4
0000
0.0
0001
-1.4
0010
-2.8
0011
-4.2
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
ADDRESS 0X20: OFFSET_COARSE
+Full Scale (0xFF)
+2%
+0.2%
ADDRESS 0X21: OFFSET_FINE
Nominal Step Size
0.016%
0.0016%
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word
as detailed in Table 7. The data format is twos complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
TABLE 7. OFFSET ADJUSTMENTS
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to“Nap/Sleep” on
page 15). This functionality can be overridden and controlled
through the SPI. This is an indexed function when controlled
from the SPI, but a global function when driven from the pin.
This register is not changed by a Soft Reset.
TABLE 10. POWER DOWN CONTROL
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
VALUE
Steps
255
255
000
Pin Control
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
001
Normal Operation
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
010
Nap Mode
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
100
Sleep Mode
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
19
0x25[2:0]
POWER DOWN MODE
FN6805.0
December 5, 2008
KAD5512P-50
Global Device Configuration/Control
CLK = CLKP – CLKN
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 80h.
CLK
1.00 ns
CLK÷2
2.00 ns
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x08)
-6.5ps
Mid–Scale (0x00)
0.0ps
+Full Scale (0x07)
+6.5ps
Nominal Step Size
51fs
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine
the synchronization of the incoming and divided clock
phases. This is particularly important when multiple ADCs
are used in a time-interleaved system. The phase slip
feature allows the rising edge of the divided clock to be
advanced by one input clock cycle, as shown in Figures 38
and 39. This register is self-clearing.
CLK = CLKP – CLKN
CLK
2.00 ns
ADC0 Clock
ADC1 Clock
4.00 ns
ADC0 Clock
Slip Once
ADC1 Clock
Slip Once
ADC0 Clock
Slip Twice
ADC1 Clock
Slip Twice
FIGURE 39. PHASE SLIP: CLK÷2 MODE, fCLOCK = 1000MHz
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512P-50 has a selectable clock divider that can be
set to divide by two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 14). This functionality can be overridden and
controlled through the SPI, as shown in Table 12. This
register is not changed by a Soft Reset.
ADC0 Clock
TABLE 12. CLOCK DIVIDER SELECTION
ADC1 Clock
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Not Allowed
4.00 ns
ADC0 Clock
Slip Once
ADC1 Clock
Slip Once
ADC0 Clock
Slip Twice
ADDRESS 0X73: OUTPUT_MODE_A
ADC1 Clock
Slip Twice
FIGURE 38. PHASE SLIP: CLK÷1 MODE, fCLOCK = 500MHz
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512P-50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive strength
in LVDS mode can be set high (3mA) or low (2mA). By
default, the tri-level OUTMODE pin selects the mode and
drive level (refer to “Digital Outputs” on page 15). This
functionality can be overridden and controlled through the
SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
20
FN6805.0
December 5, 2008
KAD5512P-50
Format” on page 16). This functionality can be overridden
and controlled through the SPI, as shown in Table 14.
This register is not changed by a Soft Reset.
config_status and XOR them. Then XOR this result with the
desired value for output_mode_B and write that XOR result
to the register.
Device Test
TABLE 13. OUTPUT MODE CONTROL
VALUE
OUTPUT MODE
0x93[7:5]
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
The KAD5512 can produce preset or user defined patterns
on the digital outputs to facilitate in-situ testing. A static word
can be placed on the output bus, or two different words can
alternate. In the alternate mode, the values defined as Word
1 and Word 2 (as shown in Table 16) are set on the output
bus on alternating clock phases. The test mode is enabled
asynchronously to the sample clock, therefore several
sample clock cycles may elapse before the data is present
on the output bus.
ADDRESS 0XC0: TEST_IO
TABLE 14. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to Table 17.
TABLE 16. OUTPUT TEST MODES
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or
slow.
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 15 shows
the allowable sample rate ranges for the slow and fast
settings.
TABLE 15. DLL RANGES
VALUE
0xC0[3:0]
OUTPUT TEST
MODE
0000
Off
0001
WORD 1
WORD 2
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
DLL RANGE
MIN
MAX
UNIT
0111
One/Zero
0xFFFF
0x0000
Slow
80
200
MSPS
1000
User Pattern
user_patt1
user_patt2
Fast
160
500
MSPS
ADDRESS 0XC2: USER_PATT1_LSB
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency
range of the DLL clock generator. The method of setting
these options is different from the other registers.
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB
Read
output_mode_B
0x74
ADDRESS 0XC5: USER_PATT2_MSB
Read
config_status
0x75
Write to
0x74
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
Desired Value
FIGURE 40. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in
Figure 45. Read the contents of output_mode_B and
21
FN6805.0
December 5, 2008
KAD5512P-50
SPI Memory Map
Device Test
Global Device Config/Control
Indexed Device Config /Control
Info SPI Config
TABLE 17. SPI MEMORY MAP
Addr
(Hex)
Parameter Name
Bit 7 (MSB)
00
01
02
03-07
08
09
10
11-1F
20
21
22
23
24
25
port_config
reserved
burst_end
reserved
chip_id
chip_version
device_index_A
reserved
offset_coarse
offset_fine
gain_coarse
gain_medium
gain_fine
modes
SDO Active
26-5F
60-6F
reserved
reserved
70
71
skew_diff
phase_slip
72
clock_divide
73
output_mode_A
74
output_mode_B
75
76-BF
C0
config_status
reserved
test _io
C1
C2
C3
C4
C5
C6-FF
Reserved
user_patt 1_lsb
user_patt 1_msb
user_patt 2_lsb
user_patt 2_msb
reserved
Bit 6
Bit 5
LSB First
Bit 4
Bit 3
Soft Reset
Bit 2
Bit 1
Mirror (bit5) Mirror (bit6)
Bit 0 (LSB)
Mirror (bit7)
Reserved
Burst end address [7:0]
Reserved
Chip ID #
Chip Version #
Reserved
Reserved
ADC01
Reserved
Coarse Offset
Fine Offset
Medium Gain
Fine Gain
ADC00
Def. Value Indexed/
(Hex) Global
00h
G
00h
G
Read only
Read only
00h
G
G
I
cal. value
cal. value
cal. value
cal. value
cal. value
00h
NOT
affected by
Soft Reset
Coarse Gain
Power Down Mode [2:0]
000=Pin Control
001=Normal Operation
010=Nap
100=Sleep
other codes=reserved
I
I
I
I
I
I
Reserved
Reserved
Different ial Skew
Reserved
Next Clock
Edge
Clock Divide [2:0]
000=Pin Control
001=divide by 1
010=divide by 2
100=divide by 4
other codes=reserved
Output Format [2:0]
000=Pin Control
001=Twos Complement
010=Gray Code
100=Offset Binary
other codes=reserved
Output Mode [2:0]
000=Pin Control
001=LVDS 2mA
010=LVDS 3mA
100=LVCMOS
other codes=reserved
DLL Range
0=fast
1=slow
XOR Result
80h
00h
G
G
00h
NOT
affected by
Soft Reset
G
00h
NOT
affected by
Soft Reset
G
00h
NOT
affected by
Soft Reset
G
Read Only
G
00h
G
00h
00h
00h
00h
00h
G
G
G
G
G
Reserved
User Test M ode [2:0]
00=Single
01=Alt ernate
10=Single Once
11=Alt ernate Once
Reset PN
Long Gen
Reset PN
Short Gen
B7
B15
B7
B15
B5
B 13
B5
B 13
B4
B12
B4
B12
22
B6
B14
B6
B14
Output Test Mode [3:0]
0=Off
1=Midscale Short
2=+FS Short
3=- FS Short
4=Checker Board
5=reserved
6=reserved
Reserved
B3
B11
B3
B11
Reserved
B2
B10
B2
B10
7=One/Zero Word Togg le
8=User Input
9-15=reserved
B1
B9
B1
B9
B0
B8
B0
B8
FN6805.0
December 5, 2008
KAD5512P-50
Equivalent Circuits
AVDD
To
Clock-Phase
Generation
AVDD
AVDD
Csamp
1.6pF
To
Charge
Pipeline
INP
AVDD
Ω
11kO
F3
Φ
F2
Φ
F
Φ1
Ω
500O
CLKP
18kO
Ω
Csamp
1.6pF
AVDD
To
Charge
Pipeline
INN
Φ
F2
Φ
F1
Ω
18kO
AVDD 11kO
Ω
F3
Φ
CLKN
FIGURE 41. ANALOG INPUTS
AVDD
FIGURE 42. CLOCK INPUTS
AVDD
AVDD
AVDD
AVDD
Ω
75kO
AVDD
Ω
75kO
To
Sense
Logic
Ω
280O
Input
Ω
75kO
280O
Ω
To
Logic
Input
75kO
Ω
FIGURE 43. TRI-LEVEL DIGITAL INPUTS
FIGURE 44. DIGITAL INPUTS
OVDD
2mA or
3mA
OVDD
DATA
DATA
D[11:0]P
OVDD
OVDD
D[11:0]N
OVDD
DATA
DATA
DATA
D[11:0]
2mA or
3mA
FIGURE 45. LVDS OUTPUTS
23
FIGURE 46. CMOS OUTPUTS
FN6805.0
December 5, 2008
KAD5512P-50
Equivalent Circuits
(Continued)
AVDD
VCM
0.535V
+
–
FIGURE 47. VCM_OUT OUTPUT
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex board
designs benefit from isolating the analog and digital
sections. Analog supply and ground planes should be laid
out under signal and clock inputs. Locate the digital planes
under outputs and logic pins. Grounds should be joined
under the chip.
floating if they are not used. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT, CLKDIV) accept a floating input as a
valid state, and therefore should be biased according to the
desired functionality.
Definitions
Clock Input Considerations
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Use matched transmission lines to the transformer inputs for
the analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Aperture Delay or Sampling Delay is the time required
after the rise of the clock input for the sampling switch to
open, at which time the signal is held for conversion.
Exposed Paddle
Aperture Jitter is the RMS variation in aperture delay for a
set of samples.
The exposed paddle must be electrically connected to
analog ground (AVSS) and should be connected to a large
copper plane using numerous vias for optimal thermal
performance.
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close to
device pins. Longer traces will increase inductance, resulting
in diminished dynamic performance and accuracy. Make
sure that connections to ground are direct and low
impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be operated do not require connection to
ensure optimal ADC performance. These inputs can be left
24
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In
dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages
that cause the lowest and highest code transitions to the fullscale voltage less 2 LSB. It is typically expressed in percent.
Integral Non-Linearity (INL) is the maximum deviation of
the ADC’s transfer function from a best fit line determined by
a least squares curve fit of that transfer function, measured
in units of LSBs.
Least Significant Bit (LSB) is the bit that has the smallest
value or weight in a digital word. Its value in terms of input
voltage is VFS/(2N-1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
Most Significant Bit (MSB) is the bit that has the largest
value or weight.
FN6805.0
December 5, 2008
KAD5512P-50
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output
pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the
observed magnitude of a spur in the ADC FFT, caused by an
AC signal superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of
the RMS signal amplitude to the RMS sum of all other
spectral components below one-half the sampling frequency,
excluding harmonics and DC.
SNR and SINAD are either given in units of dB when the
power of the fundamental is used as the reference, or dBFS
(dB to full scale) when the converter’s full-scale input power
is used as the reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the largest
spurious spectral component. The largest spurious spectral
component may or may not be a harmonic.
Revision History
DATE
REVISION
CHANGE
7/30/08
Rev 1
Initial Release of Production Datasheet
12/5/08
FN6805.0 Converted to intersil template. Assigned
file number FN6805. Rev 0 - first release
(as preliminary datasheet) with new file
number.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
25
FN6805.0
December 5, 2008
KAD5512P-50
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 11/08
10.00
A
4X 8.50
PIN 1
INDEX AREA
B
55
6
72
1
54
68X 0.50
Exp. DAP
6.00 Sq.
10.00
18
37
(4X)
PIN 1
INDEX AREA
6
0.15
36
19
72X 0.24
72X 0.40
TOP VIEW
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
C
0.10 C
0.08 C
SEATING PLANE
68X 0.50
SIDE VIEW
72X 0.24
9.80 Sq
6.00 Sq
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
72X 0.60
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
26
FN6805.0
December 5, 2008