AK4705AEQ

[AK4705A]
AK4705A
2ch 24bit DAC with AV SCART Switch
GENERAL DESCRIPTION
The AK4705A offers the ideal features for digital set-top-box systems. Using AKM's multi-bit architecture
for its modulator, the AK4705A delivers a wide dynamic range while preserving linearity for improved
THD+N performance. The AK4705A integrates a combination of SCF and CTF filters, removing the need
for high cost external filters and increasing performance for systems with excessive clock jitter. The
AK4705A also including the audio switches, volumes, video switches, video filters, etc. designed primarily
for digital set-top-box systems. The AK4705A is offered in a space saving 48-pin LQFP package.
FEATURES
DAC
† Sampling Rates Ranging from 32kHz to 50kHz
† 64dB High Attenuation 8x FIR Digital Filter
† 2nd Order Analog LPF
† On Chip Buffer with Single-Ended Output
† Digital De–Emphasis for 32k, 44.1k and 48kHz Sampling
† I/F Format: 24bit MSB Justified, I2S, 18/16bit LSB Justified
† Master Clock: 256fs, 384fs
† High Tolerance to Clock Jitter
Analog Switches for SCART
Audio Section
† THD+N: –86dB (@2Vrms)
† Dynamic Range: 96dB (@2Vrms)
† Stereo Analog Volume with Pop-noise Free Circuit
(+6dB to –60dB & Mute)
† Analog Inputs
Two Stereo Inputs (TV&VCR SCART)
One Stereo Input (Changeover to Internal DAC)
† Analog Outputs
Two Stereo Outputs (TV, VCR SCART)
One Mono Output (Modulator)
† Pop Noise Free Circuit for Power On/Off
Video Section
† Integrated LPF: –40dB@27MHz
† 75ohm Driver
† 6dB Gain for Outputs
† Adjustable Gain
† Four CVBS/Y Inputs (ENCx2, TV, VCR),
Three CVBS/Y Outputs (RF, TV, VCR)
† Three R/C Inputs (ENCx2, VCR),
Two R/C outputs (TV, VCR)
† Bi-Directional Control for VCR-Red/Chroma
† Two G and B Inputs (ENC, VCR),
One G and B Outputs (TV)
† Y/Pb/Pr Option (to 6MHz)
† VCR Input Monitor
Loop–Through Mode for Standby
Auto–Startup Mode for Power Saving
SCART Pin#16(Fast Blanking), Pin#8(Slow Blanking) Control
AK4702/04 Software Compatible
MS0698-E-00
2007/12
-1-
[AK4705A]
Power Supply
† 5V+/–5% and 12V+/–5%
† Low Power Dissipation / Low Power Standby Mode
Package
† Small 48pin LQFP
Full Compatible with AK4705
MS0698-E-00
2007/12
-2-
[AK4705A]
VD
VP
MONOOUT
VSS
+6 to -60dB
-6dB/0dB/
+2.44/+4dB
VOL
(2dB/step)
MCLK
LRCK
TVOUTL
DAC
BICK
TVOUTR
SDTI
Volume #0
Volume #1
MONO
TV1/0
VCRINL
VCRINR
TVINL
VCROUTL
VCROUTR
TVINR
VMONO
Bias (Mute)
SCK
SDA
VCR1/0
Register
DVCOM
Control
PVCOM
PDN
Audio Block(DAPD=“0”)
VD
VP
MONOOUT
VSS
+6 to -60dB
0dB/+6dB
VOL
(2dB/step)
(NC)
TVOUTL
DACL
DACR
TVOUTR
(NC)
Volume #2
Volume #1
MONO
TV1/0
VCRINL
VCRINR
TVINL
VCROUTL
VCROUTR
TVINR
VMONO
Bias (Mute)
SCK
SDA
VCR1/0
Register
DVCOM
Control
PVCOM
PDN
Audio Block(DAPD=“1”)
MS0698-E-00
2007/12
-3-
[AK4705A]
( Typical connection )
( Typical connection )
VVD1
VVD2
6dB
RFV
6dB
TVVOUT
RF Mod
VVSS
ENC CVBS/Y
ENCV
ENC Y
ENCY
VCR CVBS/Y
TV CVBS
VCRVIN
TVVIN
0, 1, 2, 3dB
ENC R/C/Pr
ENC C
VCR R/C/Pr
ENCRC
6dB
ENCC
TVRC
TV SCART
VCRRC
ENC G/CVBS
ENCG
VCR G
VCRG
ENC B/Pb
ENCB
VCR B/Pb
VCRB
6dB
TVG
6dB
TVB
Monitor
REFI
6dB
VCRVOUT
VCR SCART
6dB
VCRC
Video Block
( Typical connection )
( Typical connection )
VCR FB
VCRFB
2V
6dB
TVFB
0V
TV SCART
0/ 6/ 12V
TVSB
VCRSB
VCR SCART
0/ 6/ 12V
Monitor
INT
Video Blanking Block
MS0698-E-00
2007/12
-4-
[AK4705A]
■ Ordering Guide
-10 ∼ +70°C
48pin LQFP (0.5mm pitch)
Evaluation Board for AK4705A
AK4705AEQ
AKD4705A
PVCOM
DVCOM
VP
MONOOUT
TVOUTL
TVOUTR
VCROUTL
VCROUTR
TVINL
TVINR
VCRINL
VCRINR
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
VSS
37
24
TVSB
VD
38
23
VCRSB
MCLK
39
22
INT
BICK
40
21
VCRB
SDTI
41
20
VCRG
LRCK
42
19
VCRRC
SCL
43
18
VCRFB
SDA
44
17
VCRVIN
PDN
45
16
TVVIN
RFV
46
15
ENCY
VCRVOUT
47
14
ENCV
TVFB
48
13
ENCC
AK4705AEQ
9
10
11
12
ENCB
ENCG
ENCRC
6
TVG
REFI
5
TVRC
8
4
VVD2
VVD1
3
TVVOUT
7
2
VVSS
TVB
1
VCRC
Top View
MS0698-E-00
2007/12
-5-
[AK4705A]
■ Main difference between AK4702/4704 and AK4705/A
Items
Audio
Video
Pinout
Others
Audio bits
Digital filter attenuation level
+4dB gain at DAC volume#0 (total: +10dB max)
DAC power-down/analog input mode
Volume#1 output for VCROUTL/R switch matrix
MONO mixing for VCROUTL/R
MONO input
Video filter
150ohm video driver for modulator
Y/C mixer for modulator
VCR video input monitor
VCR Slow Blanking monitor in output mode.
TV/VCR CVBS input detection & Power Save Mode
Y/Pb/Pr option
RGB support in Auto Mode
MONOIN Pin (at AK4702 Pin #28)
ENCB Pin to TVINL Pin
I2C speed (max)
Mask bits for INT function (09H)
FB/SB loop back in auto mode.
MS0698-E-00
AK4702
18bit
54dB
X
enabled
MONOIN
Pin# 28
Pin #9 ~ #27
100kHz
-
AK4704
AK4705/A
24bit
24bit
64dB
64dB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
disabled
disabled
X
X
X
X
FILT
REFI
Pin #28
Pin #9
Pin #9 ~ #27 Pin #10 ~ #28
400kHz
400kHz
X
X
X
(-: NOT available. X: Available)
2007/12
-6-
[AK4705A]
PIN/FUNCTION
No.
1
2
3
4
Pin Name
VCRC
VVSS
TVVOUT
VVD2
I/O
O
O
-
5
6
7
8
TVRC
TVG
TVB
VVD1
O
O
O
-
9
REFI
O
10
11
12
13
14
15
16
17
18
19
20
21
22
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
INT
I
I
I
I
I
I
I
I
I
I
I
I
O
23
24
25
26
27
28
29
30
31
32
33
34
VCRSB
TVSB
VCRINR
VCRINL
TVINR
TVINL
VCROUTR
VCROUTL
TVOUTR
TVOUTL
MONOOUT
VP
35
DVCOM
O
36
PVCOM
O
I/O
O
I
I
I
I
O
O
O
O
O
-
Function
Chrominance Output Pin for VCR
Video Ground Pin. 0V.
Composite/Luminance Output Pin for TV
Video Power Supply Pin #2, 5V.
Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel with
a 10μF electrolytic cap.
Red/Chrominance/Pr Output Pin for TV
Green/Y Output Pin for TV
Blue/Pb Output Pin for TV
Video Power Supply Pin #1, 5V.
Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel with
a 10μF electrolytic cap.
Video Current Reference Setup Pin
Normally connected to VVD1 through a 10kΩ±1% resistor externally.
Blue/Pb Input Pin for Encoder
Green/Y Input Pin for Encoder
Red/Chrominance/Pr Input Pin for Encoder
Chrominance Input Pin for Encoder
Composite/Luminance Input1 Pin for Encoder
Composite/Luminance Input2 Pin for Encoder
Composite/Luminance Input Pin for TV
Composite/Luminance Input Pin for VCR
Fast Blanking Input Pin for VCR
Red/Chrominance/Pr Input Pin for VCR
Green Input Pin for VCR
Blue/Pb Input Pin for VCR
Interrupt Pin for Video Blanking.
Normally connected to VD(5V) through 10kΩ resistor externally.
Slow Blanking Input/Output Pin for VCR
Slow Blanking Output Pin for TV
Rch VCR Audio Input Pin
Lch VCR Audio Input Pin
Rch TV Audio Input Pin
Lch TV Audio Input Pin
Rch VCR Audio Output Pin
Lch VCR Audio Output Pin
Rch TV Audio Output Pin
Lch TV Audio Output Pin
MONO Analog Output Pin
Power Supply Pin. 12V.
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
10μF electrolytic cap.
DAC Common Voltage Pin
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
10μF electrolytic cap.
Audio Common Voltage Pin
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
10μF electrolytic cap. The caps affect the settling time of audio bias level.
MS0698-E-00
2007/12
-7-
[AK4705A]
PIN/FUNCTION (Continued)
37
38
VSS
VD
39
43
44
45
MCLK
(NC)
BICK
DACR
SDTI
(NC)
LRCK
DACL
SCL
SDA
PDN
46
47
48
RFV
VCRVOUT
TVFB
40
41
42
-
I
I
I
I
I
I
I
I/O
I
O
O
O
Ground Pin. 0V.
DAC Power Supply Pin. 5V.
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
10μF electrolytic cap.
Master Clock Input Pin at DAPD= “0”.
No Connect pin at DAPD= “1”. This pin should be open.
Audio Serial Data Clock Pin at DAPD= “0”.
Rch Analog Audio Input Pin at DAPD= “1”.
Audio Serial Data Input Pin at DAPD= “0”.
No Connect pin at DAPD= “1”. This pin should be open.
L/R Clock Pin at DAPD= “0”.
Lch Analog Audio Input Pin at DAPD= “1”.
Control Data Clock Pin
Control Data Pin
Power-Down Mode Pin
When at “L”, the AK4705A is in the power-down mode and is held in reset.
The AK4705A should always be reset upon power-up.
Composite Output Pin for RF modulator
Composite/Luminance Output Pin for VCR
Fast Blanking Output Pin for TV
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
VCRC, TVVOUT, TVRC, TVG, TVB, ENCB,
ENCG, ENCRC, ENCC, ENCV, ENCY, TVVIN,
VCRVIN, VCRRC, VCRG, VCRB, VCRINR,
VCRINL, TVINR, TVINL, VCROUTR, VCROUTL,
TVOUTR, TVOUTL, MONOOUT, DACR, DACL,
RFV, VCRVOUT
VCRSB (O), TVFB, TVSB
VCRFB, VCRSB (I), MCLK, BICK, SDTI, LRCK,
SCL, SDA, INT
MS0698-E-00
Setting
These pins should be open.
These pins should be open.
These pins should be connected to VSS.
2007/12
-8-
[AK4705A]
INTARNAL EQUIVALENT CIRCUITS
Pin No.
Pin Name
39
40
41
42
43
45
MCLK
BICK
SDTI
LRCK
SCL
PDN
Type
Digital IN
(DAPD= “0”)
Equivalent Circuit
VD
(60k)
Description
The 60kΩ is attached
only for BICK pin and
LRCK pin.
200
Analog IN
(DAPD= “1”)
VSS
VD
44
SDA
200
Digital I/O
I2C Bus voltage must
not exceed VD.
VSS
VP
22
INT
Normally connected to
VD(5V) through 10kΩ
resistor externally.
Digital OUT
VSS
46
47
48
1
3
5
6
7
RFV
VCROUT
TVFB
VCRC
TVVOUT
TVRC
TVG
TVB
VVD1
VVD2
Video OUT
VVSS
VVSS
VVD1
200
9
REFI
REFI IN
Normally connected to
VVD1 through a 10kΩ
±1% resistor.
VVSS
MS0698-E-00
2007/12
-9-
[AK4705A]
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
Pin Name
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
Type
Equivalent Circuit
VVD1
VCRSB
TVSB
The 60 kΩ is attached
for ENCC pin, ENCRC
(chroma mode) pin and
VCRRC (chroma
mode) pin.
200
Video IN
(60K)
VVSS
VP
23
24
Description
VP
200
The 120kΩ is not
attached for TVSB pin.
Video SB
(120k)
VSS
VSS
VSS
VP
25
26
27
28
VCRINR
VCRINL
TVINR
TVINL
150k
Audio IN
VSS
VP
29
30
31
32
33
VCROUTR
VCROUTL
TVOUTR
TVOUTL
MONOOU
T
VP
100
Audio OUT
VSS
VD
35
36
DVCOM
PVCOM
VSS
VD
VD
100
VCOM OUT
VSS VSS
MS0698-E-00
VSS
2007/12
- 10 -
[AK4705A]
ABSOLUTE MAXIMUM RATINGS
(VSS=VVSS=0V; Note: 1)
Parameter
Power Supply
(Note: 2)
Symbol
VD
VVD1
VVD2
VP
IIN
VIND
VINV
VINA
VINA
Ta
Tstg
Input Current (any pins except for supplies)
Input Voltage
Video Input Voltage
Audio Input Voltage (except DACL/R pins)
Audio Input Voltage (DACL/R pins)
Ambient Operating Temperature
Storage Temperature
Note: 1. All voltages with respect to ground.
Note: 2. VSS and VVSS must be connected to the same analog ground plane.
min
-0.3
-0.3
-0.3
-0.3-0.3
-0.3
-0.3
-0.3
-10
-65
max
6.0
6.0
6.0
14
±10
VD+0.3
VVD1+0.3
VP+0.3
VD+0.3
70
150
Units
V
V
V
V
mA
V
V
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=VVSS=0V; Note: 1)
Parameter
Power Supply (Note: 3)
Symbol
VD
VVD1/VVD2
VP
Note: 3. Analog output voltage scales with the voltage of VD.
AOUT (typ@0dB) = 2Vrms × VD/5.
The VVD1 and VVD2 must be the same voltage.
min
4.75
4.75
11.4
typ
5.0
5.0
12
max
5.25
5.25
12.6
Units
V
V
V
max
Units
126
12
mA
mA
mA
mA
100
100
100
μA
μA
μA
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTRICAL CHARACTERISTICS
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs)
Power Supplies
Parameter
min
typ
Power Supply Current
Normal Operation (PDN pin = “H”; Note: 4)
VD
14
VVD1+VVD2
46
VD+ VVD1+VVD2
VP
6
Power-Down Mode (PDN pin = “L”; Note: 5)
VD
10
VVD1+VVD2
10
VP
10
Note: 4. STBY bit = “L”, all video outputs are active.
No signal, no load for A/V switches. fs=48kHz “0”data input for DAC.
Note: 5. All digital inputs including clock pins (MCLK, BICK and LRCK) are held at VD or VSS.
MS0698-E-00
2007/12
- 11 -
[AK4705A]
DIGITAL CHARACTERISTICS
(Ta = 25°C; VD = 4.75 ∼ 5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Low-Level Output Voltage
(SDA pin: Iout= 3mA, INT pin: Iout= 1mA)
Input Leakage Current
Symbol
VIH
VIL
VOL
min
2.0
-
typ
-
max
0.8
0.4
Units
V
V
V
Iin
-
-
± 100
μA
ANALOG CHARACTERISTICS (AUDIO)
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input
Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥4.5kΩ; Volume #0=Volume #1=0dB, 0dB=2Vrms output; unless
otherwise specified)
Parameter
min
typ
max
Units
24
bit
DAC Resolution
Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins)
Analog Input Characteristics
Input Voltage
2
Vrms
Input Resistance
100
150
kΩ
Analog Input: (DACL/DACR pin)
Analog Input Characteristics
Input Voltage
1
Vrms
Input Resistance
40
60
kΩ
Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins; Note: 6)
Analog Output Characteristics
Volume#0 Gain (DAPD bit = “0”)
(DVOL1-0 = “00”)
0
dB
(DVOL1-0 = “01”)
-6
dB
(DVOL1-0 = “10”)
+2.44
dB
(DVOL1-0 = “11”. Note: 7)
+4
dB
Volume#2 Gain (DAPD bit = “1”)
(DVOL1-0 = “00”)
5.3
6
6.7
dB
(DVOL1-0 = “01”)
-0.7
0
0.7
dB
Volume#1 Step Width (+6dB to –12dB)
1.6
2
2.4
dB
(-12dB to –40dB)
0.5
2
3.5
dB
(-40dB to –60dB)
0.1
2
3.9
dB
-86
-80
dB
THD+N
(at 2Vrms output. Note: 8)
-60
dB
(at 3Vrms output. Note: 8, Note: 9)
Dynamic Range (-60dB Output, A-weighted. Note: 8)
92
96
dB
S/N
(A-weighted. Note: 8)
92
96
dB
Interchannel Isolation (Note: 8, Note: 10)
80
90
dB
Interchannel Gain Mismatch (Note: 8, Note: 10)
0.3
dB
Gain Drift
200
ppm/°C
Load Resistance (AC-Lord)
TVOUTL/R, VCROUTL/R, MONOOUT
4.5
kΩ
Load Capacitance
TVOUTL/R, VCROUTL/R, MONOOUT
20
pF
Output Voltage
(Note: 11)
1.85
2
2.15
Vrms
Power Supply Rejection (PSR. Note: 12)
50
dB
Note: 6. Measured by Audio Precision System Two Cascade.
Note: 7. Output clips over –2.5dBFS digital input.
Note: 8. DAC to TVOUT
Note: 9. Except VCROUTL/VCROUTL pins.
Note: 10. Between TVOUTL and TVOUTR with digital inputs 1kHz/0dBFS.
MS0698-E-00
2007/12
- 12 -
[AK4705A]
Note: 11. Full-scale output voltage by DAC (0dBFS). Output voltage of DAC scales with the voltage of VD,
Stereo output (typ@0dBFS) = 2Vrms × VD/5 when volume#0=volume#1=0dB. The output must not exceed 3Vrms.
Note: 12. The PSR is applied to VD with 1kHz, 100mV.
FILTER CHARACTERISTICS
(Ta = 25°C; VP=11.4∼12.6V, VD = 4.75∼5.25V, VVD1=VVD2 = 4.75∼5.25V; fs = 48kHz; DEM0 = “1”, DEM1 = “0”)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
21.77
kHz
Passband
±0.05dB
(Note: 13)
24.0
kHz
-6.0dB
Stopband
(Note: 13)
SB
26.23
kHz
Passband Ripple
PR
dB
± 0.01
Stopband Attenuation
SA
64
dB
Group Delay
(Note: 14)
GD
24
1/fs
Digital Filter + LPF
FR
dB
Frequency Response 0 ∼ 20.0kHz
± 0.5
Note: 13. The passband and stopband frequencies scale with fs.
e.g.) PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note: 14. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18/24bit data of
both channels to input register to the output of analog signal.
MS0698-E-00
2007/12
- 13 -
[AK4705A]
ANALOG CHARACTERISTICS (VIDEO)
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; VVOL1/0= “00” unless specified.)
Parameter
Conditions
min
Sync Tip Clamp Voltage
at output pin.
Chrominance Bias Voltage
at output pin.
Pb/Pr Clamp Voltage
at output pin.
Gain
Input=0.3Vp-p, 100kHz
5.5
RGB Gain
Input=0.3Vp-p,
VVOL1/0= “00”
5.5
100kHz
VVOL1/0= “01”
6.7
VVOL1/0= “10”
7.7
VVOL1/0= “11”
8.6
Interchannel Gain Mismatch TVRC, TVG, TVB. Input=0.3Vp-p, 100kHz.
-0.5
Frequency Response
Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz.
-1.0
at 10MHz.
at 27MHz.
Group Delay Distortion
At 4.43MHz with respect to 1MHz.
Input Impedance
Chrominance input (internally biased)
40
Input Signal
f=100kHz, maximum with distortion < 1.0%,
gain=6dB.
Load Resistance
(Figure 1)
150
Load Capacitance
C1 (Figure 1)
C2 (Figure 1)
Dynamic Output Signal
f=100kHz, maximum with distortion < 1.0%
Y/C Crosstalk
f=4.43MHz, 1Vp-p input. Among TVVOUT,
TVRC, VCRVOUT and VCRC outputs.
S/N
Reference Level = 0.7Vp-p, CCIR 567 weighting.
BW= 15kHz to 5MHz.
Differential Gain
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
Differential Phase
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
typ
0.7
2.2
2.2
6
6
7.2
8.2
9.1
-
-25
15
1.5
Units
V
V
V
dB
dB
dB
dB
dB
dB
dB
dB
dB
ns
kΩ
Vpp
-50
400
15
3
-
Ω
pF
pF
Vpp
dB
74
-
dB
+0.4
-
%
+0.8
-
Degree
-3
-40
60
-
max
6.5
6.5
7.7
8.7
9.6
0.5
0.5
R1
75 Ω
Video Signal Output
C1
C2
max: 15pF
R2
75 Ω
max: 400pF
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
MS0698-E-00
2007/12
- 14 -
[AK4705A]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=11.4 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V)
Parameter
Symbol
Min
typ
fCLK
8.192
Master Clock Frequency 256fs:
dCLK
40
Duty Cycle
fCLK
12.288
384fs:
dCLK
40
Duty Cycle
fs
32
LRCK Frequency
Duty
45
Duty Cycle
Audio Interface Timing
tBCK
312.5
BICK Period
tBCKL
100
BICK Pulse Width Low
tBCKH
100
Pulse Width High
tBLR
50
BICK “↑” to LRCK Edge
(Note: 15)
tLRB
50
LRCK Edge to BICK “↑”
(Note: 15)
tSDH
50
SDTI Hold Time
tSDS
50
SDTI Setup Time
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note: 16)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
Reset Timing
tPD
150
PDN Pulse Width
(Note: 17)
Note: 15. BICK rising edge must not occur at the same time as LRCK edge.
Note: 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 17. The AK4705A should be reset by PDN pin = “L” upon power up.
Note: 18. I2C is a registered trademark of Philips Semiconductors.
MS0698-E-00
max
12.8
60
19.2
60
50
55
Units
MHz
%
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
400
-
kHz
μs
μs
0.3
0.3
50
μs
μs
μs
μs
μs
μs
μs
μs
Ns
400
pF
ns
2007/12
- 15 -
[AK4705A]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Serial Interface Timing
MS0698-E-00
2007/12
- 16 -
[AK4705A]
tPD
PDN
VIL
Power-down Timing
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
I2C Bus mode Timing
MS0698-E-00
2007/12
- 17 -
[AK4705A]
OPERATION OVERVIEW
1. System Reset and Power-down options
The AK4705A should be reset once by bringing the PDN pin = “L” upon power-up. The AK4705A has several operation
modes. The PDN pin, AUTO bit, DAPD bit, MUTE bit and STBY bit control operation modes as shown in Table 1 and
Table 2.
0
PDN
pin
L
AUTO
bit
x
STBY
bit
x
MUTE
bit
x
DAPD
bit
x
1
H
1
x
x
x
2
3
H
H
0
0
1
1
1
0
x
x
4
H
0
0
1
1
5
H
0
0
1
0
6
H
0
0
0
1
7
H
0
0
0
0
Mode
Mode
Full Power-down
Auto Startup mode
(power-on default)
Standby & mute
Standby
Mute
(DAC power down)
Mute
(DAC operation)
Normal operation
(DAC power down
& Analog input)
Normal operation
(DAC operation)
(x: Don’t Care)
Table 1. Operation Mode Settings
Mode
Register
Control
0
Full Power-down
NOT
available
1
Auto Startup mode
(power-on default)
2
Standby & mute
3
Standby
Mute
(DAC power down)
Mute
(DAC operation)
Normal operation
(DAC power down
& Analog input)
Normal operation
(DAC operation)
4
5
6
7
No video
input
Video
input (3)
MCLK,
BICK,
LRCK
Not
needed
Audio Bias
Level
Video
Output
TVFB,
TVSB
VCRSB
Power
down
Hi-Z
Hi-Z
Pull-down
(2)
Active
Active
Available
Active
Power
down
Active
Power
down
Active
(4)
Hi-Z/
Active
Needed
Not
needed
Active
(1)
Needed
Notes:
(1) TVOUTL/R are muted by VMUTE bit in the default state.
(2) Internally pulled down by 120kohm(typ) resistor.
(3) Video input to TVVIN or VCRVIN.
(4) VCRC outputs 0V for termination.
Table 2. Status of each operation modes
MS0698-E-00
2007/12
- 18 -
[AK4705A]
■ Full Power-down Mode
The AK4705A should be reset once by bringing the PDN pin = “L” upon power-up.
PDN pin: Power down pin
“H”: Normal operation
“L”: Device power down.
■ Auto Startup Mode
After the PDN pin is set to “H”, the AK4705A is in the auto startup mode. In this mode, all blocks except for the video
detection circuit are powered down. Once the video detection circuit detects video signal from the TVVIN pin or
VCRVIN pin, the AK4705A goes to stand-by mode (Both Fast Blanking and Slow Blanking are also fixed to VCR-TV
Loop-through) automatically and sends “H” pulse via the INT pin. To exit auto startup mode, set the AUTO bit to “0”.
AUTO bit (00H D3): Auto startup bit
“1”: Auto startup enable (default).
“0”: Auto startup disable (Manual startup).
■ DAC Power-down Mode
The internal DAC block can be powered-down and switched to 1Vrms analog input mode. When DAPD bit =“1”, the
zero-cross detection and offset calibration does not work.
DAPD bit (00H D2): DAC power-down bit.
“1”: DAC power-down. Analog-input mode.
#39 pin: MCLK -> (NC)
#40 pin: BICK -> DACR. Rch analog input.
#41 pin: SDTI -> (NC)
#42 pin: LRCK -> DACL. Lch analog input.
“0”: DAC operation. (default)
■ Standby Mode
When the AUTO bit = MUTE bit = “0” and the STBY bit = “1”, the AK4705A is forced into TV-VCR loop through
mode. In this mode, the sources of TVOUTL/R and MONOOUT pins are fixed to VCRINL/R pins; the sources of
VCROUTL/R are fixed to TVINL/R pins respectively. The gain of volume#1 is fixed to 0dB. All register values
themselves are NOT changed by STBY bit = “1”.
STBY bit (00H D0): Standby bit.
“1”: Standby mode. (default)
“0”: Normal operation.
■ Mute Mode (Bias-off Mode. 00H: D1)
When the MUTE bit = “1”, the bias voltage on the audio output goes to GND level. Bringing MUTE bit to “0” changes
this bias voltage smoothly from GND to VP/2 by 2sec(typ.). This removes the huge click noise related the sudden change
of bias voltage at power-on. The change of MUTE bit from “1” to “0” also makes smooth transient from VP/2 to GND by
2sec(typ). This removes the huge click noise related the sudden change of bias voltage at power-off.
MUTE bit: Bias-off bit.
“1”: Set the audio bias to GND. (default)
“0”: Normal operation
MS0698-E-00
2007/12
- 19 -
[AK4705A]
■ Normal Operation Mode
To use the DAC or change analog switches, set the AUTO bit, DAPD bit, MUTE bit and STBY bit to “0”. The DAC is in
power-down mode until MCLK and LRCK are input. The AK4705A is in power-down mode until MCLK and LRCK are
input. Figure 2 shows an example of the system timing at the power-down and power-up by the PDN pin.
■ Typical Operation Sequence (of auto setup mode)
Figure 2 shows an example of the system timing at auto setup mode.
PDN pin
Low Power Mode
Low Power Mode
Clock, Data in
Low Power Mode
don’t care
TVVIN
don’t care
VCRVIN
don’t care
TVVOUT,
VCRVOUT
No Signal
No Signal
Signal in
No Signal
Hi-Z
Audio out (DC)
Signal in
(GND)
No Signal
Signal in
Active (loop-through)
Hi-Z
No Signal
Active (loop-through)
Active (loop-through)
don’t care
don’t care
Hi-Z
Active (loop-through)
Figure 2. Typical operating sequence (auto setup mode)
■ Typical Operation Sequence (of normal operation mode)
Figure 3 shows an example of the system timing at normal operation mode.
PDN pin
AUTO bit
MUTE bit
STBY bit
“Stand-by“
“Mute”
“1” (default)
“1” (default)
“Stand-by“
“0”
“0”
“1”
“1” (default)
“0”
Clock in
don’t care (2)
normal operation
Data in
don’t care
“0”
Audio data
GD
“1”
don’t care (2)
TV out
fixed to VCR in(Loop-through)
(1)
VCR in
don’t care
“0”
GD (1)
D/A Out
(internal)
TV-Source
select
“1”
“0”
DAC
VCR in
(default)
VCR in
VCR in
(3)
Figure 3. Typical operating sequence (except auto setup mode)
MS0698-E-00
2007/12
- 20 -
[AK4705A]
Notes:
(1) The analog output corresponding to the digital input has a group delay, GD.
(2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode.
(3) Mute the analog outputs externally if click noise(3) adversely affects the system.
2. Audio Block
■ System Clock
The external clocks required to operate the DAC section of the AK4705A are MCLK, LRCK and BICK. The master clock
(MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock
becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 3 illustrates
corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC section of the AK4705A is in the normal operating mode (STBY bit = “0” and DAPD bit = “0”). If these clocks are
not provided, the AK4705A may draw excess current because the device utilizes dynamically refreshed logic internally.
The DAC section of the AK4705A should be reset by STBY bit = “0” after threse clocks are provided. If the external
clocks are not present, place the AK4705A in power-down mode (STBY bit = “1”). After exiting reset at power-up etc.,
the AK4705A remains in power-down mode until MCLK and LRCK are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
256fs
384fs
8.1920MHz
12.2880MHz
11.2896MHz
16.9344MHz
12.2880MHz
18.4320MHz
Table 3. System clock example
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
■ Audio Serial Interface Format (00H: D5-D4)
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial
mode as shown in Table 4. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising
edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs.
Mode
0
1
2
DIF1
0
0
1
DIF0
0
1
0
3
1
1
SDTI Format
16bit LSB Justified
18bit LSB Justified
24bit MSB Justified
BICK
≥32fs
≥36fs
≥48fs
≥48fs or
24bit I2S Compatible
32fs
Table 4. Audio Data Formats
MS0698-E-00
Figure
Figure 4
Figure 4
Figure 5
Figure 6
(default)
2007/12
- 21 -
[AK4705A]
LRCK
BICK
SDTI
Mode 0
Don’t care
15 14
0
Don’t care
15
0
Don’t care
15 14
0
15
0
15:MSB, 0:LSB
SDTI
Mode 1
Don’t care
17
16
14
17
16
14
17:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 0/1 Timing
LRCK
BICK
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
17
16
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 2 Timing
LRCK
BICK
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
17
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 3 Timing
MS0698-E-00
2007/12
- 22 -
[AK4705A]
■ De-emphasis Filter (00H: D7-D6)
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is controlled by the
DEM0 and DEM1 bits.
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 5. De-emphasis Filter Control
(default)
■ Switch Control
The AK4705A has switch matrixes designed primarily for SCART routing. Those are controlled via the control register
as shown in Table 6, Table 7 and Table 8 (refer to the block diagram).
(01H: D1-D0)
TV1
TV0
Source of TVOUTL/R
0
0
DAC
(default)
0
1
VCRIN
1
0
Mute
1
1
(Reserved)
Table 6. TVOUT Switch Configuration
(01H: D2-D0)
VOL
TV1
TV0
Source of MONOOUT
0
0
0
DAC (L+R)/2
Bypass the
0
0
1
DAC (L+R)/2
volume #1
0
1
0
DAC (L+R)/2
0
1
1
(Reserved)
Through the
1
0
0
DAC (L+R)/2
volume #1
1
0
1
VCRIN (L+R)/2 (default)
1
1
0
Mute
1
1
1
(Reserved)
Table 7. MONOOUT Switch Configuration
(01H: D5-D4)
VCR1
VCR0
Source of VCROUTL/R
0
0
DAC
0
1
TVIN
1
0
Mute
1
1
Output of volume #1
Table 8. VCROUT Switch Configuration
MS0698-E-00
(default)
2007/12
- 23 -
[AK4705A]
■ Volume Control #0, #2 (4-Level Volume)
The AK4705A has a 4-level volume control (Volume #0, #2) as shown in Table 9 and Table 10. The volume reflects the
change of register value immediately.
(03H: D4-D3)
DVOL1
DVOL0
0
0
0
1
1
0
1
1
(03H: D4-D3)
DVOL1
DVOL0
0
0
0
1
1
0
1
1
Volume #0 Gain
0dB
-6dB
+2.44dB
Output Level (Typ)
2Vrms (with 0dBFS input & volume #1=0dB)
1Vrms (with 0dBFS input & volume #1=0dB.)
2.65Vrms (with 0dBFS input & volume #1=0dB.)
2Vrms (with –10dBFS input & volume #1=+6dB.
+4dB
Clips over –2.5dBFS digital input.)
Table 9. Volume #0 (at DAPD bit = “0”. DAC mode)
Volume #2 Gain
Output Level (Typ)
+6dB
2Vrms (with 1Vrms input & volume #1=0dB)
0dB
1Vrms (with 1Vrms input & volume #1=0dB.)
(reserved)
(reserved)
Table 10. Volume #2 (at DAPD bit = “1”. analog input mode.)
MS0698-E-00
(default)
(default)
2007/12
- 24 -
[AK4705A]
■ Volume Control #1 (Main Volume)
The AK4705A has main volume control (Volume #1) as shown in Table 11.
(02H: D5-D0)
L5
L4
L3
L2
L1
L0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
…
…
…
…
…
…
0
0
0
0
0
1
0
0
0
0
0
0
Note: The output must not exceed 3Vrms.
Table 11. Volume #1
Gain
+6dB
+4dB
+2dB
0dB
…
-60dB
Mute
(default)
When the MOD bit = “1”(default), there is no pop noise by changing levels. MDT1-0 bits select the transition time (Table
12). When the new gain value 1EH(-2dB) is written to gain register while the actual (stable) gain is 1FH(0dB), the gain
changes to 1EH(-2dB) within the transition time selected by MDT1-0 bits. The AK4705A compares the actual gain to the
value of gain register after finishing the transition time, and re-changes the actual gain to new register value within the
transition time if the register value is different from the actual gain. When the MOD bit = “0”, there is no transition time
and the gain changes immediately. This change may cause a click noise.
WR
[Gain=1EH]
Gain Register
1FH
WR
[Gain=1DH]
WR
[Gain=1CH]
compare
Actual Gain
1FH (to 1EH)
1CH
1DH
1EH
compare
1EH
(to 1DH)
compare
(to 1CH)
1CH
1DH
Transition Time (256/fs to 2048/fs. pop free.)
Figure 7. Volume Change Operation (MOD bit = “1”)
MDT1
0
0
1
1
MDT0
Transition Time
0
256/fs
1
512/fs
0
1024/fs
1
2048/fs
Table 12. Volume Transition Time
MS0698-E-00
(default)
2007/12
- 25 -
[AK4705A]
3. Video Block
■ Video Switch Control
The AK4705A has switches for TV, VCR and RF modulator. Each switches can be controlled via registers independently.
When AUTO bit = “1” or STBY bit = “1”, these switch setting are ignored and set to fixed configuration (loop-through
mode). Refer to the auto setup mode and standby mode.
(04H: D2-D0)
Mode
Shutdown
VTV2-0
bit
000
Encoder CVBS+RGB
or Encoder YPbPr
001
Encoder Y/C 1
010
Encoder Y/C 2
011
VCR
100
TV CVBS
101
(reserved)
(reserved)
110
111
Source of
TVVOUT pin
(Hi-Z)
ENCV pin.
Encoder CVBS
or Y.
ENCV pin.
Encoder Y.
ENCY pin.
Encoder Y.
VCRVIN pin.
VCR CVBS
or Y.
TVVIN pin.
TV CVBS.
-
Source of
TVRC pin
(Hi-Z)
ENCRC pin.
Encoder Red,C
or Pb.
ENCRC pin.
Encoder C.
ENCC pin.
Encoder C.
VCRRC pin.
VCR Red,C
or Pb.
Source of
TVG pin
(Hi-Z)
ENCG pin.
Encoder Green
or Y.
Source of
TVB pin
(Hi-Z)
ENCB pin.
Encoder Blue
or Pr.
(Hi-Z)
(Hi-Z)
(Hi-Z)
(Hi-Z)
VCRG pin.
VCR Green
or Y.
VCRB pin.
VCR Blue
or Pr.
(Hi-Z)
(Hi-Z)
(Hi-Z)
-
-
(Note: 19, Note: 20)
(default)
Table 13. TV Video Output
(04H: D5-D3)
Mode
VVCR2-0 bit
Shutdown
000
Encoder CVBS or Y/C 1
001
Encoder CVBS or Y/C 2
010
TV CVBS
011
VCR
100
(reserved)
(reserved)
(reserved)
101
110
111
Source of
VCRVOUT pin
(Hi-Z)
ENCV pin.
Encoder CVBS
or Y.
ENCY pin.
Encoder CVBS
or Y.
TVVIN pin.
TV CVBS.
VCRVIN pin.
VCR CVBS.
-
Source of
VCRC pin
(Hi-Z)
ENCRC pin.
Encoder C.
ENCC pin.
Encoder C.
(Hi-Z)
(default)
VCRRC pin.
VCR C.
(Note: 19)
Table 14. VCR Video Output
MS0698-E-00
2007/12
- 26 -
[AK4705A]
(04H: D7-D6)
Source of
RFV pin
ENCV pin.
Encoder CVBS1
00
Encoder CVBS.
ENCG pin.
Encoder CVBS2
01
Encoder CVBS.
(Note: 20)
VCRVIN pin.
VCR
10
(default)
VCR CVBS.
Shutdown
11
(Hi-Z)
(Note: 20)
Table 15. RF Video Output
Mode
VRF1-0
bit
Note: 19: When input the video signal via the ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively.
Note: 20 When VTV2-0 bit =“001”, TVG bit =“1” and VRF1-0 bit =“01”, the RFV pin output is same
as the TVG pin output (Encoder G).
■ Video Output Control (05H: D6-D0)
Each video outputs can be set to Hi-Z individually via control registers. These setting are ignored when the AUTO bit =
“1”. When the CIO bit = “1”, the VCRC pin outputs 0V even if the VCRC bit = “0”. When the CIO bit = “0”, the VCRC
pin follows the setting of VCRC bit. Please refer to the “Red/Chroma Bi-directional Control for VCR SCART”.
TVV:
TVR:
TVG:
TVB:
VCRV:
VCRC:
TVFB:
TVVOUT output control
TVRCOUT output control
TVGOUT output control
TVBOUT output control
VCRVOUT output control
VCRC output control
TVFB output control
0: Hi-Z (default)
1: Active.
MS0698-E-00
2007/12
- 27 -
[AK4705A]
■ Red/Chroma Bi-directional Control for VCR SCART (05H: D7, D5)
The AK4705A supports the bi-directional Red/Chroma signal on the VCR SCART.
(CIO bit &
VCRC bit)
#15 pin
75
VCRC
pin
VCRRC
pin
VCR SCART
0.1u
(AK4705A)
Figure 8. Red/Chroma Bi-directional Control
CIO
0
0
1
1
VCRC
State of VCRC pin
0
Hi-z
1
Active
0
Connected to GND
1
Connected to GND
Table 16 Red/Chroma Bi-directional Control
MS0698-E-00
(default)
2007/12
- 28 -
[AK4705A]
■ RGB Video Gain Control (06H: D1-D0)
VVOL1-0 bits set the RGB video gain.
VVOL1
0
0
1
1
VVOL0
0
1
0
1
Gain
Output level (Typ. @Input=0.7Vpp)
+6dB
1.4Vpp
+7.2dB
1.6Vpp
+8.2dB
1.8Vpp
+9.1dB
2.0Vpp
Table 17. RGB Video Gain Control
(default)
■ Clamp and DC-restore circuit control (06H: D7-D2)
Each CVBS and Y input has the sync tip clamp circuit. The DC-restore circuit has two clamp voltages 0.7V(typ) and
2.2V(typ) to support both RGB and YPbPr signal. They correspond to 0.35V(typ) and 1.1V(typ) at the SCART connector
when matched by 75ohm resistors. The CLAMP1, CLAMP0 and CLAMPB bits select the input circuit for the ENCRC
pin (Encoder Red/Chroma), ENCB pin (Encoder Blue), VCRRC pin (VCR Red/Chroma) and the VCRB pin (VCR Blue)
respectively. VCLP1-0 bits select the sync source of DC- restore circuit.
CLAMPB
CLAMP0
0
0
0
1
1
0
1
1
CLAMPB
CLAMP1
0
0
0
1
1
0
1
1
VCRRC Input Circuit
VCRB Input Circuit
DC restore clamp active
DC restore clamp active
(0.7V at sync timing/output pin)
(0.7V at sync timing/output pin)
Biased
(DC restore clamp active)
(2.2V at sync timing/output pin)
(0.7V at sync timing output pin)
DC restore clamp active
DC restore clamp active
(2.2V at sync timing/output pin)
(2.2V at sync timing/output pin)
(reserved)
(reserved)
Table 18. DC-restore Control for VCR Input
ENCRC Input Circuit
ENCB Input Circuit
DC restore clamp active
DC restore clamp active
(0.7V at sync timing/output pin)
(0.7V at sync timing/output pin)
Biased
DC restore clamp active
(2.2V at sync timing/output pin)
(0.7V at sync timing output pin)
DC restore clamp active
DC restore clamp active
(2.2V at sync timing/output pin)
(2.2V at sync timing/output pin)
(reserved)
(reserved)
Table 19. DC-restore Control for Encoder Input
CLAMP2
0
1
ENCG Input Circuit
DC restore clamp active
(0.7V at sync timing/output pin)
Sync tip clamp active
(0.7V at sync timing/output pin)
note
for RGB
for Y/C
(default)
for Y/Pb/Pr
note
for RGB
(default)
for Y/C
for Y/Pb/Pr
note
for RGB
(default)
for Y/Pb/Pr
Note: When the VTV2-0 bits = “001”(source for TV = Encoder CVBS /RGB), TVG bit = “1” (TVG
= active) and VCLP1-0 bits = “11”(DC restore source = ENCG), the sync tip is selected even
if the CLAMP2 bit = “0”.
Table 20. DC-restore Control for Encoder Green/Y Input
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[AK4705A]
VCLP1-0: DC restore source control
VCLP1
0
0
1
1
VCLP0
0
1
0
1
Sync Source of DC Restore
ENCV
ENCY
VCRVIN
ENCG
(default)
Note: When the AUTO bit = “1”, the source is fixed to VCRVIN.
Table 21. DC-restore Source Control
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[AK4705A]
4. Blanking Control
The AK4705A supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART.
■ Input/Output Control for Fast/Slow Blanking
FB1-0: TV Fast Blanking output control (07H: D1-D0)
FB1 bit
0
0
1
1
FB0 bit
0
1
0
1
TVFB pin Output Level
0V
(default)
2V<, 4V(typ) at 150Ω load
Same as VCR FB input (4V/0V)
(Reserved)
(Note: Minimum load is 150ohm)
Table 22. TV Fast Blanking Output
SBT1-0: TV Slow Blanking output control (07H: D3-D2)
SBT1
0
0
1
1
SBT0
0
1
0
1
TVSB pin Output Level
(default)
<2V
5V to 7V
(Reserved)
10V<
(Note: Minimum load is 10kohm)
Table 23. TV Slow Blanking Output
SBV1-0: VCR Slow Blanking output control (07H: D5-D4)
SBV1
0
0
1
1
SBV0
0
1
0
1
VCRSB pin Output Level
(default)
<2V
5V to 7V
(Reserved)
10V<
(Note: Minimum load is 10kohm)
Table 24. VCR Slow Blanking Output
SBIO1-0: TV/VCR Slow Blanking I/O control (07H: D7-D6)
SBIO1
SBIO0
0
0
0
1
1
0
1
1
VCRSB pin Direction
TVSB pin Direction
Output
Output
(Controlled by SBV1,0)
(Controlled by SBT1,0)
(Reserved)
(Reserved)
Input
Output
(Stored in SVCR1,0)
(Controlled by SBT1,0)
Input
Output
(Stored in SVCR1,0)
(Same output as VCR SB)
Table 25. TV/VCR Slow Blanking I/O Control
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[AK4705A]
5. Monitor Options and INT function
■ Monitor Options (08H: D4-D0)
The AK4705A has several detection functions. SVCR1-0 bits, FVCR bit, VCMON bit and TVMON bit reflect the input
DC level of VCR slow blanking, the input DC level of VCR fast blanking and signals input to the TVVIN or VCRVIN
pins.
SVCR1-0: VCR Slow blanking status monitor
SVCR1-0 reflect the voltage at VCRSB pin only when the VCRSB pin is in the input mode.
When the VCRSB is in the output mode, SVCR1-0 hold previous value.
VCRSB pin input level
SVCR1
SVCR0
< 2V
0
0
4.5 to 7V
0
1
(Reserved)
1
0
9.5<
1
1
Table 26. VCR Slow Blanking Monitor
FVCR: VCR Fast blanking input level monitor
This bit is enabled when TVFB bit = “1”.
VCRFB pin input level
FVCR
<0.4V
0
1 V<
1
Table 27. VCR Fast Blanking Monitor (Typical threshold is 0.7V)
VCMON: VCRVIN pin video input monitor (MCOMN bit = “1”),
TVVIN pin or VCRVIN pin video input monitor (MCOMN bit = “0”. AK4704 compatible.)
0: No video signal detected.
1: Detects video signal.
TVMON: TVVIN pin video input monitor (active when MCOMN bit = “1”)
0: No video signal detected.
1: Detects video signal.
AUTO
(00H D3)
0
0
0
0
MCOMN
(09H D7)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
TVMON
(08H D4)
0
0
0
0
VCMON
(08H D3)
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
1
1
TVVIN signal
VCRVIN signal
0
0
1
1
1
1
1
1
x
x
x
x
(x: Don’t care)
Note 1. TVVIN/VCRVIN signal: 0 = No signal applied, 1 = signal applied
Table 28. TV/VCR Monitor Function
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[AK4705A]
■ INT Function and Mask Options (09H: D7, D4-D1)
Changes of the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes “L” for
2μsec(typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kohm resistor.
MTV bit, MVC bit, MCOMN bit, MFVCR bit and MSVCR bit control the reflection of the status change of these
monitors onto the INT pin from report to prevent to masks each monitor.
AK4705A
VD
R=10kΩ
INT
uP
Figure 9. INT pin
MVC: VCMON Mask. Refer Table 30
MTV: TVMON Mask. Refer Table 29
MCOMN: Refer Table 28
AUTO
(00H D3)
0
0
0
0
TVMON
MTV
INT
(08H D4)
(09H D4)
No Change
0
Hi-Z
No Change
1
Hi-Z
Change
0
Generates “L” Pulse
Change
1
Hi-Z
No Change
0
Hi-Z
1
1
No Change
1
Hi-Z
Note: 21. When the STBY bit = “0”, the TV Monitor Mask function is enabled.
Note: 22. When AUTO bit = “1”, TVMON does not change.
Table 29. TV Monitor Mask
AUTO
(00H D3)
0
0
0
0
VCMON
(08H D3)
No Change
No Change
Change
Change
MVC
(09H D3)
0
1
0
1
INT
Hi-Z
Hi-Z
Generates “L” Pulse
Hi-Z
1
No Change
0
Hi-Z
1
No Change
1
Hi-Z
1
Change
0
Generates “L” Pulse
1
Change
1
Generates “L” Pulse
Note: 23. When the STBY bit = “0”, the VCR Monitor Mask function is enabled.
Table 30. VCR Monitor Mask
MFVCR: FVCR Monitor mask.
0: Change of FVCR is reflected to INT pin. (default)
1: Change of FVCR is NOT reflected to INT pin.
MSVCR: SVCR1-0 Monitor mask
0: Change of SVCR1-0 is reflected to INT pin. (default)
1: Change of SVCR1-0 is NOT reflected to INT pin.
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[AK4705A]
6. Control Interface
I2C-bus Control Mode
1. WRITE Operations
Figure 10 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 16). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction
bit (R/W). The most significant seven bits of the slave address are fixed as “0010001”. When the AK4705A receives the
slave address, the AK4705A generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 17). “1”
for R/W bit indicates that the read operation is to be executed. “0” indicates that the write operation is to be executed. The
second byte consists of the address for control registers of the AK4705A. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 12). The data after the second byte contain control data. The format is MSB
first, 8bits (Figure 13). The AK4705A generates an acknowledge after each byte is received. A data transfer is always
terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 16).
The AK4705A can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4705A
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 18) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
Data(n+1)
Data(n)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 10. Data Transfer Sequence at I2C-bus Mode
0
0
1
0
0
0
1
R/W
A2
A1
A0
D2
D1
D0
Figure 11. The First Byte
0
0
0
A4
A3
Figure 12. The Second Byte
D7
D6
D5
D4
D3
Figure 13. Byte Structure After The Second Byte
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[AK4705A]
2. READ Operations
Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by
generating an acknowledge instead of terminating the write cycle after receiving the first data word. After the receipt of
each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If
the address exceeds 09H prior to generating the stop condition, the address counter will “roll over” to 00H and the
previous data will be overwritten.
The AK4705A supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-1. CURRENT ADDRESS READ
The AK4705A contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4705A generates an
acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4705A
discontinues transmission
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n+1)
Data(n)
A
C
K
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 14. CURRENT ADDRESS READ
2-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start condition,
slave address(R/W=“0”) and then the register address to read. After the register’s address is acknowledge, the master
immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4705A generates
an acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but generate the stop condition, the AK4705A discontinues transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 15. RANDOM ADDRESS READ
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[AK4705A]
SDA
SCL
S
P
start condition
stop condition
Figure 16. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 17. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 18. Bit Transfer on the I2C-bus
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[AK4705A]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control
DEM1
DEM0
DIF1
DIF0
AUTO
DAPD
MUTE
STBY
01H
Switch
VMUTE
1
VCR1
VCR0
MONO
VOL
TV1
TV0
02H
Main volume
0
0
L5
L4
L3
L2
L1
L0
03H
Zerocross
0
VMONO
1
DVOL1
DVOL0
MOD
MDT1
MDT0
04H
Video switch
VRF1
VRF0
VVCR2
VVCR1
VVCR0
VTV2
VTV1
VTV0
05H
Video output enable
CIO
TVFB
VCRC
VCRV
TVB
TVG
TVR
TVV
06H
Video volume/clamp
CLAMPB
VCLP1
VCLP0
CLAMP2
CLAMP1
CLAMP0
VVOL1
VVOL0
07H
S/F Blanking control
SBIO1
SBIO0
SBV1
SBV0
SBT1
SBT0
FB1
FB0
0
0
0
TVMON
VCMON
FVCR
SVCR1
SVCR0
MCOMN
0
0
MTV
MVC
MFVCR
MSVCR
0
08H
S/F Blanking monitor
09H
Monitor mask
Note: 24. When the PDN pin goes “L”, the registers are initialized to their default values.
Note: 25. While the PDN pin =“H”, all registers can be accessed.
Note: 26. Do not write any data to the register over 09H.
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[AK4705A]
■ Register Definitions
Addr
Register Name
00H
Control
D7
D6
D5
D4
DEM1
DEM0
DIF1
DIF0
R/W
default
D3
D2
D1
D0
AUTO
DAPD
MUTE
STBY
1
0
1
1
R/W
0
1
STBY: Standby control
0: Normal Operation
1: Standby Mode (default).
DAC
Gain of Volume#1
Source of TVOUT
Source of VCROUT
Source of MONOOUT
Source of TVVOUT
Source of TVRC
Source of TVG
Source of TVB
Source of TVFB
Source of TVSB
Source of VCRVOUT
Source of VCRC
1
:
:
:
:
:
:
:
:
:
:
:
1
powered down and timings are reset.
fixed to 0dB
fixed to VCRIN
fixed to TVIN
fixed to VCRIN
fixed to VCRVIN(or Hi-Z)
: fixed to VCRRC(or Hi-Z)
fixed to VCRG(or Hi-Z)
fixed to VCRB(or Hi-Z)
fixed to VCRFB (or Hi-Z)
fixed to VCRSB
fixed to TVVIN(or Hi-Z)
: fixed to Hi-Z or VSS(controlled by CIO bit)
MUTE: Audio output control
0: Normal operation
1: ALL Audio outputs to GND (default)
DAPD: DAC power down control
0: Normal operation (default).
1: DAC power down.
When DAPD bit = “1”, the soft transition for volume does not work.
AUTO: Auto startup bit
0: Auto startup disable (Manual startup).
1: Auto startup enable (default).
Note: When the SBIO1bit = “1”(default= “0”), the change of AUTO bit may cause a “L” pulse on INT pin.
DIF1-0: Audio data interface format control
00: 16bit LSB Justified
01: 18bit LSB Justified
10: 24bit MSB Justified
11: 24bit I2S Compatible (default)
DEM1-0: De-emphasis Response Control
00: 44.1kHz
01: off (default)
10: 48kHz
11: 32kHz
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[AK4705A]
Addr
01H
Register Name
Switch
D7
D6
D5
D4
VMUTE
1
VCR1
VCR0
R/W
default
D3
D2
D1
D0
MONO
VOL
TV1
TV0
R/W
1
1
0
1
0
1
0
1
TV1-0: TVOUTL/R pins source switch
00: DAC
01: VCRINL/R pins (default)
10: MUTE
11: (Reserved)
VOL: MONOOUT pin source switch
0: Bypass the volume (fixed to DAC out)
1: Through the volume (default)
MONO: Mono select for TVOUTL/R pins
0: Stereo. (default)
1: Mono. (L+R)/2
VCR1-0: VCROUTL/R pins source switch
00: DAC
01: TVINL/R pins (default)
10: MUTE
11: Volume #1 output
VMUTE: Mute switch for volume #1
0: Normal operation
1: Mute the volume #1 (default)
Addr
Register Name
02H
Main volume
D7
D6
D5
D4
D3
D2
D1
D0
0
0
L5
L4
L3
L2
L1
L0
1
1
1
1
R/W
default
R/W
0
0
0
1
L5-0: Volume #1 control
Those registers control both Lch and Rch of Volume #1.
111111 to
100011: (Reserved)
100010: Volume gain = +6dB
100001: Volume gain = +4dB
100000: Volume gain = +2dB
011111: Volume gain = +0dB (default)
011110: Volume gain = -2dB
...
000011: Volume gain = -56dB
000010: Volume gain = -58dB
000001: Volume gain = -60dB
000000: Volume gain = Mute
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[AK4705A]
Addr
Register Name
03H
Zerocross
D7
D6
D5
D4
D3
D2
D1
D0
0
VMONO
1
DVOL1
DVOL0
MOD
MDT1
MDT0
0
1
1
1
R/W
default
R/W
0
0
1
0
MDT1-0: The time length control of volume transition time
00: typ. 256/fs
01:
512/fs
10:
1024/fs
11:
2048/fs (default)
MOD: Soft transition enable for volume #1 control
0: Disable
The volume value changes immediately without soft transition.
1: Enable (default)
The volume value changes with soft transition.
This function is disabled when STBY bit or DAPD bit = “1”.
DVOL1-0: Volume #0/Volume #2 control.
Refer to Table 9 and Table 10
VMONO: Mono select for VCROUTL/R pins
0: Stereo. (default)
1: Mono. (L+R)/2
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[AK4705A]
Addr
Register Name
04H
Video switch
R/W
default
D7
D6
D5
D4
VRF1
VRF0
VVCR2
VVCR1
D3
D2
D1
D0
VVCR0
VTV2
VTV1
VTV0
R/W
1
0
0
1
1
1
0
0
VTV2-0: Selector for TV video output
Refer to Table 13.
VVCR2-0: Selector for VCR video output
Refer to Table 14
VRF1-0: Selector for RFV pin output.
Refer to Table 15.
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
05H
Output enable
CIO
TVFB
VCRC
VCRV
TVB
TVG
TVR
TVV
0
0
0
0
R/W
default
TVV:
TVR:
TVG:
TVB:
VCRV:
VCRC:
TVFB:
0:
1:
R/W
0
0
0
0
TVVOUT output control
TVRCOUT output control
TVGOUT output control
TVBOUT output control
VCRVOUT output control
VCRC output control (Table 16)
TVFB output control
Hi-Z (default)
Active.
When the CIO pin = “1”, the VCRC pin is connected to GND even if VCRC= “0”.
When the CIO pin = “0”, the VCRC pin follows the setting of VCRC bit.
CIO: VCRC pin I/O control
Refer to Table 16.
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[AK4705A]
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
06H
Video volume
CLAMPB
VCLP1
VCLP0
CLAMP2
CLAMP1
CLAMP0
VVOL1
VVOL0
0
1
0
0
R/W
default
R/W
0
0
0
0
VVOL1-0: RGB video gain control
00: +6dB (default)
01: +7.2dB
10: +8.2dB
11: +9.1dB
CLAMPB, CLAMP2-0: Clamp control.
Refer to Table 18, Table 19 and Table 20.
VCLP1-0: DC restore source control
00: ENCV pin (default)
01: ENCY pin
10: VCRVIN pin
11: (Reserved)
When the AUTO bit = “1”, the source is fixed to VCRVIN pin.
Addr
Register Name
07H
S/F Blanking
R/W
default
D7
D6
D5
D4
D3
D2
D1
D0
SBIO1
SBIO0
SBV1
SBV0
SBT1
SBT0
FB1
FB0
0
0
0
0
0
0
0
0
R/W
FB1-0: TV Fast Blanking output control (for TVFB pin)
00: 0V (default)
01: 4V
10: follow VCR FB input (4V/0V)
11: (Reserved)
SBT1-0: TV Slow Blanking output control (for TVSB pin. Minimum load is 10kohm.)
00: <2V (default)
01: 5V to 7V
10: (Reserved)
11: 10V<
SBV1-0: VCR Slow Blanking output control (for VCRSB pin. Minimum load is 10kohm)
00: <2V (default)
01: 5V to 7V
10: (Reserved)
11: 10V<
SBIO1-0: TV/VCR Slow Blanking I/O control (Table 25)
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[AK4705A]
Addr
08H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
TVMON
VCMON
FVCR
SVCR1
SVCR0
0
0
0
Monitor
R/W
default
READ
0
0
0
0
0
SVCR1-0: VCR Slow blanking status monitor
SVCR1-0 reflect the voltage at VCRSB pin only when the VCRSB is in the input mode.
When the VCRSB is in the output mode, SVCR1-0 hold previous value.
VCRSB pin input level
SVCR1
SVCR0
< 2V
0
0
4.5 to 7V
0
1
(Reserved)
1
0
9.5<
1
1
Table 31. VCR Slow Blanking monitor
FVCR: VCR Fast blanking input level monitor
This bit is enabled when TVFB bit = “1”.
VCRFB pin input level
FVCR
<0.4V
0
1 V<
1
Table 32. VCR Fast Blanking monitor (Typical threshold is 0.7V)
VCMON:
TVMON:
Refer to Table 28.
Addr
Register Name
09H
Monitor mask
D7
D6
D5
D4
D3
D2
D1
D0
MCOMN
0
0
MTV
MVC
MFVCR
MSVCR
0
0
0
0
0
1
0
0
0
R/W
default
R/W
MSVCR: SVCR1-0 Monitor mask.
0: The INT pin reflects the change of SVCR1-0 bits. (default)
1: The INT pin does not reflect the change of SVCR1-0 bit.
MFVCR: FVCR Monitor mask.
0: The INT pin reflects the change of MFVCR bit. (default)
1: The INT pin does not reflect the change of MFVCR bit.
MVC:
MTV:
Refer to Table 29, Table 30.
MCOMN:.
Refer to Table 28.
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[AK4705A]
SYSTEM DESIGN
RFV
MONOOUT
CVBS
Audio MONO
RF Mod
Phono
TVOUTL
TVOUTR
TVRC
TVG
TVB
TVFB
TVVOUT
CVBS/Y
Y
C
Encoder
R/C
G/CVBS
B
MCLK
MPEG
BICK
Decoder
LRCK
SDATA
TVVIN
ENCV
TVINL
ENCY
TVINR
ENCC
TVSB
ENCRC
ENCGV
VCRFB
ENCB
VCRVIN
VCRRC
MCLK
Processor
SCK
SDA
PDN
Interrupt
Audio R
R/C
G
B
Fast Blank
TV SCART
Y/CVBS
Y/CVBS
Audio L
Audio R
Slow Blank
Fast Blank
Y/CVBS
R/C
VCRC
BICK
VCRG
LRCK
VCRB
SDTI
VCRINL
Micro
Audio L
VCRINR
VCRVOUT
SCK
SDA
VCROUTL
PDN
VCROUTR
INT
VCRSB
G
B
VCR SCART
Audio L
Audio R
Y/CVBS
Audio L
Audio R
Slow Blank
Figure 19. Typical Connection Diagram
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[AK4705A]
■ Grounding and Power Supply Decoupling
VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit with low impedance and be
separated from system digital supply. An electrolytic capacitor 10μF parallel with a 0.1μF ceramic capacitor should be
attached to these pins to eliminate the effects of high frequency noise. The 0.1μF ceramic capacitors should be placed as
near to VD (VP, VVD1, VVD2) as possible.
■ Voltage Reference
DVCOM and PVCOM are signal common of this chip. An electrolytic capacitor 10μF parallel with a 0.1μF ceramic
capacitor should be attached to these VCOM pins to eliminate the effects of high frequency noise. No load current may be
taken from these VCOM pins. All signals, especially clocks, should be kept away from these VCOM pins in order to
avoid unwanted coupling into the AK4705A.
■ Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(typ.). The output signal range is typically 2Vrms
(typ@VD=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigma modulator beyond the audio pass band. Therefore, any external filters are not required for typical application.
The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The
ideal output is 5.6V(typ.) for 000000H (@24bit). The DC voltage offset on analog outputs are eliminated by AC
coupling.
■ REFI Pin
The REFI pin is video current reference pin. This pin should be connected to VVD1 through a 10kΩ±1% resistor
externally as shown in Figure 20. No load current may be drawn from this pin. All signals, especially clocks, should be
kept away from this pin in order to avoid unwanted coupling.
AK4705A
VDD1
R=10kΩ±1%
IREF
Figure 20. REFI Pin
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[AK4705A]
■ External Circuit Example
Analog Audio Input pin
300ohm
TVINL/R
VCRINL/R
DACL/R
0.47μF
(Cable)
Analog Audio Output pin
MONOOUT
TVOUTL/R
VCROUTL/R
300ohm
10μF
(Cable)
Total > 4.5kohm
Analog Video Input pin
75ohm
(Cable)
0.1μF
75ohm
ENCV, ENCY, VCRVIN,
TVVIN, ENCRC, ENCC,
VCRRC, ENCG, VCRG,
ENCB, VCRB
Analog Video Output pin
TVVOUT, TVRC
TVG, TVR, RFV
VCRVOUT, VCRC
max
15pF
75ohm
(Cable)
max
400pF
MS0698-E-00
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[AK4705A]
Slow Blanking pin
TVSB
VCRSB
(Cable)
400ohm
(max 500ohm)
max 3nF
(with 400ohm)
min: 10k ohm
Fast Blanking Input pin
VCRFB
75ohm
(Cable)
75ohm
Fast Blanking Output pin
75ohm
TVFB
(Cable)
75ohm
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[AK4705A]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0 ± 0.2
25
12
0.09~0.20
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.3~0.75
0.10
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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[AK4705A]
MARKING
4705AEQ
XXXXXXX
1
XXXXXXXX: Date code identifier
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[AK4705A]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
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