Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC33937
Rev. 9.0, 11/2015
Three Phase Field Effect Transistor
Pre-driver
33937A
The 33937A is a field effect transistor (FET) pre-drivers designed for three
phase motor control and similar applications. The integrated circuit (IC) uses
SMARTMOS technology.
The IC contains three high-side FET pre-drivers and three low-side FET predrivers. Three external bootstrap capacitors provide gate charge to the highside FETs.
The IC interfaces to a MCU via six direct input control signals, an SPI port for
device setup and asynchronous reset, enable and interrupt signals. Both 5.0
and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are
provided.
THREE PHASE PRE-DRIVER
Features
•
•
•
•
Extended operating range from 6.0 V to 58 V covers 12 V and 42 V systems
Gate drive capability of 1.0 A to 2.5 A
Fully specified from 8.0 V to 40 V covers 12 and 24 V automotive systems
Protection against reverse charge injection from CGD and CGS of external
FETs
• Includes a charge pump to support full FET drive at low battery voltages
• Dead time is programmable via the SPI port
• Simultaneous output capability enabled via safe SPI command
EK SUFFIX (Pb-FREE)
98ASA99334D
54-PIN SOICW-EP
Applications
Automotive systems
• Cooling fan
• Water pump
• Actuator controls
• Fuel pump
• Electro-hydraulic and electric power steering
• Engine control
• Motor control
VSYS
33937
VPUMP
VSUP
PUMP
VPWR
VLS
VDD
VSS
3
3
3
MCU
OR
DSP
PX_HS
PX_LS
PHASEX
CS
SI
SCLK
SO
RST
INT
EN1
GND
EN2
PA_HS_G
PB_HS_G
PC_HS_G
PA_HS_S
PB_HS_S
PC_HS_S
PA_LS_G
PB_LS_G
PC_LS_G
PX_LS_S
AMP_P
AMP_N
AMP_OUT
RSEN
Figure 1. 33937A Simplified Application Diagram
© Freescale Semiconductor, Inc., 2011-2015. All rights reserved.
1
Orderable Parts
Table 1. Orderable Part Variations
Part Number (1)
MC33937APEK
Temperature (TA)
Package
-40 °C to 135 °C
54 SOICW-EP
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
33937A
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Internal Block Diagram
PUMP
VPUMP
VPWR
VSUP
MAIN
CHARGE
PUMP
PGND
TRICKLE
CHARGE
PUMP
HOLD
-OFF
CIRCUIT
VLS
REG.
5.0 V
REG.
VDD
OSCILLATOR
VLS
VDD
UV
DETECT
3X
RST
PX_BOOT
T-LIM
INT
VSUP
EN1
EN2
3
PX_HS
CONTROL
LOGIC
3
PX_LS
+
DESAT. 1.4 V
COMP
+
-
HIGHSIDE
DRIVER
PX_HS_S
CS
SI
+
-
SCLK
PHASE
VSUP
COMP.
SO
LOWSIDE
DRIVER
3
PHASEX
OC_OUT
GND(2)
PX_HS_G
+
OVERCUR.
COMP.
PX_LS_G
+
PX_LS_S
I-SENSE
AMP.
VSS OC_TH AMP_OUT
AMP_N
AMP_P
VLS_CAP
Figure 2. 33937A Simplified Internal Block Diagram
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
3
Pin Connections
3.1
Pinout Diagram
PHASEA
PGND
EN1
EN2
RST
N/C
PUMP
VPUMP
VSUP
PHASEB
PHASEC
PA_HS
PA_LS
VDD
PB_HS
PB_LS
INT
CS
SI
SCLK
SO
PC_LS
PC_HS
AMP_OUT
AMP_N
AMP_P
OC_OUT
Transparent
Top View
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
.35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
VPWR
N/C
N/C
VLS
N/C
N/C
PA_BOOT
PA_HS_G
PA_HS_S
PA_LS_G
PA_LS_S
PB_BOOT
PB_HS_G
PB_HS_S
PB_LS_G
PB_LS_S
PC_BOOT
PC_HS_G
PC_HS_S
PC_LS_G
PC_LS_S
N/C
VLS_CAP
GND1
GND0
VSS
OC_TH
Figure 3. 33937A Pin Connections
3.2
Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 21.
Table 2. 33937A Pin Definitions
Pin
Pin Name
Pin Function
Formal Name
Definition
1
PHASEA
Digital Output
Phase A
Totem Pole output of Phase A comparator. This output is low when the voltage on
PA_HS_S (Source of High-side FET) is less than 50% of VSUP
2
PGND
Ground
Power Ground
3
EN1
Digital Input
Enable 1
Logic signal input must be high (ANDed with EN2) to enable any gate drive output.
Logic signal input must be high (ANDed with EN1) to enable any gate drive output
Power ground for charge pump
4
EN2
Digital Input
Enable 2
5
RST
Digital Input
Reset
6, 33, 49, 50,
52, 53
N/C
–
No Connect
7
PUMP
Power Drive
Out
Pump
Charge pump output
8
VPUMP
Power Input
Voltage Pump
Charge pump supply
9
VSUP
Analog Input
Supply Voltage
Supply voltage to the load. This pin is to be connected to the common Drains of the
external high-side FETs
Reset input
Do not connect these pins
33937A
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 2. 33937A Pin Definitions (continued)
Pin
Pin Name
Pin Function
Formal Name
Definition
10
PHASEB
Digital Output
Phase B
Totem Pole output of Phase B comparator. This output is low when the voltage on
PB_HS_S (Source of high-side FET) is less than 50% of VSUP
11
PHASEC
Digital Output
Phase C
Totem Pole output of Phase C comparator. This output is low when the voltage on
PC_HS_S (Source of high-side FET) is less than 50% of VSUP
12
PA_HS
Digital Input
Phase A High-side
Active low input logic signal enables the high-side driver for Phase A
13
PA_LS
Digital Input
Phase A Low-side
Active high input logic signal enables the low-side driver for Phase A
14
VDD
Analog
Output
VDD Regulator
15
PB_HS
Digital Input
Phase B High-side
Active low input logic signal enables the high-side driver for Phase B
16
PB_LS
Digital Input
Phase B Low-side
Active high input logic signal enables the low-side driver for Phase B
17
INT
Digital Output
Interrupt
18
CS
Digital Input
Chip Select
19
SI
Digital Input
Serial In
20
SCLK
Digital Input
Serial Clock
21
SO
Digital Output
Serial Out
22
PC_LS
Digital Input
Phase C Low-side
Active high input logic signal enables the low-side driver for Phase C
23
PC_HS
Digital Input
Phase C High-side
Active low input logic signal enables the high-side driver for Phase C
24
AMP_OUT
Analog
Output
Amplifier Output
Output of the current-sensing amplifier
25
AMP_N
Analog Input
Amplifier Invert
Inverting input of the current-sensing amplifier
26
AMP_P
Analog Input
Amplifier Non-Invert
27
OC_OUT
Digital Output
Overcurrent Out
28
OC_TH
Analog Input Overcurrent Threshold
VDD regulator output capacitor connection.
Interrupt pin output
Chip Select input. It frames SPI commands and enables SPI port
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
Clock for SPI port and typically is 3.0 MHz
Output data for SPI port. Tri-state until CS becomes low
Non-inverting input of the current-sensing amplifier
Totem pole digital output of the overcurrent comparator
Threshold of the overcurrent detector
29
VSS
Ground
30, 31
GND
Ground
Voltage Source Supply Ground reference for logic interface and power supplies
Ground
32
VLS_CAP
Analog
Output
VLS Regulator Output
Capacitor
34
PC_LS_S
Power Input
Phase C Low-side
Source
Source connection for Phase C low-side FET
35
PC_LS_G
Power Output
Phase C Low-side
Gate Drive
Gate drive output for Phase C low-side
36
PC_HS_S
Power Input
Phase C High-side
Source
Source connection for Phase C high-side FET
37
PC_HS_G
Power Output
Phase C High-side
Gate Drive
Gate Drive for output Phase C high-side FET
38
PC_BOOT
Analog Input
Phase C Bootstrap
Bootstrap capacitor for Phase C
39
PB_LS_S
Power Input
Phase B Low-side
Source
Source connection for Phase B low-side FET
40
PB_LS_G
Power Output
Phase B Low-side
Gate Drive
Gate Drive for output Phase B low-side
41
PB_HS_S
Power Input
Phase B High-side
Source
Source connection for Phase B high-side FET
42
PB_HS_G
Power Output
Phase B High-side
Gate Drive
Gate Drive for output Phase B high-side
43
PB_BOOT
Analog Input
Phase B Bootstrap
Bootstrap capacitor for Phase B
44
PA_LS_S
Power Input
Phase A Low-side
Source
Source connection for Phase A low-side FET
Substrate and ESD reference, connect to VSS
VLS Regulator connection for additional output capacitor, providing lowimpedance supply source for low-side gate drive
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
Table 2. 33937A Pin Definitions (continued)
Pin
Pin Name
Pin Function
Formal Name
Definition
45
PA_LS_G
Power Output
Phase A Low-side
Gate Drive
Gate Drive for output Phase A low-side
46
PA_HS_S
Power Input
Phase A High-side
Source
Source connection for Phase A high-side FET
47
PA_HS_G
Power Output
Phase A High-side
Gate Drive
Gate Drive for output Phase A high-side
48
PA_BOOT
Analog Input
Phase A Bootstrap
Bootstrap capacitor for Phase A
51
VLS
Analog
Output
VLS Regulator
VLS regulator output. Power supply for the gate drives
54
VPWR
Power Input
Voltage Power
Power supply input for gate drives
EP
Ground
Exposed Pad
Device will perform as specified with the exposed pad un-terminated (floating)
however, it is recommended that the exposed pad be terminated to pin 29 (VSS)
and system ground
33937A
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
Electrical Characteristics
4.1
Maximum Ratings
Table 3. Maximum Ratings
All voltages are with respect to VSS unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to
the device.
Symbol
Ratings
Value
Unit
Notes
ELECTRICAL RATINGS
VSUP
VSUP Supply Voltage
• Normal Operation (Steady-state)
• Transient Survival
58
-1.5 to 80
V
VPWR
VPWR Supply Voltage
• Normal Operation (Steady-state)
• Transient Survival
58
-1.5 to 80
V
VPUMP
Charge Pump (PUMP, VPUMP)
-0.3 to 40
V
VLS
VLS Regulator Outputs (VLS, VLS_CAP)
-0.3 to 18
V
VDD
Logic Supply Voltage
-0.3 to 7.0
V
VOUT
Logic Output (INT, SO, PHASEA, PHASEB, PHASEC, OC_OUT)
-0.3 to 7.0
V
VIN
Logic Input Pin Voltage (EN1, EN2, Px_HS, Px_LS, SI, SCLK, CS, RST) 10 mA
-0.3 to 7.0
V
VIN_A
Amplifier Input Voltage
• (Both Inputs-GND), (AMP_P - GND) or (AMP_N - GND) 6.0 mA source or sink
-7.0 to 7.0
V
VOC
Overcurrent comparator threshold 10 mA
-0.3 to 7.0
V
VBOOT
VHS_G
VLS_G
VHS_G
VHS_S
VLS_G
VLS_S
VESD
Notes
2.
3.
4.
5.
6.
Driver Output Voltage
• High-side bootstrap (PA_BOOT, PB_BOOT, PC_BOOT)
• High-side (PA_HS_G, PB_HS_G, PC_HS_G)
• Low-side (PA_LS_G, PB_LS_G, PC_LS_G)
Driver Voltage Transient Survival
• High-side (PA_HS_G, PB_HS_G, PC_HS_G, PA_HS_S, PB_HS_S,
PC_HS_S)
• Low-side (PA_LS_G, PB_LS_G, PC_LS_G, PA_LS_S, PB_LS_S, PC_LS_S)
ESD Voltage
• Human Body Model - HBM (All pins except for the pins listed below)
Pins: PA_Boot, PA_HS_S, PA_HS_G, PB_Boot, PB_HS_S, PB_HS_G,
PC_Boot, PC_HS_S, PC_HS_G, VPWR
• Charge Device Model - CDM
• Corner pins
• All other pins
75
75
16
-7.0 to 75.0
-7.0 to 75.0
-7.0 to 18.0
-7.0 to 7.0
(2)
(2)
(3)
V
(4)
V
(5)
V
(6)
±2000
±1000
±750
±300
The device will withstand load dump transient as defined by ISO7637 with peak voltage of 80 V.
Short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within this range.
This voltage should not be applied without also taking voltage at HS_S and voltage at PX_LS_S into account.
Actual operational limitations may differ from survivability limits. The VLS - VLS_S differential and the VBOOT - VHS_S differential must be greater
than 3.0 V to insure the output gate drive will maintain a commanded OFF condition on the output.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model
(CDM), Robotic (CZAP = 4.0 pF).
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
Table 3. Maximum Ratings (continued)
All voltages are with respect to VSS unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to
the device.
Symbol
Ratings
Value
Unit
Notes
Storage Temperature
-55 to +150
°C
Operating Junction Temperature
-40 to +150
°C
3.0
°C/W
(7)
Note 9
°C
(8)
THERMAL RATINGS
TSTG
TJ
RθJC
TSOLDER
Thermal Resistance
• Junction-to-Case
Soldering Temperature
Notes
7. Case is considered EP - pin 55 under the body of the device. The actual power dissipation of the device is dependent on the operating mode, the
heat transfer characteristics of the board and layout and the operating voltage. See Figure 24 and Figure 25 for examples of power dissipation
profiles of two common configurations. Operation above the maximum operating junction temperature will result in a reduction in reliability leading
to malfunction or permanent damage to the device.
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature
and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to
view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33937A
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.2
Static Electrical Characteristics
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VPWR Supply Voltage Startup Threshold
–
6.0
8.0
V
(10)
VSUP Supply Current, VPWR = VSUP = 40 V, RST and
ENABLE = 5.0 V
• No output loads on Gate Drive Pins, No PWM
• No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle
–
–
1.0
–
–
10
–
–
11
–
20
95
–
–
14
56
30
100
µA
Sleep State Output Gate Voltage
• IG < 100 µA
–
–
1.3
V
Trickle Charge Pump (Bootstrap Voltage)
• VSUP = 14 V
22
28
32
V
Bootstrap Diode Forward Voltage at 10 mA
–
–
1.2
V
4.5
–
5.5
V
–
–
12
mA
Peak Output Current, VPWR = 16 V, VLS = 10 V
350
600
800
mA
Linear Regulator Output Voltage, IVLS = 0 to 60 mA, VPWR > VLS +
2.0 V
13.5
15
17
V
(13)
VLS Disable Threshold
7.5
8.0
8.5
V
(14)
POWER INPUTS
VPWR_ST
ISUP
IPWR_ON
VPWR Supply Current, VPWR = VSUP = 40 V, RST and
ENABLE = 5.0 V
• No output loads on Gate Drive Pins, No PWM, Outputs initialized
• Output Loads = 620 nC per FET, 20 kHz PWM
ISUP
IPWR
VGATESS
VBoot
VF
Sleep State Supply Current, RST = 0 V
• VSUP = 40 V
• VPWR = 40 V
mA
mA
(11)
(15)
VDD INTERNAL REGULATOR
VDD
VDD Output Voltage, VPWR = 8 to 40 V, C = 0.47 µF
• External Load IDD_EXT = 0 to 1.0 mA
IDD
Internal VDD Supply Current, VDD = 5.5 V, No External Load
(12)
VLS REGULATOR
IPEAK
VLS
VTHVLS
Notes
10. Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. VPWR must exceed this threshold in
order for the Charge Pump and VDD regulator to startup and drive VPWR to > 8.0 V. Once VPWR exceeds 8.0 V, the circuits will continue to operate
even if system voltage drops below 6.0 V.
11. This parameter is guaranteed by design. It is not production tested.
12. Minimum external capacitor for stable VDD operation is 0.47 µF.
13.
Recommended external capacitor for the VLS regulator is 2.2 µF low ESR at each pin VLS and VLS_CAP.
14.
When VLS is less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery requires initialization when VLS rises above
this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transients on VLS.
15.
See Figure 11 for typical capability to maintain gate voltage with a 5.0 µA load.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
–
–
250
6.0
5.0
500
10
9.4
900
Ω
Ω
mV
8.5
12
9.5
–
–
–
V
–
–
–
–
6.0
8.5
Ω
High-side Driver On Resistance (Sinking)
• VPWR = VSUP = 16 V
–
–
3.0
Ω
High-side Current Injection Allowed Without Malfunction
–
–
0.5
A
–
–
–
–
6.0
8.5
Ω
Low-side Driver On-Resistance (Sinking)
• VPWR = VSUP = 16 V
–
–
3.0
Ω
Low-side Current Injection Allowed Without Malfunction
–
–
0.5
Α
(18), (19)
13
13
14.8
15.4
16.5
17
V
(20)
–
–
–
10
10
–
15
15
15
V
(21)
CHARGE PUMP
RDS(on)_HS
RDS(on)_LS
VTHREG
VCP
Charge Pump
• High-side Switch On Resistance
• Low-side Switch On Resistance
• Regulation Threshold Difference
Charge Pump Output Voltage
• IOUT = 40 mA, 6.0 V < VSYS < 8.0 V
• IOUT = 40 mA, VSYS > = 8.0 V
(16), (18)
(17), (18)
GATE DRIVE
RDS(on)_H_SRC
High-side Driver On Resistance (Sourcing)
• VPWR = VSUP = 16 V, - 40 °C ≤ TA ≤ 25 °C
• VPWR = VSUP = 16 V, 25 °C < TA ≤ 135 °C
RDS(on)_H_SINK
IHS_INJ
RDS(on)_L_SRC
Low-side Driver On Resistance (Sourcing)
• VPWR = VSUP = 16 V, - 40 °C ≤ TA ≤ 25 °C
• VPWR = VSUP = 16 V, 25 °C < TA ≤ 135 °C
RDS(on)_L_SINK
ILS_INJ
VGS_H
VGS_L
Gate Source Voltage, VPWR = VSUP = 40 V
• High-side, IGATE = 0
• Low-side, IGATE = 0
(18), (19)
Reverse High-side Gate Holding Voltage
VHS_G_HOLD
Gate Output Holding Current = 2.0 µA
Gate Output Holding Current = 5.0 µA, VSUP<26 V
Gate Output Holding Current = 5.0 µA, VSUP<40 V
Notes
16. When VLS is this amount below the normal VLS linear regulation threshold, the charge pump is enabled.
17. VSYS is the system voltage on the input to the charge pump. Recommended external components: 1.0 µF MLC, MUR 120 diode.
18.
19.
20.
21.
This parameter is a design characteristic, not production tested.
Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of approximately 1.0 µs
after an output switch transition. 1.0 µs is sufficient for all intended applications of this IC.
If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not recover
completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap and the VLS
capacitors.
High-side Gate Holding voltage is the voltage between the Gate and Source of the high-side FET when held in an on condition. The trickle charge
pump supplies bias and holding current for the High-side FET gate driver and output to maintain voltages after bootstrap events. See Figure 11
for typical 100% high-side gate voltage with a 5.0 µA load. This parameter is a design characteristic, not production tested.
33937A
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Common Mode Input Range
2.0
–
VDD-0.02
V
(23)
Input Offset Voltage
-50
–
50
mV
Overcurrent Comparator Threshold Hysteresis
50
300
mV
OVERCURRENT COMPARATOR
VCM
VOS_OC
VOC_HYST
VOH
VOL
Output Voltage
• High Level at IOH = -500 µA
• Low Level at IOL = 500 µA
0.85 VDD
–
–
–
VDD
0.5
V
10
–
300
µA
0.5 VSUP
–
0.65 VSUP
V
(22)
HOLD OFF CIRCUIT
IHOLD
Hold Off Current (At Each GATE Pin)
• 3.0 V < VSUP < 40 V, VGATE = 1.0 V
(24)
PHASE COMPARATOR
VIH_TH
High Level Input Voltage Threshold
VIL_TH
Low Level Input Voltage Threshold
0.3 VSUP
–
0.45 VSUP
V
VOH
High Level Output Voltage at IOH = -500 µA
0.85 VDD
–
VDD
V
VOL
Low Level Output Voltage at IOL = 500 µA
–
–
0.5
V
RIN
High-side Source Input Resistance
–
40
–
kΩ
(22), (27)
1.2
1.4
1.6
V
(25)
–
1.0
–
kW
5.0
–
15
DESATURATION DETECTOR
VDES_TH
Desaturation Detector Threshold
CURRENT SENSE AMPLIFIER
RS
Recommended External Series Resistor (See Figure 9)
RFB
Recommended External Feedback Resistor (See Figure 9)
• Limited by the Output Voltage Dynamic Range
VID
Maximum Input Differential Voltage (See Figure 9)
• VID = VAMP_P - VAMP_N
-800
–
+800
VCM
Input Common Mode Range
-0.5
–
3.0
VOS
Input Offset Voltage
• RS = 1.0 kΩ, VCM = 0.0 V
-15
–
+15
–
-10
–
-200
–
+200
δVOS/δT
Ib
Input Offset Voltage Drift
Input Bias Current
• VCM = 2.0 V
kW
(28)
mV
V
(22), (26)
mV
µV/°C
(22)
nA
Notes
22. This parameter is a design characteristic, not production tested.
23. As long as one input is in the common mode range there is no phase inversion on the output.
24. The hold off circuit is designed to operate over the full operating range of VSUP. The specification indicates the conditions used in production test.
Hold off is activated at VPOR or VTHVLS.
25.
27.
Desaturation is measured as the voltage drop below VSUP, thus the threshold is compared to the drain-source voltage of the external High-side
FET. See Figure 5.
As long as one input is within VCM the output is guaranteed to have the correct phase. Exceeding the common mode rails on one input will not
cause a phase inversion on the output.
Input resistance is impedance from the high-side source and is referenced to VSS. Approximate tolerance is ±20%.
28.
The current sense amplifier is unity gain stable with a phase margin of approximately 45°. See Figure 10.
26.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
CURRENT SENSE AMPLIFIER (CONTINUED)
IOS
Input Offset Current
• IOS = IAMP_P - IAMP_N
-80
–
+80
δIOS/δT
Input Offset Current Drift
–
40
–
pA/°C
VDD-0.2
–
–
–
VDD
0.2
V
VOH
VOL
Output Voltage
• High Level with RLOAD = 10 kΩ to VSS
• Low Level with RLOAD = 10 kΩ to VDD
nA
RI
Differential Input Resistance
1.0
–
–
MΩ
ISC
Output Short-circuit Current
5.0
–
–
mA
CI
Common Mode Input Capacitance at 10 kHz
–
–
10
pF
Common Mode Rejection Ratio at DC
• CMRR = 20*Log ((VOUT_DIFF/VIN_DIFF) * (VIN_CM/VOUT_CM))
60
80
–
AOL
Large Signal Open Loop Voltage Gain (DC)
–
78
–
NL
Nonlinearity
• RL = 1.0 kΩ, CL = 500 pF, 0.3 < VO < 4.8 V, Gain = 5.0 to 15
-1.0
–
+1.0
CMRR
(29)
(29), (30)
dB
dB
(29), (30)
%
(29), (30)
Notes
29. This parameter is a design characteristic, not production tested.
30. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
33937A
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
SUPERVISORY AND CONTROL CIRCUITS
VIH
VIL
Logic Inputs (Px_LS, Px_HS, EN1, EN2)
• High Level Input Voltage Threshold
• Low Level Input Voltage Threshold
2.1
–
–
–
–
0.9
V
(32)
VIH
VIL
Logic Inputs (SI, SCLK, CS)
• High Level Input Voltage Threshold
• Low Level Input Voltage Threshold
2.1
–
–
–
–
0.9
V
(31), (32)
100
250
450
mV
(31)
8.0
–
18
µA
Input Pull-up Current, (CS, Px_HS)
• 0 ≤ VIN ≤ 0.7 VDD
10
–
25
µA
(33)
Input Capacitance
• 0.0 V ≤ VIN ≤ 5.5 V
–
15
–
pF
(31)
1.0
–
2.1
V
(34)
40
60
85
kW
3.4
4.0
4.5
V
VIHYS
IINPD
IINPU
CIN
VTH_RST
RRST
Input Logic Threshold Hysteresis
• Inputs Px_LS, SI, SCLK, CS, Px_HS, EN1, EN2
Input Pull-down Current, (Px_LS, SI, SCLK, EN1, EN2)
• 0.3 VDD ≤ VIN ≤ VDD
RST Threshold
RST Pull-down Resistance
• 0.3 VDD ≤ VIN ≤ VDD
VPOR
Power-OFF RST Threshold, (VDD Falling)
VSOH
SO High Level Output Voltage
• IOH = 1.0 mA
0.9 VDD
–
–
V
VSOL
SO Low Level Output Voltage
• IOL = 1.0 mA
–
–
0.1 VDD
V
-1.0
–
1.0
–
15
–
ISO_LEAK_T
CSO_T
SO Tri-state Leakage Current
• CS = 0.7 VDD, 0.3 VDD ≤ VSO ≤ 0.7 VDD
SO Tri-state Capacitance
• 0.0 V ≤ VIN ≤ 5.5 V
VOH
INT High Level Output Voltage
• IOH = -500 µA
0.85 VDD
–
VDD
VOL
INT Low Level Output Voltage
• IOL = 500 µA
–
–
0.5
µA
pF
(31), (35)
V
V
THERMAL WARNING
TWARN
Thermal Warning Temperature
150
170
185
°C
(31), (36)
THYST
Thermal Hysteresis
8.0
10
12
°C
(31)
Notes
31. This parameter is guaranteed by design, not production tested.
32. Logic threshold voltages derived relative to a 3.3 V 10% system.
33. Pull-up circuits will not allow back biasing of VDD.
34.
35.
36.
There are two elements in the RST circuit: 1) one generally lower threshold enables the internal regulator; 2) the second removes the reset from
the internal logic.
This parameter applies to the OFF state (tri-stated) condition of SO is guaranteed by design but is not production tested.
The Thermal Warning circuit does not force IC shutdown above this temperature. It is possible to set a bit in the MASK register to generate an
interrupt when overtemperature is detected, and the status bit will always indicate if any of the three individual Thermal Warning circuits in the IC
sense a fault.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
4.3
Dynamic Electrical Characteristics
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
INTERNAL REGULATORS
tPU_VDD
VDD Power-up Time (Until INT High)
• 8.0 V ≤ VPWR
–
–
2.0
ms
(37), (39)
tPU_VLS
VLS Power-up Time
• 16 V ≤ VPWR
–
–
2.0
ms
(38), (39)
FOSC
Charge Pump Oscillator Frequency
90
125
190
kHz
SRCP
Charge Pump Slew Rate
–
100
–
V/µs
(40)
High-side Turn On Time
• Transition Time from 1.0 V to 10 V, Load: C = 500 pF, Rg = 0,
(Figure 7)
–
20
35
ns
(41)
130
265
386
ns
(42)
–
20
35
ns
(41)
130
265
386
ns
(42)
–
20
35
ns
(41)
130
265
386
ns
(42)
–
20
35
ns
(41)
130
265
386
ns
(42)
CHARGE PUMP
GATE DRIVE
tONH
tD_ONH
tOFFH
tD_OFFH
tONL
tD_ONL
tOFFL
tD_OFFL
High-side Turn On Delay
• Delay from Command to 1.0 V, (Figure 7)
High-side Turn Off Time
• Transition Time from 10 V to 1.0 V, Load: C = 500 pF, Rg = 0,
(Figure 8)
High-side Turn Off Delay
• Delay from Command to 10 V, (Figure 8)
Low-side Turn On Time
• Transition Time from 1.0 V to 10 V, Load: C = 500 pF, Rg = 0,
(Figure 7)
Low-side Turn On Delay
• Delay from Command to 1.0 V, (Figure 7)
Low-side Turn Off Time
• Transition Time from 10 V to 1.0 V, Load: C = 500 pF, Rg = 0,
(Figure 8)
Low-side Turn Off Delay
• Delay from Command to 10 V, (Figure 8)
Notes
37. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on VDD.
38.
The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitors on VLS and VLS_CAP.
This delay includes the expected time for VDD to rise.
39.
40.
This specification is based on capacitance of 0.47 µF on VDD, 2.2 µF on VLS and 2.2 µF on VLS_CAP.
The charge pump operating at 12 V VSYS, 1.0 μF pump capacitor, MUR120 diodes and 47 µF filter capacitor.
41.
42.
This parameter is guaranteed by characterization, not production tested.
These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes one clock
period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and output driver propagation
delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision block. Synchronization time accounts
for up to one clock period of variation. See Figure 6.
33937A
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Same Phase Command Delay Match
-20
0.0
+20
ns
(43)
tDUR
Thermal Filter Duration
8.0
–
30
µs
(44)
tDC
Duty Cycle
0.0
–
96
%
(45), (46)
tDC
100% Duty Cycle Duration
–
–
Unlimited
s
(45), (46)
tMAX
Maximum Programmable Deadtime
10.2
15
19.6
µs
(47)
GATE DRIVE (CONTINUED)
tD_DIFF
OVERCURRENT COMPARATOR
tOC
Overcurrent Protection Filter Time
0.9
–
3.5
µs
tROC
Rise Time (OC_OUT)
• 10% - 90%
• CL = 100 pF
10
–
240
ns
tFOC
Fall Time (OC_OUT)
• 90% - 10%
• CL = 100 pF
10
–
200
ns
–
–
–
–
200
350
ns
–
–
100
ns
(45)
DESATURATION DETECTOR AND PHASE COMPARATOR
tR
tF
Phase Comparator Propagation Delay Time to 50% of VDD;
CL ≤ 100 pF
• Rising Edge Delay
• Falling Edge Delay
tMATCH
Phase Comparator Match (Prop Delay Mismatch of Three Phases)
• CL = 100 pF
tBLANK
Desaturation and Phase Error Blanking Time
4.7
7.1
9.1
µs
(48)
Desaturation Filter Time (Filter Time is digital)
• Fault Must be Present for This Time to Trigger
640
937
1231
ns
(45)
–
1.0
2.0
µs
(45), (49)
tFILT
CURRENT SENSE AMPLIFIER
tSETTLE
Output Settle Time to 99%
• RL = 1.0 kΩ, CL = 500 pF, 0.3 V < VO < 4.8 V, Gain = 5 to 15
Notes
43. The maximum separation or overlap of the High and Low-side gate drives, due to propagation delays when commanding one ON and the other
OFF simultaneously, is guaranteed by design.
44. The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
45. This parameter is guaranteed by design, not production tested.
46. As duty cycle approaches the limit of 100% or 0% there is a maximum and minimum which is not achievable due to deadtime, propagation delays,
switching times and charge time of the bootstrap capacitor (for the High-side FET). 0% is available by definition (FET always OFF) and unlimited
ON (100%) is possible as long as gate charge maintenance current is within the trickle charge pump capacity.
47. A Minimum Deadtime of 0.0 can be set via an SPI command. When Deadtime is set via a DEADTIME command, a minimum of 1 clock cycle
duration and a maximum of 255 clock cycles is set using the internal time base clock as a reference. Commands exceeding this value limits at this
value.
48. Blanking time, tBLANK, is applied to all phases simultaneously when switching ON any output FET. This precludes false errors due to system noise
during the switching event.
49. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
CURRENT SENSE AMPLIFIER (CONTINUED)
tIS_RISE
Output Rise Time to 90%
• RL = 1.0 kΩ, CL = 500 pF, 0.3 V < VO < 4.8 V, Gain = 5.0 to 15
–
–
1.0
µs
(51)
tIS_FALL
Output Fall Time to 10%
• RL = 1.0 kΩ, CL = 500 pF, 0.3 V < VO < 4.8 V, Gain = 5.0 to 15
–
–
1.0
µs
(51)
SR(5)
Slew Rate at Gain = 5.0
• RL = 1.0 kΩ, CL = 20 pF
5.0
–
–
V/µs
(50)
fM
Phase Margin at Gain = 5.0
–
30
–
°
(50)
GBW
Unity Gain Bandwidth
• RL = 1.0 kΩ, CL = 100 pF
–
20
–
MHz
(50)
BWG
Bandwidth at Gain = 15
• RL = 1.0 kΩ, CL = 50 pF
–
–
MHz
(50)
2.0
dB
(50)
Common Mode Rejection (CMR) with VIN
• VIN_CM = 400 mV*sin(2*π*freq*t)
CMR
• VIN_DIF = 0.0 V, RS = 1.0 kΩ
• RFB = 15 kΩ, VREFIN = 0.0 V
CMR = 20*Log(VOUT/VIN_CM)
• Freq = 100 kHz
• Freq = 1.0 MHz
• Freq = 10 MHz
50
40
30
–
–
–
–
–
–
SUPERVISORY AND CONTROL CIRCUITS
tPROP
EN1 and EN2 Propagation Delay
–
–
280
ns
tRINT
INT Rise Time CL = 100 pF
10
–
250
ns
tFINT
INT Fall Time CL = 100 pF
10
–
200
ns
INT Propagation Time
–
–
250
ns
RST Transition Time (Rise and Fall)
–
–
1.25
µs
tPROPINT
tTRRST
(50),(52)
Notes
50. This parameter is guaranteed by design, not production tested.
51. Rise and fall times are measured from the transition of a step function on the input to 90% of the change in output voltage.
52. tTRRST is given as a design guideline. The bounds for this specification are VPWR ≤ 58 V, total capacitance on VLS > 1.0 µF.
33937A
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, - 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
4.0
MHz
Notes
SPI INTERFACE TIMING
fOP
Maximum Frequency of SPI Operation
–
fTB
Internal Time Base
13
17
25
MHz
TCTB
Internal Time Base drift from value at 25 °C
-5.0
–
5.0
%
(53)
tLEAD
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
100
–
–
ns
(53)
tLAG
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
100
–
–
ns
(53)
tSISU
SI to Falling Edge of SCLK (Required Setup Time)
25
–
–
ns
(53)
tSIHOLD
Falling Edge of SCLK to SI (Required Setup Time)
25
–
–
ns
(53)
tRSI
SI, CS, SCLK Signal Rise Time
–
5.0
–
ns
(53), (54)
tFSI
SI, CS, SCLK Signal Fall Time
–
5.0
–
ns
(53), (54)
tSOEN
Time from Falling Edge of CS to SO Low-impedance
–
55
100
ns
(53), (55)
tSODIS
Time from Rising Edge of CS to SO High-impedance
–
100
125
ns
(53), (56)
tVALID
Time from Rising Edge of SCLK to SO Data Valid
–
80
125
ns
(53), (57)
200
–
–
ns
(53)
tDT
Notes
53.
54.
55.
56.
57.
4.4
Time from Rising Edge of CS to Falling Edge of the next CS
This parameter is guaranteed by design, not production tested.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
Timing diagrams
CS
0.2 VDD
tL EA D
SCLK
ttLAG
LA G
0 .7 VD D
0 .2 VD D
tDI(S
U) tSIHOLD
DI(HO LD)
tSISU
0 .7 VD D
0 .2 VD D
SI
MSB in
tSOEN
tDO(E
N)
SO
tV A LI D
0 .7 VD D
0 .2 VD D
MSB out
tSODIS
tDO
(DIS )
LSB out
Figure 4. SPI Interface Timing
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
PX_HS
PX_LS
DESATURATION
FAULT
FROM DELAY
TIMER
Figure 5. Desaturation Blanking and Filtering Detail
B
PX_HS
D
STATE
MACHINE
Q
CLK
MUX
D
Q
A OUT
D
CLK
Q
PX_HS_G
CLK
DEADTIME
CONTROL
PX_LS
D
Q
1ST PULSE
PX_HS_S
D
D
CLK
CLK
Q
CLK
Q
PX_LS_G
A OUT
MUX
B
EN1
EN2
RST
Figure 6. Deadtime Control Delays
50%
Px_HS
10V
tD_ONH
Px_HS _G
tONH
1 .0 V
50%
Px_LS
10V
Px_LS_G
tD_ONL
1.0V
tONL
Figure 7. Driver Turn-on Time and Turn-on Delay
33937A
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
50%
Px_HS
10V
tD_OFFH
Px_HS_G
1 .0 V tOFFH
50%
Px_ LS
1 0V
tD_OFFL
Px_LS_G
1.0V tOFFL
Figure 8. Driver Turn-off Time and Turn-off Delay
RE F
R FB P
To P rotection Circuits
AMP_P
+
V ID
AMP_N
OC_TH
Rs
+
V IN
-
R sens e
Rs
AMP_O UT
R FBN
-400mV to + 400mV
-400mV to + 400mV
0V
0V
0μS - 0.5μS
0.5μS - 50μS
0.5μS - 50μS
Figure 9. Current Amplifier and Input Waveform (VIN Voltage Across RSENSE)
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
Phase (degrees)
Gain (db)
Phase
Gain
Figure 10. Typical Amplifier Open-loop Gain and Phase vs. Frequency
TypicalHighSide100%OnGateVoltagewith5PAGateLoad
16
VSUP =40V
14
VSUP =24V
12
VSUP =14V
VCBOOTVHS_S (V)
10
VSUP =9V
8
6
4
2
0
50
30
10
10
30
50
70
90
110
130
150
Temperature(°C)
Figure 11. Typical High-side 100% On Gate Voltage with 5.0 µA Gate Load
33937A
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
Functional Descriptions
5.1
Introduction
The 33937A provides an interface between an MCU and the large FETs used to drive three phase loads. A typical load FET may have
an on resistance of 4.0 mΩ or less and could require a gate charge of over 400 nC to fully turn on. The IC can operate in automotive 12 V
to 42 V environments.
Because there are so many methods of controlling three phase systems, the IC enforces few constraints on driving the FETs. It does
provide deadtime (cross-over) blanking and logic, both of which can be overridden, ensuring both FETs in a phase are not simultaneously
enabled. A SPI port is used to configure the IC modes.
5.2
Functional Pin Description
5.2.1
Phase A (PHASEA)
This pin is the totem pole output of the Phase A comparator. This output is low when the voltage on Phase A high-side source (source of
the high-side load FET) is less than 50 percent of VSUP.
5.2.2
Power Ground (PGND)
This pin is power ground for the charge pump. It should be connected to VSS, however routing to a single point ground on the PCB may
help to isolate charge pump noise.
5.2.3
Enable 1 and Enable 2 (EN1, EN2)
Both of these logic signal inputs must be high to enable any gate drive output. When either or both are low, the internal logic (SPI port,
etc.) still functions normally, but all gate drives are forced off (external power FET gates pulled low). The signal is asynchronous.
When EN1 and EN2 return high to enable the outputs, each LS driver must be pulsed ON before the corresponding HS driver can be
commanded ON. This ensures that the bootstrap capacitors are charged. See 7.3, Initialization Requirements on page 41.
5.2.4
Reset (RST)
When the reset pin is low the integrated circuit (IC) is in a low power state. In this mode, all outputs are disabled, internal bias circuits are
turned off, and a small pull-down current is applied to the output gate drives. The internal logic will be reset within 77 ns of RESET going
low. When RST is low, the IC consumes minimal current.
5.2.5
Charge Pump Out (PUMP)
This pin is the switching node of the charge pump circuit. The output of the internal charge pump support circuit. When the charge pump
is used, it is connected to the external pumping capacitor. This pin may be left floating if the charge pump is not required.
5.2.6
Charge Pump Input (VPUMP)
This pin is the input supply for the charge pump circuit. When the charge pump is required, this pin should be connected to a polarity
protected supply. This input should never be connected to a supply greater than 40 V. If the charge pump is not required this pin may be
left floating.
5.2.7
VSUP Input (VSUP)
The supply voltage pin should be connected to the common connection of the high-side FETs. It is the reference bias for the Phase
Comparators and Desaturation Comparator. It is also used to provide power to the internal steady state trickle charge pump and to
energize the hold off circuit.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
5.2.8
Phase B (PHASEB)
This pin is the totem pole output of the Phase B comparator. This output is low when the voltage on Phase B high-side source (source of
the high-side load FET) is less than 50 percent of VSUP.
5.2.9
Phase C (PHASEC)
This pin is the totem pole output of the Phase C comparator. This output is low when the voltage on Phase C high-side source (source of
the high-side load FET) is less than 50 percent of VSUP.
5.2.10 Phase A High-side Input (PA_HS)
This input logic signal pin enables the high-side driver for Phase A. The signal is active low, and is pulled up by an internal current source.
5.2.11 Phase A Low-side Input (PA_LS)
This input logic signal pin enables the low-side driver for Phase A. The signal is active high, and is pulled down by an internal current sink.
5.2.12 VDD Voltage Regulator (VDD)
VDD is an internally generated 5.0 V supply. The internal regulator provides continuous power to the IC and is a supply reference for the
SPI port. A 0.47 µF (min) decoupling capacitor must be connected to this pin. This regulator is intended for internal IC use and can supply
only a small (1.0 mA) external load current. A power-on-reset (POR) circuit monitors this pin and until the voltage rises above the threshold,
the internal logic will be reset; driver outputs are tri-stated and SPI communication is disabled. The VDD regulator can be disabled by
asserting the RST signal low. The VDD regulator is powered from the VPWR pin.
5.2.13 Phase B High-side Control Input (PB_HS)
This pin is the input logic signal, enabling the high-side driver for Phase B. The signal is active low, and is pulled up by an internal current
source.
5.2.14 Phase B Low-side Input (PB_LS)
This pin is the input logic signal, enabling the low-side driver for Phase B. The signal is active high, and is pulled down by an internal current
sink.
5.2.15 Interrupt (INT)
The Interrupt pin is a totem pole logic output. When a fault is detected, this pin pulls high until it is cleared by executing the Clear Interrupt
command via the SPI port. The faults capable of causing an interrupt can be masked via the MASK0 and MASK1 SPI registers to
customize the response.
5.2.16 Chip Select (CS)
Chip select is a logic input that frames the SPI commands and enables the SPI port. This signal is active low, and is pulled up by an internal
current source.
5.2.17 Serial In (SI)
The Serial In pin is used to input data to the SPI port. Clocked on the falling edge of SCLK, it is the most significant bit (MSB) first. This
pin is pulled down by an internal current sink.
33937A
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
5.2.18 Serial Clock (SCLK)
This logic input is the clock is used for the SPI port. The SCLK typically runs at 3.0 MHz (up to 5.0 MHz) and is pulled down by an internal
current sink.
5.2.19 Serial Out (SO)
Output data for the SPI port streams from this pin. It is tri-stated until CS is low. New data appears on rising edges of SCLK in preparation
for latching by the falling edge of SCLK on the master.
5.2.20 Phase C Low-side Input (PC_LS)
This input logic pin enables the low-side driver for Phase C. This pin is an active high, and is pulled down by an internal current sink.
5.2.21 Phase C High-side Input (PC_HS)
This input logic pin enables the high-side driver for Phase C. This signal is active low, and is pulled up by an internal current source.
5.2.22 Amplifier Output (AMP_OUT)
This pin is the output for the current sensing amplifier. It is also the sense input to the overcurrent comparator.
5.2.23 Amplifier Inverting Input (AMP_N)
The inverting input to the current sensing amplifier.
5.2.24 Amplifier Non-Inverting Input (AMP_P)
The non-inverting input to the current sensing amplifier.
5.2.25 Overcurrent Comparator Output (OC_OUT)
The overcurrent comparator output is a totem pole logic level output. A logic high indicates an overcurrent condition.
5.2.26 Overcurrent Comparator Threshold (OC_TH)
This input sets the threshold level of the overcurrent comparator.
5.2.27 Voltage Source Supply (VSS)
VSS is the ground reference for the logic interface and power supplies.
5.2.28 Ground (GND0, GND1)
These two pins are connected internally to VSS by a 1.0 Ω resistor. They provide device substrate connections and also the primary return
path for ESD protection.
5.2.29 VLS Regulator Capacitor (VLS_CAP)
This connection is for a capacitor which provides a low-impedance for switching currents on the gate drive. A low ESR decoupling
capacitor, capable of sourcing the pulsed drive currents must be connected between this pin and VSS. This is the same DC node as VLS,
but it is physically placed on the opposite end of the IC to minimize the source impedance to the gate drive circuits.
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Freescale Semiconductor
23
5.2.30 Phase C Low-side Source (PC_LS_S)
The phase C low-side source is the pin used to return the gate currents from the low-side FET. Best performance is realized by connecting
this node directly to the source of the low-side FET for phase C.
5.2.31 Phase C Low-side Gate (PC_LS_G)
This is the gate drive for the Phase C low-side output FET. It provides high-current through a low-impedance to turn on and off the lowside FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the
external FET. This output has also been designed to resist the influence of negative currents.
5.2.32 Phase C High-side Source (PC_HS_S)
The source connection for the Phase C high-side output FET is the reference voltage for the gate drive on the high-side FET and also the
low-voltage end of the bootstrap capacitor.
5.2.33 Phase C High-side Gate (PC_HS_G)
This is the gate drive for the Phase C high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate
voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome
an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of
negative currents.
5.2.34 Phase C Bootstrap (PC_BOOT)
This is the bootstrap capacitor connection for Phase C. A capacitor connected between PC_HS_S and this pin provides the gate voltage
and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage
across this capacitor is limited to about 15 V.
5.2.35 Phase B Low-side Source (PB_LS_S)
The Phase B low-side source is the pin used to return the gate currents from the Low-side FET. Best performance is realized by connecting
this node directly to the source of the low-side FET for Phase B.
5.2.36 Phase B Low-side Gate (PC_LS_G)
This is the gate drive for the Phase B low-side output FET. It provides high-current through a low-impedance to turn on and off the lowside FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the
external FET. This output has also been designed to resist the influence of negative currents.
5.2.37 Phase B High-side Source (PB_HS_S)
The source connection for the Phase B high-side output FET is the reference voltage for the gate drive on the high-side FET and also the
low-voltage end of the bootstrap capacitor.
5.2.38 Phase B High-side Gate (PB_HS_G)
This is the gate drive for the Phase B high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate
voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome
an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of
negative currents.
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Analog Integrated Circuit Device Data
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5.2.39 Phase B Bootstrap (PB_BOOT)
This is the bootstrap capacitor connection for phase B. A capacitor connected between PC_HS_S and this pin provides the gate voltage
and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage
across this capacitor is limited to about 15 V.
5.2.40 PHASE A Low-side Source (PA_LS_S)
The Phase A low-side source is the pin used to return the gate currents from the low-side FET. Best performance is realized by connecting
this node directly to the source of the low-side FET for phase A.
5.2.41 Phase A Low-side Gate (PA_LS_G)
This is the gate drive for the Phase A low-side output FET. It provides high-current through a low-impedance to turn on and off the lowside FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the
external FET. This output has also been designed to resist the influence of negative currents.
5.2.42 Phase A High-side Source (PA_HS_S)
The source connection for the Phase A high-side output FET is the reference voltage for the gate drive on the high-side FET and also the
low-voltage end of the bootstrap capacitor.
5.2.43 Phase A High-side Gate (PA_HS_G)
This is the gate drive for the Phase A high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate
voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not
overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the
influence of negative currents.
5.2.44 Phase A Bootstrap (PA_BOOT)
This is the bootstrap capacitor connection for phase A. A capacitor connected between PC_HS_S and this pin provides the gate voltage
and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage
across this capacitor is limited to about 15 V.
5.2.45 VLS Regulator (VLS)
VLS is the gate drive power supply regulated at approximately 15 V. This is an internally generated supply from VPWR. It is the source
for the low-side gate drive voltage, and also the high-side bootstrap source. A low ESR decoupling capacitor, capable of sourcing the
pulsed drive currents, must be connected between this pin and VSS.
5.2.46 VPWR Input (VPWR)
VPWR is the power supply input for VLS and VDD. Current flowing into this input recharges the bootstrap capacitors as well as supplying
power to the low-side gate drivers and the VDD regulator. An internal regulator regulates the actual gate voltages. This pin can be
connected to system battery voltage if power dissipation is not a concern.
5.2.47 Exposed Pad (EP)
The primary function of the exposed pad is to conduct heat out of the device. This pad may be connected electrically to the substrate of
the device.The device performs as specified with the exposed pad un-terminated (floating). However, it is recommended the exposed pad
be terminated to pin 29 (VSS) and the system ground.
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Freescale Semiconductor
25
6
Functional Internal Block Description
MC33937 - Functional Block Diagram
Integrated Supply
Main Charge Pump
5V Regulator
Trickle Charge Pump
VLS Regulator
Sensing & Protection
Hold-off
Under-voltage
Temperature
De-sat
Current Sense
Phase
Over-current
High Side
and
Low Side
Output
Pre-drivers
Logic & Control
Fault Register
Dead Time
Phase Control
Mode Control
SPI Communication
Integrated Supply
Sensing & Protection
Logic & Control
Drivers
Figure 12. Functional Internal Block Description
All functions of the IC can be described as the following five major functional blocks:
• Logic Inputs and Interface
• Bootstrap Supply
• Low-side Drivers
• High-side Drivers
• Charge Pump
6.1
Logic Inputs and Interface
This section contains the SPI port, control logic, and shoot-through timers.
The IC logic inputs have Schmitt trigger inputs with hysteresis. Logic inputs are 3.0 V compatible. The logic outputs are driven from the
internal supply of approximately 5.0 V. The SPI registers and functionality is described completely in 7.2, Logic Commands and Registers
on page 35. SPI functionality includes the following:
• Programming of deadtime delay—This delay is adjustable in approximately 50 ns steps from 0 ns to 12 µs. Calibration of the delay,
because of internal IC variations, is performed via the SPI.
• Enabling of simultaneous operation of high-side and low-side FETs—Normally, both FETs would not be enabled simultaneously.
However, for certain applications where the load is connected between the high-side and low-side FETs, this could be advantageous.
If this mode is enabled, the blanking time delay will be disabled. A sequence of commands may be required to enable this function to
prevent inadvertent enabling. In addition, this command can only be executed once after reset to enable or disable simultaneous turnon.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
• Setting of various operating modes of the IC and enabling of interrupt sources. The 33937A allows different operating modes to be
set and locked by an SPI command (FULLON, Desaturation Fault, Zero Deadtime). SPI commands can also determine how the various
faults are (or are not) reported.
• Read back of internal registers. The status of the 33937A status registers can be read back by the Master (DSP or MCU).
The Px_HS and Px_LS logic inputs are edge sensitive. This means the leading edge on an input causes the complementary output to
immediately turn off and the selected one to turn on after the deadtime delay as illustrated in Figure 13. The deadtime delay timer always
starts at the time a FET is commanded off and prevents the complementary FET from being commanded on until after the deadtime has
elapsed. Commands to turn on the complementary FET after the deadtime has elapsed are executed immediately without any further
delay (see Figure 6 and Figure 13).
PA _HS
PA_LS
De adt ime
De lay
PA_HS_G
PA_LS_G
Figure 13. Edge Sensitive Logic Inputs (Phase A)
6.1.1
Low-side and Bootstrap Supply (VLS)
This is the portion of the IC providing current to recharge the bootstrap capacitors. It also supplies the peak currents required for the lowside gate drivers. The power for the gate drive circuits is provided by VLS which is supplied from the VPWR pin. This pin can be connected
to system battery voltage and is capable of withstanding up to the full load dump voltage of the system. However, the IC only requires a
low-voltage supply on this pin, typically 13 V to 16 V. Higher voltages on this pin increases the IC power dissipation.
In 12 V systems, the supply voltage can fall as low as 6.0 V. This limits the gate voltage capable of being applied to the FETs and reduces
system performance due to the higher FET on-resistance. To allow a higher gate voltage to be supplied, the IC also incorporates a charge
pump. The switches and control circuitry are internal; the capacitors and diodes are external (see Figure 22).
6.1.2
Low-side Drivers
These three drivers turn on and off the external Low-side FETs. The circuits provide a low-impedance drive to the gate, ensuring the FETs
remain off in the presence of high dV/dt transients on their drains. Additionally, these output drivers isolate the other portions of the IC
from currents capable of being injected into the substrate due to rapid dV/dt transients on the FET drains.
Low-side drivers switch power from VLS to the gates of the Low-side FETs. The Low-side drivers are capable of providing a typical peak
current of 2.0 A. This gate drive current may be limited by external resistors in order to achieve a good trade-off between the efficiency
and EMC (Electro-Magnetic Compatibility) compliance of the application. the low-side driver uses high-side PMOS for turn on and lowside isolated LDMOS for turn off. The circuit ensures the impedance of the driver remains low, even during periods of reduced current.
Current limit is blanked immediately after subsequent input state change to ensure device stays off during dV/dt transients.
6.1.3
High-side Drivers
These three drivers switch the voltage across the bootstrap capacitor to the external high-side FETs. The circuits provide a low-impedance
drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their sources. Further, these output drivers
isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FETs.
The high-side drivers deliver power from their bootstrap capacitor to the gate of the external high-side FET, thus turning the high-side FET
on. The high-side driver uses a level shifter, allowing the gate of the external high-side FET to be turned off by switching to the high-side
FET source.
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Freescale Semiconductor
27
The gate supply voltage for the high-side drivers is obtained from the bootstrap supply, so, a short time is required after the application of
power to the IC to charge the bootstrap capacitors. To ensure this occurrence, the internal control logic does not allow a high-side switch
to be turned on after entering the ENABLE state until the corresponding low-side switch is enabled at least once. Caution must be
exercised after a long period of inactivity of the low-side switches to verify the bootstrap capacitor is not discharged. It is charged by
activating the low-side switches for a brief period, or by attaching external bleed resistors from the HS_S pins to GND. See 7.3, Initialization
Requirements on page 41.
In order to achieve a 100% duty cycle operation of the high-side external FETs, a fully integrated trickle charge pump provides the charge
necessary to maintain the external FET gates at fully enhanced levels. The trickle charge pump has limited ability to supply external
leakage paths while performing it’s primary function. The graph in Figure 11 shows the typical margin for supplying external current loads.
These limits are based on maintaining the voltage at CBOOT at least 3.0 V greater than the voltage on the HS_S for that phase. If this
voltage differential becomes less than 3.0 V, the corresponding high-side FET most likely does not remain fully enhanced and the highside driver may malfunction due to insufficient bias voltage between CBOOT and HS_S.
The slew rate of the external output FET is limited by the driver output impedance, overall (external and internal) gate resistance and the
load capacitance. To ensure the low-side FET is not turned on by a large positive dV/dt on the drain of the low-side FET, the turn-on slew
rate of the high-side should be limited. If the slew rate of the high-side is limited by the gate-drain capacitance of the high-side FET, then
the displacement current injected into the low-side gate drive output is approximately the same value. Therefore, to ensure the low-side
drivers can be held off, the voltage drop across the low-side gate driver must be lower than the threshold voltage of the low-side FET (see
Figure 14).
Similarly, during large negative dV/dt, the high-side FET is able to remain off if its gate drive low-side switch, develops a voltage drop less
than the threshold voltage of the high-side FET. The gate drive low-side switch discharges the gate to the source. Additionally, during
negative dV/dt the low-side gate drive could be forced below ground. The low-side FETs must not inject detrimental substrate currents in
this condition. The occurrence of these cases depends on the polarity of the load current during switching.
33937A
33927
Px_HS_S
VLS
LS
Control
Phase x
Output
Low
-Side
Driver
Zo
D
Discrete
FET
Package
CDG
iCDG
G
Px_LS_G
-
+
CDS
Rg
CGS
S
Px_LS_S
Phase
Return
Px_HS_G
Deadtime
Px_LS_G
Phase x Output Voltage
VSUP
dV/dt
-VD
Figure 14. Positive DV/dt Transient
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Analog Integrated Circuit Device Data
Freescale Semiconductor
6.1.4
Driver Fault Protection
The 33937A IC integrates several protection mechanisms against various faults. The first of them is the current sense amplifier with the
overcurrent comparator. These two blocks are common for all three driver phases.
6.1.4.1
Current Sense Amplifier
This amplifier is usually connected as a differential amplifier (see Figure 9). It senses a current flowing through the external FETs as a
voltage across the current sense resistor RSENSE. Since the amplifier common mode range does not extend below ground, it is necessary
to use an external reference to permit measuring both positive and negative currents. The amplifier output can be monitored directly (e.g.
by the microcontroller’s ADC) at the AMP_OUT pin, providing the means for closed loop control with the 33937A. The output voltage is
internally compared with the overcurrent comparator threshold voltage (see Figure 22).
6.1.4.2
Overcurrent Comparator
The amplified voltage across RSENSE is compared with the pre-set threshold value by the overcurrent comparator input. If the current
sense amplifier output voltage exceeds the threshold of the overcurrent comparator, it would change the status of its output (OC_OUT
pin) and the fault condition would be latched (see 7.2.3.2Figure 18).
The occurrence of this fault would be signalled by the return value of the Status Register 0. If the proper interrupt mask has been set, this
fault condition generates an interrupt - the INT pin asserts High. The INT is held in the High state until the fault is removed, and the
appropriate bit in the Status Register 0 is cleared by the CLINT0 command. This fault reporting technique is described in detail in 7.2,
Logic Commands and Registers on page 35.
6.1.4.3
Desaturation Detector
The Desaturation Detector is a comparator integrated into the output driver of each phase channel. It provides an additional means to
protect against “Short-to-Ground” fault condition. A short to ground is detected by an abnormally high-voltage drop in VDS of the highside FET. Note that if the gate-source voltage of the high-side FET drops below saturation, the device goes into linear mode of conduction,
which can also cause a desaturation error.
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VSUP
VLS
3x
T-Lim
VSUP
High Px_BOOT
-Side
Driver
HS
Control
Px_HS_G
+
-
Desat.
Comp.
1.4V
Phase x
Output
Px_HS_S
Phase
Comp.
LS
Control
R
Phase x Output
Shorted to Ground
(Low-Side
FET Shorted)
Low
-Side
Driver
VSUP
Px_LS_G
R
Px_LS_S
To Current
Sense Amplif.
VLS_CAP
Px_HS_G
Phase
Return
RSense
tBLANK
Deadtime
tFILT
Px_LS_G
V SUP
Correct Phase x Output Voltage
0.5V SUP
Phase x Output
Voltage Shorted to Ground
-V D
Correct
PHASEx
Fault
Phase Error
Desaturation Error
Figure 15. Short to Ground Detection
When switching from low-side to high-side, the high-side is commanded ON after the end of the deadtime. The deadtime period starts
when the low-side is commanded OFF. If the voltage at Px_HS_S is less than 1.4 V below VSUP after the blanking time (tBLANK), a
desaturation fault is initiated. An additional 1.0 μs digital filter is applied from the initiation of the desaturation fault before it is registered,
and all phase drivers are turned OFF (Px_HS_G clamped to Px_HS_S and Px_LS_G clamped to Px_LS_S). If the desaturation fault
condition clears before the filter time expires, the fault is ignored and the filter timer resets.
Valid faults are registered in the fault status register, which can be retrieved by way of the SPI. Additional SPI commands mask the INT
flag and disable an output stage shutdown, due to desaturation and phase errors. See 7.2, Logic Commands and Registers on page 35
for details on masking INT behavior and disabling the protective function.
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Analog Integrated Circuit Device Data
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V SUP
VLS
3x
T-Lim
VSUP
Desat.
Comp.
High Px_BOOT
-Side
Driver
HS
Control
+
-
1. 4V
Px_HS_S
LS
Control
R
Phase x
Output
Low
-Side
Driver
VSUP
Phase
Comp.
Phase x Output
Shorted to VSUP
(High-Side
FET Shorted)
Px_HS_G
Px_LS_G
R
Px_LS_S
To Current
Sense Amplif.
VLS_CAP
Phase
Return
RSense
Px_HS_G
Deadtime
tBLANK
Px_LS_G
VSUP
Phase x Output Voltage Shorted to VSUP
0.5VSUP
Correct Phase x Output Voltage
-VD
Fault
PHASEx
Correct
Phase Error
Figure 16. Short to Supply Detection
6.1.4.4
Phase Comparator
Faults could also be detected as phase errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the
drive conditions.
A phase error is detected by a Phase comparator. The Phase comparator compares the voltage at the Px_HS_S node with a reference
of one half the voltage at the VSUP pin. A high-side phase error (which also triggers the Desaturation Detector) occurs when the highside FET is commanded on, and Px_HS_S is still low at the end of the deadtime and blanking time duration. Similarly, a LS phase error
occurs when the low-side FET is commanded on, and the Px_HS_S is still high at the end of the deadtime and blanking time duration.
The Phase Error flag is the triple OR of phase errors from each phase. Each phase error is the OR of the high-side and low-side phase
errors. This flag can generate an interrupt if the appropriate mask bit is set. The INT is held in the high state until the fault is removed, and
the appropriate bit in the Status Register 0 is cleared by the CLINT1 command. This fault reporting mechanism is described in detail in
7.2, Logic Commands and Registers on page 35.
6.1.5
VLS Undervoltage
Since VLS supplies both the gate driver circuits and the gate voltage, it is critical it maintains sufficient potential to place the power stage
FETs in saturation. Since proper operation cannot continue with insufficient levels, a low VLS condition shuts down driver operation. The
VLS undervoltage threshold is between 7.5 V and 8.5 V. When a decreasing level reaches the threshold, both the HS and the LS output
gate circuit drive the gates OFF for about 8.0 μs before reducing the drive to hold off levels. Since low VLS is a condition for turning on
the Hold Off circuit, Hold Off then provides a weak pull-down on all gates. A filter timeout of about 700 ns insures noise on VLS does not
cause premature protective action.
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31
When VLS rises above this threshold again, the LS Gate immediately follows the level of the input. However, a short initialization sequence
must be executed to restore operation of the HS Gate. (See 7.3, Initialization Requirements on page 41) Since VLS is no longer
undervoltage, the Hold Off circuit is turned off and the HS Gate is in a high-impedance state until the LS Gate responds to an input
command to turn off.
6.1.6
Hold Off Circuit
The IC guarantees the output FETs are turned off in the absence of VDD or VPWR by means of the Hold off circuit. A small current source,
generated from VSUP, typically 100 µA, is mirrored and pulls all the output gate drive pins low when VDD is less than about 3.0 V, RST is
active (low), or when VLS is lower than the VLS_Disable threshold. A minimum of 3.0 V is required on VSUP to energize the Hold off circuit.
6.1.7
Charge Pump
The charge pump circuit provides the basic switching elements required to implement a charge pump, when combined with external
capacitors and diodes for enhanced low-voltage operation. When the 33937A is connected per the typical application using the charge
pump (see Figure 22), the regulation path for VLS includes the charge pump and a linear regulator. The regulation set point for the linear
regulator is nominally at 15.34 V. As long as VLS output voltage (VLSOUT) is greater than the VLS analog regulator threshold (VLSATH)
minus VTHREG, the charge pump is not active.
If VLSOUT < VLSATH – VTHREG the charge pump turns ON until VLSOUT > VLSATH – VTHREG + VHYST
VHYST is approximately 200 mV. VLSATH does not interfere with this cycle even when there is overlap in the thresholds, due to the design
of the regulator system. The maximum current the charge pump can supply is dependent on the pump capacitor value and quality, the
pump frequency (nominally 130 kHz), and the RDS(on) of the pump FETs. The effective charge voltage for the pump capacitor would be
VSYS – 2 * VDIODE. The total charge transfer would then be CPUMP * (VSYS – 2*VDIODE). Multiplying by the switch frequency gives the
theoretical current the pump can transfer: FPUMP * CPUMP * (VSYS – 2*VDIODE).
NOTE: There is also another smaller, fully integrated charge pump (Trickle Charge Pump - see Figure 2), which is used to maintain the
high-side drivers’ gate VGS in 100 percent duty cycle modes.
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7
Functional Device Operation
7.1
Operational Modes
7.1.1
Reset and Enable
The 33937A has three power modes of operation described in Table 6. There are three global control inputs (RST, EN1, EN2), which
together with the status of VDD, VLS, and DESAT/PHASE faults control the behavior of the IC.
The operating status of the IC can be described by the following five modes:
• Sleep Mode - When RST is low, the IC is in Sleep mode. The current consumption of the IC is at minimum.
• Standby Mode - The RST input is high while one of the Enable inputs is low. The IC is fully biased up and operating, all the external
FETs are actively turned off by both high-side and low-side gate drives. The IC is ready to enter the Enable mode.
• Initialization Mode - When EN1, EN2, and RST all go high, the device enters the Initialization mode. Toggling the LS and then the HS
initializes the driver and normal operation in the Enable mode begins. (See 7.3, Initialization Requirements on page 41)
• Enable Mode - After initialization is complete, the device goes into the Enable mode and operates normally. Normal operation
continues in this mode as long as both enable pins and RST are high.
• Fault Protection Mode - If a protective fault occurs (either Desat/Phase or VLS UV) the device enters a Fault Protection mode. After
a fault clears, the device requires initialization again before resuming normal Enable mode operation.
Table 6. Functions of RST, EN1, and EN2 Pins
RST
EN1,
EN2
Mode of Operation (Driver Condition)
0
xx
Sleep Mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error and SPI
registers are cleared. The internal 5.0 V regulator is turned off and VDD is pulled low. All logic outputs except SO are clamped to VSS.
1
0x
x0
Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external FETs (after
initialization). The SPI port is functional. Logic level outputs are driven with low-impedance. SO is high-impedance unless CS is low.
VDD, Charge Pump and VLS regulators are all operating. The IC is ready to move to Enable mode.
Initialization Mode - Low-side drivers are enabled, SPI is fully operational. Ready for initialization (See 7.3, Initialization
Requirements on page 41).
1
11
Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs require a pulse
on Px_LS before corresponding HS outputs are turn on to charge the bootstrap capacitor. All error pins and register bits are active if
detected.
Fault Protection Mode - Drivers are turned OFF or disabled per the fault and protection mode registers. Recovery requires
initialization (See 7.3, Initialization Requirements on page 41).
Table 7. Functional Ratings
(TJ = -40 °C to 150 °C and supply voltage range VSUP = VPWR = 5.0 V to 45 V, C = 0.47 µF)
Characteristic
Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open (58)
(Driver output is switched off, high-impedance mode)
Default State of input pin Px_HS, CS if left open (58)
(Driver output is switched off, high-impedance mode)
Value
Low (<1.0 V)
High (>2.0 V)
Notes
58. To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.
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Freescale Semiconductor
33
Sleep Mode
Sleep
Y
RST
N
Standby Mode
STBY
Initialization
N
EN
ENABLE LS
Y
Enable (Normal) Mode
N
LS Toggle
Y
HS Toggle
ENABLE
Y
HS
N
DESAT
Disabled
Fault Protection
N
DESAT/
PHASE
Driver OFF
Y
VLS UV
DESAT/
PHASE
N
Y
N
Y
N
Disable Driver
Holdoff Active
Driver OFF
Y
VLS UV
N
Y
EN
N
Y
Y
RST
N
Figure 17. Device Operational Flow Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
7.2
Logic Commands and Registers
7.2.1
Command Descriptions
The IC contains internal registers to control the various operating parameters, modes, and interrupt characteristics. These commands are
sent and status is read via 8-bit SPI commands. The IC uses the last eight bits in a SPI transfer, so devices can be daisy-chained. The
first three bits in an SPI word can be considered to be the Command with the trailing five bits being the data. The SPI logic generates a
framing error and ignores the SPI message if the number of received bits is not eight or not a multiple of eight. After RST, the first SPI
result returned is Status Register 0.
Table 8. Command List
Command
Name
Description
000x xxxx
NULL
These commands are used to read IC status. These commands do not change any internal IC status. Returns Status
Register 0-3, depending on sub command.
0010 xxxx
MASK0
Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation for this flag.
INT remains asserted if uncleared faults are still present. Returns Status Register 0.
0011 xxxx
MASK1
Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation for this flag.
INT remains asserted if uncleared faults are still present. Returns Status Register 0.
010x xxxx
Mode
Enables Desat/Phase Error mode. Enables FULLON mode. Locks further mode changes. Returns Status Register 0.
0110 xxxx
CLINT0
Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears the interrupt
latch for this flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0.
0111 xxxx
CLINT1
Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears the interrupt
latch for this flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0.
100x xxxx
DEADTIME
7.2.2
Set deadtime with calibration technique. Returns Status Register 0.
Fault Reporting and Interrupt Generation
Different fault conditions described in the previous chapters can generate an interrupt - INT pin output signal asserted high. When an
interrupt occurs, the source can be read from Status Register 0, which is also the return word of most SPI messages. Faults are latched
on occurrence, and the interrupt and faults are only cleared by sending the corresponding CLINTx command. A fault still existing continue
to assert an interrupt.
Note: If there are multiple pending interrupts, the INT line does not toggle when one of the faults is cleared. Interrupt processing circuitry
on the host must be level sensitive to correctly detect multiple simultaneous interrupt.
Thus, when an interrupt occurs, the host can query the IC by sending a NULL command; the return word contains flags indicating any
faults not cleared since the CLINTx command was last written (rising edge of CS) and the beginning of the current SPI command (falling
edge of CS). The NULL command causes no changes to the state of any of the fault or mask bits.
The logic clearing the fault latches occurs only when:
1. A valid command had been received(i.e. no framing error);
2. A state change did not occur during the SPI message (if the bit is being returned as a 0 and a fault change occurs during the middle
of the SPI message, the latch remains set). The latch is cleared on the trailing (rising) edge of the CS pulse. Note, to prevent
missing any faults the CLINTx command should not generally clear any faults without being observed; i.e. it should only clear faults
returned in the prior NULL response.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
7.2.3
NULL Commands
This command is sent by sending binary 000x xxxx data. This can be used to read IC status in the SPI return word. Message 000x xx00
reads Status Register 0. Message 000x xx01 through 000x xx11 read additional internal registers.
Table 9. NULL Commands
SPI Data Bits
7
6
5
4
3
2
1
0
Write
0
0
0
x
x
x
0
0
Reset
NULL Commands are described in detail in the STATUS REGISTERS section of this document.
7.2.3.1
MASK Command
This is the mask for interrupts. A bit set to “1” enables the corresponding interrupt. Because of the number of MASK bits, this register is in
two portions:
1. MASK0
2. MASK1
Both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. Figure 18 illustrates how interrupts are enabled and faults cleared.
CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively, but the action is to clear the interrupt latch and status
register 0 bit corresponding to the lower nibble of the command.
Table 10. MASK0 Register
SPI Data Bits
7
6
5
4
Write
0
0
1
0
Reset
7.2.3.2
3
2
1
0
x
x
x
x
1
1
1
1
Interrupt Handling
From MASKx:N Register
MASK Bit
To Status Register
INT Source
INT Clear
From Clint Command
net N
Fault
S
Various Faults
Latch
R
INT
net 0
Figure 18. Interrupt Handling
Table 11. MASK1 Register
SPI Data Bits
7
6
5
4
Write
0
0
1
1
Reset
3
2
1
0
x
x
x
x
1
1
1
1
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Analog Integrated Circuit Device Data
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Table 12. Setting Interrupt Masks
Mask:bit
Description
MASK0:0
Overtemperature on any gate drive output generates an interrupt if this bit is set.
MASK0:1
Desaturation event on any output generates an interrupt if this bit is set.
MASK0:2
VLS Undervoltage generates an interrupt if this bit is set.
MASK0:3
Overcurrent Error–if the overcurrent comparator threshold is exceeded, an interrupt is generated.
MASK1:0
Phase Error–if any Phase comparator output is not at the expected value when an output is command on, an interrupt is generated.
This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration of the desaturation
blanking interval. In FULLON mode, this signal is blanked and cannot generate an error.
MASK1:1
Framing Error–if a framing error occurs, an interrupt is generated.
MASK1:2
Write Error after locking.
MASK1:3
Reset Event–If the IC is reset or disabled, an interrupt occurs. Since the IC always starts from a reset condition, this can be used to
test the interrupt mechanism, because when the IC comes out of RESET, an interrupt immediately occurs.
7.2.3.3
MODE Command
This command is sent by sending binary 010x xxxx data.
Table 13. MODE Command
SPI Data Bits
Write
7
0
6
1
Reset
5
0
4
3
2
1
0
0
Desaturation
Fault Mode
0
FULLON Mode
Mode Lock
0
0
0
0
• Bit 0–Mode Lock is used to enable or disable Mode Lock. This bit can only be cleared with a device reset. Since the Mode Lock mode
can only be set, this bit prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being
received. If an attempt is made to write to a register when Mode Lock is enabled, a Write Error fault is generated.
• Bit 1–FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both high and low-side
drivers in a phase on simultaneously. This could be useful in special applications such as alternator regulators, or switched-reluctance
motor drive applications. There is no deadtime control in FULLON mode. Input signals directly control the output stages, synchronized
with the internal clock. This bit is a “0”, after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents
both outputs from being turned on simultaneously.
• Bit 3– Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to “0”, any desaturation on
any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the CLINT command. When 1,
desaturation faults are completely ignored. Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities
are:
• 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates an Interrupt,
if interrupts are enabled.
• 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked.
Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any
further changes.
7.2.3.4
DEADTIME Command
Deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. The deadtime timer starts when a
FET is commanded off (see Figure 6 and Figure 13). The deadtime control is disabled by enabling the FULLON mode.
The deadtime is set by sending the DEADTIME command (100x xxx1), and then sending a calibration pulse of CS. This pulse must be
16 times longer than the required deadtime (see Figure 19). Deadtime is measured in cycle times of the internal time base, fTB. This
measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high and low
gate transactions in the same phase.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
For example: the internal time base is running at 20 MHz and a 1.5 µs deadtime is required. First a DEADTIME command is sent (using
the SPI), then a CS is sent. The CS pulse is 16*1.5 = 24 µs wide. The IC measures this pulse as 24000 ns/50 ns = 480 clock cycles and
stores 480/16 = 30 in the deadtime register. Until the next deadtime calibration is performed, 30 clock cycles separates the turn off and
turn on gate signals in the same phase. The worst case error immediately after calibration is +0/-1 time base cycle, for this example +0 ns/
-50 ns. Note that if the internal time base drifts, the effect on dead time scales directly.
Sending a ZERO DEADTIME command (100x xxx0) sets the deadtime timer to 0. However, simultaneous turn-on of high-side and lowside FETs in the same phase is still prevented unless the FULLON command has been transmitted. There is no calibration pulse expected
after receiving the ZERO DEADTIME command. After RESET, deadtime is set to the maximum value of 255 time base cycles (typically
15 µs). The IC ignores any SPI data sent during the calibration pulse. If there are any transitions on SI or SCLK while the Deadtime CS
pulse is low, a Framing error is generated, however, the CS pulse is used to calibrate the deadtime
Table 14. .DEADTIME Command
SPI Data Bits
7
6
5
4
3
2
1
0
Write
1
0
0
x
x
x
x
ZERO/
CALIBRATE
x
x
x
x
Reset
Deadtime Calibration
Deadtime
CalibrationPulse
Pulse
CS
CS
SCLK
SCLK
SISI
Deadtime
DEADTIME
Command
Command
SO
SO
Figure 19. Deadtime Calibration
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Analog Integrated Circuit Device Data
Freescale Semiconductor
7.2.4
Status Registers
After any SPI command, the status of the IC is reported in the return value from the SPI port. There are four variants of the NULL command
used to read various status in the IC. Other commands return a general status word in the Status Register 0. There are four Status
Registers in the IC. Status Register 0 is most commonly used for general status. Registers one through three are used to read or confirm
internal IC settings.
7.2.4.1
Status Register 0 (Status Latch Bits)
This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command returns
the following data:
Table 15. Status Register 0
SPI Data Bits
Results
Register 0 Read
Reset
7
6
5
4
3
2
1
0
RESET Event
Write Error
Framing Error
Phase Error
Overcurrent
Low VLS
DESAT
Detected on
any Channel
TLIM Detected
on any
Channel
1
0
0
0
0
0
0
0
All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits set. If the
status is still present, this bit does not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively.
• Bit 0–is a flag for Overtemperature on any channel. This bit is the OR of the latched three internal TLIM detectors.This flag can
generate an interrupt if the appropriate mask bit is set.
• Bit 1–is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal high-side desaturation
detectors and phase error logic. Faults are also detected on the low-side as phase errors. A phase error is generated if the output
signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR of phase errors from each phase.
Each phase error is the OR of the HS and LS phase errors. An HS phase error (which also triggers the desaturation detector) occurs
when the HS FET is commanded on, and the Px_HS_S is still low in the deadtime duration after it is driven ON. Similarly, a LS phase
error occurs when the LS FET is commanded on, and the Px_HS_S is still high in the deadtime duration after the FET is driven ON.
This flag can generate an interrupt if the appropriate mask bit is set.
• Bit 2– is a flag for Low Supply Voltage. This flag can generate an interrupt if the appropriate mask bit is set.
• Bit 3–is a flag for the output of the Overcurrent Comparator. This flag can generate an interrupt if the appropriate mask bit is set.
• Bit 4–is a flag for a Phase Error. If any Phase comparator output is not at the expected value when just one of the individual high or
Low-side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output with the output driver state,
and blanked for the duration of the desaturation blanking interval. This flag can generate an interrupt if the appropriate mask bit is set.
• Bit 5–is a flag for a Framing Error. A framing error is a SPI message not containing one or more multiples of eight bits. SCLK toggling
while measuring the Deadtime calibration pulse is also a framing error. This would typically be a transient or permanent hardware error,
perhaps due to noise on the SPI lines. This flag can generate an interrupt if the appropriate mask bit is set.
• Bit 6–indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a Deadtime
command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one defined in the Table 8.
This would typically be a software error. This flag can generate an interrupt if the appropriate mask bit is set.
• Bit 7–is set upon exiting RST. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets reset without
the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set.
33937A
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Freescale Semiconductor
39
7.2.4.2
Status Register 1 (MODE Bits)
This register is read by sending the NULL1 command (000x xx01). This is guaranteed to not affect IC operation and returns the following
data:
Table 16. Status Register 1
SPI Data Bits
7
6
5
4
3
2
1
0
Results
Register 1 Read
0
Desaturation
Mode
Zero Deadtime
Set
Calibration
Overflow
Deadtime
Calibration
0
FULLON Mode
Lock Bit
Reset
0
0
0
0
0
0
0
0
• Bit 0–Lock Bit indicates the IC registers (Deadtime, MASKn, CLINTn, and Mode) are locked. Any subsequent write to these registers
is ignored and sets the Write Error flag.
• Bit 1– is the present status of FULLON Mode. If this bit is set to “0”, the FULLON mode is not allowed. A “1” indicates the IC can
operate in FULLON Mode (both high-side and low-side FETs of one phase can be simultaneously turned on).
• Bit 3–indicates Deadtime Calibration occurred. It is “0” until a successful Deadtime command is executed. This includes the Zero
Deadtime setting, as well as a Calibration Overflow.
• Bit 4–is a flag for a Deadtime Calibration Overflow.
• Bit 5–is set if Zero Deadtime is commanded.
• Bit 6–reflects the current state of the Desaturation/Phase Error turn-off mode.
7.2.4.3
Status Register 2 (MASK bits)
This register is read by sending the NULL2 command (000x xx10). This is guaranteed to not affect IC operation and returns the following
data:
Table 17. Status Register 2
SPI Data Bits
Results
Register 2 Read
Reset
7.2.4.4
7
6
5
4
3
2
1
0
Mask1:3
Mask1:2
Mask1:1
Mask1:0
Mask0:3
Mask0:2
Mask0:1
Mask0:0
1
1
1
1
1
1
1
1
Status Register 3 (Deadtime)
This register is read by sending the NULL3 command (000x xx11). This is guaranteed to not affect IC operation and returns the following
data:
Table 18. Status Register 3
SPI Data Bits
Results
Register 3 Read
Reset
7
6
5
4
3
2
1
0
Dead7
Dead6
Dead5
Dead4
Dead3
Dead2
Dead1
Dead0
0
0
0
0
0
0
0
0
These bits represent the calibration applied to the internal oscillator to generate the requested deadtime. If calibration is not yet
performed, all these bits return 0 even though the actual dead time is the maximum.
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Analog Integrated Circuit Device Data
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7.3
Initialization Requirements
The 33937A provides safe, dependable gate control for three phase BLDC motor control units when it is properly configured. However, if
improperly initialized, the high-side gate drive can be left in a high-impedance mode which allows charge to accumulate from external
sources, eventually turning on the high-side output transistor. It is prudent to follow a well defined initialization procedure which establishes
known states on the gates of all the phase drivers before any current flows in the motor.
7.3.1
Recovery from Sleep Mode (RESET)
The output gate drive is pulled low with the hold off circuit as long as VLS is low, there is a Power On Reset condition or +5.0 V is low.
These conditions are present during a reset condition. When first coming out of a reset condition, the gate drive circuits are in a highimpedance state until the first command is given for operation. After the reset line goes high, the supplies begin to operate and the hold
off circuit is deactivated. The phase input lines do not have any effect on the gate drive until both ENABLE1 and ENABLE2 go high, and
even then the low-side gate must be commanded on before the high-side gate can be operated. This is to insure the bootstrap capacitor
has been charged before commencing normal operation. The high-side gate must then be commanded on and then off to initialize the
output latches. A proper initialization sequence places the output gate drives in a low-impedance known condition prior to releasing the
device for normal operation.
A valid initialization sequence would go something like this:
1. RESET goes high (ENABLE1 and ENABLE2 remain low)
2. SPI commands to configure valid interrupts, DESAT mode and Dead Time are issued
3. SPI command to clear all interrupt conditions
4. ENABLE1 and ENABLE2 are set HIGH (LS outputs are now enabled)
5. PA_LS, PB_LS, and PC_LS are toggled HIGH for about 1.0 μs (HS outputs are enabled, but not latched)
6. Toggle nPA_HS, nPB_HS, and nPC_HS LOW for DEAD TIME plus at least 0.1 μs (HS outputs are now latched and operational).
End of initialization.
Doing step 6 simultaneously on all HS inputs places the motor into High-side Recirculation mode and does not cause motion during the
time they are ON.
This action forces the high-side gate drive out of tri-state mode and leaves it with the HS_G shorted to HS_S on all phases. The HS output
FETs is OFF and ready for normal motor control.
Step 5 and step 6 can be done on all the stated inputs simultaneously. It may be desirable for the HS (step 6) to be toggled simultaneously
to prevent current from flowing in the motor during initialization.
Note the inputs PA_LS, PB_LS, PC_LS, nPA_HS, nPB_HS, and nPC_HS are edge sensitive. Toggling the LS inputs enables the HS
drivers, so for the HS drivers to be initialized correctly the edge of the input signal to the HS drivers must come after the LS input toggle.
A failure to do this results in the HS gate output remaining in a high-impedance mode. This can result in an accumulation of charge, from
internal and external leakage sources, on the gate of the HS output FET causing it to turn ON even though the input level to the 33937A
would appear to indicate it should be OFF. When this happens, the logic of the 33937A allows the LS output FET to be turned ON without
taking any action on the HS gate because the logic is still indicating the HS gate is OFF. The initial LS input transition from low to high
needs to be after both ENABLE inputs are high (the device in NORMAL mode) for the same reason. The delay between ENABLE and the
LS input should be 280 ns minimum to insure the device is out of STBY mode. Once initialized the output gate drives continues to operate
in a low-impedance mode as commanded by the inputs until the next reset event.
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Freescale Semiconductor
41
INT
SPI
CS
Px_HS
Px_LS
EN1-2
RST
VDD
VLS
VPWR
VSUP
tPU_VDD
tPU_VLS
t1
t2
t3
t4
t5
t6
Figure 20. Full Initialization
Table 19. Full Initialization Timing Description
Time
Min.
Comments
Power up time from RESET
2.0 ms
RESET must remain high long enough for VDD and VLS to reach the full regulated voltage. The
normal time for this to occur is specified as 2.0 ms maximum. If there is more capacitance on
VLS or VDD than the normal values given in the specification, this time may need to be
increased. In general, the time may be safely scaled linearly with the capacitance. If the charge
pump is used, it may also increase this time. An estimate of increased time, due to the charge
pump, would be to add 25%. For example, the nominal VLS capacitance is 2.2 µF on each pin,
the power up time should be increased to 4.0 ms, 5.0 ms if using the charge pump.
t1
End of SPI communication to
EN1 and EN2 rising edge
0 ns
t2
EN1 and EN2 rising edge to
first LS output command
280 ns
Restricted by EN1 and EN2 propagation delay
t3
Initial LS ON period
1.0 µs
Nominally 1.0 µs is more that enough. The calculated value is 5*CBOOT(RSENSE + RDSON_LS).
100 ns for default recovery.
t4
LS OF to HS ON
0 ns
No defined maximum, but HS is undefined until beginning of toggle on the HS
Initial HS ON period
100 ns
+ dead
time
Minimum: Dead-time + 100 ns to guarantee the HS is switched.
t5
t6
HS OFF to Normal Operation
0 ns
Immediately begin Normal Operation
tPU_VDD,
tPU_VLS
Description
Maximum: Same limitations as Normal Operation. Unlimited time if leakage currents are less
than trickle charge pump margin.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
7.3.2
Recovery from Standby Mode or a Fault
When the 33937A is placed in Standby mode or a fault condition causes a shutdown, the Gate outputs are all driven low. The high-side
gate drive is then disabled and locked to prevent unauthorized transitions. This requires an initialization sequence to recover normal
operation at the end of this mode of operation. The initialization sequence is nearly identical to recovery from Sleep mode, with the
modification that the initial pulse to the low-side control inputs can be reduced to a 100 ns pulse (the low-side gates may not actually
change state). The initialization is then completed by cycling the high-side gates to re-engage the gate drive and insure that it is in the
proper state prior to resuming normal operation.
A valid initialization sequence would go something like this:
1. SPI command to clear all interrupt conditions
2. ENABLE1 and ENABLE2 are set HIGH (LS outputs are now enabled)
3. PA_LS, PB_LS and PC_LS are toggled HIGH for at least 100 ns (HS gate drive outputs are enabled) longer if bootstrap capacitors
need charged.
4. Toggle nPA_HS, nPB_HS and nPC_HS LOW for DEAD TIME plus at least 100 ns.
End of initialization.
Doing step 4 simultaneously on all HS inputs places the motor into High-side Recirculation mode and does not cause motion during the
time they are ON.
This action restores the high-side gate drive operation and leave it with the HS_G shorted to HS_S on all phases. The HS output FETs
will be OFF and ready for normal motor control.
Step 3 and step 4 can be done on all the stated inputs simultaneously. In fact it is desirable for the HS (step 4) to be toggled simultaneously
to prevent current from flowing in the motor during initialization.
Note the inputs PA_LS, PB_LS, PC_LS, nPA_HS, nPB_HS, and nPC_HS are edge sensitive. Toggling the LS inputs enables the HS
drivers, so for the HS drivers to be initialized correctly, the edge of the input signal to the HS drivers must come after the LS input toggle.
A failure to do this results in the HS gate output remaining locked out from input control. The initial LS input transition from low to high
needs to be after both ENABLE inputs are high (the device in Normal mode) for the same reason. The delay between ENABLE and the
LS input should be 280 ns minimum to insure the device is out of STBY mode.
INT
SPI
nCS
Px_Combined
nPx_HS
Clear
0.1µs
0.1µs
Px_LS
EN2
EN1
Figure 21. Recovery Initialization
The horizontal divisions are not to scale. They are a reference to show the sequence of operation. Either individual nPx_HS and Px_LS
or nPx_Combined may be used. nPx_Combined is defined as both nPx_HS and Px_LS tied together or operated to the same logic level
simultaneously.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
43
7.3.3
IC Initialization
This process flow initializes the IC and its software environment.
1. Apply power (VSYS) to module
2. Remove RST (RST goes high, EN1 and EN2 are still low)
a) When RST rises above the threshold, the device powers up. The charge pump (if configured) starts and allows VDD and VLS to
stabilize.
2. Initialize registers
a) Clear all interrupt status flags (send CINT0 and CINT1)
b) Initialize MASK register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts.
c) Set desired dead time either by commanding zero dead time or calibrating the dead time.
d) Send MODE command with desired bits, and also the Lock bit. e.g. 01000001. This prevents further mode changes.
5. Bring EN1 & EN2 high
6. Initialize the outputs
a) Command all Px_HS to logic 1 (High-side OFF)
b) Command all Px_LS to logic 1 (commanding Low-side ON). The input must transition from low to high after EN1 and EN2 have
gone high.
c) Wait for the bootstrap capacitors to charge (about 1.0 μs typically)
d) Command all Px_LS to logic 0 (command low-side OFF)
e) Command all Px_HS to logic 0 (command high-side ON)
f) Command all Px_HS to logic 1 (command high-side OFF)
The device is now ready for normal operation.
7.3.4
Interrupt Handler
When an interrupt occurs, the general procedure is to send NULL0 and NULL1 commands to determine what happened, take corrective
action (if needed), clear the fault, and return. Because the return value from an SPI command is actually returned in the subsequent
message, main-loop software trying to read SR1, SR2, or SR3, may experience an interrupt between sending the SPI command and the
subsequent read. Thus if these registers are to be read, special care must be taken in the software to ensure the correct results are being
interpreted.
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8
Typical Applications
VSYS
+12V Nom.
D1
C2
C1
PUMP
VPUMP
VPWR
VSUP
Main
Charge
Pump
PGND
To Other
Two Phases
C6
D2
Trickle
Charge
Pump
5V
Reg.
VDD
Hold
-Off
Circuit
VLS
Reg.
VLS
Oscillator
C3
VDD
UV
Detect
3x
Px_BOOT
T-Lim
RST
INT
EN1
EN2
VSUP
Px_HS
Px_LS
3
Control
3
Logic
Desat.
Comp.
+
-
C4
High
-Side
Driver
Cx_Boot
Rg_HS
Px_HS_G
QHS
(Optional)
1.4V
Phase x
Output
To Motor
Px_HS_S
CS
SI
SCLK
SO
QLS
Phase VSUP
Comp.
3
PHASE_x
Low
-Side
Driver
OC_OUT
GND
Over-Cur.
Comp.
OC_TH
+
-
To ADC
Px_LS_G
(Optional)
Phase
Return
Px_LS_S
I-sense
Amp.
AMP_OUT
AMP_N
Rg_LS
R1
AMP_P
VLS_CAP
C5
R3
R2
RSense
+
-
Rfb
Figure 22. Typical Application Diagram Using Charge Pump (+12 V Battery System)
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Freescale Semiconductor
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VSYS
+42V Nom.
To Other
Two Phases
C6
+14V Nom.
C2
PUMP
VPUMP
VPWR
VSUP
Main
Charge
Pump
PGND
Trickle
Charge
Pump
5V
Reg.
VDD
Hold
-Off
Circuit
VLS
Reg.
VLS
Oscillator
C3
VDD
UV
Detect
3x
T-Lim
RST
INT
EN1
EN2
Px_HS
Px_LS
VSUP
3
Control
3
Logic
Desat.
Comp.
+
-
Px_BOOT
High
-Side
Driver
(Optional)
To Motor
Px_HS_S
QLS
Phase VSUP
Comp.
3
Low
-Side
OC_OUT
Over-Cur.
Comp.
OC_TH
+
-
To ADC
Px_HS_G
QHS
Phase x
Output
Driver
GND
Cx_Boot
Rg_HS
1.4V
CS
SI
SCLK
SO
PHASE_x
C4
Px_LS_G
(Optional)
Phase
Return
Px_LS_S
I-sense
Amp.
AMP_OUT
AMP_N
Rg_LS
R1
AMP_P
VLS_CAP
C5
R3
R2
RSense
+
-
Rfb
Figure 23. High-voltage Application Diagram (+42 V Battery System)
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Analog Integrated Circuit Device Data
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1
0.9
Power Dissipated (W)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
Figure 24. Power Dissipation Profile of Application Using Charge Pump
Reference application with:
• Pump capacitor: 1.0 μF MLC
• Pump filter capacitor: 47 μF low ESR aluminum electrolytic
• Pump diodes: MUR120
• Output FET gate charge: 240 nC @ 10 V
• PWM Frequency: 20 kHz
• Switching Single Phase
Below approximately 17 V the charge pump is actively regulating VPWR. The increased power dissipation is due to the charge pump
losses. Above this voltage the charge pump oscillator shuts down and VSYS is passed through the pump diodes directly to VPWR.
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1.500
1.400
1.300
1.200
Power Dissipation (W)
1.100
1.000
0.900
0.800
0.700
0.600
0.500
0.400
0.300
0.200
0.100
0.000
10
15
20
25
30
35
40
45
50
55
60
Supply Voltage (V)
Figure 25. Power Dissipation Profile of Application Not Using Charge Pump
Reference application with:
• Output FET gate charge: 240 nC @ 10 V
• PWM Frequency: 20 kHz
• Switching Single Phase
• No connections to PUMP or VPUMP
• VPWR connected to VSYS
If VPWR is supplied by a separate pre-regulator, the power dissipation profile is nearly flat at the value of the pre-regulator voltage for all
VSYS voltages.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
Packaging
9.1
Packaging Dimension
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98ASA99334D” listed below. Dimensions
shown are provided for reference ONLY.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
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33937A
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Analog Integrated Circuit Device Data
Freescale Semiconductor
10
Revision History
Revision
Date
1.0
6/2008
• Initial Release
7/2008
• Updated specifications for current sense amplifier and overcurrent comparator
• Added Gain/Phase curves for current sense amplifier
• Added typical curves for load margin on Px_CBOOT
• Added discussion about bootstrap capacitors and requirements for external bootstrap diodes
• Updated application drawings
• Added VSUP requirement for hold-off
11/2008
• Updated Freescale form and style
• Added note to VLS Regulator Outputs (VLS, VLS_CAP)
• Changed Charge Device Model - CDM
• Corrected title to No output loads on Gate Drive Pins, No PWM, Outputs initialized
• Changed In order to achieve a 100% duty cycle operation of the high-side external FETs, a fully integrated trickle
charge pump provides the charge necessary to maintain the external FET gates at fully enhanced levels. The
trickle charge pump has limited ability to supply external leakage paths while performing it’s primary function. The
graph in Figure 11 shows the typical margin for supplying external current loads. These limits are based on
maintaining the voltage at CBOOT at least 3.0 V greater than the voltage on the HS_S for that phase. If this voltage
differential becomes less than 3.0 V, the corresponding high-side FET most likely does not remain fully enhanced
and the high-side driver may malfunction due to insufficient bias voltage between CBOOT and HS_S. and
associated paragraphs
4.0
12/2008
• Added PCZ33937AEK/R2 Part number throughout.
• Added Note and changed parameters for Desaturation Detector and Phase Comparator to Dynamic Electrical
Characteristics Table.
• Replaced Typical Application Diagrams (Pages 40 and 41).
• Page 10 remove VDD Threshold (VDD Falling) change note 23
5.0
4/2009
• Note 41 clarification.
6.0
9/2009
• Changed part number from PCZ33937A to MCZ33937A on page 1. Added Device Variation table on page 2.
7.0
3/2011
• Revised per Specific customer requirements (not published)
8.0
8/2012
• Removed part number MCZ33937AEK and replaced with part number MC33937APEK.
• Removed part number MCZ33937EK/R2 and specific differences. Noted in ordering information to see
specification MC33937 Rev 6.0 for obsolete parts.
9.0
11/2015
• Clarified Gate Capability feature on page 1.
• Updated Freescale form and style.
2.0
3.0
Description of Changes
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Document Number: MC33937
Rev. 9.0
11/2015