Datasheet PROGRAMMABLE TIMING CONTROL HUB FOR INTEL BASED SYSTEMS ICS9LRS3187B Recommended Application: Features/Benefits: CK505 version 1.1 clock, with fully integrated voltage regulators and series resistors • Supports spread spectrum modulation, 0 to -0.5% down spread for CPU and SRC clocks • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Available in commercial (0 to +70°C) and industrial (-40 to +85°C) temperature ranges • Meets PCIe Gen2 specifications Output Features: 2 - CPU differential low power push-pull pairs 1 - SRC differential low power push-pull pair 1 - SATA differential low power push-pull pair 1 - DOT differential low power push-pull pair 1 - REF, able to drive 3 loads, 14.318MHz 1 - 27MHz_SS/non_SS single-ended output pair Key Specifications: CLKPWRGD/PD#_3.3 GNDREF CPU outputs cycle-cycle jitter <85ps SRC outputs cycle-cycle jitter <125ps +/- 100ppm frequency accuracy on all clocks X2 X1 SDATA_3.3 SCLK_3.3 Pin Configuration VDDREF_3.3 • • • REF_2L/FSLC_3.3** • • • • • • 32 31 30 29 28 27 26 25 VDDDOT96MHz_3.3 1 24 VDDCPU_3.3 23 CPUT0_LPR GNDDOT96MHz 2 DOT96T_LPR 3 DOT96C_LPR 4 22 CPUC0_LPR 21 GNDCPU 9LRS3187 VDD_27MHz 5 20 CPUT1_LPR 27MHz_nonSS 6 27MHz_SS 7 19 CPUC1_LPR 18 VDDCPU_IO GND27MHz 8 17 VDDSRC_3.3 VDDSRC_IO *CPU_STOP# SRCC1_LPR GNDSRC SRCT1_LPR SATAC_LPR GNDSATA SATAT_LPR 9 10 11 12 13 14 15 16 ** Internal Pull-Down Resistor * Internal Pull-Up Resistor 32-pin MLF IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 1 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Pin Description Pin# Pin Name Type Pin Description 1 VDDDOT96MHz_3.3 PWR Power pin for the 96MHz output 3.3V. 2 GNDDOT96MHz 3 DOT96T_LPR 4 DOT96C_LPR 5 VDD_27MHz PWR Ground pin for the 96MHz output True DOT96 output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. Complement DOT96 output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. PWR Power pin for the 27MHz output 3.3V. 6 27MHz_nonSS OUT 7 27MHz_SS OUT 3.3V Single-ended 27MHz spread clock. 8 GND27MHz OUT Ground pin for the 27MHz outputs. 9 GNDSATA 10 SATAT_LPR 11 SATAC_LPR 12 GNDSRC 13 SRCT1_LPR 14 SRCC1_LPR 15 VDDSRC_IO 16 *CPU_STOP# 17 VDDSRC_3.3 PWR Ground pin for the SATA outputs. True clock of differential 0.8V push-pull SATA/SRC output with OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SATA/SRC OUT output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. PWR Ground pin for the SRC outputs True clock of differential 0.8V push-pull SRC output with OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output OUT with integrated 33ohm series resistor. No 50ohm resistor to GND needed. PWR 1.05V to 3.3V from external power supply Stops all CPU clocks, except those set to be free running IN clocks PWR Supply for SRC clocks, 3.3V nominal 18 VDDCPU_IO 19 CPUC1_LPR 20 CPUT1_LPR 21 GNDCPU 22 CPUC0_LPR 23 CPUT0_LPR 24 VDDCPU_3.3 3.3V Single-ended 27MHz non-spread clock. PWR 1.05V to 3.3V from external power supply Complementary clock of differential pair 0.8V push-pull CPU OUT outputs with integrated 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. PWR Ground pin for the CPU outputs. Complementary clock of differential pair 0.8V push-pull CPU OUT outputs with integrated 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. PWR Supply for CPU clocks, 3.3V nominal 25 CLKPWRGD/PD#_3.3 26 GNDREF PWR Ground pin for the REF outputs. IN 27 X2 OUT 28 X1 29 VDDREF_3.3 30 REF_2/FSLC_3.3** 31 SDATA_3.3 32 SCLK_3.3 IN Notifies CK505 to sample latched inputs, or PWRDWN# mode Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz PWR Power pin for the XTAL and REF clocks, nominal 3.3V 14.318 MHz reference clock, which can drive 2 loads / 3.3V I/O tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. I/O Data pin for SMBus circuitry, 3.3V tolerant IN Clock pin of SMBus circuitry, 3.3V tolerant. IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 2 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet General Description The ICS9LRS3187B is a CK505 clock synthesizer. The ICS9LRS3187B provides a single-chip solution for Intel based systems. The ICS9LRS3187B is driven with a 14.318MHz crystal. Functional Block Diagram 14.318M Xtal REFCLK SS PLL 27MHz_SS SRC SS PLL PLL SRC(1) CPUCLK CPUCLK(1:0) 0 SATA_nonSS Table: Power Distribution Ground VDD_IO VDD 3.3V 2 8 9 12 21 26 15 15 18 1 5 17 17 24 29 COUT_DIV Non-SS PLL SATA 1 B0b1 27MHz nonSS DOT96MHz Output DOT96 27M SATA SRC CPU REF IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 3 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Table 1: CPU Frequency Select Table FSLC B0b7 0 (Default) 1 CPU MHz 133.33 100.00 SRC MHz REF MHz DOT MHz 100.00 14.318 96.00 1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. Table 2: pin 6, 7 Configuration B1b3 B1b2 B1b1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 Pin 6 Pin 7 MHz MHz 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS Spread % Comment -1.75% +-0.5% -0.5% Default -1% -1.5% -2% -0.75% -1.25% Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0 0 0 0.3V 0 0 1 0.4V 0 1 0 0.5V 0 1 1 0.6V 1 0 0 0.7V 1 0 1 0.8V 1 1 0 0.9V 1 1 1 1.0V IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 4 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems CPU Power Management Table SMBus PD# CPU_STOP# CPU1 Reg. OE 1 Enable Running 1 X Enable Low/20K 0 1 Enable High 0 1 X Low/20K Disable M1 Running Datasheet CPU1# CPU0 CPU0# Running Low Low Low Running Running Low/20K High Low/20K Low/20K Running Low Low Low Low SRC and DOT96MHz Power Management Table PD# CPU_STOP# 0 1 1 X X X SMBus Reg. OE Enable Enable Disable M1 SRC SRC# DOT DOT# Low/20K Running Low/20K Low/20K Low Running Low Low Low/20K Running Low/20K Low/20K Low Running Low Low Singled-ended Power Management Table SMBus PD# CPU_STOP# 27M Reg. OE 1 X Enable Running X Enable Low 0 1 X Low Disable M1 Low REF Running Hi-Z Low Hi-Z IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 5 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet General SMBus serial interface information for the ICS9LRS3187B How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controlle r (Host) starT bit T Slave Address D2(H ) W Rite WR Controller (host) will send start bit. Controller (host) sends the write address D2 (H) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N + X -1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Controlle r (Host) T starT bit Slave Address D2(H ) WR W Rite IDT (Sla ve /Re ce ive r) IDT (Sla ve /Re ce ive r) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H ) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDT® Programmable Timing Control Hub for Intel Based Systems Not acknowledge stoP bit 1602F—11/04/11 6 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Byte 0 FS Readback and PLL Selection Register Bit Pin 7 6 5 4 - iAMT_EN Set via SMBus 3 2 - Reserved Reserved Reserved Reserved Type R RW RW RW (Sticky "1") RW RW 1 - SATA_SEL Select source for SATA clock RW SATA (SRC2 100MHz_SS) = SRC_Main SATA (100MHz non_SS) = SATA PLL 0 PD_Restore 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold poweron and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. RW Configuration Not Saved Configuration Saved 1 0 Down spread - 1 Center spread - 0 - Name FSLC Reserved Reserved Description CPU Freq. Sel. Bit Reserved Reserved 0 1 - - Default Latch 0 1 Legacy Mode iAMT Enabled 0 0 0 Byte 1 DOT96 Select and PLL3 Quick Config Register, Bit Pin Name 7 Reserved 6 SRC_PLL_SSC_SEL 5 Reserved 4 Reserved 3 27SS PLL CF2 2 27SS PLL _CF1 1 27SS PLL CF0 0 Reserved Description Reserved Select 0.5% down or center SSC Reserved Reserved 27SS PLL Quick Config Bit 2 27SS PLL Quick Config Bit 1 27SS PLL Quick Config Bit 0 Reserved Type RW RW RW RW RW RW RW RW - - Default 1 0 1 0 0 1 0 1 Description Output enable for REF0, if disabled output is tristated Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default RW Output Disabled Output Enabled 1 RW RW RW RW RW RW RW - - 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW RW 0 - 1 - - - Default 1 1 1 1 1 1 1 1 See Table 2: pin 6/7 Configuration Byte 2 Output Enable Register Bit Pin Name 7 REF_3L_OE 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 3 Output Enable Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 7 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Byte 4 Output Enable and Spread Spectrum Disable Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved SATA_OE SRC1_OE DOT96_OE CPU1_OE CPU0_OE 27SS_ON SRC_SSC_ON Description Reserved Output enable for SATA Output enable for SRC1 Output enable for DOT96 Output enable for CPU1 Output enable for CPU0 Enable 27SS's spread modulation Enable SRC's spread modulation Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 - 1 - Default 1 1 1 1 1 1 1 1 Description Reserved Reserved Slew Rate Control Reserved Slew Rate Control Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 2 V/ns 2 V/ns - 1 1 V/ns 1 V/ns - Default 0 0 0 0 0 0 0 0 Description Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 Type R R R R RW RW RW RW 0 1 Default 1 0 0 0 0 0 1 1 Byte 5 Reserved Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 6 Slew Rate Control Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved Reserved REF Slew Reserved 27MHz Slew Reserved Reserved Reserved Byte 7 Vendor ID/ Revision ID Bit Pin 7 6 5 4 3 2 1 0 Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Revision ID Vendor ID ICS is 0001, binary Vendor specific Byte 8 Device ID and Output Enable Register Bit Pin 7 6 5 4 3 2 1 0 Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved 27MHz_nonSS_OE 27MHz_SS_OE Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Output enable for 27MHz_nonSS Output enable for 27MHz_SS IDT® Programmable Timing Control Hub for Intel Based Systems See Device ID Table Disabled Disabled Enabled Enabled 1602F—11/04/11 8 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Byte 9 Output Control Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Reserved Reserved Reserved Reserved Reserved IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW R RW RW RW RW RW RW 0 - 1 - See Table 3: V_IO Selection (Default is 0.8V) Default 0 0 1 0 0 1 0 1 Byte 10 Output Control Register Bit Pin Name 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 CPU 1 Stop Enable 0 CPU 0 Stop Enable Description Reserved Reserved Reserved Reserved Reserved Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Type RW RW RW RW RW RW RW RW 0 Free Running Free Running 1 Stoppable Stoppable Default 0 0 0 0 0 0 1 1 Name Reserved Reserved Reserved Reserved Reserved CPU1_AMT_EN Description Reserved Reserved Reserved Reserved Reserved M1 mode clk enable Type RW RW RW RW RW RW 0 1 Disable 1 PCI-E_GEN2 Determines if PCI-E Gen2 compliant R non-Gen2 0 Reserved Reserved RW - Enable PCI-E Gen2 Compliant - Default 0 0 0 0 0 1 Description Type RW RW RW RW RW RW RW RW 0 1 Byte 11 Reserved Register Bit Pin 7 6 5 4 3 2 1 1 Byte 12 Byte Count Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Read Back byte count register, max bytes = 32 IDT® Programmable Timing Control Hub for Intel Based Systems Default 0 0 0 0 1 1 0 1 1602F—11/04/11 9 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Absolute Maximum Ratings - DC Parameters, Commercial Temperature Range PARAMETER SYMBOL CONDITIONS Maximum Supply Voltage VDDxxx Supply Voltage MIN TYP MAX 4.6 V 1 Maximum Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 3.8 V 1 Maximum Input Voltage VIH 3.3V Inputs V 1,2 Minimum Input Voltage VIL Any Input GND - 0.5 Storage Temperature Ts - -65 Input ESD protection ESD prot Human Body Model 2000 4.6 150 UNITS Notes V 1 ° C 1 V 1,3 Notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Operation under these conditions is neither implied, nor guaranteed. Maximum VIH is not to exceed VDD 3 Human Body Model 2 Electrical Characteristics - Input/Supply/Common Output DC Parameters, Commercial Temperature Range PARAMETER SYMBOL CONDITIONS MIN Ambient Operating Temp Tambient - 0 70 Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 0.9975 3.465 V Input High Voltage VIHSE Single-ended 3.3V inputs 2 VDD + 0.3 V 3 Input Low Voltage VILSE Single-ended 3.3V inputs VSS - 0.3 0.8 V 3 Low Threshold Input- FSC = '1' Voltage VIH_FSC 3.3 V +/-5% 0.7 3.3 V 4 Low Threshold Input-Low Voltage VIL_FSC 3.3 V +/-5% VSS - 0.3 0.35 V Input Leakage Current I IN -5 5 uA Input Leakage Current IINRES VIN = VDD , VIN = GND Inputs with pull up or pull down resistors VIN = VDD , VIN = GND -200 200 uA Output High Voltage VOHSE Single-ended outputs, IOH = -1mA V 1 Output Low Voltage VOLSE Single-ended outputs, IOL = 1 mA 0.4 V 1 IDDOP3.3 Full Active, CL = Full load; Idd 3.3V 85 110 mA I DDOPIO Full Active, CL = Full load; IDD IO 18 25 mA IDDiAMT3.3 M1 mode, 3.3V Rail 48 60 mA Operating Supply Current iAMT Mode Current Powerdown Current TYP MAX 2.4 UNITS Notes °C IDDiAMTIO M1 Mode, IO Rail 6 10 mA IDDPD3.3 Power down mode, 3.3V Rail 6 5 mA IDDPDIO Power down mode, IO Rail 0 0.1 mA Input Frequency Fi VDD = 3.3 V 14.3182 15 MHz Pin Inductance Lpin 7 nH CIN Logic Inputs Input Capacitance COUT Output pin capacitance CINX X1 & X2 pins Clk Stabilization TSTAB From VDD Power-Up or de-assertion of PD to 1st clock Tfall_SE TFALL Trise_SE TRISE SMBus Voltage VDD Low-level Output Voltage VOLSMB @ IPULLUP Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 1.5 1.0 Fall/rise time of all 3.3V control inputs from 20-80% TRI2C TFI2C 2.7 IDT® Programmable Timing Control Hub for Intel Based Systems pF 6 pF 30 5 5 5 6 pF ms 10 ns 1 10 ns 1 5.5 V 5 32.54 2 1.8 0.4 4 FSMBUS Spread Spectrum Modulation Frequency f SSMOD Triangular Modulation Notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Signal is required to be monotonic in this region. 2 Input leakage current does not include inputs with pull-up or pull-down resistors 3 3.3V referenced inputs are: SCLK, SDATA, and CKPWRGD 4 Frequency Select pins which have tri-level input 5 If present, not all parts have this feature. 5 5 V mA 1000 ns 300 ns 100 kHz 33 kHz 1602F—11/04/11 10 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet AC Electrical Characteristics - Low Power Differential Outputs, Commercial Temperature Range PARAMETER SYMBOL CONDITIONS MIN TYP MAX Rising Edge Slew Rate tSLR Averaging on 2.5 3.7 4 UNITS Notes V/ns 2, 3 Falling Edge Slew Rate tFLR Averaging on 2.5 3.7 4 V/ns 2, 3 Slew Rate Variation tSLVAR Averaging on 3.6 20 % 1, 6 Differential Voltage Swing VSWING Averaging off 300 Crossing Point Voltage VXABS Averaging off 300 Crossing Point Variation VXABSVAR Averaging off Maximum Output Voltage VHIGH Averaging off Minimum Output Voltage VLOW Averaging off -300 Duty Cycle DCYC Averaging on 45 49.8 CPU Skew CPUSKEW Averaging on 35 SRC Skew tSKEWSRC Averaging on, SRC to SATA skew when Byte0, bit 1 = 0 259 350 ps mV 2 446 550 mV 1,4,5 70 140 mV 1,4,9 1150 mV 1,7 mV 1,8 55 % 2 100 ps NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). CL = 2pF, Rs = 0 ohms. 1 Measurement taken for single ended waveform on a component test board (not in system) 2 Measurement taken from differential waveform on a component test board. (not in system) 3 Slew rate emastured through V_swing voltage range centered about differential zero 4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) 5 Only applies to the differential rising edge (Clock rising, Clock# falling) 6 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage 7 The max voltage including overshoot. 8 The min voltage including undershoot. 9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute Clock Jitter Specs - Low Power Differential Outputs, Commercial Temperature Range PARAMETER SYMBOL CONDITIONS TYP MAX CPU Jitter - Cycle to Cycle CPUJC2C Differential Measurement 50 85 ps 1 SRC/SATA Jitter - Cycle to Cycle SRCJC2C Differential Measurement 50 125 ps 1,2 DOT Jitter - Cycle to Cycle DOTJC2C Differential Measurement 50 250 tjphasePLL PCIe Gen 1 35 86 1.8 3 2.3 3.1 SRC Phase Jitter tjphaseLo tjphaseHigh PCIe Gen 2 10kHz < f < 1.5MHz PCIe Gen 2 1.5MHz < f < Nyquist (50MHz) MIN UNITS Notes ps 1 ps (p1,2,3 p) ps 1,2,3 (RMS) ps 1,2,3 (RMS) NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). CL = 2pF, Rs = 0 ohms. 1 JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured in a real system. 2 Phase jitter requirement: The designated Gen2 outputs will meet the reference clock jitter requirements from the PCI Express Gen2 Base Spec. The test is performed on a component test board under quiet conditions with all outputs on. 3 See http://www.pcisig.com for complete specs IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 11 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Electrical Characteristics - REF-14.318MHz, Commercial Temperature Range PARAMETER SYMBOL CONDITIONS MIN TYP MAX Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm 2, 4 Clock period Tperiod 14.318MHz output nominal 69.82033 69.84129 69.86224 ns 2, 3 Absolute min/max period Tabs 14.318MHz output nominal 69.83400 70.84800 ns 2 CLK High Time THIGH 29.97543 38.46654 V 29.57543 38.26654 V -33 -33 mA 30 38 mA CLK Low time TLOW Output High Current IOH Output Low Current IOL Rising/Falling Edge Slew Rate tSLEW VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured between 0.8 to 2.0 V Duty Cycle dt1 VT = 1.5 V Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V UNITS Notes 1 1.7 4 V/ns 45 53 55 % 1 2 115 1000 ps 2 TYP MAX NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Edge rate in system is measured from 0.8V to 2.0V. 2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V 3 The average period over any 1us period of time 4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequency is 14.318180 MHz Electrical Characteristics - 27MHz_Spread / 27MHz_NonSpread, Commercial Temperature Range PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values Clock period Tperiod 27.000MHz output nominal Output High Current I OH Output Low Current IOL Rising/Falling Edge Slew Rate tslewr/f VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Rising/Falling edge rate Duty Cycle dt1 VT = 1.5 V tltj Long Term (10us) VT = 1.5 V VT = 1.5 V VT = 1.5 V SS% <= 1.5% pk to pk VT = 1.5 V, SS% > 1.5% pk to pk Jitter, 27MHz_NonSpread Output Jitter, 27MHz_Spread Output tjpk-pk t jcyc-cyc t jcyc-cyc MIN UNITS Notes -50 50 -15 15 37.0365 37.0376 -29 -23 mA 1 29 27 mA 1 ppm 1,2 1,2,3 1 2 4 V/ns 1 45 50.4 55 % 1 485 800 100 120 200 200 ps ps ps ps ps 4 4 -100 57 82 134 NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Edge rate in system is measured from 0.8V to 2.0V at default slew rate control setting. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF out is at 14.31818MHz 3 At nominal temperature and voltage. 4 Long term and peak to peak jitter do not apply to the 27MHz spreading output. The spread modulation directly impacts these values. IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 12 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Absolute Maximum Ratings - DC Parameters, Industrial Temperature Range PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V Tolerant Inputs Any Input Human Body Model MIN TYP GND - 0.5 -65 2000 MAX 4.6 3.8 4.6 UNITS V V V V ° 150 C V Notes 1 1 1,2 1 1 1,3 Notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Operation under these conditions is neither implied, nor guaranteed. Maximum VIH is not to exceed VDD 3 Human Body Model 2 Electrical Characteristics - Input/Supply/Common Output DC Parameters, Industrial Temperature Range PARAMETER Ambient Operating Temp SYMBOL Tambind CONDITIONS Industrial Range MIN -40 TYP MAX 85 UNITS °C Supply Voltage, Core Supply Voltage, I/O VDDxxx VDDxxx_IO Supply Voltage Low-Voltage Differential I/O Supply 3.135 0.9975 3.3 1.05 3.465 3.465 V V Input High Voltage VIHSE Single-ended 3.3V inputs 2 2.4 VDD + 0.3 V 3 Input Low Voltage Low Threshold Input - High Voltage Low Threshold Input - Low Voltage Input Leakage Current VILSE VIH_FSC VIL_FSC IIN VSS - 0.3 0.7 VSS - 0.3 -5 0.4 0.8 3.3 0.35 5 V V V uA 3 4 Input Leakage Current IINRES 200 uA Output High Voltage Output Low Voltage VOHSE VOLSE Operating Supply Current I DDOP3.3 I DDOPIO Single-ended 3.3V inputs 3.3 V +/-5%, Voltage for which FSC = '1' 3.3 V +/-5% VIN = VDD , VIN = GND Inputs with pull up or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, I OH = -1mA Single-ended outputs, I OL = 1 mA Full Active, CL = Full load; Idd 3.3V Full Active, CL = Full load; IDD IO M1 mode, 3.3V Rail M1 Mode, IO Rail Power down mode, 3.3V Rail Power down mode, IO Rail VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins 1.5 0.4 110 25 65 15 8 0.05 15 7 5 6 6 V V mA mA mA mA mA mA MHz nH pF pF pF From VDD Power-Up or de-assertion of PD to 1st clock 1.8 ms Tfall_SE TFALL Fall/rise time of all 3.3V control inputs from 20-80% Trise_SE TRISE SMBus Voltage VDD Low-level Output Voltage VOLSMB @ I PULLUP IPULLUP SMB Data Pin Current sinking at VOLSMB = 0.4 V SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time Maximum SMBus Operating Frequency FSMBUS Spread Spectrum Modulation Frequency f SSMOD Triangular Modulation Notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Signal is required to be monotonic in this region. 2 Input leakage current does not include inputs with pull-up or pull-down resistors 3 3.3V referenced inputs are: SCLK, SDATA, and CKPWRGD 4 Frequency Select pins which have tri-level input 5 If present, not all parts have this feature. 10 10 5.5 0.4 ns ns V V mA 1000 ns 300 ns 100 33 kHz kHz iAMT Mode Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization IDDiAMT3.3 I DDiAMTIO I DDPD3.3 IDDPDIO Fi Lpin CIN COUT CINX TSTAB IDT® Programmable Timing Control Hub for Intel Based Systems -200 2.4 92 18 48 6 3.2 0 14.318 5 4 5 4 2.7 3.3 4 5 30 32.54 Notes 5 2 1 1 5 5 5 1 1 1602F—11/04/11 13 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet AC Electrical Characteristics - Low Power Differential Outputs, Industrial Temperature Range PARAMETER SYMBOL CONDITIONS MIN TYP MAX Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Maximum Output Voltage Minimum Output Voltage Duty Cycle CPU Skew t SLR tFLR Averaging on Averaging on Averaging on Averaging off Averaging off Averaging off Averaging off Averaging off Averaging on Averaging on 2.5 2.5 3.7 3.7 12.2 4.2 4.2 20 447 19 941 -43 49.8 35 550 140 1150 t SLVAR VSWING VXABS VXABSVAR VHIGH VLOW DCYC t SKEWCPU 300 300 -300 45 55 100 UNITS NOTES V/ns V/ns % mV mV mV mV mV % ps 2, 3 2, 3 1, 6 2 1,4,5 1,4,9 1,7 1,8 2 288 350 ps SRC Skew t SKEWSRC Averaging on, SRC to SATA skew when Byte0, bit 1 = 0 NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). CL = 2pF, Rs = 0 ohms. 1 Measurement taken for single ended waveform on a component test board (not in system) 2 Measurement taken from differential waveform on a component test board. (not in system) 3 Slew rate measured through mimimum V_swing voltage range centered about differential zero 4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) 5 Only applies to the differential rising edge (Clock rising, Clock# falling) 6 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage 7 The max voltage including overshoot. 8 The min voltage including undershoot. 9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/max (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute Clock Jitter Specifications - Low Power Differential Outputs, Industrial Temperature Range PARAMETER SYMBOL CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle SATA Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPUJC2C SRCJC2C SATAJ C2C DOTJC2C t jphasePLL CONDITIONS MIN TYP MAX Differential Measurement 55 85 Differential Measurement 55 125 Differential Measurement 55 125 Differential Measurement 55 250 PCIe Gen 1 45 86 PCIe Gen 2 2 3 t jphaseLo SRC Phase Jitter 10kHz < f < 1.5MHz PCIe Gen 2 2.6 3.1 tjphaseHigh 1.5MHz < f < Nyquist (50MHz) NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). CL = 2pF, Rs = 0 ohms. UNITS NOTES ps ps ps ps ps (p-p) ps (RMS) ps (RMS) 1 1 1 1 1,2,3 1,2,3 1,2,3 1 JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured in a real system. 2 Phase jitter requirement: The designated Gen2 outputs will meet the reference clock jitter requirements from the PCI Express Gen2 Base Spec. The test is performed on a component test board under quiet conditions with all outputs on. 3 See http://www.pcisig.com for complete specs IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 14 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Electrical Characteristics - REF-14.318MHz, Industrial Temperature Range PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time SYMBOL ppm Tperiod Tabs THIGH TLOW CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal MIN TYP MAX UNITS -100 0 100 ppm 69.82033 69.84129 69.86224 ns 69.83400 70.84800 ns 29.97543 38.46654 V 29.57543 38.26654 V VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, Output Low Current IOL VOL @MAX = 0.4 V Rising/Falling Edge Slew Rate t SLEW Measured between 0.8 to 2.0 V Duty Cycle dt1 VT = 1.5 V Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Edge rate in system is measured from 0.8V to 2.0V at default slew rate control setting. Output High Current IOH -33 -33 mA 30 38 mA 1.8 52.8 122 4 55 500 V/ns % ps 1 2 2 TYP MAX 50 UNITS Notes 1,2 1 45 2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V 3 The average period over any 1us period of time 4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequency is 14.318180 MHz Notes 2, 4 2, 3 2 Electrical Characteristics - 27MHz_Spread / 27MHz_NonSpread, Industrial Temperature Range PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values Clock period Tperiod 27.000M outputs, 27M SS with SS OFF VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, Output Low Current IOL VOL @MAX = 0.4 V Measured between 0.8 to 2.0 V Rising/Falling Edge Slew Rate t SLEW VT = 1.5 V Duty Cycle dt1 t ltj Long Term (10us) Jitter, 27MHz_NonSpread Output VT = 1.5 V t jpk-pk VT = 1.5 V t jcyc-cyc VT = 1.5 V SS% <= 1.5% pk to pk Jitter, 27MHz_Spread Output t jcyc-cyc VT = 1.5 V, SS% > 1.5% pk to pk NOTES: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Edge rate in system is measured from 0.8V to 2.0V at default slew rate control setting. Output High Current I OH MIN -50 15 37.0365 37.0376 -29 -23 mA 29 27 mA 4 55 800 100 120 200 200 V/ns % ps ps ps ps ps 1 45 2 50.4 485 -100 57 108 140 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF out is at 14.31818MHz 3 At nominal temperature and voltage. 4 Long term and peak to peak jitter do not apply to the 27MHz spreading output. The spread modulation directly impacts these values. IDT® Programmable Timing Control Hub for Intel Based Systems ppm -15 1,2,3 1 4 4 1602F—11/04/11 15 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Single Ended Outputs Test Load Zo Rs CL=5pF Zo Rs CL=5pF Zo Rs CL=5pF Suggested Suggested termination resistors for various driving conditions are as follows for transmission lines with Zo = 50 ohms: REF Output 27M SS and Non-SS outputs Driving 1 load, Rs = 39 ohms Driving 2 loads, Rs = 22 ohms Driving 1 load, Rs = 39 ohms Driving 2 loads, Rs = 22 ohms IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 16 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window Symbol 1us 0.1s 0.1s 0.1s 1us 1 Clock SRC 100 9.87400 9.99900 9.99900 +SSC + c-c jitter + ppm error Long-Term Short-term Absolute Period Average Average Period Nominal Maximum Maximum Maximum Units Notes 10.00000 10.00100 10.05130 10.17630 ns 1,2 CPU 100 9.91400 9.99900 9.99900 10.00000 10.00100 10.05130 10.13630 ns 1,2 CPU 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2 CPU 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2 CPU 200 4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2 CPU 266 3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2 CPU 333 2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2 CPU 400 2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2 1us 1 Clock Definition Signal Name 1 Clock - c-c jitter -SSC -ppm error Absolute Short-term Long-Term Average Period Average Minimum Minimum Minimum 0ppm Clock Periods Differential Outputs with Spread Spectrum Disabled Measurement Window Symbol 1us 0.1s 0.1s 0.1s SRC 100 9.87400 9.99900 + ppm error +SSC + c-c jitter Long-Term Short-term Absolute Period Average Period Average Nominal Maximum Maximum Maximum Units Notes 10.00000 10.00100 10.17630 ns 1,2 CPU 100 9.91400 9.99900 10.00000 10.00100 10.13630 ns 1,2 CPU 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2 CPU 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2 CPU 200 4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2 CPU 266 3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2 CPU 333 2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2 CPU 400 2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2 DOT 96 10.16560 10.41560 10.41670 10.41770 10.66770 ns 1,2 Definition Signal Name 1 Clock - c-c jitter -SSC -ppm error Absolute Short-term Long-Term Average Period Average Minimum Minimum Minimum 0ppm Notes: 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 17 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Test Clarification Table HW Comments Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control SW FSLC/ TEST_SEL HW PIN FSLB/ TEST_MODE HW PIN TEST ENTRY BIT B9b3 REF/N or HI-Z B9b4 <2.0V >2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N <2.0V X 1 0 HI-Z <2.0V X 1 1 REF/N B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z) IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 18 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL A A1 A3 b e DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.20 Reference 0.18 0.3 0.50 BASIC SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. Marking Diagrams ICS RS3187BL YYWW COO LOT ICS 32L TOLERANCE 32 8 8 5.00 x 5.00 3.0/ 3.3 3.0/ 3.3 0.30 / 0.50 ICS S3187BIL YYWW COO LOT Ordering Information Part / Order Number 9LRS3187BKLF 9LRS3187BKLFT 9LRS3187BKILF 9LRS3187BKILFT Shipping Package Tubes Tape and Reel Tubes Tape and Reel Package 32-pin MLF 32-pin MLF 32-pin MLF 32-pin MLF Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “B” is the device revision designator (will not correlate to the datasheet revision). IDT® Programmable Timing Control Hub for Intel Based Systems 1602F—11/04/11 19 ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Revision History A B C D E F 04/13/10 04/15/10 06/02/10 10/01/10 04/29/11 11/04/11 RDW RDW LPL LPL RDW DC Released to final Revised Commercial and Industrial Electrical Tables for Consistency Added Features bullet: Meets PCIe Gen2 Specifications Updated pins 1/2 descriptions Updated marking diagrams Updated CPU/SRC specs under Key Specifications 1 2 19 1 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 20