Power Sequencing in Distributed Power Applications: Sequenced Turn-on of Seven DC/DC Power Supplies with Latched Shutdown ® Application Note April 26, 2005 AN161.0 Author: Carlos Martinez resequencing requires a separate reset signal or the main supply to be cycled off, then on. It is becoming more common today to see many different power supplies in a system. There can be from 3 to 7 or more different DC/DC controllers. This is typically the result of the proliferation of new microprocessors, ASICs and FPGAs, each with their own variety of power supply voltages and power sequencing requirements. The X80140 provides a selectable delay for each supply. The options are 100ms, 500ms, 1s, and 5s. Sequencing seven supplies requires a minimum of 700ms (plus the turn on time for each supply.) The eighth voltage monitor in the circuit is used as a watchdog timer (WDT). This timer starts when the master (first) voltage is applied. For the circuit to work, the timer is set to 1 second or 5 seconds. If the WDT (ViGDO) output goes active before all of the supplies have reached their proper level, then one or both of the RESET outputs will be active. In this event, the latch is clocked and the MR pins are pulled HIGH, turning off all supplies. With the WDT set to 5 seconds there is some flexibility in the individual turn on delays. With the WDT set to 1 second, all delay times will likely need to be set to 100ms. In this application, two X80140 quad sequencers (See Figure 1) are used to sequence seven DC/DC converters (See Figure 2). The X80140 devices monitor the output of each DC/DC converter. After the supply reaches a minimum operating level, the X80140 powers up the next supply after a fixed delay. When all supplies have reached their proper level, the RESET outputs go inactive (HIGH) (See Figure 3 for timing). Because of the way the voltage monitors are configured, the failure of any one supply causes either of the two reset outputs to become active. This triggers the latch, which pulls the MR pin on both devices LOW, thus turning off all supplies. To allow RESET VCC Reset Logic and Delay POR Control and Fault Registers MR Bus Interface SDA VSS SCL WP A0 A1 EEPROM 2kbits VP OSC VMON Logic V1MON Divider Reset 4 VREF1 V2MON VREF2 VSS 4 V1GDO Select 0.1s 0.5s 1s 5s V2GDO delay1 V3MON V3GDO delay2 VREF3 V4MON VREF4 delay3 Delay circuit repeated 4 times VSS V4GDO delay4 VSS FIGURE 1. X80140 BLOCK DIAGRAM 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 161 5V Power Supply On/Off 3.3V Power Supply On/Off 1.2V Power Supply On/Off 1.8V Power Supply On/Off 2.5V Power Supply On/Off 1.2V Power Supply On/Off 1.8V Power Supply On/Off 2.5V 1 2 3 4 5 6 Note: Power supply #7 is not monitored if V4MON is used as a WDT. 7 X80140/41/42/43 V4GDO V4MON V3GDO V3MON V2GDO V2MON V1GDO V1MON RESET A0 SCL SCA VCC MR X80140/41/42/43 V4GDO V4MON V3GDO V3MON 5V 74HC76 V2GDO V2MON K RESET A0 SCL SCA VCC Q J 1 V1GDO V1MON Q C P MR 5V 74HC4078 5V K Q J 2 Q Reset C P SCL SDA FIGURE 2. EXAMPLE OF RELAY POWER SUPPLY SEQUENCING 2 AN161.0 April 26, 2005 Application Note 161 V1MON tDELAY1 V1MON threshold Timing Not To Scale 100ms 500ms 1sec Example: 7 Independent Power Supplies in relay timing Programmable Delay Power Supply #2 ON V1GDO Power Supply #2 OUTPUT tDELAY2 V2MON 100ms threshold 500ms 1sec Programmable Delay Power Supply #3 ON V2GDO Power Supply #3 OUTPUT V3MON threshold tDELAY3 100ms 500ms 1sec Programmable Delay Power Supply #4 ON V3GDO Power Supply #n-1 ON Vn-1GDO Power Supply #n OUTPUT VnMON threshold tDELAYn 100ms 500ms 1sec Programmable Delay Power Supply #n ON VnGDO RESET1 RESET2 RESET “Wire” AND (J-K FF #1 clock) Q1 MR Assume WDT times out before supplies are good WDT (V4GDO) also J-K FF#2 clock Q2 MR FIGURE 3. RELAY SEQUENCING OF DC/DC SUPPLIES. (TIMING) Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN161.0 April 26, 2005