Power On Conditions for the X9258 ® Application Note April 26, 2005 AN162.0 Introduction VCC Supply Quality The process of powering up a part like the X9258 can be challenging. There are up to five different supply voltages connected to the part. Because of the protection mechanisms built into the device there is a lot of flexibility in how the supplies power-up. However, not all possible power supply conditions can be handled internally. The following conditions are highly recommended for proper POR: The power supply issue is complicated further, because as the various voltages are applied to the part, initial conditions are being recalled from internal registers. These recalled values set the wiper position and initialize of the serial interface circuit. There are two main failure conditions that result from improper power on sequencing. These are: 1. Damage to the device due to latchup caused by reverse voltage application. 2. Improper Power On Recall (POR) of initial conditions. This document explores the failure mechanisms and recommends conditions for consistent device operation. Power Supply Limits The following conditions are specified in the data sheet and MUST be observed. Failure to follow these recommendations can result in device failure or improper Power On Reset (POR). 1. The V- supply is NOT to go more positive than VSS by more than 0.5V at ANY time. 1. The VCC supply should power up with a maximum ramp rate 50V/ms and minimum ramp rate of 0.2V/ms (as per the data sheet). See Figure 2. 2. The voltage ramp on VCC should be monotonic (does not reverse direction) and contain no noise greater than 100mV. See Figure 3. 3. Noise or voltage direction changes are especially significant when VCC is in the range of 1.9 to 2.4V. See Figure 4. 4. If the voltage on VCC reaches 1.9 to 2.4V, but has not reached 2.7V, and then falls to less than 1V, it must recover to 2.4V within 1ms or remain below 1V for more than 10ms. This is a "brownout" condition. A brown-out condition that happens before VCC reaches the 1.9 to 2.4V region or when VCC is greater than 2.7V always retains the proper configuration. See Figure 4. NOTES: It is possible for devices to function properly while violating one or more of these recommendations. However, these conditions are recommended to provide proper POR over a wide range of environmental, system and fabrication variations. Power Supply Sequencing Starting with all VCC, V-, V+ and VSS at 0V. For proper POR, the recommended power on sequence is: 1. VSS. 2. V-. VL can be connected to V- and power up simultaneously with V-. 2. The V+ supply is NOT to go more negative than VSS by more than -0.5V at ANY time. 3. VCC. 3. The VCC supply is NOT to go more negative than VSS by more than -0.5V at ANY time. 4. V+. VH can be connected to V+ and power up simultaneously with V+. NOTES: It is advised that the excursions above be limited to <0.3V if possible to minimize leakage effects. If any of the above situations is possible, then it is highly recommended that a clamping diode (schottky required) be added to the circuit to protect the DCP device and any other devices connected to that supply. 5. VW, VL and VH (Potentiometer Voltages) last. VL and VH can power up earlier as indicated above. 6. V- should be at least -2.7V as VCC reaches 2V. If not, the POR circuit is more susceptable to VCC noise and VCC power-up brown-out conditions. See Figure 5. 7. VCC and V+ should be greater than 2V within 100ms of Vreaching the maximum value of V-. This condition has not been known to cause POR issues, but it can stress the device as the result of improper biasing. See Figure 6. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 162 NOTES: It may be possible to power up V+, V- and VCC simultaneously, or in other sequences, if VCC Supply Quality conditions are met. X9258 V+ If the power sequencing cannot be guaranteed, then it is important to do the following: • Add resistors to VH, VL and VW to limit the current to less than 10mA into any of the terminals as shown in Figure 1. • Make sure that the VCC power supply is a clean, monotonic ramp that meets the specified ramp rate conditions. Supplemental Information V- must go to a negative value first because this controls the substrate voltage, which must be stable prior to the VCC turn on. This is because the Power on Recall circuit, which recalls the E2 memory contents, has a VCC trip point of about 2.2 volts when V- is in the range of -2.7 to -5.0 volts. But if V- is at 0 volts then the POR trip point drops from 2.2 volts to about 1.9 volts and the recall operation happens at a voltage that is lower than the design value. Also, an unasserted V- input can be pulled above VSS by the application of the V+ supply in some applications, increasing the chance of incorrect wiper recall. VCC must turn on 2nd with a ramp rate between 0.2V/ms and 50V/ms. This is required because the POR operation must be performed to set the correct wiper position before power is applied to the DCP pins (VH and VL). Otherwise the wiper setting could be unknown, allowing possibly excessive currents to flow between the DCP pins and the external circuits. If the ramp rate is too slow, the POR occurs when VCC is too low and the wiper data may be recalled incorrectly. If the ramp rate is too fast, the POR circuit responds before the internal circuits have had a chance to “charge up”, again causing a recall when the voltage internal to the device is too low. V+ should turn on after VCC powers up because the correct wiper position will have been recalled, leaving no chance of a transient erroneous wiper setting. VH, VL and VW voltages are generally applied last (with the exceptions noted above). This will assure a uniform poweron at the correct wiper setting and no stress on the internal circuits. VH R* VW R* VL R* VH’ VW’ VL’ V- NOTE: If the power-on sequence cannot be controlled, resistors are required to protect against a worst case condition, where VH’, VL’ or VW’ experience voltage levels that reach V+ or V-. Current should be limited to 10mA, so a 270Ω resistor is required for V+/V- of 2.7V and a 500Ω resistor is required for V+/V- of 5V. FIGURE 1. X9258 INTERNAL PROTECTION DIODES VH, VL, VW If these pins are powered out of sequence, and there are no current limiting resistors, then it is possible to forward bias a PN junction on the chip (which should always be reverse biased). If this occurs, damage to the chip can occur. VIf V- powers up more than 100ms before VCC and V+, then internal biasing causes the un-controlled wiper selection FETs to partially turn on. This causes current leakage between V+ and V-. Improper sequencing can cause these general issues: 8. Permanent damage which appears to be a stuck wiper position that can't be moved or set properly. 9. An SCR latchup condition which can cause large transient currents resulting in permanent damage to the device. 10. Improper recall of the non-volatile wiper setting and in rare cases improper initialization of the serial port. 11. Long term degradation of internal circuits with unknown failure mechanisms. Incorrect Sequencing Issues The X9258 has protection diodes on each of the supplies as shown in Figure 1. 2 AN162.0 April 26, 2005 Fast Ram p (50V/ms) Application Note 162 VCC Proper Operating s) Range V /m 2 . (0 mp Ra w Slo VCC 100mV 100mV V2 = VCC(t2) V1 V2 VSS VSS V1 = VCC(t1) t2 > t1 + 1ms t1 t2 FIGURE 3. VCC MONOTONICITY AND NOISE RESTRICTIONS FIGURE 2. VCC RISE TIME Incorrect POR Not Possible Incorrect POR Possible VCC 2.5V VCC POR errors possible if VCC noise and VCC Power-up Brown-out limits exceeded 2V 0V 2.4V 1.9V 1.0V -2.7V VSS 1ms max. Recommended. POR not affected by VCC Power-up Brownout 10ms min. FIGURE 4. VCC POWER-ON BROWN-OUT CONDITION V- FIGURE 5. V-/VCC POWER-ON TIMING VCC and V+ 0V 2V 100ms max. VFIGURE 6. V-/VCC/V+ Power-on Timing Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN162.0 April 26, 2005