IRDC3842W SupIRBuck TM USER GUIDE FOR IR3842W EVALUATION BOARD DESCRIPTION The IR3842W is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 5mmx6mm Power QFN package. An output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance. Key features offered by the IR3842W include programmable soft-start ramp, precision 0.7V reference voltage, Power Good, thermal protection, programmable switching frequency, Sequence input, Enable input, input under-voltage lockout for proper start-up, and pre-bias start-up. This user guide contains the schematic and bill of materials for the IR3842W evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3842W is available in the IR3842W data sheet. BOARD FEATURES • Vin = +12V (13.2V Max) • Vcc=+5V (5.5V Max) • Vout = +1.8V @ 0- 4A • Fs=600kHz • L= 1.5uH • Cin= 2x10uF (ceramic 1206) + 330uF (electrolytic) • Cout= 4x22uF (ceramic 0805) 10/27/2009 1 IRDC3842W CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 4A load should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IR3842W has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate supplies should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it would be connected to Vcc+ and Vcc-. If single 12V application is required connect R7 (zero Ohm resistor) which enables the on board bias regulator (see schematic). In this case there is no need of external Vcc supply. The output can track a sequencing input at the start-up. For sequencing application, R16 should be removed and the external sequencing source should be applied between Seq. and Agnd. The value of R14 and R28 can be selected to provide the desired ratio between the output voltage and the tracking input. For proper operation of IR3842W, the voltage at Seq. pin should not exceed Vcc. Table I. Connections Connection Signal Name VIN+ Vin (+12V) VIN- Ground of Vin Vcc+ Vcc input Vcc- Ground for Vcc input VOUT- Ground of Vout VOUT+ Vout (+1.8V) Enable Enable Seq. Sequence Input P_Good Power Good Signal LAYOUT The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3842W SupIRBuck and all of the passive components are mounted on the top side of the board. Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located close to IR3842W. The feedback resistors are connected to the output voltage at the point of regulation and are located close to the SupIRBuck. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 10/27/2009 2 IRDC3842W Connection Diagram Vin GND Enable GND Seq AGND Vo PGood SS Vcc GND Fig. 1: Connection diagram of IR384xW evaluation boards 10/27/2009 3 IRDC3842W Fig. 2: Board layout, top overlay Fig. 3: Board layout, bottom overlay (rear view) 10/27/2009 4 IRDC3842W PGND Plane Single point connection between AGND and PGND. AGND Plane Fig. 4: Board layout, mid-layer I. Fig. 5: Board layout, mid-layer II. 10/27/2009 5 Vcc- PGood 1 1 R17 10K Vcc+ R14 N/S 1 VCC R28 N/S R16 0 C11 150pF Agnd C26 R1 3.09K 5600pF R9 23.7K 1 SS C10 0.1uF 7 6 5 4 3 2 Seq1 R19 7.50k 1 IR3842W R3 2.49K 130 R4 C13 0.1uF VCC 3.92K R2 PGnd SW Vin 49.9K R18 10 11 12 A R12 1.82k B 0 R* L1 1.5uH Vin C30 N/S R7 N/S C29 N/S C7 0.1uF Ground and Signal ( “analog” ) Ground Single point of connection between Power R6 20 C8 2200pF PGND 0.1uF C24 1 Fig. 6: Schematic of the IR3842W evaluation board OCset SS Rt AGnd COMP FB Seq U1 C25 N/S 13 Boot 1 14 En PGood 8 Vcc 9 AGnd1 15 1 Enable 1 VCC 1 Seq. C21 N/S C28 N/S + C19 N/S C4 N/S C3 10uF C2 10uF + Optional +5V supply for Vcc D1 MM3Z5V6B C36 N/S Vcc C18 C17 C16 22uF 22uF 22uF Q1 MMBT3904-TP C35 N/S C20 N/S C5 N/S C32 0.1uF R5 3.30K C22 N/S C27 N/S C6 N/S 2 10/27/2009 1 C34 10uF C15 22uF + C1 330uF 1 1 1 1 1 1 1 1 C14 0.1uF Vout Vin Vout- Vout- Vout+ Vout+ Vin- Vin- Vin+ Vin+ IRDC3842W 6 IRDC3842W Bill of Materials Item Quantity Part Reference 1 2 3 4 5 6 1 2 1 6 1 1 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 4 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 C1 C3 C2 C34 C7 C10 C13 C14 C24 C32 C8 C11 C15 C16 C17 C18 C26 D1 L1 Q1 R5 R18 R4 R6 R9 R16 R12 R3 R17 R19 R1 R2 U1 10/27/2009 Value Description Manufacturer Part Number 330uF 10uF 10uF 0.1uF 2200pF 150pF SMD Elecrolytic, Fsize, 25V, 20% 1206, 16V, X5R, 20% 0805, 10V, X5R, 20% 0603, 25V, X7R, 10% 0603, 50V, NP0, 5% 0603, 50V, NP0, 5% Panasonic Panasonic - ECG Panasonic - ECG Panasonic - ECG Murata Panasonic- ECG EEV-FK1E331P ECJ-3YB1C106M ECJ-GVB1A106M ECJ-1VB1E104K GRM1885C1H222JA01D ECJ-1VC1H151J 22uF 5600pF MM3Z5V6B 1.5uH MMBT3904/SOT 3.3k 49.9k 130 20 23.7k 0 1.82k 2.49k 10.0k 7.50k 3.09k 3.92k IR3842W 0805, 6.3V, X5R, 20% 0603, 50V, X7R, 10% MM3Z5V6B,Zener, 5.6V 11.5x10x4mm, 20%, 3.8mOhm NPN, 40V, 200mA, SOT-23 Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10 W,5% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% PQFN 6mmx5mm, 4A SupIRBuck Panasonic- ECG Panasonic - ECG Fairchild Delta Fairchild Rohm Rohm Panasonic - ECG Vishey/Dale Rohm Vishay/Dale Rohm Rohm Rohm Rohm Rohm Rohm International Rectifier ECJ-2FB0J226M ECJ-1VB1H562K MM3Z5V6B MPO104-1R5 MMBT3904/SOT MCR03EZPFX3301 MCR03EZPFX4992 ERJ-3EKF1300V CRCW060320R0FKEA MCR03EZPFX2372 CRCW06030000Z0EA MCR03EZPFX1871 MCR03EZPFX2491 MCR03EZPFX1002 MCR03EZPFX7501 MCR03EZPFX3091 MCR03EZPFX3921 IR3842WMPbF 7 IRDC3842W TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-4A, Room Temperature, No Air Flow Fig. 17. Start up at 4A Load Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:Enable Fig. 18. Start up at 4A Load, Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:VPGood Fig. 19. Start up with 1.62V Pre Bias, 0A Load, Ch2:Vo, Ch3:VSS Fig. 20. Output Voltage Ripple, 4A load Ch2: Vo Fig. 21. Inductor node at 4A load Ch2:LX Fig. 22. Short (Hiccup) Recovery Ch2:Vo , Ch3:VSS 10/27/2009 8 IRDC3842W TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=0-4A, Room Temperature, No Air Flow Fig. 23. Transient Response, 2A to 4A step 2.5A/s Ch2:Vo, Ch4:Io 10/27/2009 9 IRDC3842W TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow Fig. 24. Bode Plot at 4A load shows a bandwidth of 98kHz and phase margin of 53 degrees 10/27/2009 10 IRDC3842W TYPICAL OPERATING WAVEFORMS Vin=12V, Vo=1.8V, Io=0- 4A, Room Temperature, No Air Flow 93 92 91 Efficiency (%) 90 89 88 87 86 85 84 83 10 20 30 40 50 60 70 80 90 100 90 100 Load Percentage (%) Fig.15: Efficiency versus load current 0.70 0.65 0.60 Power Loss (W) 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 10 20 30 40 50 60 70 80 Load Percentage(%) Fig.16: Power loss versus load current 10/27/2009 11 IRDC3842W THERMAL IMAGES Vin=12V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow Fig. 17: Thermal Image at 4A load Test points 1 and 2 are IR3842W and inductor, respectively. 10/27/2009 12 IRDC3842W Simultaneous Tracking at Power Up and Power Down Vin=12V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow In order to run the IR3842W in the simultaneous tracking mode, the following steps should be taken: - Remove R16 from the board. - Set the value of R14 and R28 as R2 (3.92K) and R3 (2.49K), respectively. - Connect the controlling input across SEQ and AGND test points on the board. This voltage should be at least 1.15 time greater than Vo. For the following test results a 0-3.3V source is applied to SEQ input. - The controlling input should be applied after the SS pin is clamped to 3.0V. Fig. 18: Simultaneous Tracking a 3.3V input at power-up and shut-down Ch2: SEQ Ch3:Vout Ch4: SS 10/27/2009 13 IRDC3842W PCB Metal and Components Placement The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper. 10/27/2009 IRDC3842W Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. 10/27/2009 IRDC3842W Stencil Design • • The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. 10/27/2009 IRDC3842W BOTTOM VIEW IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 11/07 10/27/2009