Low Cost Multi-Chemistry Battery Charger Controller ISL6251, ISL6251A Features The ISL6251, ISL6251A is a highly integrated battery charger controller for Li-Ion/Li-Ion polymer batteries and NiMH batteries. High efficiency is achieved by a synchronous buck topology and the use of a MOSFET, instead of a diode, for selecting power from the adapter or battery. The low side MOSFET emulates a diode at light loads to improve the light load efficiency and prevent system bus boosting. • ±0.5% Charge Voltage Accuracy (-10°C to +100°C) The constant output voltage can be selected for 2, 3 and 4 series Li-Ion cells with 0.5% accuracy over-temperature. It can be also programmed between 4.2V+5%/cell and 4.2V-5%/cell to optimize battery capacity. When supplying the load and battery charger simultaneously, the input current limit for the AC adapter is programmable to within 3% accuracy to avoid overloading the AC adapter, and to allow the system to make efficient use of available adapter power for charging. It also has a wide range of programmable charging current. The ISL6251, ISL6251A provides outputs that are used to monitor the current drawn from the AC adapter, and monitor for the presence of an AC adapter. The ISL6251, ISL6251A automatically transitions from regulating current mode to regulating voltage mode. PART NUMBER (Notes 1, 2, 3) PART MARKING • ±3% Accurate Battery Charge Current Limit • ±25% Accurate Battery Trickle Charge Current Limit (ISL6251A) • Programmable Charge Current Limit, Adapter Current Limit and Charge Voltage • Fixed 300kHz PWM Synchronous Buck Controller with Diode Emulation at Light Load • Output for Current Drawn from AC Adapter • AC Adapter Present Indicator • Fast Input Current Limit Response • Input Voltage Range 7V to 25V • Supports 2, 3 and 4 Cells Battery Pack • Up to 17.64V Battery-Voltage Set Point • Thermal Shutdown • Support Pulse Charging • Less than 10µA Battery Leakage Current Ordering Information TEMP RANGE (°C) • ±3% Accurate Input Current Limit • Charge Any Battery Chemistry: Li-Ion, NiCd, NiMH, etc. PACKAGE (Pb-Free) PKG. DWG. # • Pb-Free (RoHS Compliant) Applications ISL6251HRZ ISL 6251HRZ -10 to +100 28 Ld 5x5 QFN L28.5×5 • Notebook, Desknote and Sub-notebook Computers ISL6251HAZ ISL 6251HAZ -10 to +100 24 Ld QSOP • Personal Digital Assistant M24.15 ISL6251AHRZ ISL6251 AHRZ -10 to +100 28 Ld 5x5 QFN L28.5×5 ISL6251AHAZ ISL6251 AHAZ -10 to +100 24 Ld QSOP M24.15 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6251, ISL6251A. For more information on MSL please see techbrief TB363. March 13, 2014 FN9202.3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2006, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL6251, ISL6251A Pin Configurations ISL6251, ISL6251A (28 LD QFN) ISL6251, ISL6251A (24 LD QSOP) TOP VIEW EN NA ACSET VDD DCIN NA ACPRN CSON TOP VIEW 28 27 26 25 24 23 22 1 21 VDD 1 24 DCIN ACSET 2 23 ACPRN EN 3 22 CSON CSOP CELLS 4 21 CSOP ICOMP 5 20 CSIN VCOMP 6 19 CSIP ICM 7 18 PHASE 17 UGATE CELLS 2 20 CSIN ICOMP 3 19 CSIP VCOMP 4 18 NA VREF 8 ICM 5 17 NA CHLIM 9 16 BOOT ACLIM 10 15 VDDP VADJ 11 14 LGATE GND 12 13 PGND 8 9 10 11 12 13 14 BOOT UGATE VDDP 15 LGATE CHLIM 7 PGND PHASE GND 16 VADJ 6 ACLIM VREF Submit Document Feedback 2 FN9202.3 March 13, 2014 ISL6251, ISL6251A Absolute Maximum Ratings Thermal Information DCIN, CSIP, CSON to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V PHASE to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-7V to 30V BOOT to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +35V ACLIM, ACPRN, CHLIM, VDD to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V ICM, ICOMP, VCOMP to GND . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT+0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP+0.3V Thermal Resistance θJA(°C/W) θJC (°C/W) QFN Package (Notes 5, 7) . . . . . . . . . . . . . . 39 9.5 QSOP Package (Note 6). . . . . . . . . . . . . . . . 88 N/A Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-10°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. When the voltage across ACSET is below 0V, the current through ACSET should be limited to less than 1mA. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 8. BOOT-PHASE voltage is -0.3V to -0.7V during start-up. This is due to a small current (<1mA) that flows from the battery to the PHASE pin and to an internal current sink on the BOOT pin through an internal diode. This does not harm the part. Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA, TA = -10°C to +100°C, TJ ≤ 125°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -10°C to +100°C. PARAMETER TEST CONDITIONS MIN (Note 10) MAX (Note 10) UNITS 25 V 1.4 3 mA 3 10 µA 4.925 5.075 5.225 V TYP SUPPLY AND BIAS REGULATOR DCIN Input Voltage Range 7 DCIN Quiescent Current EN = VDD or GND, 7V ≤ DCIN ≤ 25V Battery Leakage Current (Note 9) DCIN = 0, no load VDD Output Voltage/Regulation 7V ≤ DCIN ≤ 25V, 0 ≤ IVDD ≤ 30mA VDD Undervoltage Lockout Trip Point VDD Rising 4.0 4.4 4.6 V Hysteresis 200 250 400 mV 2.365 2.39 2.415 V Reference Output Voltage VREF 0 ≤ IVREF ≤ 300µA Battery Charge Voltage Accuracy CSON = 16.8V, CELLS = VDD, VADJ = Float -0.5 0.5 % CSON = 12.6V, CELLS = GND, VADJ = Float -0.5 0.5 % CSON = 8.4V, CELLS = Float, VADJ = Float -0.5 0.5 % CSON = 17.64V, CELLS = VDD, VADJ = VREF -0.5 0.5 % CSON = 13.23V, CELLS = GND, VADJ = VREF -0.5 0.5 % CSON = 8.82V, CELLS = Float, VADJ = VREF -0.5 0.5 % CSON = 15.96V, CELLS = VDD, VADJ = GND -0.5 0.5 % CSON = 11.97V, CELLS = GND, VADJ = GND -0.5 0.5 % CSON = 7.98V, CELLS = Float, VADJ = GND -0.5 0.5 % TRIP POINTS ACSET Threshold 1.24 1.26 1.28 V ACSET Input Bias Current Hysteresis 2.2 3.4 4.4 µA 2.2 3.4 4.4 µA ACSET ≥ 1.26V ACSET Input Bias Current Submit Document Feedback 3 FN9202.3 March 13, 2014 ISL6251, ISL6251A Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA, TA = -10°C to +100°C, TJ ≤ 125°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued) PARAMETER TEST CONDITIONS ACSET Input Bias Current ACSET < 1.26V MIN (Note 10) TYP MAX (Note 10) UNITS -1 0 1 µA 245 300 355 kHz OSCILLATOR Frequency PWM Ramp Voltage (Peak-Peak) CSIP = 18V 1.6 V CSIP = 11V 1 V SYNCHRONOUS BUCK REGULATOR Maximum Duty Cycle 97 99 99.6 % 3.0 Ω UGATE Pull-Up Resistance BOOT-PHASE = 5V, 500mA source current 1.8 UGATE Source Current BOOT-PHASE = 5V, BOOT-UGATE = 2.5V 1.0 UGATE Pull-Down Resistance BOOT-PHASE = 5V, 500mA sink current 1.0 UGATE Sink Current BOOT-PHASE = 5V, UGATE-PHASE = 2.5V 1.8 LGATE Pull-Up Resistance VDDP-PGND = 5V, 500mA source current 1.8 LGATE Source Current VDDP-PGND = 5V, VDDP-LGATE = 2.5V 1.0 LGATE Pull-DOWN Resistance VDDP-PGND = 5V, 500mA sink current 1.0 LGATE Sink Current VDDP-PGND = 5V, LGATE = 2.5V 1.8 A 1.8 Ω A 3.0 Ω A 1.8 Ω A CHARGING CURRENT SENSING AMPLIFIER Input Common-Mode Range 0 V 0 2.5 mV Input Offset Voltage Note 11 Input Bias Current at CSOP 0 < CSOP < 18V 0.25 2 µA Input Bias Current at CSON 0 < CSON < 18V 75 100 µA 3.6 V CHLIM Input Voltage Range -2.5 18 0 CSOP to CSON Full-Scale Current Sense Voltage ISL6251: CHLIM = 3.3V 157 165 173 mV ISL6251A, CHLIM = 3.3V 160 165 170 mV ISL6251: CHLIM = 2.0V 95 100 105 mV ISL6251A: CHLIM = 2.0V 97 100 103 mV ISL6251: CHLIM = 0.2V 5.0 10 15.0 mV ISL6251A: CHLIM = 0.2V 7.5 10 12.5 mV CHLIM Input Bias Current CHLIM = GND or 3.3V, DCIN = 0V -1 1 µA CHLIM Power-Down Mode Threshold Voltage CHLIM rising 80 88 95 mV 15 25 40 mV 7 25 V -2 2 mV CHLIM Power-Down Mode Hysteresis Voltage ADAPTER CURRENT SENSING AMPLIFIER Input Common-Mode Range Input Offset Voltage Note 11 Input Bias Current at CSIP and CSIN Combined CSIP = CSIN = 25V 100 130 µA Input Bias Current at CSIN 0 < CSIN < DCIN (Note 11) 0.10 1 µA Submit Document Feedback 4 FN9202.3 March 13, 2014 ISL6251, ISL6251A Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = 1.5V, ACLIM = VREF, VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1µF, IVDD = 0mA, TA = -10°C to +100°C, TJ ≤ 125°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued) MIN (Note 10) TYP MAX (Note 10) UNITS ACLIM = VREF 97 100 103 mV ACLIM = Float 72 75 78 mV ACLIM = GND 47 50 53 mV ACLIM = VREF 10 16 20 µA ACLIM = GND -20 -16 -10 µA PARAMETER TEST CONDITIONS ADAPTER CURRENT LIMIT THRESHOLD CSIP to CSIN Full-Scale Current Sense Voltage ACLIM Input Bias Current VOLTAGE REGULATION ERROR AMPLIFIER Error Amplifier Transconductance from CSON to VCOMP CELLS = VDD 30 µA/V Charging Current Error Amplifier Transconductance 50 µA/V Adapter Current Error Amplifier Transconductance 50 µA/V CURRENT REGULATION ERROR AMPLIFIER BATTERY CELL SELECTOR CELLS Input Voltage for 4 Cell Select 4.3 V CELLS Input Voltage for 3 Cell Select CELLS Input Voltage for 2 Cell Select 2 V 2.1 4.2 V 0 VDD V V LOGIC INTERFACE EN Input Voltage Range EN Threshold Voltage Rising 1.030 1.06 1.100 Falling 0.985 1.000 1.025 V Hysteresis 30 60 90 mV EN Input Bias Current EN = 2.5V 1.8 2.0 2.2 µA ACPRN Sink Current ACPRN = 0.4V 3 8 ACPRN Leakage Current ACPRN = 5V ICM Output Accuracy (Vicm = 19.9 x (Vcsip-Vcsin)) CSIP - CSIN = 100mV -3 CSIP - CSIN = 75mV CSIP - CSIN = 50mV 11 mA 0.5 µA 0 +3 % -4 0 +4 % -5 0 +5 % -0.5 Thermal Shutdown Temperature 150 °C Thermal Shutdown Temperature Hysteresis 25 °C NOTES: 9. This is the sum of currents in these pins (CSIP, CSIN, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN, ACSET, VADJ, CELLS, ACLIM, CHLIM. 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 11. Limits established by characterization and are not production tested. Submit Document Feedback 5 FN9202.3 March 13, 2014 ISL6251, ISL6251A Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, TA = 25°C, unless otherwise noted. 0.1 VREF LOAD REGULATION ACCURACY (%) VDD LOAD REGULATION ACCURACY (%) 0.6 VDD=5.075V EN=0 0.3 0 -0.3 -0.6 0 8 16 24 32 VREF=2.390V 0.08 0.06 0.04 0.02 0 0 40 100 200 300 400 LOAD CURRENT (µA) LOAD CURRENT (mA) FIGURE 2. VREF LOAD REGULATION FIGURE 1. VDD LOAD REGULATION 1 10 0 .9 6 8 VCSON=12.6V (3 CELLS) 0 .9 2 7 EFFICIENCY (%) | ICM ACCURACY | (%) 9 6 5 4 3 VCSON=8.4V 2 CELLS VCSON=16.8V 4 CELLS 0 .8 8 0 .8 4 0 .8 2 1 0 0 .76 10 20 30 40 50 60 70 CSIP-CSIN (mV) 80 90 100 Submit Document Feedback 6 1 1.5 2 2.5 3 3 .5 4 FIGURE 4. SYSTEM EFFICIENCY vs CHARGE CURRENT LOAD CURRENT 5A/div CSON 5V/div ADAPTER CURRENT 5A/div EN 5V/div CHARGE CURRENT 2A/div FIGURE 5. LOAD TRANSIENT RESPONSE 0 .5 CHARGE CURRENT (A) FIGURE 3. ICM ACCURACY vs AC ADAPTER CURRENT LOAD STEP: 0-4A CHARGE CURRENT: 3A AC ADAPTER CURRENT LIMIT: 5.15A 0 BATTERY VOLTAGE 2V/div INDUCTOR CURRENT 2A/div CHARGE CURRENT 2A/div FIGURE 6. CHARGE ENABLE AND SHUTDOWN FN9202.3 March 13, 2014 ISL6251, ISL6251A Typical Operating Performance INDUCTOR CURRENT 2A/div CHLIM=0.2V CSON=8V PHASE 10V/div BATTERY REMOVAL BATTERY INSERTION DCIN = 20V, 4S2P Li-Battery, TA = 25°C, unless otherwise noted. (Continued) CSON 10V/div INDUCTOR CURRENT 1A/div VCOMP 2V/div VCOMP ICOMP ICOMP 2V/div FIGURE 7. BATTERY INSERTION AND REMOVAL UGATE 5V/div FIGURE 8. SWITCHING WAVEFORMS AT DIODE EMULATION CHARGE CURRENT 1A/div PHASE 10V/div UGATE 2V/div CHLIM 1V/div LGATE 2V/div FIGURE 9. SWITCHING WAVEFORMS IN CC MODE Submit Document Feedback 7 FIGURE 10. TRICKLE TO FULL-SCALE CHARGING FN9202.3 March 13, 2014 ISL6251, ISL6251A Functional Pin Descriptions PGND BOOT PGND is the power ground. Connect PGND to the source of the low side MOSFET for the low side MOSFET gate driver. Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin and connect to the cathode of the bootstrap schottky diode. VDD UGATE VDD is an internal LDO output to supply IC analog circuit. Connect a 1μF ceramic capacitor to ground. UGATE is the high side MOSFET gate drive output. LGATE VDDP LGATE is the low side MOSFET gate drive output; swing between 0V and VDDP. VDDP is the supply voltage for the low-side MOSFET gate driver. Connect a 4.7Ω resistor to VDD and a 1μF ceramic capacitor to power ground. PHASE ICOMP The Phase connection pin connects to the high side MOSFET source, output inductor, and low side MOSFET drain. ICOMP is a current loop error amplifier output. CSOP/CSON VCOMP VCOMP is a voltage loop amplifier output. CSOP/CSON is the battery charging current sensing positive/negative input. The differential voltage across CSOP and CSON is used to sense the battery charging current, and is compared with the charging current limit threshold to regulate the charging current. The CSON pin is also used as the battery feedback voltage to perform voltage regulation. CSIP/CSIN CSIP/CSIN is the AC adapter current sensing positive/negative input. The differential voltage across CSIP and CSIN is used to sense the AC adapter current, and is compared with the AC adapter current limit to regulate the AC adapter current. GND CELLS This pin is used to select the battery voltage. CELLS = VDD for a 4S battery pack, CELLS = GND for a 3S battery pack, CELLS = Float for a 2S battery pack. VADJ VADJ adjusts battery regulation voltage. VADJ = VREF for 4.2V+5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND for 4.2V-5%/cell. Connect to a resistor divider to program the desired battery cell voltage between 4.2V-5% and 4.2V+5%. CHLIM CHLIM is the battery charge current limit set pin. CHLIM input voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the set point for CSOP-CSON is 165mV. The charger shuts down if CHLIM is forced below 88mV. GND is an analog ground. DCIN The DCIN pin is the input of the internal 5V LDO. Connect it to the AC adapter output. Connect a 0.1μF ceramic capacitor from DCIN to PGND. ACSET ACSET is an AC adapter detection input. Connect to a resistor divider from the AC adapter output. ACPRN Open-drain output signals AC adapter is present. ACPRN pulls low when ACSET is higher than 1.26V; and pulled high when ACSET is lower than 1.26V. ACLIM ACLIM is the adapter current limit set pin. ACLIM = VREF for 100mV, ACLIM = Floating for 75mV, and ACLIM = GND for 50mV. Connect a resistor divider to program the adapter current limit threshold between 50mV and 100mV. VREF VREF is a 2.39V reference output pin. It is internally compensated. Do not connect a decoupling capacitor. EN EN is the Charge Enable input. Connecting EN to high enables the charge control function, connecting EN to low disables charging functions. Use with a thermistor to detect a hot battery and suspend charging. ICM ICM is the adapter current output. The output of this pin produces a voltage proportional to the adapter current. Submit Document Feedback 8 FN9202.3 March 13, 2014 ISL6251, ISL6251A ICM CSIP ACSET CSIN + CA1 CA1 ×19.9 + ACPRN DCIN + VREF + LDO Regulator 1.26V gm3 + gm3 - 152K 152k Adapter 1.27V Current Limit Set Adapter ACLIM 152K 152k VCOMP VADJ gm1 Voltage + Selector 2.1V + +0.25V CA2 0.25 V CA2 Voltage Selector Reference GND VDDP VCA2V CA2 PGND 1.06V - 1.065V × 20 CA2 -- CA2 + + CSON CSOP LGATE gm2 + VDD VREF PHASE PWM + VDDP 514K 514k CELLS UGATE Min Min Voltage Voltage Buffer Buffer + gm1 - VREF 514K 514k BOOT Min Current Buffer ICOMP 2.1V LDO Regulator + Current Limit Set VDD + EN CHLIM FIGURE 11. FUNCTIONAL BLOCK DIAGRAM Submit Document Feedback 9 FN9202.3 March 13, 2014 ISL6251, ISL6251A D4 AC ADAPTER R8 130k 1% D3 R9 10.2k 1% C8 0.1µF DCIN CSIP CSIP ACSET ACSET C2 0.1µF ISL6251 ISL6251, ISL6251A ISL6251A C7 1µF VDDP VDDP SYSTEM LOAD CSIN CSIN R3 18Ω R10 4.7Ω 3.3V To Host Controller BOOT BOOT C9 1µF D2 ACPRN ACPRN UGATE UGATE ICOMP ICOMP PHASE PHASE C6:6.8nF Q2 VCOMP VCOMP CHARGE ENABLE VREF R12 20k 1% Trickle Charge PGND PGND EN EN CSOP CSOP D1 Optional C3 1µF CHLIM CHLIM R11 130k 1% R4 2.2Ω L 10µH R1 40mΩ BAT+ CSON CSON ACLIM ACLIM VREF VREF Q3 LGATE LGATE VADJ VADJ 2.6A CHARGE LIMIT 253mA Trickle Charge R13 1.87k 1% Q1 C4 0.1µF R6:10k C5:10nF FLOATING 4.2V/CELL C1 10µF VDDP VDD VDD R5 100k R2 20mΩ CELLS CELLS VDD 4 CELLS Battery Pack C10 10µF BAT- ICM ICM R7: 100Ω GND GND C11 3300pF FIGURE 12. ISL6251, ISL6251A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS Submit Document Feedback 10 FN9202.3 March 13, 2014 ISL6251, ISL6251A D4 AC ADAPTER C8 0.1µF D3 R8 130k 1% R9 10.2k,1% DCIN DCIN CSIP CSIP ACSET ACSET C2 0.1µF R2 20mΩ SYSTEM LOAD VDDP VDDP C7 1µF R10 4.7Ω VCC R5 100k DIGITAL INPUT C9 1µF D/A OUTPUT OUTPUT ISL6251 ISL6251, CSIN CSIN R3: 18Ω ISL6251A ISL6251A VDD VDD BOOT BOOT D2 ACPRN ACPRN UGATE UGATE CHLIM CHLIM PHASE PHASE EN EN LGATE LGATE R7: 100Ω C11 3300pF 5.15A INPUT CURRENT LIMIT C6 6.8nF ICM ICM PGND PGND ACLIM ACLIM CSOP CSOP VCOMP VCOMP AVDD/VREF C3 1µF VREF VREF ICOMP ICOMP R6 10k Q1 C4 0.1µF D1 Optional Q2 A/D INPUT HOST C1 10µF VDDP C5 10nF L 10µH R1 40mΩ R4 2.2Ω CSON CSON CELLS CELLS BAT+ 3 CELLS C10 10µF GND GND Battery Pack VADJ VADJ R11, R12, R13 10k FLOATING 4.2V/CELL SCL SDL TEMP BAT- SCL SDL A/D INPUT GND FIGURE 13. ISL6251, ISL6251A TYPICAL APPLICATION CIRCUIT WITH MICRO-CONTROLLER Submit Document Feedback 11 FN9202.3 March 13, 2014 ISL6251, ISL6251A Theory of Operation Introduction The ISL6251, ISL6251A includes all of the functions necessary to charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10A. The ISL6251, ISL6251A has input current limiting and analog inputs for setting the charge current and charge voltage; CHLIM inputs are used to control charge current and VADJ inputs are used to control charge voltage. The ISL6251, ISL6251A charges the battery with constant charge current, set by the CHLIM input, until the battery voltage rises up to a programmed charge voltage set by VADJ input; then the charger begins to operate at a constant voltage charge mode. The EN input allows shutdown of the charger through a command from a micro-controller. It also uses EN to safely shutdown the charger when the battery is in extremely hot conditions. The amount of adapter current is reported on the ICM output. Figure 11 shows the IC functional block diagram. The synchronous buck converter uses external N-channel MOSFETs to convert the input voltage to the required charging current and charging voltage. Figure 12 shows the ISL6251, ISL6251A typical application circuit with charging current and charging voltage fixed at specific values. The typical application circuit shown in Figure 13 shows the ISL6251, ISL6251A typical application circuit, which uses a micro-controller to adjust the charging current set by CHLIM input. The voltage at CHLIM and the value of R1 sets the charging current. The DC/DC converter generates the control signals to drive two external N-channel MOSFETs to regulate the voltage and current set by the ACLIM, CHLIM, VADJ and CELLS inputs. The ISL6251, ISL6251A features a voltage regulation loop (VCOMP) and two current regulation loops (ICOMP). The VCOMP voltage regulation loop monitors CSON to ensure that its voltage never exceeds the voltage and regulates the battery charge voltage set by VADJ. The ICOMP current regulation loops regulate the battery charging current delivered to the battery to ensure that it never exceeds the charging current limit set by CHLIM; and the ICOMP current regulation loops also regulate the input current drawn from the AC adapter to ensure that it never exceeds the input current limit set by ACLIM, and to prevent a system crash and AC adapter overload. PWM Control The ISL6251, ISL6251A employs a fixed frequency PWM current mode control architecture with a feed forward function. The feed-forward function maintains a constant modulator gain of 11 to achieve fast line regulation as the buck input voltage changes. When the battery charge voltage approaches the input voltage, the DC/DC converter operates in dropout mode, where there is a timer to prevent the frequency from dropping into the audible frequency range. It can achieve a duty cycle of up to 99.6%. To prevent boosting of the system bus voltage, the battery charger operates in standard-buck mode when CSOP-CSON drops below 4.25mV. Once in standard-buck mode, hysteresis Submit Document Feedback 12 does not allow synchronous operation of the DC/DC converter until CSOP-CSON rises above 12.5mV. An adaptive gate drive scheme is used to control the dead time between two switches. The dead time control circuit monitors the LGATE output and prevents the upper side MOSFET from turning on until LGATE is fully off, preventing cross-conduction and shoot-through. In order for the dead time circuit to work properly, there must be a low resistance, low inductance path from the LGATE driver to MOSFET gate, and from the source of MOSFET to PGND. The external Schottky diode is between the VDDP pin and BOOT pin to keep the bootstrap capacitor charged. Setting the Battery Regulation Voltage The ISL6251, ISL6251A uses a high-accuracy trimmed band-gap voltage reference to regulate the battery charging voltage. The VADJ input adjusts the charger output voltage, and the VADJ control voltage can vary from 0 to VREF, providing a 10% adjustment range (from 4.2V -5% to 4.2V +5%) on CSON regulation voltage. An overall voltage accuracy of better than 0.5% is achieved. The per-cell battery termination voltage is a function of the battery chemistry. Consult the battery manufacturers to determine this voltage. • Float VADJ to set the battery voltage VCSON = 4.2V × number of the cells, • Connect VADJ to VREF to set 4.41V × number of cells, • Connect VADJ to ground to set 3.99V × number of the cells. So, the maximum battery voltage of 17.6V can be achieved. Note that other battery charge voltages can be set by connecting a resistor divider from VREF to ground. The resistor divider should be sized to draw no more than 100µA from VREF; or connect a low impedance voltage source like the D/A converter in the micro-controller. The programmed battery voltage per cell can be determined by Equation 1: (EQ. 1) VCELL = 0.175 VVADJ + 3.99 V An external resistor divider from VREF sets the voltage at VADJ according to Equation 2: R bot_VADJ || 514k V VADJ = VREF × ------------------------------------------------------------------------------------------------R top_VADJ || 514k + R || 514k (EQ. 2) bot_VADJ where Rbot_VADJ and Rtop_VADJ are external resistors at VADJ. To minimize accuracy loss due to interaction with VADJ’s internal resistor divider, ensure the AC resistance looking back into the external resistor divider is less than 25k. Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+ cells. When charging other cell chemistries, use CELLS to select an output voltage range for the charger. The internal error amplifier gm1 maintains voltage regulation. The voltage error amplifier is compensated at VCOMP. The component values shown in Figure 12 provide suitable performance for most applications. Individual compensation of the voltage regulation and currentregulation loops allows for optimal compensation. FN9202.3 March 13, 2014 ISL6251, ISL6251A power the system and prevent the AC adapter from overloading and crashing the system bus. TABLE 1. CELL NUMBER PROGRAMMING CELLS CELL NUMBER VDD 4 GND 3 Float 2 Setting the Battery Charge Current Limit The CHLIM input sets the maximum charging current. The current set by the current sense-resistor connects between CSOP and CSON. The full-scale differential voltage between CSOP and CSON is 165mV for CHLIM = 3.3V, so the maximum charging current is 4.125A for a 40mΩ sensing resistor. Other battery charge current-sense threshold values can be set by connecting a resistor divider from VREF or 3.3V to ground, or by connecting a low impedance voltage source like a D/A converter in the micro-controller. Unlike VADJ and ACLIM, CHLIM does not have an internal resistor divider network. The charge current limit threshold is given by Equation 3: 165mV V CHLIM I CHG = ------------------- ---------------------3.3V R1 (EQ. 3) To set the trickle charge current for the dumb charger, a resistor in series with a switch Q3 (Figure 12) controlled by the microcontroller is connected from CHLIM pin to ground. The trickle charge current is determined by Equation 4: 165mV V CHLIM ,trickle I CHG = ------------------- ---------------------------------------3.3V R1 (EQ. 4) When the CHLIM voltage is below 88mV (typical), it will disable the battery charger. When choosing the current sensing resistor, note that the voltage drop across the sensing resistor causes further power dissipation, reducing efficiency. However, adjusting CHLIM voltage to reduce the voltage across the current sense resistor R1 will degrade accuracy due to the smaller signal to the input of the current sense amplifier. There is a trade-off between accuracy and power dissipation. A low pass filter is recommended to eliminate switching noise. Connect the resistor to the CSOP pin instead of the CSON pin, as the CSOP pin has lower bias current and less influence on current-sense accuracy and voltage regulation accuracy. Setting the Input Current Limit The total input current from an AC adapter, or other DC source, is a function of the system supply current and the battery-charging current. The input current regulator limits the input current by reducing the charging current, when the input current exceeds the input current limit set point. System current normally fluctuates as portions of the system are powered up or down. Without input current regulation, the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using the input current limiter, the current capability of the AC adapter can be lowered, reducing system cost. The ISL6251, ISL6251A limits the battery charge current when the input current-limit threshold is exceeded, ensuring the battery charger does not load down the AC adapter voltage. This constant input current regulation allows the adapter to fully Submit Document Feedback 13 An internal amplifier gm3 compares the voltage between CSIP and CSIN to the input current limit threshold voltage set by ACLIM. Connect ACLIM to REF, Float and GND for the full-scale input current limit threshold voltage of 100mV, 75mV and 50mV, respectively, or use a resistor divider from VREF to ground to set the input current limit as shown in Equation 5: IINPUT = 1 ⎛ 0.05 ⎞ VACLIM + 0.050 ⎟ ⎜ R2 ⎝ VREF ⎠ (EQ. 5) An external resistor divider from VREF sets the voltage at ACLIM according to Equation 6: R bot_ACLIM || 152k V ACLIM = VREF × ------------------------------------------------------------------------------------------------------ (EQ. 6) R top_ACLIM || 152k + R || 152k bot_ACLIM where Rbot_ACLIM and Rtop_ACLIM are external resistors at ACLIM. To minimize accuracy loss due to interaction with ACLIM’s internal resistor divider, ensure the AC resistance looking back into the external resistor divider is less than 25k. When choosing the current sense resistor, note that the voltage drop across this resistor causes further power dissipation, reducing efficiency. The AC adapter current sense accuracy is very important. Use a 1% tolerance current-sense resistor. The highest accuracy of ±3% is achieved with 100mV current-sense threshold voltage for ACLIM = VREF, but it has the highest power dissipation. For example, it has 400mW power dissipation for rated 4A AC adapter and 1W sensing resistor may have to be used. ±4% and ±6% accuracy can be achieved with 75mV and 50mV current-sense threshold voltage for ACLIM = Floating and ACLIM = GND, respectively. A low pass filter is suggested to eliminate the switching noise. Connect the resistor to CSIN pin instead of CSIP pin because CSIN pin has lower bias current and less influence on the current-sense accuracy. AC Adapter Detection Connect the AC adapter voltage through a resistor divider to ACSET to detect when AC power is available, as shown in Figure 12. ACPRN is an open-drain output and is high when ACSET is less than Vth,rise, and active low when ACSET is above Vth,fall. Vth,rise and Vth,fall are given by Equations 7 and 8: ⎞ ⎛R Vth ,rise = ⎜⎜ 8 + 1 ⎟⎟ • VACSET ⎠ ⎝ R9 ⎞ ⎛R Vth,fall = ⎜⎜ 8 + 1 ⎟⎟ • V ACSET − I hys R8 ⎠ ⎝ R9 (EQ. 7) (EQ. 8) Where Ihys is the ACSET input bias current hysteresis and VACSET = 1.24V (min), 1.26V (typ) and 1.28V (max). The hysteresis is IhysR8, where Ihys = 2.2µA (min), 3.4µA (typ) and 4.4µA (max). Current Measurement Use ICM to monitor the input current being sensed across CSIP and CSIN. The output voltage range is 0 to 2.5V. The voltage of ICM is proportional to the voltage drop across CSIP and CSIN, and FN9202.3 March 13, 2014 ISL6251, ISL6251A is given by Equation 9: (EQ. 9) ICM = 19.9 • I INPUT • R 2 where IINPUT is the DC current drawn from the AC adapter. ICM has ±3% accuracy. A low pass filter connected to ICM output is used to filter the switching noise. LDO Regulator losses in the magnetic core and the windings, which decrease the system efficiency. On the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but it has higher DCR (DC resistance of the inductor) loss, and has slower transient response. So, the practical inductor design is based on the inductor ripple current being ±(15-20)% of the maximum operating DC current at maximum input voltage. The required inductance can be calculated from Equation 10: L= VIN ,MAX − VBAT VBAT VIN ,MAX fs (EQ. 10) VDD provides a 5.075V supply voltage from the internal LDO regulator from DCIN and can deliver up to 30mA of current. The MOSFET drivers are powered by VDDP, which must be connected to VDDP as shown in Figure 12. VDDP connects to VDD through an external resistor. Bypass VDDP and VDD with a 1µF capacitor. Where VIN,MAX, VBAT, and fs are the maximum input voltage, battery voltage and switching frequency, respectively. The inductor ripple current ΔI is found from Equation 11: Shutdown Δ I L = 30% ⋅ I BAT,MAX The ISL6251, ISL6251A features a low-power shutdown mode. Driving EN low shuts down the charger. In shutdown, the DC/DC converter is disabled, and VCOMP and ICOMP are pulled to ground. The ICM, ACPRN outputs continue to function. where the maximum peak-to-peak ripple current is 30% of the maximum charge current is used. EN can be driven by a thermistor to allow automatic shutdown when the battery pack is hot. Often a NTC thermistor is included inside the battery pack to measure its temperature. When connected to the charger, the thermistor forms a voltage divider with a resistive pull-up to the VREF. The threshold voltage of EN is 1.06V with 60mV hysteresis. The thermistor can be selected to have a resistance vs temperature characteristic that abruptly decreases above a critical temperature. This arrangement automatically shuts down the charger when the battery pack is above a critical temperature. Another method for inhibiting charging is to force CHLIM below 88mV (typ). Short Circuit Protection and 0V Battery Charging Since the battery charger will regulate the charge current to the limit set by CHLIM, it automatically has short circuit protection and is able to provide the charge current to wake up an extremely discharged battery. Over-Temperature Protection If the die temp exceeds +150°C, it stops charging. Once the die temp drops below +125°C, charging will start up again. Application Information The following battery charger design refers to the typical application circuit in Figure 12, where typical battery configuration of 4S2P is used. This section describes how to select the external components including the inductor, input and output capacitors, switching MOSFETs, and current sensing resistors. Inductor Selection The inductor selection has trade-offs between cost, size and efficiency. For example, the lower the inductance, the smaller the size, but ripple current is higher. This also results in higher AC Submit Document Feedback 14 Δ IL (EQ. 11) For VIN,MAX = 19V, VBAT = 16.8V, IBAT,MAX = 2.6A, and fs = 300kHz, the calculated inductance is 8.3µH. Choosing the closest standard value gives L = 10µH. Ferrite cores are often the best choice since they are optimized at 300kHz to 600kHz operation with low core loss. The core must be large enough not to saturate at the peak inductor current IPeak: I Peak = I BAT ,MAX + 1 Δ IL 2 (EQ. 12) Output Capacitor Selection The output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and smooth the output voltage. The RMS value of the output ripple current Irms is given by Equation 13: IRMS = VIN ,MAX 12 L fs D (1 − D ) (EQ. 13) where the duty cycle D is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode which is typical operation for the battery charger. During the battery charge period, the output voltage varies from its initial battery voltage to the rated battery voltage. So, the duty cycle change can be in the range of between 0.53 and 0.88 for the minimum battery voltage of 10V (2.5V/Cell) and the maximum battery voltage of 16.8V. For VIN,MAX = 19V, VBAT = 16.8V, L = 10µH, and fs = 300kHz, the maximum RMS current is 0.19A. A typical 10F ceramic capacitor is a good choice to absorb this current and also has very small size. The tantalum capacitor has a known failure mechanism when subjected to high surge current. EMI considerations usually make it desirable to minimize ripple current in the battery leads. Beads may be added in series with the battery pack to increase the battery impedance at 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and battery impedance. If the ESR of the output FN9202.3 March 13, 2014 ISL6251, ISL6251A capacitor is 10mΩ and battery impedance is raised to 2Ω with a bead, then only 0.5% of the ripple current will flow in the battery. For the low-side MOSFET, the worst-case power dissipation occurs at minimum battery voltage and maximum input voltage: MOSFET Selection ⎛ V PQ2 = ⎜⎜1 − OUT VIN ⎝ The Notebook battery charger synchronous buck converter has the input voltage from the AC adapter output. The maximum AC adapter output voltage does not exceed 25V. Therefore, 30V logic MOSFET should be used. The high side MOSFET must be able to dissipate the conduction losses plus the switching losses. For the battery charger application, the input voltage of the synchronous buck converter is equal to the AC adapter output voltage, which is relatively constant. The maximum efficiency is achieved by selecting a high side MOSFET that has the conduction losses equal to the switching losses. Ensure that ISL6251, ISL6251A LGATE gate driver can supply sufficient gate current to prevent it from conduction, which is due to the injected current into the drain-tosource parasitic capacitor (Miller capacitor Cgd), and caused by the voltage rising rate at phase node at the time instant of the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Reasonably slowing turn-on speed of the high-side MOSFET by connecting a resistor between the BOOT pin and gate drive supply source, and the high sink current capability of the low-side MOSFET gate driver help reduce the possibility of cross-conduction. For the high-side MOSFET, the worst-case conduction losses occur at the minimum input voltage: PQ1,Conduction = VOUT 2 I BAT R DSON VIN PQ1,Switching = Qgd Qgd 1 1 + VIN ILP fs + QrrVIN fs VIN ILV fs 2 Ig ,source 2 Ig ,sin k (EQ. 15) Where Qgd: drain-to-gate charge, Qrr: total reverse recovery charge of the body-diode in low side MOSFET, ILV: inductor valley current, ILP: Inductor peak current, Ig,sink and Ig,source are the peak gate-drive source/sink current of Q1, respectively. To achieve low switching losses, it requires low drain-to-gate charge Qgd. Generally, the lower the drain-to-gate charge, the higher the on-resistance. Therefore, there is a trade-off between the on-resistance and drain-to-gate charge. Good MOSFET selection is based on the Figure of Merit (FOM), which is a product of the total gate charge and on-resistance. Usually, the smaller the value of FOM, the higher the efficiency for the same application. Choose a Schottky diode in parallel with low-side MOSFET Q2 with a forward voltage drop low enough to prevent the low-side MOSFET Q2 body-diode from turning on during the dead time. This also reduces the power loss in the high-side MOSFET associated with the reverse recovery of the low-side MOSFET Q2 body diode. As a general rule, select a diode with DC current rating equal to one-third of the load current. One option is to choose a combined MOSFET with the Schottky diode in a single package. The integrated packages may work better in practice because there is less stray inductance due to a short connection. This Schottky diode is optional and may be removed if efficiency loss can be tolerated. In addition, ensure that the required total gate drive current for the selected MOSFETs should be less than 24mA. So, the total gate charge for the high-side and low-side MOSFETs is limited by Equation 17: QGATE ≤ I GATE fs 15 (EQ. 17) Where IGATE is the total gate drive current and should be less than 24mA. Substituting IGATE = 24mA and fs = 300kHz into the above equation yields that the total gate charge should be less than 80nC. Therefore, the ISL6251, ISL6251A easily drives the battery charge current up to 10A. Input Capacitor Selection The input capacitor absorbs the ripple current from the synchronous buck converter, which is given by Equation 18: Irms = IBAT VOUT (VIN − VOUT ) (EQ. 18) VIN This RMS ripple current must be smaller than the rated RMS current in the capacitor datasheet. Non-tantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents when the AC adapter is plugged into the battery charger. For Notebook battery charger applications, it is recommend that ceramic capacitors or polymer capacitors from Sanyo be used due to their small size and reasonable cost. Table 2 shows the component lists for the typical application circuit in Figure 12. TABLE 2. COMPONENT LIST PARTS C1, C10 C2, C4, C8 Submit Document Feedback (EQ. 16) Choose a low-side MOSFET that has the lowest possible onresistance with a moderate-sized package like the SO-8 and is reasonably priced. The switching losses are not an issue for the low side MOSFET because it operates at zero-voltage-switching. (EQ. 14) The optimum efficiency occurs when the switching losses equal the conduction losses. However, it is difficult to calculate the switching losses in the high-side MOSFET since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the MOSFET internal gate resistance, gate charge, threshold voltage, stray inductance, pullup and pull-down resistance of the gate driver. The following switching loss calculation provides a rough estimate. ⎞ 2 ⎟ I BAT R DSON ⎟ ⎠ PART NUMBERS AND MANUFACTURER 10μF/25V ceramic capacitor, Taiyo Yuden TMK325 MJ106MY X5R (3.2x2.5x1.9mm) 0.1μF/50V ceramic capacitor FN9202.3 March 13, 2014 ISL6251, ISL6251A Power Stage Transfer Functions TABLE 2. COMPONENT LIST (Continued) PARTS C3, C7, C9 PART NUMBERS AND MANUFACTURER 1μF/10V ceramic capacitor, Taiyo Yuden LMK212BJ105MG C5 10nF ceramic capacitor C6 6.8nF ceramic capacitor C11 3300pF ceramic capacitor D1 D2, D3 D4 L Transfer function F1(S) from control to output voltage is: F1 (S ) = v̂ o d̂ 1+ = Vin S2 ω o2 Where ω esr = 30V/3A Schottky diode, EC31QS03L (optional) 100mA/30V Schottky Diode, Central Semiconductor 8A/30V Schottky rectifier, STPS8L30B (optional) 10μH/3.8A/26mΩ, Sumida, CDRH104R-100 + S ω esr (EQ. 20) S +1 ω oQ p 1 Co ω o = , Q p ≈ Ro , Rc Co L 1 LC o Transfer function F2(S) from control to inductor current is: Vin F2 (S ) = = Ro + RL S 2 d̂ î L ω o2 1+ + S ωz S ω oQ p , where ω z ≈ +1 1 . Ro Co Q1, Q2 30V/35mΩ, FDS6912A, Fairchild. Q3 Signal N-channel MOSFET, 2N7002 R1 40mΩ, ±1%, LRC-LR2512-01-R040-F, IRC R2 20mΩ, ±1%, LRC-LR2010-01-R020-F, IRC R3 18Ω, ±5%, (0805) R4 2.2Ω, ±5%, (0805) where RT is the trans-resistance in current loop. RT is usually equal to the product of the charging current sensing resistance and the gain of the current sense amplifier, CA2. For ISL6251, ISL6251A, RT = 20R1. R5 100kΩ, ±5%, (0805) The voltage gain with open current loop is: R6 10k, ±5%, (0805) T v ( S ) = KM F 1 ( S )A V ( S ) R7 100Ω, ±5%, (0805) R8, R11 130k, ±1%, (0805) R9 10.2kΩ, ±1%, (0805) R10 4.7Ω, ±5%, (0805) R12 20kΩ, ±1%, (0805) R13 1.87kΩ, ±1%, (0805) Current loop gain Ti(S) is expressed as shown in Equation 21: (EQ. 21) T i ( S ) = 0.25 R T F 2 ( S )M Where K = (EQ. 22) VFB , VFB is the feedback voltage of the voltage error Vo amplifier. The Voltage loop gain with current loop closed is given by Equation 23: Lv ( S ) = Tv (S ) 1 + Ti (S ) (EQ. 23) If Ti(S)>>1, then it can be simplified as follows: Loop Compensation Design ISL6251, ISL6251A uses constant frequency current mode control architecture to achieve fast loop transient response. An accurate current sensing resistor in series with the output inductor is used to regulate the charge current, and the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design. The inductor is not considered as a state variable for current mode control and the system becomes single order system. It is much easier to design a compensator to stabilize the voltage loop than voltage mode control. Figure 14 shows the small signal model of the synchronous buck regulator. S 1 + -----------4 VF B ( RO + RL ) ω esr 1 L V ( S ) = --------------- ------------------------------ ------------------------ A V ( S ), ω P ≈ ----------------- (EQ. 24) RO CO S RT VO ------1+ ωP From the above equation, it is shown that the system is a single order system, which has a single pole located at ω p before the half switching frequency. Therefore, simple type II compensator can be easily used to stabilize the system. PWM Comparator Gain Fm: The PWM comparator gain Fm for peak current mode control is given by Equation 19: 11 M = --------- . V IN Submit Document Feedback (EQ. 19) 16 FN9202.3 March 13, 2014 ISL6251, ISL6251A îL + î in v̂ o 8 π fC VO CO RT R 1 = --------------------------------------g m V FB Vin d̂ 1:D ILd̂ v̂ in L The loop gain Tv(S) at cross over frequency of fc has unity gain. Therefore, the compensator resistance R1 is determined by Equation 27: + RT VCA2 Rc Ro where gm is the trans-conductance of the voltage loop error amplifier. Compensator capacitor C1 is then given by Equation 28: Co Ti(S) d̂ K 11/Vin 0.25VCA2 + - Tv(S) v̂ comp -Av(S) FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR Figure 15 shows the voltage loop compensator, and its transfer function is expressed as follows: Av (S ) = v̂ comp v̂ FB where ω cz = S 1+ = gm (EQ. 25) ω cz 1 R1C1 Vo VREF (EQ. 28) Example: Vin = 19V, Vo = 16.8V, Io = 2.6A, fs = 300kHz, Co = 10μF/10mΩ, L = 10μH, gm = 250μs, RT = 0.8Ω, VFB = 2.1V, fc = 20kHz, then compensator resistance R1 = 10kΩ. Choose R1 = 10kΩ. Put the compensator zero at 1.5kHz. The compensator capacitor is C1 = 6.5nF. Therefore, choose voltage loop compensator: R1 = 10k, C1 = 6.5nF. PCB Layout Considerations Power and Signal Layers Placement on the PCB 2. Signal Ground + gm VCOMP 3. Power Layers: Power Ground 4. Bottom Layer: Power MOSFET, Inductors and other Power traces Separate the power voltage and current flowing path from the control and logic level signal path. The controller IC will stay on the signal layer, which is isolated by the signal ground to the power signal traces. C1 FIGURE 15. VOLTAGE LOOP COMPENSATOR Component Placement Compensator design goal: The power MOSFET should be close to the IC so that the gate drive signal, the LGATE, UGATE, PHASE, and BOOT, traces can be short. • High DC gain 1 ⎞ ⎛1 − ⎟ fs ⎝ 5 20 ⎠ • Loop bandwidth fc: ⎜ Place the components in such a way that the area under the IC has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. • Gain margin: >10dB • Phase margin: 40° The compensator design procedure is as follows: Signal Ground and Power Ground Connection. 1. Put compensator zero at: 1 RoCo (EQ. 26) 2. Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero frequency or half switching frequency, whichever is lower. Submit Document Feedback 1 R1 ω cz 1. Top Layer: signal lines, or half board for signal lines and the other half board for power lines R1 ωcz = (1 − 3 ) C1 = As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. As an example, layer arrangement on a 4-layer board is shown below: SC1 VFB (EQ. 27) 17 At minimum, a reasonably large area of copper, which will shield other noise couplings through the IC, should be used as signal ground beneath the IC. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the IC is not recommended. FN9202.3 March 13, 2014 ISL6251, ISL6251A GND and VDD Pin CSOP, CSON Pins At least one high quality ceramic decoupling cap should be used to cross these two pins. The decoupling cap can be put close to the IC. The current sense resistor connects to the CSON and the CSOP pins through a low pass filter. The CSON pin is also used as the battery voltage feedback. The traces should be away from the high dv/dt and di/di pins like PHASE, BOOT pins. In general, the current sense resistor should be close to the IC. Other layout arrangements should be adjusted accordingly. LGATE Pin This is the gate drive signal for the bottom MOSFET of the buck converter. The signal going through this trace has both high dv/dt and high di/dt, and the peak charging and discharging current is very high. These two traces should be short, wide, and away from other traces. There should be no other traces in parallel with these traces on any layer. PGND Pin PGND pin should be laid out to the negative side of the relevant output cap with separate traces. The negative side of the output capacitor must be close to the source node of the bottom MOSFET. This trace is the return path of LGATE. PHASE Pin This trace should be short, and positioned away from other weak signal traces. This node has a very high dv/dt with a voltage swing from the input voltage to ground. No trace should be in parallel with it. This trace is also the return path for UGATE. Connect this pin to the high-side MOSFET source. UGATE Pin This pin has a square shape waveform with high dv/dt. It provides the gate drive current to charge and discharge the top MOSFET with high di/dt. This trace should be wide, short, and away from other traces similar to the LGATE. BOOT Pin This pin’s di/dt is as high as the UGATE; therefore, this trace should be as short as possible. EN Pin This pin stays high at enable mode and low at idle mode and is relatively robust. Enable signals should refer to the signal ground. DCIN Pin This pin connects to AC adapter output voltage, and should be less noise sensitive. Copper Size for the Phase Node The capacitance of PHASE should be kept very low to minimize ringing. It would be best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. Identify the Power and Signal Ground The input and output capacitors of the converters, the source terminal of the bottom switching MOSFET PGND should connect to the power ground. The other components should connect to signal ground. Signal and power ground are tied together at one point. Clamping Capacitor for Switching MOSFET It is recommended that ceramic caps be used closely connected to the drain of the high-side MOSFET, and the source of the lowside MOSFET. This capacitor reduces the noise and the power loss of the MOSFET. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 18 FN9202.3 March 13, 2014 ISL6251, ISL6251A Package Outline Drawing L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/07 4X 3.0 5.00 24X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 28 22 1 5.00 21 3 .10 ± 0 . 15 15 (4X) 7 0.15 8 14 TOP VIEW 0.10 M C A B - 0.07 4 28X 0.25 + 0.05 28X 0.55 ± 0.10 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 65 TYP ) ( 24X 0 . 50) ( SIDE VIEW 3. 10) (28X 0 . 25 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. ( 28X 0 . 75) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. Submit Document Feedback 19 FN9202.3 March 13, 2014 ISL6251, ISL6251A Package Outline Drawing M24.15 24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (QSOP/SSOP) 0.150” WIDE BODY Rev 3, 2/13 24 6.19 5.80 INDEX 3.98 3.81 AREA 5 4 0.25(0.010) M B M -B- 1 TOP VIEW DETAIL “X” SEATING PLANE -A- 8.74 8.55 3 1.75 1.35 GAUGE PLANE -C- SIDE VIEW 1 1.27 0.41 0.25 0.10 0.635 BSC 7 0.30 0.20 0.25 0.010 0.10(0.004) 0.49 x 45° 5 0.26 0.17(0.007) M C A M B S 7.11 8° 0° 1.54 5.59 SIDE VIEW 2 0.25 0.18 4.06 0.38 0.635 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. Terminal numbers are shown for reference only. 7. Lead width does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 8. Controlling dimension: MILLIMETER. TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 20 FN9202.3 March 13, 2014