INTERSIL ISL6322GIRZ

ISL6322G
®
Data Sheet
May 22, 2008
FN6715.0
Two-Phase Buck PWM Controller with
Integrated MOSFET Drivers, I2C Interface,
and Phase Dropping
Features
The ISL6322G two-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors and memory. The integration of power
MOSFET drivers into the controller IC marks a departure
from the separate PWM controller and driver configuration of
previous multiphase product families. By reducing the
number of external parts, this integration is optimized for a
cost and space saving power management solution.
• Phase Dropping for Higher Efficiency at Low Output
Current Loads
One outstanding feature of this controller IC is its
multi-processor compatibility, allowing it to work with both Intel
and AMD microprocessors. Included are programmable VID
codes for Intel VR10, VR11, as well as AMD DAC tables. A
unity gain, differential amplifier is provided for remote voltage
sensing, compensating for any potential difference between
remote and local grounds. The output voltage can also be
positively or negatively offset through the use of a single
external resistor.
The ISL6322G includes an I2C interface, allowing the
controller to communicate with other devices over an I2C
bus. Signals sent over this bus can command the ISL6322G
to adjust the number of active phases, voltage margining
offset, phase switching frequency, overvoltage protection
levels, and can select the integrated driver adaptive dead
time scheme.
The ISL6322G also includes advanced control loop features
for optimal transient response to load apply and removal.
One of these features is highly accurate, fully differential,
continuous DCR current sensing for channel-current
balance. Active Pulse Positioning (APP) modulation is
another unique feature, allowing for quicker initial response
to high di/dt load transients.
This controller also allows the user the flexibility to choose
between PHASE detect or LGATE detect adaptive dead time
schemes. This ability allows the ISL6322G to be used in a
multitude of applications where either scheme is required.
Protection features of this controller IC include a set of
sophisticated overvoltage, undervoltage, and overcurrent
protection. Furthermore, the ISL6322G includes protection
against an open circuit on the remote sensing inputs.
Combined, these features provide advanced protection for the
microprocessor and power system.
1
• Integrated Multiphase Power Conversion
- 2-Phase or 1-Phase Operation with Internal Drivers
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Transient Response
- Active Pulse Positioning (APP) Modulation
- Adaptive Phase Alignment (APA)
• Fully Differential, Continuous DCR Current Sensing
- Precision Channel-Current Balancing
• I2C Interface
- Phase Dropping
- Voltage Margining Offset
- Switching Frequency Adjustment
- Overvoltage Protection Level Adjustment
- Selects Adaptive Dead Time Scheme
• User Selectable I2C “Slave Only” Device Address:
1000_110x or 1000_111x
• User Selectable Adaptive Dead Time Scheme
- PHASE Detect or LGATE Detect for Application
Flexibility
• Variable Gate Drive Bias: 5V to 12V
• Multi-Processor Compatible
- Intel VR10 and VR11 Modes of Operation
- AMD Mode of Operation
• Microprocessor Voltage Identification Inputs
- 8-bit DAC
- Selectable between Intel’s Extended VR10, VR11, AMD
5-bit, and AMD 6-bit DAC Tables
- Dynamic VID Technology
• Maximum Allowable Output Voltage of 1.6V
• Overcurrent Protection
• Multi-Tiered Overvoltage Protection
• Digital Soft-Start
• Selectable Operation Frequency up to 1.5MHz Per Phase
• Pb-Free (RoHS Compliant)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6322G
Ordering Information
PART NUMBER (Note)
PART MARKING
TEMP. (°C)
PACKAGE (Pb-Free)
PKG. DWG. #
ISL6322GCRZ*
ISL6322G CRZ
0 to +70
48 Ld 7x7 QFN
L48.7x7
ISL6322GIRZ*
ISL6322G IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
VID5
VID6
VID7
FS
NC
NC
NC
NC
NC
NC
NC
PGOOD
ISL6322G
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VID4
1
36 EN
VID3
2
35 ISEN1+
VID2
3
34 ISEN1-
VID1
4
33 PHASE1
VID0
5
32 UGATE1
VRSEL
6
SCL
7
30 LGATE1
SDA
8
29 PVCC
SS/RST/A0
9
28 LGATE2
2
31 BOOT1
49
GND
16
17
18
19
20
21
22
23
24
NC
NC
EN_PH2
NC
15
ISEN2-
14
ISEN2+
13
VSEN
25 PHASE2
VDIFF
OFS 12
RGND
26 UGATE2
IOUT
REF 11
FB
27 BOOT2
COMP
VCC 10
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May 22, 2008
ISL6322G
Block Diagram
EN
PGOOD
OPEN SENSE
LINE PREVENTION
0.85V
VSEN
x1
VCC
POWER-ON
RESET
RGND
VDIFF
PVCC
SOFT-START
AND
FAULT LOGIC
OVERVOLTAGE
AND
UNDERVOLTAGE
DETECTION
LOGIC
BOOT1
0.2V
SS/RST/A0
SCL
UGATE1
MOSFET
DRIVER
LOAD APPLY
TRANSIENT
ENHANCEMENT
PHASE1
LGATE1
I2C
LOGIC
SDA
CLOCK AND
MODULATOR
WAVEFORM
GENERATOR
VRSEL
FS
MODE/DAC
SELECT
PWM1
∑
VID7
VID6
VID5
VID4
VID3
DYNAMIC
VID
D/A
BOOT2
VID2
UGATE2
MOSFET
DRIVER
VID1
VID0
PHASE2
PWM2
∑
REF
LGATE2
E/A
FB
I2C
COMP
OFS
PH2
DETECT
CHANNEL
CURRENT
BALANCE
AND CURRENT
LIMIT
OFFSET
IAVG
EN_PH2
1
N
ITRIP
OCP
OCP
ISEN1+ISEN2
∑
ISEN1
GND
3
ISEN2
CH1
CURRENT
SENSE
CH2
CURRENT
SENSE
ISEN1- ISEN1+
ISEN2- ISEN2+
IOUT
OCP
OCP
2.0V
FN6715.0
May 22, 2008
ISL6322G
ISL6322G Integrated Driver Block Diagram
PVCC
DRSEL
BOOT
UGATE
20kΩ
PWM
GATE
CONTROL
LOGIC
SOFT-START
SHOOTPHASE
THROUGH
PROTECTION
10kΩ
AND
FAULT LOGIC
LGATE
Simplified I2C Bus Architecture
+5V
I2C BUS
MASTER
+5V
SDA
SCL
SCL
SDA
SCL
SLAVE
IC #1
SDA
SLAVE
IC #2
SCL
SDA
SCL
ISL6322G
A0
SLAVE ADDRESS:
1000_110x
SDA
ISL6322G
RSS
+5V
RSS
A0
SLAVE ADDRESS:
1000_111x
NOTE: PIN A0 SELECTS THE SLAVE ADDRESS FOR THE ISL6322G
4
FN6715.0
May 22, 2008
ISL6322G
Typical Application - ISL6322G
VDIFF
FB
COMP
+12V
VSEN
RGND
BOOT1
+5V
UGATE1
VCC
PHASE1
OFS
LGATE1
IOUT
ISEN1ISEN1+
FS
REF
SCL
SDA
SS/RST/A0
ISL6322G
LOAD
+12V
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PVCC
BOOT2
UGATE2
PHASE2
VRSEL
PGOOD
LGATE2
EN_PH2
ISEN2ISEN2+
+12V
EN
NC
GND
5
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May 22, 2008
ISL6322G
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
BOOT Voltage, VBOOT . . . . . . . . . . . . . . GND - 0.3V to GND + 36V
BOOT to PHASE Voltage, VBOOT - PHASE . . . . . -0.3V to 15V (DC)
-0.3V to 16V (<10ns, 10µJ)
PHASE Voltage, VPHASE . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT - PHASE = 12V)
UGATE Voltage, VUGATE. . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE Voltage, VLGATE . . . . . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC + 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . . .
27
2.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Ambient Temperature
ISL6322GCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6322GIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Limits established by characterization and are not production tested.
Electrical Specifications Recommended Operating Conditions, Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
BIAS SUPPLIES
Input Bias Supply Current
IVCC; EN = high
15
20
25
mA
Gate Drive Bias Current - PVCC Pin
IPVCC; EN = high
2
4.3
6
mA
VCC POR (Power-On Reset) Threshold
VCC rising
4.25
4.38
4.50
V
VCC falling
3.75
3.88
4.00
V
PVCC rising
4.25
4.38
4.50
V
PVCC falling
3.60
3.88
4.00
V
Oscillator Frequency Accuracy, fSW
RT = 100kΩ (±0.1%)
225
250
275
kHz
Adjustment Range of Switching Frequency
(Note 3)
0.08
1.0
MHz
Oscillator Ramp Amplitude, VP-P
(Note 3)
PVCC POR (Power-On Reset) Threshold
PWM MODULATOR
1.50
V
EN Rising Threshold
0.85
V
EN Hysteresis
110
mV
CONTROL THRESHOLDS
EN_PH2 Input High Voltage
3.0
V
EN_PH2 Input Low Voltage
COMP Shutdown Threshold
COMP falling
0.1
0.2
2.0
V
0.3
V
REFERENCE AND DAC
System Accuracy (1.000V to 1.600V)
-0.5
0.5
%
System Accuracy (0.600V to 1.000V)
-1.0
1.0
%
System Accuracy (0.375V to 0.600V)
-2.0
2.0
%
0.4
V
DAC Input Low Voltage (VR10, VR11)
6
FN6715.0
May 22, 2008
ISL6322G
Electrical Specifications Recommended Operating Conditions, Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
TEST CONDITIONS
DAC Input High Voltage (VR10, VR11)
MIN
TYP
MAX
UNITS
0.8
V
DAC Input Low Voltage (AMD)
0.6
DAC Input High Voltage (AMD)
V
1.0
V
PIN-ADJUSTABLE OFFSET
OFS Sink Current Accuracy (Negative Offset)
ROFS = 10kΩ from OFS to GND
37.0
40.0
43.0
µA
OFS Source Current Accuracy (Positive Offset)
ROFS = 30kΩ from OFS to VCC
50.5
53.5
56.5
µA
ERROR AMPLIFIER
DC Gain
RL = 10k to ground, (Note 3)
96
dB
Gain-Bandwidth Product
CL = 100pF, RL = 10k to ground, (Note 3)
20
MHz
Slew Rate
CL = 100pF, Load = ±400µA, (Note 3)
8
V/µs
Maximum Output Voltage
Load = 1mA
4.20
V
Minimum Output Voltage
Load = -1mA
1.30
VR10/VR11, RS = 100kΩ
1.563
mV/µs
AMD
2.063
mV/µs
3.90
1.5
V
SOFT-START RAMP
Soft-Start Ramp Rate
Adjustment Range of Soft-Start Ramp Rate (Note 3)
0.625
6.25
mV/µs
0.5
V
PWM OUTPUT
PWM Output Voltage LOW Threshold
ILoad = ±500µA
PWM Output Voltage HIGH Threshold
ILoad = ±500µA
4.5
Current Sense Resistance, RISEN
T = +25°C
297
300
303
Ω
Sensed Current Tolerance
ISEN1 + ISEN2 = 80µA
69
78
85
µA
1-Phase normal operation
110
126
140
µA
2-Phase normal operation
224
252
280
µA
1-Phase Dynamic VID change
142
164
184
µA
2-Phase Dynamic VID change
290
327
360
µA
Normal operation
150
177
204
µA
209.4
238
266.6
µA
55
60
65
%VID
V
CURRENT SENSING
OVERCURRENT PROTECTION
Overcurrent Trip Level - Average Channel
Overcurrent Trip Level - Individual Channel
Dynamic VID change (Note 3)
PROTECTION
Undervoltage Threshold
VSEN falling
Undervoltage Hysteresis
VSEN rising
Overvoltage Threshold During Soft-Start
VR10/VR11
1.24
1.28
1.32
V
AMD
2.13
2.20
2.27
V
10
%VID
Overvoltage Threshold (Default)
VSEN rising
VDAC +
225mV
VDAC +
250mV
VDAC +
275mV
V
Overvoltage Threshold (Alternate)
VSEN rising
VDAC +
150mV
VDAC +
175mV
VDAC +
200mV
V
Overvoltage Hysteresis
VSEN falling
7
100
mV
FN6715.0
May 22, 2008
ISL6322G
Electrical Specifications Recommended Operating Conditions, Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING TIME (Note 3)
UGATE Rise Time
tRUGATE; VPVCC = 12V, 3nF load, 10% to 90%
26
ns
LGATE Rise Time
tRLGATE; VPVCC = 12V, 3nF load, 10% to 90%
18
ns
UGATE Fall Time
tFUGATE; VPVCC = 12V, 3nF load, 90% to 10%
18
ns
LGATE Fall Time
tFLGATE; VPVCC = 12V, 3nF load, 90% to 10%
12
ns
UGATE Turn-On Non-Overlap
tPDHUGATE; VPVCC = 12V, 3nF load, adaptive
10
ns
LGATE Turn-On Non-Overlap
tPDHLGATE; VPVCC = 12V, 3nF load, adaptive
10
ns
Upper Drive Source Resistance
VPVCC = 12V, 15mA source current
2.0
Ω
Upper Drive Sink Resistance
VPVCC = 12V, 15mA sink current
1.65
Ω
Lower Drive Source Resistance
VPVCC = 12V, 15mA source current
1.25
Ω
Lower Drive Sink Resistance
VPVCC = 12V, 15mA sink current
0.80
Ω
Thermal Shutdown Setpoint
160
°C
Thermal Recovery Setpoint
100
°C
GATE DRIVE RESISTANCE (Note 3)
OVER TEMPERATURE SHUTDOWN (Note 3)
Timing Diagram
tPDHUGATE
tRUGATE
tFUGATE
UGATE
LGATE
tFLGATE
tRLGATE
tPDHLGATE
8
FN6715.0
May 22, 2008
ISL6322G
Functional Pin Description
VCC
VCC is the bias supply for the ICs small-signal circuitry.
Connect this pin to a +5V supply and decouple using a
quality 0.1µF ceramic capacitor.
PVCC
This pin is the power supply pin for Channel 1 and 2’s
MOSFET drive, and can be connected to any voltage from
+5V to +12V depending on the desired MOSFET gate-drive
level. Decouple this pin with a quality 1.0µF ceramic
capacitor.
FB and COMP
These pins are the internal error amplifier inverting input and
output respectively. FB, VDIFF, and COMP are tied together
through external R-C networks to compensate the regulator.
IOUT
The IOUT pin is the total channel-sense current output.
Connecting this pin through a resistor to ground allows the
controller to set the overcurrent protection trip level. This pin
pin can also be used as a load current indicator to monitor
what the output load current is.
GND is the bias and reference ground for the IC.
Since the current coming out of the IOUT pin is equal to the
addition of Channel 1 and 2’s sense currents, the current will
be twice as large in 2-phase mode then when in single
phase mode.
EN
REF
This pin is a threshold-sensitive (approximately 0.85V) enable
input for the controller. Held low, this pin disables controller
operation. Pulled high, the pin enables the controller for
operation.
The REF input pin is the positive input of the error amplifier. It
is internally connected to the DAC output through a 1kΩ
resistor. A capacitor is used between the REF pin and ground
to smooth the voltage transition during Dynamic VID
operations.
GND
FS
A resistor, placed from FS to ground, sets the switching
frequency of the controller.
VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7
These are the inputs for the internal DAC that provides the
reference voltage for output regulation. These pins respond to
TTL logic thresholds. These pins are internally pulled high, to
approximately 1.2V, by 40µA internal current sources for Intel
modes of operation, and pulled low by 20µA internal current
sources for AMD modes of operation. The internal pull-up
current decreases to 0 as the VID voltage approaches the
internal pull-up voltage. All VID pins are compatible with
external pull-up voltages not exceeding the IC’s bias voltage
(VCC).
VRSEL
The state of this pin selects which of the available DAC tables
will be used to decode the VID inputs and puts the controller
into the corresponding mode of operation. For VR10 mode of
operation VRSEL should be less then 0.6V. The VR11 mode of
operation can be selected by setting VRSEL between 0.6V and
3.0V, and AMD compliance is selected if this pin is between
3.0V and VCC.
VSEN and RGND
VSEN and RGND are inputs to the precision differential
remote-sense amplifier and should be connected to the sense
pins of the remote load.
VDIFF
VDIFF is the output of the differential remote-sense amplifier.
The voltage on this pin is equal to the difference between
VSEN and RGND.
9
OFS
The OFS pin provides a means to program a DC current for
generating an offset voltage across the resistor between FB
and VDIFF. The offset current is generated via an external
resistor and precision internal voltage references. The polarity
of the offset is selected by connecting the resistor to GND or
VCC. For no offset, the OFS pin should be left unconnected.
ISEN1-, ISEN1+, ISEN2-, and ISEN2+
These pins are used for differentially sensing the
corresponding channel output currents. The sensed currents
are used for channel-current balancing and protection.
Connect ISEN1- and ISEN2-to the node between the RC
sense elements surrounding the inductor of their respective
channel. Tie the ISEN+ pins to the VCORE side of their
corresponding channel’s sense capacitor.
UGATE1 and UGATE2
Connect these pins to the corresponding upper MOSFET
gates. These pins are used to control the upper MOSFETs
and are monitored for shoot-through prevention purposes.
BOOT1 and BOOT2
These pins provide the bias voltage for the corresponding
upper MOSFET drives. Connect these pins to
appropriately-chosen external bootstrap capacitors. Internal
bootstrap diodes connected to the PVCC pins provide the
necessary bootstrap charge.
PHASE1 and PHASE2
Connect these pins to the sources of the corresponding
upper MOSFETs. These pins are the return path for the
upper MOSFET drives.
FN6715.0
May 22, 2008
ISL6322G
LGATE1 and LGATE2
PGOOD is pulled low. PGOOD is always low prior to the end
of soft-start.
These pins are used to control the lower MOSFETs. Connect
these pins to the corresponding lower MOSFETs’ gates.
NC
EN_PH2
These are “no connect” pins. They should be left floating.
This pin is a digital logic input which tells the controller to
operate in single phase or 2-phase mode. The number of
active phases can be changed while the controller is
operating by changing the state of this pin. Tying this pin
high commands the part to operate in single phase mode
only. If EN_PH2 is tied low the part can operate in either
single phase or 2-phase mode depending on the state of
Bit 6 of I2C register 2. The default I2C setting is 2-phase
mode, so if Bit 6 of register 2 is not changed tieing EN_PH2
low commands the controller to operate in 2-phase mode.
If EN_PH2 is tied high the controller will ignore the state of
bit 6 in register 2 and will not allow the I2C interface to
control the number of channel’s firing.
Operation
Multiphase Power Conversion
Microprocessor load current profiles have changed to the
point that using single-phase regulators is no longer a viable
solution. Designing a regulator that is cost-effective,
thermally sound, and efficient has become a challenge that
only multiphase converters can accomplish. The ISL6322G
controller helps simplify implementation by integrating vital
functions and requiring minimal external components. The
“Block Diagram” on page 3 provides a top level view of
multiphase power conversion using the ISL6322G controller.
SS/RST/A0
This pin has three different functions associated with it. The
first is that a resistor (RSS), placed from this pin to ground, or
VCC, will set the soft-start ramp slope for the Intel DAC
modes of operation. Refer to Equations 15 and 16 for proper
resistor calculation.
The second function of this pin is that it selects which of the
two 8-bit Slave I2C addresses the controller will use.
Connecting the RSS resistor on this pin to ground will
choose slave address one(1000_110x), while connecting
this resistor to VCC will select slave address
two(1000_111x).
The third function of this pin is a reset to the I2C registers.
During normal operation of the part, if this pin is ever
grounded, all of the I2C registers are reset to 0000_0000. An
open drain device is recommended as the means of
grounding this pin for resetting the I2C registers.
SCL
Connect this pin to the clock signal for the I2C bus, which is
a logic level input signal. The clock signal tells the controller
when data is available on the I2C bus.
SDA
Connect this pin to the bidirectional data line of the I2C bus,
which is a logic level input/output signal. All I2C data is sent
over this line, including the address of the device the bus is
trying to communicate with, and what functions the device
should perform.
PGOOD
During normal operation PGOOD indicates whether the
output voltage is within specified overvoltage and
undervoltage limits. If the output voltage exceeds these limits
or a reset event occurs (such as an overcurrent event),
10
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Interleaving
The switching of each channel in a multiphase converter is
timed to be symmetrically out of phase with each of the other
channels. For example, in a 3-phase converter, each
channel switches 1/3 cycle after the previous channel and
1/3 cycle before the following channel. As a result, the
3-phase converter has a combined ripple frequency 3x
greater than the ripple frequency of any one phase. In
addition, the peak-to-peak amplitude of the combined
inductor currents is reduced in proportion to the number of
phases (Equations 1 and 2). Increased ripple frequency and
lower ripple amplitude mean that the designer can use less
per-channel inductance and lower total output capacitance
for any performance specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has 3x the ripple frequency of
each individual channel-current. Each PWM pulse is
FN6715.0
May 22, 2008
ISL6322G
terminated 1/3 of a cycle after the PWM pulse of the previous
phase. The peak-to-peak current for each phase is about 7A,
and the DC components of the inductor currents combine to
feed the load.
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.
( V IN – V OUT ) ⋅ V OUT
I P-P = --------------------------------------------------------L ⋅ fS ⋅ V
(EQ. 1)
IN
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
( V IN – N ⋅ V OUT ) ⋅ V OUT
I C ( P-P ) = ------------------------------------------------------------------L ⋅ fS ⋅ V
(EQ. 2)
IN
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND
INPUT-CAPACITOR RMS CURRENT FOR
3-PHASE CONVERTER
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
11
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
11.9ARMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent 3-phase converter.
Active Pulse Positioning (APP) Modulated PWM
Operation
The ISL6322G uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. The advantage of Intersil’s proprietary Active Pulse
Positioning (APP) modulator is that the PWM signal has the
ability to turn on at any point during this PWM time interval,
and turn off immediately after the PWM signal has
transitioned high. This is important because is allows the
controller to quickly respond to output voltage drops
associated with current load spikes, while avoiding the ring
back affects associated with other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, VCOMP, minus the current correction
signal relative to the proprietary modulator ramp waveform
as illustrated in Figure 3. At the beginning of each PWM time
interval, this modified VCOMP signal is compared to the
internal modulator waveform. As long as the modified
VCOMP voltage is lower then the modulator waveform
voltage, the PWM signal is commanded low. The internal
MOSFET driver detects the low state of the PWM signal and
turns off the upper MOSFET and turns on the lower
synchronous MOSFET. When the modified VCOMP voltage
crosses the modulator ramp, the PWM output transitions
high, turning off the synchronous MOSFET and turning on
the upper MOSFET. The PWM signal will remain high until
the modified VCOMP voltage crosses the modulator ramp
again. When this occurs the PWM signal will transition low
again.
During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
To further improve the transient response, ISL6322G also
implements Intersil’s proprietary Adaptive Phase Alignment
(APA) technique, which turns on all phases together under
transient events with large step current. With both APP and
APA control, ISL6322G can achieve excellent transient
performance and reduce the demand on the output
capacitors.
FN6715.0
May 22, 2008
ISL6322G
Phase Dropping
The ISL6322G has the ability to change the number of active
phases firing on-the-fly. This can be done through one of two
ways; through the use of the EN_PH2 pin, and through the
I2C interface.
The EN_PH2 pin is a digital logic input pin. Tieing this pin
high commands the part to operate in single phase mode
only. If EN_PH2 is tied low the part can operate in either
single phase or 2-phase mode depending on the state of
Bit 6 of I2C register 2. When the controller first powers up
Bit 6 is preset to “0”, which commands the controller to
operate in 2-phase mode. Changing bit 6 to a “1” commands
the controller to operate in single phase mode. For details on
how to change the state of the I2C registers please refer to
the “I2C Bus Interface” on page 26. If EN_PH2 is tied high,
the controller will operate in single phase mode only and will
ignore the state of Bit 6 in register 2, not allowing the I2C
interface to control the number of channel’s firing.
Once the ISL6322G receives a signal to change the number
of active phases it immediately responds by dropping or
adding phase 2 with no delay. When dropping from 2-phase
to single phase mode both LGATE2 and UGATE2 are
immediately tied low. These signals will stay in this state until
the controller is commanded to run in 2-phase mode again.
At this point LGATE2 and UGATE2 will be released to fire
normally.
Channel-Current Balance
One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to
carry equal amounts of current at any load level. To achieve
this, the currents through each channel must be sampled
every switching cycle. The sampled currents, In, from each
active channel are summed together and divided by the
number of active channels. The resulting cycle average
current, IAVG, provides a measure of the total load-current
demand on the converter during each switching cycle.
Channel-current balance is achieved by comparing the
sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented
current-balance method is illustrated in Figure 3, with error
correction for Channel 1 represented. In the figure, the cycle
average current, IAVG, is compared with the Channel 1
sample, I1 , to create an error signal IER.
IER toward zero. The same method for error signal
correction is applied to each active channel
.
+
VCOMP
+
MODULATOR
RAMP
WAVEFORM
FILTER
PWM1
-
TO GATE
CONTROL
LOGIC
f(s)
IER
IAVG
-
Σ
÷N
ISEN2
+
ISEN1
FIGURE 3. CHANNEL-1 PWM FUNCTION AND
CURRENT-BALANCE ADJUSTMENT
Continuous Current Sampling
In order to realize proper current-balance, the currents in
each channel are sensed continuously every switching
cycle. During this time the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
inductor current, IL. This sensed current, ISEN, is simply a
scaled version of the inductor current.
PWM
SWITCHING PERIOD
IL
ISEN
TIME
FIGURE 4. CONTINUOUS CURRENT SAMPLING
The ISL6322G supports inductor DCR current sensing to
continuously sense each channel’s current for
channel-current balance (see Figure 4). The internal
circuitry, shown in Figure 5 represents Channel N of an
N-Channel converter. This circuitry is repeated for each
channel in the converter, but may not be active depending
on how many channels are operating.
The filtered error signal modifies the pulse width
commanded by VCOMP to correct any unbalance and force
12
FN6715.0
May 22, 2008
ISL6322G
.
VIN
I
L
UGATE(n)
L
MOSFET
LGATE(n)
+
VL(s)
R1
COUT
VC(s)
-
+
INDUCTOR
VOUT
-
DRIVER
DCR
SAMPLE
+
VC(s)
RISEN
-
-
ISEN-(n)
ISEN+(n)
*R2 is OPTIONAL
ISEN(n)
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 5. The channel-current
IL, flowing through the inductor, passes through the DCR.
Equation 3 shows the S-domain equivalent voltage, VL,
across the inductor.
(EQ. 3)
A simple R-C network across the inductor (R1 and C)
extracts the DCR voltage, as shown in Figure 5. The voltage
across the sense capacitor, VC, can be shown to be
proportional to the channel-current IL, shown in Equation 4.
s⋅L
⎛ ------------+ 1⎞
⎝ DCR
⎠
V C ( s ) = -------------------------------------- ⋅ DCR ⋅ I L
( s ⋅ R1 ⋅ C + 1 )
(EQ. 6)
DCR
I SEN = K ⋅ I L ⋅ -----------------R ISEN
(EQ. 7)
Output Voltage Setting
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
V L ( s ) = I L ⋅ ( s ⋅ L + DCR )
R2
K = --------------------R2 + R1
The capacitor voltage VC, is then replicated across the
sense resistor RISEN. The current through RISEN is
proportional to the inductor current. Equation 7 shows that
the proportion between the channel-current and the sensed
current (ISEN) is driven by the value of the sense resistor,
the resistor divider ratio, and the DCR of the inductor.
ISEN(n)
+
(EQ. 5)
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time
constant, then VC is equal to the voltage drop across the
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1.
C
R2*
ISL6322G INTERNAL CIRCUIT
s⋅L
⎛ ------------+ 1⎞
⎝ DCR
⎠
V C ( s ) = -------------------------------------------------------- ⋅ K ⋅ DCR ⋅ I L
⎛ ( R1 ⋅ R2 )
⎞
⎜ s ⋅ ------------------------ ⋅ C + 1⎟
R
+
R
⎝
⎠
1
2
(EQ. 4)
In some cases it may be necessary to use a resistor divider
R-C network to sense the current through the inductor. This
can be accomplished by placing a second resistor, R2,
across the sense capacitor. In these cases the voltage
across the sense capacitor, VC, becomes proportional to the
channel-current IL, and the resistor divider ratio, K.
The ISL6322G uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the VID pins. The DAC decodes the logic signals into one of
the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel
modes of operation, each VID pin is pulled up to an internal
1.2V voltage by a weak current source (40µA), which
decreases to 0A as the voltage at the VID pin varies from 0
to the internal 1.2V pull-up voltage. In AMD modes of
operation the VID pins are pulled low by a weak 20µA
current source. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
The ISL6322G accommodates four different DAC ranges:
Intel VR10 (Extended), Intel VR11, AMD K8/K9 5-bit, and
AMD 6-bit. The state of the VRSEL and VID7 pins decide
which DAC version is active. Refer to Table 1 for a
description of how to select the desired DAC version.
TABLE 1. ISL6322G DAC SELECT TABLE
DAC VERSION
VRSEL PIN
VID7 PIN
VR10(Extended)
VRSEL < 0.6V
-
VR11
0.8V < VRSEL < 3.0V
-
AMD 5-bit
3.0V < VRSEL < VCC
Low
AMD 6-bit
3.0V < VRSEL < VCC
High
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES
13
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
0
1
0
1
0
1
1
1.60000
0
1
0
1
0
1
0
1.59375
FN6715.0
May 22, 2008
ISL6322G
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued)
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
0
1
0
1
1
0
1
1.58750
1
0
1
0
0
1
0
1.34375
0
1
0
1
1
0
0
1.58125
1
0
1
0
1
0
1
1.33750
0
1
0
1
1
1
1
1.57500
1
0
1
0
1
0
0
1.33125
0
1
0
1
1
1
0
1.56875
1
0
1
0
1
1
1
1.32500
0
1
1
0
0
0
1
1.56250
1
0
1
0
1
1
0
1.31875
0
1
1
0
0
0
0
1.55625
1
0
1
1
0
0
1
1.31250
0
1
1
0
0
1
1
1.55000
1
0
1
1
0
0
0
1.30625
0
1
1
0
0
1
0
1.54375
1
0
1
1
0
1
1
1.30000
0
1
1
0
1
0
1
1.53750
1
0
1
1
0
1
0
1.29375
0
1
1
0
1
0
0
1.53125
1
0
1
1
1
0
1
1.28750
0
1
1
0
1
1
1
1.52500
1
0
1
1
1
0
0
1.28125
0
1
1
0
1
1
0
1.51875
1
0
1
1
1
1
1
1.27500
0
1
1
1
0
0
1
1.51250
1
0
1
1
1
1
0
1.26875
0
1
1
1
0
0
0
1.50625
1
1
0
0
0
0
1
1.26250
0
1
1
1
0
1
1
1.50000
1
1
0
0
0
0
0
1.25625
0
1
1
1
0
1
0
1.49375
1
1
0
0
0
1
1
1.25000
0
1
1
1
1
0
1
1.48750
1
1
0
0
0
1
0
1.24375
0
1
1
1
1
0
0
1.48125
1
1
0
0
1
0
1
1.23750
0
1
1
1
1
1
1
1.47500
1
1
0
0
1
0
0
1.23125
0
1
1
1
1
1
0
1.46875
1
1
0
0
1
1
1
1.22500
1
0
0
0
0
0
1
1.46250
1
1
0
0
1
1
0
1.21875
1
0
0
0
0
0
0
1.45625
1
1
0
1
0
0
1
1.21250
1
0
0
0
0
1
1
1.45000
1
1
0
1
0
0
0
1.20625
1
0
0
0
0
1
0
1.44375
1
1
0
1
0
1
1
1.20000
1
0
0
0
1
0
1
1.43750
1
1
0
1
0
1
0
1.19375
1
0
0
0
1
0
0
1.43125
1
1
0
1
1
0
1
1.18750
1
0
0
0
1
1
1
1.42500
1
1
0
1
1
0
0
1.18125
1
0
0
0
1
1
0
1.41875
1
1
0
1
1
1
1
1.17500
1
0
0
1
0
0
1
1.41250
1
1
0
1
1
1
0
1.16875
1
0
0
1
0
0
0
1.40625
1
1
1
0
0
0
1
1.16250
1
0
0
1
0
1
1
1.40000
1
1
1
0
0
0
0
1.15625
1
0
0
1
0
1
0
1.39375
1
1
1
0
0
1
1
1.15000
1
0
0
1
1
0
1
1.38750
1
1
1
0
0
1
0
1.14375
1
0
0
1
1
0
0
1.38125
1
1
1
0
1
0
1
1.13750
1
0
0
1
1
1
1
1.37500
1
1
1
0
1
0
0
1.13125
1
0
0
1
1
1
0
1.36875
1
1
1
0
1
1
1
1.12500
1
0
1
0
0
0
1
1.36250
1
1
1
0
1
1
0
1.11875
1
0
1
0
0
0
0
1.35625
1
1
1
1
0
0
1
1.11250
1
0
1
0
0
1
1
1.35000
1
1
1
1
0
0
0
1.10625
14
FN6715.0
May 22, 2008
ISL6322G
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES (Continued)
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VDAC
1
1
1
1
0
1
1
1.10000
0
1
0
0
0
0
0
0.88125
1
1
1
1
0
1
0
1.09375
0
1
0
0
0
1
1
0.87500
1
1
1
1
1
0
1
OFF
0
1
0
0
0
1
0
0.86875
1
1
1
1
1
0
0
OFF
0
1
0
0
1
0
1
0.86250
1
1
1
1
1
1
1
OFF
0
1
0
0
1
0
0
0.85625
1
1
1
1
1
1
0
OFF
0
1
0
0
1
1
1
0.85000
0
0
0
0
0
0
1
1.08750
0
1
0
0
1
1
0
0.84375
0
0
0
0
0
0
0
1.08125
0
1
0
1
0
0
1
0.83750
0
0
0
0
0
1
1
1.07500
0
1
0
1
0
0
0
0.83125
0
0
0
0
0
1
0
1.06875
0
0
0
0
1
0
1
1.06250
0
0
0
0
1
0
0
1.05625
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
0
0
0
1
1
1
1.05000
0
0
0
0
0
0
0
0
OFF
0
0
0
0
1
1
0
1.04375
0
0
0
0
0
0
0
1
OFF
0
0
0
1
0
0
1
1.03750
0
0
0
0
0
0
1
0
1.60000
0
0
0
1
0
0
0
1.03125
0
0
0
0
0
0
1
1
1.59375
0
0
0
1
0
1
1
1.02500
0
0
0
0
0
1
0
0
1.58750
0
0
0
1
0
1
0
1.01875
0
0
0
0
0
1
0
1
1.58125
0
0
0
1
1
0
1
1.01250
0
0
0
0
0
1
1
0
1.57500
0
0
0
1
1
0
0
1.00625
0
0
0
0
0
1
1
1
1.56875
0
0
0
1
1
1
1
1.00000
0
0
0
0
1
0
0
0
1.56250
0
0
0
1
1
1
0
0.99375
0
0
0
0
1
0
0
1
1.55625
0
0
1
0
0
0
1
0.98750
0
0
0
0
1
0
1
0
1.55000
0
0
1
0
0
0
0
0.98125
0
0
0
0
1
0
1
1
1.54375
0
0
1
0
0
1
1
0.97500
0
0
0
0
1
1
0
0
1.53750
0
0
1
0
0
1
0
0.96875
0
0
0
0
1
1
0
1
1.53125
0
0
1
0
1
0
1
0.96250
0
0
0
0
1
1
1
0
1.52500
0
0
1
0
1
0
0
0.95625
0
0
0
0
1
1
1
1
1.51875
0
0
1
0
1
1
1
0.95000
0
0
0
1
0
0
0
0
1.51250
0
0
1
0
1
1
0
0.94375
0
0
0
1
0
0
0
1
1.50625
0
0
1
1
0
0
1
0.93750
0
0
0
1
0
0
1
0
1.50000
0
0
1
1
0
0
0
0.93125
0
0
0
1
0
0
1
1
1.49375
0
0
1
1
0
1
1
0.92500
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
0
1
0
0.91875
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
0
1
0.91250
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
0
0
0.90625
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
1
1
0.90000
0
0
0
1
1
0
0
0
1.46250
0
0
1
1
1
1
0
0.89375
0
0
0
1
1
0
0
1
1.45625
0
1
0
0
0
0
1
0.88750
0
0
0
1
1
0
1
0
1.45000
15
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES
FN6715.0
May 22, 2008
ISL6322G
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
0
0
1
1
0
1
1
1.44375
0
1
0
0
0
0
1
0
1.20000
0
0
0
1
1
1
0
0
1.43750
0
1
0
0
0
0
1
1
1.19375
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
1
0
0
1.18750
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
1
0
1
1.18125
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
1
1
0
1.17500
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
0
1
1
1
1.16875
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
1
0
0
0
1.16250
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
1
0
0
1
1.15625
0
0
1
0
0
0
1
1
1.39375
0
1
0
0
1
0
1
0
1.15000
0
0
1
0
0
1
0
0
1.38750
0
1
0
0
1
0
1
1
1.14375
0
0
1
0
0
1
0
1
1.38125
0
1
0
0
1
1
0
0
1.13750
0
0
1
0
0
1
1
0
1.37500
0
1
0
0
1
1
0
1
1.13125
0
0
1
0
0
1
1
1
1.36875
0
1
0
0
1
1
1
0
1.12500
0
0
1
0
1
0
0
0
1.36250
0
1
0
0
1
1
1
1
1.11875
0
0
1
0
1
0
0
1
1.35625
0
1
0
1
0
0
0
0
1.11250
0
0
1
0
1
0
1
0
1.35000
0
1
0
1
0
0
0
1
1.10625
0
0
1
0
1
0
1
1
1.34375
0
1
0
1
0
0
1
0
1.10000
0
0
1
0
1
1
0
0
1.33750
0
1
0
1
0
0
1
1
1.09375
0
0
1
0
1
1
0
1
1.33125
0
1
0
1
0
1
0
0
1.08750
0
0
1
0
1
1
1
0
1.32500
0
1
0
1
0
1
0
1
1.08125
0
0
1
0
1
1
1
1
1.31875
0
1
0
1
0
1
1
0
1.07500
0
0
1
1
0
0
0
0
1.31250
0
1
0
1
0
1
1
1
1.06875
0
0
1
1
0
0
0
1
1.30625
0
1
0
1
1
0
0
0
1.06250
0
0
1
1
0
0
1
0
1.30000
0
1
0
1
1
0
0
1
1.05625
0
0
1
1
0
0
1
1
1.29375
0
1
0
1
1
0
1
0
1.05000
0
0
1
1
0
1
0
0
1.28750
0
1
0
1
1
0
1
1
1.04375
0
0
1
1
0
1
0
1
1.28125
0
1
0
1
1
1
0
0
1.03750
0
0
1
1
0
1
1
0
1.27500
0
1
0
1
1
1
0
1
1.03125
0
0
1
1
0
1
1
1
1.26875
0
1
0
1
1
1
1
0
1.02500
0
0
1
1
1
0
0
0
1.26250
0
1
0
1
1
1
1
1
1.01875
0
0
1
1
1
0
0
1
1.25625
0
1
1
0
0
0
0
0
1.01250
0
0
1
1
1
0
1
0
1.25000
0
1
1
0
0
0
0
1
1.00625
0
0
1
1
1
0
1
1
1.24375
0
1
1
0
0
0
1
0
1.00000
0
0
1
1
1
1
0
0
1.23750
0
1
1
0
0
0
1
1
0.99375
0
0
1
1
1
1
0
1
1.23125
0
1
1
0
0
1
0
0
0.98750
0
0
1
1
1
1
1
0
1.22500
0
1
1
0
0
1
0
1
0.98125
0
0
1
1
1
1
1
1
1.21875
0
1
1
0
0
1
1
0
0.97500
0
1
0
0
0
0
0
0
1.21250
0
1
1
0
0
1
1
1
0.96875
0
1
0
0
0
0
0
1
1.20625
0
1
1
0
1
0
0
0
0.96250
16
FN6715.0
May 22, 2008
ISL6322G
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 3. VR11 VOLTAGE IDENTIFICATION
CODES (Continued)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
1
1
0
1
0
0
1
0.95625
1
0
0
1
0
0
0
0
0.71250
0
1
1
0
1
0
1
0
0.95000
1
0
0
1
0
0
0
1
0.70625
0
1
1
0
1
0
1
1
0.94375
1
0
0
1
0
0
1
0
0.70000
0
1
1
0
1
1
0
0
0.93750
1
0
0
1
0
0
1
1
0.69375
0
1
1
0
1
1
0
1
0.93125
1
0
0
1
0
1
0
0
0.68750
0
1
1
0
1
1
1
0
0.92500
1
0
0
1
0
1
0
1
0.68125
0
1
1
0
1
1
1
1
0.91875
1
0
0
1
0
1
1
0
0.67500
0
1
1
1
0
0
0
0
0.91250
1
0
0
1
0
1
1
1
0.66875
0
1
1
1
0
0
0
1
0.90625
1
0
0
1
1
0
0
0
0.66250
0
1
1
1
0
0
1
0
0.90000
1
0
0
1
1
0
0
1
0.65625
0
1
1
1
0
0
1
1
0.89375
1
0
0
1
1
0
1
0
0.65000
0
1
1
1
0
1
0
0
0.88750
1
0
0
1
1
0
1
1
0.64375
0
1
1
1
0
1
0
1
0.88125
1
0
0
1
1
1
0
0
0.63750
0
1
1
1
0
1
1
0
0.87500
1
0
0
1
1
1
0
1
0.63125
0
1
1
1
0
1
1
1
0.86875
1
0
0
1
1
1
1
0
0.62500
0
1
1
1
1
0
0
0
0.86250
1
0
0
1
1
1
1
1
0.61875
0
1
1
1
1
0
0
1
0.85625
1
0
1
0
0
0
0
0
0.61250
0
1
1
1
1
0
1
0
0.85000
1
0
1
0
0
0
0
1
0.60625
0
1
1
1
1
0
1
1
0.84375
1
0
1
0
0
0
1
0
0.60000
0
1
1
1
1
1
0
0
0.83750
1
0
1
0
0
0
1
1
0.59375
0
1
1
1
1
1
0
1
0.83125
1
0
1
0
0
1
0
0
0.58750
0
1
1
1
1
1
1
0
0.82500
1
0
1
0
0
1
0
1
0.58125
0
1
1
1
1
1
1
1
0.81875
1
0
1
0
0
1
1
0
0.57500
1
0
0
0
0
0
0
0
0.81250
1
0
1
0
0
1
1
1
0.56875
1
0
0
0
0
0
0
1
0.80625
1
0
1
0
1
0
0
0
0.56250
1
0
0
0
0
0
1
0
0.80000
1
0
1
0
1
0
0
1
0.55625
1
0
0
0
0
0
1
1
0.79375
1
0
1
0
1
0
1
0
0.55000
1
0
0
0
0
1
0
0
0.78750
1
0
1
0
1
0
1
1
0.54375
1
0
0
0
0
1
0
1
0.78125
1
0
1
0
1
1
0
0
0.53750
1
0
0
0
0
1
1
0
0.77500
1
0
1
0
1
1
0
1
0.53125
1
0
0
0
0
1
1
1
0.76875
1
0
1
0
1
1
1
0
0.52500
1
0
0
0
1
0
0
0
0.76250
1
0
1
0
1
1
1
1
0.51875
1
0
0
0
1
0
0
1
0.75625
1
0
1
1
0
0
0
0
0.51250
1
0
0
0
1
0
1
0
0.75000
1
0
1
1
0
0
0
1
0.50625
1
0
0
0
1
0
1
1
0.74375
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
1
0
0
0.73750
1
1
1
1
1
1
1
0
OFF
1
0
0
0
1
1
0
1
0.73125
1
1
1
1
1
1
1
1
OFF
1
0
0
0
1
1
1
0
0.72500
1
0
0
0
1
1
1
1
0.71875
17
FN6715.0
May 22, 2008
ISL6322G
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION
CODES (Continued)
TABLE 4. AMD 5-BIT VOLTAGE IDENTIFICATION
CODES
VID4
VID3
VID2
VID1
VID0
VDAC
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
1
1
1
1
1
Off
0
0
0
1
0
0
1.4500
1
1
1
1
0
0.800
0
0
0
1
0
1
1.4250
1
1
1
0
1
0.825
0
0
0
1
1
0
1.4000
1
1
1
0
0
0.850
0
0
0
1
1
1
1.3750
1
1
0
1
1
0.875
0
0
1
0
0
0
1.3500
1
1
0
1
0
0.900
0
0
1
0
0
1
1.3250
1
1
0
0
1
0.925
0
0
1
0
1
0
1.3000
1
1
0
0
0
0.950
0
0
1
0
1
1
1.2750
1
0
1
1
1
0.975
0
0
1
1
0
0
1.2500
1
0
1
1
0
1.000
0
0
1
1
0
1
1.2250
1
0
1
0
1
1.025
0
0
1
1
1
0
1.2000
1
0
1
0
0
1.050
0
0
1
1
1
1
1.1750
1
0
0
1
1
1.075
0
1
0
0
0
0
1.1500
1
0
0
1
0
1.100
0
1
0
0
0
1
1.1250
1
0
0
0
1
1.125
0
1
0
0
1
0
1.1000
1
0
0
0
0
1.150
0
1
0
0
1
1
1.0750
0
1
1
1
1
1.175
0
1
0
1
0
0
1.0500
0
1
1
1
0
1.200
0
1
0
1
0
1
1.0250
0
1
1
0
1
1.225
0
1
0
1
1
0
1.0000
0
1
1
0
0
1.250
0
1
0
1
1
1
0.9750
0
1
0
1
1
1.275
0
1
1
0
0
0
0.9500
0
1
0
1
0
1.300
0
1
1
0
0
1
0.9250
0
1
0
0
1
1.325
0
1
1
0
1
0
0.9000
0
1
0
0
0
1.350
0
1
1
0
1
1
0.8750
0
0
1
1
1
1.375
0
1
1
1
0
0
0.8500
0
0
1
1
0
1.400
0
1
1
1
0
1
0.8250
0
0
1
0
1
1.425
0
1
1
1
1
0
0.8000
0
0
1
0
0
1.450
0
1
1
1
1
1
0.7750
0
0
0
1
1
1.475
1
0
0
0
0
0
0.7625
0
0
0
1
0
1.500
1
0
0
0
0
1
0.7500
0
0
0
0
1
1.525
1
0
0
0
1
0
0.7375
0
0
0
0
0
1.550
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION
CODES
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
1
0
0
1
1
0
0.6875
0
0
0
0
0
0
1.5500
1
0
0
1
1
1
0.6750
0
0
0
0
0
1
1.5250
1
0
1
0
0
0
0.6625
0
0
0
0
1
0
1.5000
1
0
1
0
0
1
0.6500
0
0
0
0
1
1
1.4750
1
0
1
0
1
0
0.6375
18
FN6715.0
May 22, 2008
ISL6322G
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION
CODES (Continued)
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
EXTERNAL CIRCUIT
ISL6322 INTERNAL CIRCUIT
COMP
VID DAC
CC
REF
1k
RC
CREF
FB
RFB
ERROR
AMPLIFIER
+
-
VCOMP
IOFS
+
VOFS
VDIFF
VOUT+
VOUT-
VSEN
+
-
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Voltage Regulation
Output-Voltage Offset Programming
The integrating compensation network shown in Figure 6
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6322G to include the
combined tolerances of each of these elements.
The ISL6322G allows the designer to accurately adjust the
offset voltage by connecting a resistor, ROFS, from the OFS
pin to VCC or GND. When ROFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into the FB pin.
If ROFS is connected to ground, the voltage across it is
regulated to 0.4V, and IOFS flows out of the FB pin. The
offset current flowing through the resistor between VDIFF
and FB will generate the desired offset voltage which is
equal to the product (IOFS x RFB). These functions are
shown in Figures 7 and 8.
The output of the error amplifier, VCOMP, is compared to the
triangle waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 8. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 6.
(EQ. 8)
V OUT = V REF – V OFS
The ISL6322G incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point
19
Once the desired output offset voltage has been determined,
use Equations 9 and 10 to set ROFS:
For Negative Offset (connect ROFS to GND):
0.4 ⋅ R FB
R OFS = -------------------------V OFFSET
(EQ. 9)
For Positive Offset (connect ROFS to VCC):
1.6 ⋅ R FB
R OFS = -------------------------V OFFSET
(EQ. 10)
FN6715.0
May 22, 2008
ISL6322G
INTEL DYNAMIC VID TRANSITIONS
FB
VOFS
+
RFB
E/A
IOFS
REF
1:1
CURRENT
MIRROR
VDIFF
IOFS
VCC
1.6V
+
ROFS
When in Intel VR10 or VR11 mode, the ISL6322G checks
the VID inputs on the positive edge of an internal 3MHz
clock. If a new code is established and it remains stable for 3
consecutive readings (1µs to 1.33µs), the ISL6322G
recognizes the new code and changes the internal DAC
reference directly to the new level. The Intel processor
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VR10 and VR11 settings, the ISL6322G will immediately
change the internal DAC reference to the new requested
value as soon as the request is validated, which means the
fastest recommended rate at which a bit change can occur is
once every 2µs. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
overvoltage events.
OFS
ISL6322G
VCC
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6322G
to do this by making changes to the VID inputs. The
ISL6322G is required to monitor the DAC inputs and respond
to on-the-fly VID changes in a controlled manner, supervising
a safe output voltage transition without discontinuity or
disruption. The DAC mode the ISL6322G is operating in
determines how the controller responds to a dynamic VID
change.
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
an internal 1kΩ resistor between the DAC and the REF pin,
and the external capacitor CREF, between the REF pin and
ground. The selection of CREF is based on the time duration
for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every TVID, the relationship between CREF and TVID is
given by Equation 11.
C REF = 0.001 ( S ) ⋅ T VID
(EQ. 11)
As an example, for a VID step change rate of 5µs per bit, the
value of CREF is 5600pF based on Equation 11.
AMD DYNAMIC VID TRANSITIONS
FB
+
VOFS
-
When running in AMD 5-bit or 6-bit modes of operation, the
ISL6322G responds differently to a dynamic VID change than
when in Intel VR10 or VR11 mode. In the AMD modes, the
ISL6322G still checks the VID inputs on the positive edge of
an internal 3MHz clock. In these modes the VID code can be
changed by more than a 1-bit step at a time. If a new code is
established and it remains stable for 3 consecutive readings
(1µs to 1.33µs), the ISL6322G recognizes the change and
begins slewing the DAC in 6.25mV steps at a stepping
frequency of 330kHz until the VID and DAC are equal. Thus,
the total time required for a VID change, tDVID, is dependent
only on the size of the VID change (ΔVVID).
E/A
RFB
IOFS
REF
VDIFF
VCC
1:1
CURRENT
MIRROR
IOFS
+
0.4V
OFS
ROFS
ISL6322G
GND
GND
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
20
The time required for a ISL6322G-based converter in AMD
5-bit DAC configuration to make a 1.1V to 1.5V reference
voltage change is about 194µs, as calculated using
Equation 12.
ΔV VID
1
t DVID = -------------------------- ⋅ ⎛ ---------------------⎞
3 ⎝ 0.00625⎠
330 × 10
(EQ. 12)
In order to ensure the smooth transition of output voltage
during an AMD VID change, a VID step change smoothing
network is required. This network is composed of an internal
FN6715.0
May 22, 2008
ISL6322G
User Selectable Adaptive Deadtime Control
Techniques
The ISL6322G integrated drivers incorporate two different
adaptive deadtime control techniques, which the user can
choose between. Both of these control techniques help to
minimize deadtime, resulting in high efficiency from the reduced
freewheeling time of the lower MOSFET body-diode
conduction, and both help to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
The difference between the two adaptive deadtime control
techniques is the method in which they detect that the lower
MOSFET has transitioned off in order to turn on the upper
MOSFET. The state of the internal I2C registers determines
which of the two control techniques is active (refer beginning
on page 27 for details of controlling deadtime control with
I2C). The default setting is PHASE Detect. If the PHASE
Detect Scheme is chosen, the voltage on the PHASE pin is
monitored to determine if the lower MOSFET has
transitioned off or not. Choosing the LGATE Detect Scheme
instructs the controller to monitor the voltage on the LGATE
pin to determine if the lower MOSFET has turned off or not.
For both schemes, the method for determining whether the
upper MOSFET has transitioned off in order to signal to turn
on the lower MOSFET is the same.
PHASE DETECT
For the PHASE detect scheme, during turn-off of the lower
MOSFET, the PHASE voltage is monitored until it reaches a
-0.3V/+0.8V (forward/reverse inductor current). At this time the
UGATE is released to rise. An auto-zero comparator is used to
correct the rDS(ON) drop in the phase voltage preventing false
detection of the -0.3V phase level during rDS(ON) conduction
period. In the case of zero current, the UGATE is released after
35ns delay of the LGATE dropping below 0.5V. When LGATE
first begins to transition low, this quick transition can disturb the
PHASE node and cause a false trip, so there is 20ns of
blanking time once LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
LGATE DETECT
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 13:
Q GATE
C BOOT_CAP ≥ -------------------------------------ΔV BOOT_CAP
(EQ. 13)
Q G1 ⋅ PVCC
Q GATE = ---------------------------------- ⋅ N Q1
V GS1
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. The ΔVBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
1.6
1.4
1.2
CBOOT_CAP (µF)
1kΩ resistor between the DAC and the REF pin, and the
external capacitor CREF, between the REF pin and ground.
For AMD VID transitions CREF should be a 1000pF
capacitor.
1.0
0.8
0.6
QGATE = 100nC
0.4
50nC
0.2
20nC
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
ΔVBOOT_CAP (V)
FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6322G provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
For the LGATE detect scheme, during turn-off of the lower
MOSFET, the LGATE voltage is monitored until it reaches
1.75V. At this time the UGATE is released to rise.
21
FN6715.0
May 22, 2008
ISL6322G
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC and the VID pins. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, the controller asserts
PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met, for both Intel and
AMD modes of operation, before the ISL6322G is released
from shutdown mode to begin the soft-start startup
sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6322G is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6322G will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” on page 6).
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6322G in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 6).
For Intel VR10, VR11 and AMD 6-bit modes of operation
these are the only conditions that must be met for the
controller to immediately begin the soft-start sequence. If
running in AMD 5-bit mode of operation there is one more
condition that must be met:
4. The VID code must not be 11111 in AMD 5-bit mode. This
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
to the user designated level.
Intel Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different then the AMD soft-start
sequence.
VOUT, 500mV/DIV
tD1
ISL6322G INTERNAL CIRCUIT
tD2
tD3
tD4
tD5
EXTERNAL CIRCUIT
EN_VTT
VCC
PVCC
+12V
POR
CIRCUIT
PGOOD
500µs/DIV
ENABLE
COMPARATOR
10.7kΩ
EN
+
-
1.40kΩ
0.85V
SOFT-START
AND
FAULT LOGIC
FIGURE 10. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
3. The driver bias voltage applied at the PVCC pin must
reach the internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
assure that once enabled, the ISL6322G will not
22
FIGURE 11. INTEL SOFT-START WAVEFORMS
For the Intel VR10 and VR11 modes of operation, the
soft-start sequence is composed of four periods, as shown in
Figure 11. Once the ISL6322G is released from shutdown
and soft-start begins (as described in the “Enable and
Disable” on page 22), the controller will have fixed delay
period tD1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V VBOOT
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period tD3. At the end of tD3 period,
ISL6322G will read the VID signals. If the VID code is valid,
ISL6322G will initiate the second soft-start ramp until the
output voltage reaches the VID voltage plus/minus any offset
voltage.
The soft-start time is the sum of the four periods as shown in
Equation 14.
T SS = t D1 + t D2 + t D3 + t D4
(EQ. 14)
FN6715.0
May 22, 2008
ISL6322G
TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
voltage to the final DAC voltage is referred to as TDB, and
can be calculated as shown in Equation 17.
During tD2 and tD4, ISL6322G digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor RSS from SS pin to GND. The
second soft-start ramp time tD2 and tD4 can be calculated
based on Equations 15 and 16:
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay tDC. The typical value
for tDC can range between 1.5ms and 3.0ms.
1.1 ⋅ R SS
t D2 = ------------------------ ( μs )
6.25 ⋅ 25
(EQ. 15)
( V VID – 1.1 ) ⋅ R SS
t D4 ( 2 ) = ---------------------------------------------------- ( μs )
6.25 ⋅ 25
(EQ. 16)
(EQ. 17)
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
For example, when VID is set to 1.5V and the RSS is set at
100kΩ, the first soft-start ramp time tD2 will be 704µs and the
second soft-start ramp time tD4 will be 256µs.
NOTE: If the SS pin is grounded, the soft-start ramp in tD2
and tD4 will be defaulted to a 6.25mV step frequency of
330kHz.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay tD5. The typical value
for tD5 is 440µs.
VOUT, 500mV/DIV
tDA
V VID
1
TDB = -------------------------- ⋅ ⎛ ---------------------⎞
3 ⎝ 0.00625⎠
330 × 10
tDB
tDC
EN_VTT
VOUT (0.5V/DIV)
GND>
EN (5V/DIV)
t1 t2
t3
FIGURE 13. SOFT-START WAVEFORMS FOR
ISL6322G-BASED MULTIPHASE CONVERTER
Pre-Biased Soft-Start
The ISL6322G also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
PGOOD
500µs/DIV
FIGURE 12. AMD SOFT-START WAVEFORMS
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of three periods, as shown
in Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period tDA. After this delay period the ISL6322G will
begin ramping the output voltage to the desired DAC level at
a fixed rate of 6.25mV per step, with a stepping frequency of
330kHz. The amount of time required to ramp the output
23
Fault Monitoring and Protection
The ISL6322G actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6322G is regulating the
output voltage within the proper levels, and whether any fault
FN6715.0
May 22, 2008
ISL6322G
conditions exist. This pin should be tied to a +5V source
through a resistor.
During shutdown and soft-start PGOOD pulls low and
releases high after a successful soft-start and the output
voltage is operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected or when the controller is disabled by a reset from
EN, POR, or one of the no-CPU VID codes. In the event of
an overvoltage or overcurrent condition, the controller
latches off and PGOOD will not return high until after a
successful soft-start. In the case of an undervoltage event,
PGOOD will return high when the output voltage returns to
within the undervoltage.
120µA OR
240µA
ISEN1+ISEN2
-
-
OCP
170µA
OCL
+
+
ISEN1
REPEAT FOR
EACH CHANNEL
VDAC
I2C OVP
REGISTER
+
+175mV,
+250mV,
+350mV
IOUT
OCP
-
changes depending on what mode of operation the controller
is in and what state the I2C registers and the VRSEL pin are
in. Tables 6 and 7 list what the OVP trip levels are under all
conditions (refer beginning on page 24 for details of
controlling OVP thresholds with I2C).
At the inception of an overvoltage event LGATE1 and
LGATE2 are commanded high and the PGOOD signal is
driven low. This turns on the all of the lower MOSFETs and
pulls the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high and
until VDIFF falls 100mV below the OVP threshold that
tripped the overvoltage protection circuitry. The ISL6322G
will continue to protect the load in this fashion as long as the
overvoltage condition recurs.
Once an overvoltage condition ends, the ISL6322G latches
off and must be reset by toggling EN, or through POR,
before a soft-start can be re-initiated.
TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS
MODE OF
OPERATION
DEFAULT
ALTERNATE
Soft-Start
(tD1 and tD2)
1.280V and
VDAC + 250mV
(higher of the two)
1.280V and
VDAC + 175mV
(higher of the two)
Soft-Start
(tD3 and tD4)
VDAC + 250mV
VDAC + 175mV
Normal Operation
VDAC + 250mV
VDAC + 175mV
VOCP
VRSEL
SOFT-START, FAULT
AND CONTROL LOGIC
VOVP
TABLE 7. AMD OVP THRESHOLDS
MODE OF
OPERATION
VSEN
+
+
OV
PGOOD
Soft-Start
x1
RGND
+
UV
VDIFF
0.60 x DAC
ISL6322G INTERNAL CIRCUITRY
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage (VSEN - RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 70% of the VID code.
Overvoltage Protection
The ISL6322G constantly monitors the sensed output voltage
on the VDIFF pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level
actions are taken by the ISL6322G to protect the
microprocessor load. The overvoltage protection trip level
24
Normal Operation
DEFAULT
ALTERNATE
2.200V and
VDAC + 250mV
(higher of the two)
2.200V and
VDAC + 175mV
(higher of the two)
VDAC + 250mV
VDAC + 175mV
One exception that overrides the overvoltage protection
circuitry is a dynamic VID transition in AMD modes of
operation. If a new VID code is detected during normal
operation, the OVP protection circuitry is disabled from the
beginning of the dynamic VID transition, until 50µs after the
internal DAC reaches the final VID setting. This is the only
time during operation of the ISL6322G that the OVP circuitry
is not active.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6322G is designed to protect the load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10kΩ resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
FN6715.0
May 22, 2008
ISL6322G
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Open Sense Line Prevention
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6322G is designed to prevent
the controller from regulating. This is accomplished by
means of a small 5µA pull-up current on VSEN, and a pulldown current on RGND. If the sense lines are opened at any
time, the voltage difference between VSEN and RGND will
increase until an overvoltage event occurs, at which point
overvoltage protection activates and the controller stops
regulating. The ISL6322G will be latched off and cannot be
restarted until the controller is reset.
Overcurrent Protection
The ISL6322G takes advantage of the proportionality
between the load current and the total channel sense
current, ISEN1+ISEN2, to detect an overcurrent condition.
Two different methods of detecting overcurrent events are
available on the ISL6322G. The first method continually
compares the average sense current with an OCP reference
current as shown in Figure 14. The value of the OCP
reference current is dependant upon the number of channels
operating. If the controller is operating in 2-phase mode the
OCP reference current is 240µA. If the controller is operating
in single phase mode the OCP reference current is 120µA.
This ensures that the OCP trip current scales properly with
the number of channels firing. Once the total sense current
exceeds the OCP reference current, a comparator triggers
the converter to begin overcurrent protection procedures.
This first method for detecting overcurrent events limits the
minimum overcurrent trip threshold because of the fact the
ISL6322G uses set internal RISEN current sense resistors.
For this first method the minimum overcurrent trip threshold
is dictated by the DCR of the inductors and the number of
active channels. To calculate the minimum overcurrent trip
level, IOCP,min, use Equation 18, where N is the number of
active channels, DCR is the individual inductor’s DCR, and
RISEN is the 300Ω internal current sense resistor.
–6
⎛ 120 ⋅ 10 ⋅ R ISEN ⋅ N⎞ ⎛ R 1 + R 2⎞
I OCP = ⎜ ----------------------------------------------------------⎟ ⋅ ⎜ ---------------------⎟
DCR
⎝
⎠ ⎝ R2 ⎠
(EQ. 19)
I OCP > I OCP, min
If an overcurrent trip level lower then IOCP,min is desired,
then a second method for setting the OCP trip level is
available.
The second method for detecting overcurrent events
continuously compares the voltage on the IOUT pin, VIOUT,
to the overcurrent protection voltage, VOCP, as shown in
Figure 14. The total channel sense current flows out the
IOUT pin and through RIOUT, creating the IOUT pin voltage
which is proportional to the output current. When the IOUT
pin voltage exceeds the VOCP voltage of 2.0V, the
overcurrent protection circuitry activates. Since the IOUT pin
voltage is proportional to the output current, the overcurrent
trip level, IOCP, can be set by selecting the proper value for
RIOUT, as shown in Equation 20.
V OCP ⋅ R ISEN
I OCP = -------------------------------------DCR ⋅ R IOUT
I OCP < I OCP, min
(EQ. 20)
Once the output current exceeds the overcurrent trip level,
VIOUT will exceed VOCP and a comparator will trigger the
converter to begin overcurrent protection procedures.
At the beginning of overcurrent shutdown, the controller sets
all of the UGATE and LGATE signals low and forces PGOOD
low. This turns off all of the upper and lower MOSFETs. The
system remains in this state for a fixed period of 12ms. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start. If the fault remains, the trip-retry cycles
will continue indefinitely until either the controller is disabled
or the fault is cleared. Note that the energy delivered during
trip-retry cycling is much less than during full-load operation,
so there is no thermal hazard.
OUTPUT CURRENT, 50A/DIV
0A
–6
120 ⋅ 10 ⋅ R ISEN ⋅ N
I OCP, min = --------------------------------------------------------DCR
OUTPUT VOLTAGE,
500mV/DIV
(EQ. 18)
If the desired overcurrent trip level is greater than the
minimum overcurrent trip level, IOCP,min, then the resistor
divider R-C circuit around the inductor shown in Figure 15
should be used to set the desired trip level.
0V
3ms/DIV
FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE
Individual Channel Overcurrent Limiting
The ISL6322G has the ability to limit the current in each
individual channel without shutting down the entire regulator.
25
FN6715.0
May 22, 2008
ISL6322G
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 170µA OCL
reference current as shown in Figure 14. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the
rise of current in that channel, forcing the current in the
channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel-current falls
back below the 170µA reference.
the POR rising threshold. The I2C will continue to remain
active until the voltage on the VCC pin falls back below the
falling POR threshold level.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 16.
SDA
I2C Bus Interface
The ISL6322G includes an I2C bus interface which allows
for user programmability of five of the controller’s operating
parameters. The operating parameters that can be adjusted
through the I2C are:
1. Number of Phases Firing: Selects whether the
controller should run in single phase or 2-phase mode.
The EN_PH2 pin must be tied low for the number of
phases firing to be controlled by the I2C bus interface.
2. Voltage Margining Offset: The output voltage can be
positively offset up to +787.5mV in 12.5mV increments.
3. Adaptive Deadtime Control: Selects between LGATE
Detect and PHASE Detect deadtime control schemes as
described in the “User Selectable Adaptive Deadtime
Control Techniques” on page 21.
SCL
DATA LINE CHANGE
STABLE
OF DATA
DATA VALID ALLOWED
FIGURE 16. DATA VALIDITY
START and STOP Conditions
As shown in Figure 17, a START (S) condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The STOP (P) condition is a LOW to HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be sent
before each START condition.
4. Overvoltage Trip Level: Selects the overvoltage
protection trip threshold as described in the “Overvoltage
Protection” on page 24.
SDA
5. Switching Frequency: The switching frequency can be
increased by a fixed +15% or +30%, or can be decreased
by -15% or -30%.
SCL
To adjust these five parameters, data transmission from the
main microprocessor to the ISL6322G and vice versa must
take place through the two wire I2C bus interface. The two
wires of the I2C bus consist of the SDA line, over which all data
is sent, and the SCL line, which is a clock signal used to
synchronize sending/receiving of the data.
Both SDA and SCL are bidirectional lines, externally connected
to a positive supply voltage via a pull-up resistor. Pull-up
resistor values should be chosen to limit the input current to
less then 3mA. When the bus is free, both lines are HIGH. The
output stages of ISL6322G have an open drain/open collector
in order to perform the wired-AND function. Data on the I2C bus
can be transferred up to 100kbps in the standard-mode or up to
400Kbps in the fast-mode. The level of logic “0” and logic “1” is
dependent on associated value of VDD as per the “Electrical
Specifications” table on page 6. One clock pulse is generated
for each data bit transferred. The ISL6322G is a “SLAVE only”
device, so the SCL line must always be controlled by an
external master.
S
P
START
CONDITION
STOP
CONDITION
FIGURE 17. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB) and the least significant bit last (LSB).
Acknowledge
Each address and data transmission uses 9-clock pulses.
The ninth pulse is the acknowledge bit (A). After the start
condition, the master sends 7-slave address bits and a R/W
bit during the next 8-clock pulses. During the ninth clock
pulse, the device that recognizes its own address holds the
data line low to acknowledge. The acknowledge bit is also
used by both the master and the slave to acknowledge
receipt of register addresses and data as described as
follows.
It is important to note that the I2C interface of the ISL6322G
only works once the voltage on the VCC pin has risen above
26
FN6715.0
May 22, 2008
ISL6322G
Writing to the Internal Registers
.
SCL
1
8
2
9
SDA
In order to change any of the four operating parameters via
the I2C bus, the internal registers must be written to. The two
registers inside the ISL6322G can be written individually with
two separate write transactions or sequentially with one write
transaction by sending two data bytes as described below.
MSB
START
ACKNOWLEDGE
FROM SLAVE
FIGURE 18. ACKNOWLEDGE ON THE I2C BUS
ISL6322G I2C Slave Address
All devices on the I2C bus must have a 7-bit I2C address in
order to be recognized. The ISL6322G has two user
selectable addresses to ensure it does not interfere with
other devices on the bus. The address is programmed via
the Rss resistor on the SS/RST/A0 pin. Placing the Rss
resistor from the SS/RST/A0 pin to ground sets the I2C
address to be 1000_110. If the Rss resistor is placed from
the SS/RST/A0 pin to VCC the address is 1000_111.
Please note that the I2C address of the ISL6322G is
programmed from the SS/RST/A0 pin as soon as VCC rises
above the POR threshold. The ISL6322G’s I2C address
stays the same and can not be reprogrammed until VCC
falls back below the POR falling threshold.
Communicating Over the I2C Bus
Two transactions are supported on the I2C interface:
1. Write register,
2. Read register from current address.
All transactions start with a control byte sent from the I2C
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address. The last bit sent by the
master is the R/W bit and is 0 for a write or 1 for a read. If any
slaves on the I2C bus recognize their address, they will
Acknowledge by pulling the serial data line low for the last clock
cycle in the control byte. If no slaves exist at that address or are
not ready to communicate, the data line will be 1, indicating a
Not Acknowledge condition.
To write to a single register in the ISL6322G, the master
sends a control byte with the R/W bit set to 0, indicating a
write. If it receives an Acknowledge from the ISL6322G, it
sends a register address byte representing the internal
register it wants to write to (0000_0000 for RGS1 or
0000_0001 for RGS2). The ISL6322G will respond with an
Acknowledge. The master then sends a byte representing
the data byte to be written into the desired register. The
ISL6322G will respond with an Acknowledge. The master
then issues a Stop condition, indicating to the ISL6322G that
the current transaction is complete. Once this transaction
completes, the ISL6322G will immediately update and
change the operating parameters on-the-fly.
It is also possible to write to both registers sequentially. To
do this the master must write to register RGS1 first. This
transaction begins with the master sending a control byte
with the R/W bit set to 0. If it receives an Acknowledge from
the ISL6322G, it sends the register address byte 0000_0000,
representing the internal register RGS1. The ISL6322G will
respond with an Acknowledge. After sending the data byte to
RGS1 and receiving an Acknowledge from the ISL6322G,
instead of sending a Stop condition, the master sends the
data byte to be stored in register RGS2. The ISL6322G will
respond with an Acknowledge. The master then issues a
Stop condition, indicating to the ISL6322G that the current
transaction is complete. Once this transaction completes the
ISL6322G will immediately update and change the operating
parameters on-the-fly.
Once the control byte is sent, and the ISL6322G
acknowledges it, the 2nd byte sent by the master must be a
register address byte. This register address byte tells the
ISL6322G which one of the two internal registers it wants to
write to or read from. The address of the first internal
register, RGS1, is 0000_0000. This register sets the Voltage
Margining Offset. The address of the second internal
register, RGS2, is 0000_0001. This register sets the
Adaptive Deadtime Control, Overvoltage Protection, and
Switching Frequency parameters. Once the ISL6322G
receives a correct register address byte, it responds with an
acknowledge.
27
FN6715.0
May 22, 2008
ISL6322G
I2C Read and Write Protocol
Write to a Single Register
S
slave_addr + W
A
reg_addr
A
reg_data
A
P
A
0000_0000
A
reg_RGS1_data
A
reg_RGS2_data
reg_addr
A
P
S
slave_addr + R
A
reg_data
N
P
0000_0000
A
P
S
slave_addr + R
A
reg_RGS1_data
A
reg_RGS2_data
Write to Both Registers
S
slave_addr + W
A
P
Read from a Single Register
S
slave_addr + W
A
Read from Both Registers
S
slave_addr + W
A
Driven by Master
S = START Condition
A = Acknowledge
Driven by ISL6322
P = STOP Condition
N = No Acknowledge
N
P
Reading from the Internal Registers
Resetting the Internal Registers
The ISL6322G has the ability to read from both registers
separately or read from them consecutively. Prior to reading
from an internal register, the master must first select the
desired register by writing to it and sending the register’s
address byte. This process begins by the master sending a
control byte with the R/W bit set to 0, indicating a write. Once
it receives an Acknowledge from the ISL6322G, it sends a
register address byte representing the internal register it
wants to read from (0000_0000 for RGS1 or 0000_0001 for
RGS2). The ISL6322G will respond with an Acknowledge.
The master must then respond with a Stop condition. After
the Stop condition, the master follows with a new Start
condition, and then sends a new control byte with the R/W
bit set to 1, indicating a read. The ISL6322G will then
respond by sending the master an Acknowledge, followed by
the data byte stored in that register. The master must then
send a Not Acknowledge followed by a Stop command,
which will complete the read transaction.
The ISL6322G’s two internal I2C registers always initialize to
0000_0000 when the controller first receives power. Once
the voltage on the VCC pin rises above the POR rising
threshold level, these registers can be changed at any time
via the I2C interface. If the voltage on the VCC pin falls
below the POR falling threshold, the internal registers are
automatically reset to 0000_0000.
It is also possible for both registers to be read consecutively.
To do this the master must read from register RGS1 first.
This transaction begins with the master sending a control
byte with the R/W bit set to 0. If it receives an Acknowledge
from the ISL6322G, it sends the register address byte
0000_0000, representing the internal register RGS1. The
ISL6322G will respond with an Acknowledge. The master
must then respond with a Stop condition. After the Stop
condition the master follows with a new Start condition, and
then sends a new control byte with the R/W bit set to 1,
indicating a read. The ISL6322G will then respond by
sending the master an Acknowledge, followed by the data
byte stored in register RGS. The master must then send an
Acknowledge, and after doing so, the ISL6322G will respond
by sending the data byte stored in register RGS2. The
master must then send a Not Acknowledge followed by a
Stop command, which will complete the read transaction.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
X
VO5
VO4
VO3
VO2
VO1
VO0
VOFFSET
(mV)
x
x
0
0
0
0
0
0
0.0
x
x
0
0
0
0
0
1
12.5
x
x
0
0
0
0
1
0
25.0
x
x
0
0
0
0
1
1
37.5
x
x
0
0
0
1
0
0
50.00
x
x
0
0
0
1
0
1
62.5
x
x
0
0
0
1
1
0
75.0
x
x
0
0
0
1
1
1
87.5
x
x
0
0
1
0
0
0
100.0
x
x
0
0
1
0
0
1
112.5
28
It is possible to reset the internal registers without powering
down the controller and without requiring the controller to
stop regulating and soft-start again. This can be done by one
of two methods. The first method is to simply write to the
internal registers over the I2C interface to be 0000_0000.
The other method is pull the voltage on the SS/RST/A0 pin
down below 0.4V. This will immediately reset the internal
registers to 0000_0000 and will not stop the controller from
regulating the output voltage or cause soft-start to recycle.
TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING
OFFSET)
FN6715.0
May 22, 2008
ISL6322G
TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING
OFFSET) (Continued)
TABLE 8. REGISTER RGS1 (VOLTAGE MARGINING
OFFSET) (Continued)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
X
VO5
VO4
VO3
VO2
VO1
VO0
VOFFSET
(mV)
125.0
x
x
1
1
0
0
0
0
600.0
1
137.5
x
x
1
1
0
0
0
1
612.5
0
0
150.0
x
x
1
1
0
0
1
0
625.0
1
0
1
162.5
x
x
1
1
0
0
1
1
637.5
1
1
1
0
175.0
x
x
1
1
0
1
0
0
650.0
0
1
1
1
1
187.5
x
x
1
1
0
1
0
1
662.5
0
1
0
0
0
0
200.00
x
x
1
1
0
1
1
0
675.0
x
0
1
0
0
0
1
212.5
x
x
1
1
0
1
1
1
687.5
x
x
0
1
0
0
1
0
225.0
x
x
1
1
1
0
0
0
700.0
x
x
0
1
0
0
1
1
237.5
x
x
1
1
1
0
0
1
712.5
x
x
0
1
0
1
0
0
250.0
x
x
1
1
1
0
1
0
725.0
x
x
0
1
0
1
0
1
262.5
x
x
1
1
1
0
1
1
737.5
x
x
0
1
0
1
1
0
275.0
x
x
1
1
1
1
0
0
750.0
x
x
0
1
0
1
1
1
287.5
x
x
1
1
1
1
0
1
762.5
x
x
0
1
1
0
0
0
300.0
x
x
1
1
1
1
1
0
775.0
x
x
0
1
1
0
0
1
312.5
x
x
1
1
1
1
1
1
787.5
x
x
0
1
1
0
1
0
325.0
x
x
0
1
1
0
1
1
337.5
x
x
0
1
1
1
0
0
350.0
x
x
0
1
1
1
0
1
362.5
x
x
0
1
1
1
1
0
375.0
x
x
0
1
1
1
1
1
387.5
x
x
1
0
0
0
0
0
400.0
x
x
1
0
0
0
0
1
412.5
x
x
1
0
0
0
1
0
425.0
x
x
1
0
0
0
1
1
437.5
x
x
1
0
0
1
0
0
450.0
x
x
1
0
0
1
0
1
462.5
x
x
1
0
0
1
1
0
475.0
x
x
1
0
0
1
1
1
487.5
x
x
1
0
1
0
0
0
500.0
x
x
1
0
1
0
0
1
512.5
x
x
1
0
1
0
1
0
525.0
x
x
1
0
1
0
1
1
537.5
x
x
1
0
1
1
0
0
550.0
x
x
1
0
1
1
0
1
562.5
x
x
1
0
1
1
1
0
575.0
x
x
1
0
1
1
1
1
587.5
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
X
VO5
VO4
VO3
VO2
VO1
VO0
VOFFSET
(mV)
x
x
0
0
1
0
1
0
x
x
0
0
1
0
1
x
x
0
0
1
1
x
x
0
0
1
x
x
0
0
x
x
0
x
x
x
29
FN6715.0
May 22, 2008
ISL6322G
TABLE 9. REGISTER RGS2 (# OF PHASES/ADAPTIVE DEADTIME CONTROL/OVERVOLTAGE PROTECTION/SWITCHING
FREQUENCY)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
CH0
DT1
DT0
OVP
FS2
FS1
FS0
NUMBER OF
CHANNELS
ADAPTIVE DEADTIME
CONTROL
x
0
0
0
0
0
0
0
2-Phase
PHASE DETECT
DEFAULT
NOMINAL
x
0
0
0
0
0
0
1
2-Phase
PHASE DETECT
DEFAULT
-15%
x
0
0
0
0
0
1
0
2-Phase
PHASE DETECT
DEFAULT
-30%
x
0
0
0
0
0
1
1
2-Phase
PHASE DETECT
DEFAULT
+15%
x
0
0
0
0
1
0
0
2-Phase
PHASE DETECT
DEFAULT
+30%
x
0
0
0
1
0
0
0
2-Phase
PHASE DETECT
ALTERNATE
NOMINAL
x
0
0
0
1
0
0
1
2-Phase
PHASE DETECT
ALTERNATE
-15%
x
0
0
0
1
0
1
0
2-Phase
PHASE DETECT
ALTERNATE
-30%
x
0
0
0
1
0
1
1
2-Phase
PHASE DETECT
ALTERNATE
+15%
x
0
0
0
1
1
0
0
2-Phase
PHASE DETECT
ALTERNATE
+30%
x
0
0
1
0
0
0
0
2-Phase
LGATE DETECT
DEFAULT
NOMINAL
x
0
0
1
0
0
0
1
2-Phase
LGATE DETECT
DEFAULT
-15%
x
0
0
1
0
0
1
0
2-Phase
LGATE DETECT
DEFAULT
-30%
x
0
0
1
0
0
1
1
2-Phase
LGATE DETECT
DEFAULT
+15%
x
0
0
1
0
1
0
0
2-Phase
LGATE DETECT
DEFAULT
+30%
x
0
0
1
1
0
0
0
2-Phase
LGATE DETECT
ALTERNATE
NOMINAL
x
0
0
1
1
0
0
1
2-Phase
LGATE DETECT
ALTERNATE
-15%
x
0
0
1
1
0
1
0
2-Phase
LGATE DETECT
ALTERNATE
-30%
x
0
0
1
1
0
1
1
2-Phase
LGATE DETECT
ALTERNATE
+15%
x
0
0
1
1
1
0
0
2-Phase
LGATE DETECT
ALTERNATE
+30%
x
1
0
0
0
0
0
0
1-Phase
PHASE DETECT
DEFAULT
NOMINAL
x
1
0
0
0
0
0
1
1-Phase
PHASE DETECT
DEFAULT
-15%
x
1
0
0
0
0
1
0
1-Phase
PHASE DETECT
DEFAULT
-30%
x
1
0
0
0
0
1
1
1-Phase
PHASE DETECT
DEFAULT
+15%
x
1
0
0
0
1
0
0
1-Phase
PHASE DETECT
DEFAULT
+30%
x
1
0
0
1
0
0
0
1-Phase
PHASE DETECT
ALTERNATE
NOMINAL
x
1
0
0
1
0
0
1
1-Phase
PHASE DETECT
ALTERNATE
-15%
x
1
0
0
1
0
1
0
1-Phase
PHASE DETECT
ALTERNATE
-30%
x
1
0
0
1
0
1
1
1-Phase
PHASE DETECT
ALTERNATE
+15%
x
1
0
0
1
1
0
0
1-Phase
PHASE DETECT
ALTERNATE
+30%
x
1
0
1
0
0
0
0
1-Phase
LGATE DETECT
DEFAULT
NOMINAL
x
1
0
1
0
0
0
1
1-Phase
LGATE DETECT
DEFAULT
-15%
x
1
0
1
0
0
1
0
1-Phase
LGATE DETECT
DEFAULT
-30%
x
1
0
1
0
0
1
1
1-Phase
LGATE DETECT
DEFAULT
+15%
x
1
0
1
0
1
0
0
1-Phase
LGATE DETECT
DEFAULT
+30%
x
1
0
1
1
0
0
0
1-Phase
LGATE DETECT
ALTERNATE
NOMINAL
x
1
0
1
1
0
0
1
1-Phase
LGATE DETECT
ALTERNATE
-15%
x
1
0
1
1
0
1
0
1-Phase
LGATE DETECT
ALTERNATE
-30%
30
OVERVOLTAGE
SWITCHING
PROTECTION LEVEL FREQUENCY
FN6715.0
May 22, 2008
ISL6322G
TABLE 9. REGISTER RGS2 (# OF PHASES/ADAPTIVE DEADTIME CONTROL/OVERVOLTAGE PROTECTION/SWITCHING
FREQUENCY) (Continued)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
CH0
DT1
DT0
OVP
FS2
FS1
FS0
NUMBER OF
CHANNELS
ADAPTIVE DEADTIME
CONTROL
x
1
0
1
1
0
1
1
1-Phase
LGATE DETECT
ALTERNATE
+15%
x
1
0
1
1
1
0
0
1-Phase
LGATE DETECT
ALTERNATE
+30%
OVERVOLTAGE
SWITCHING
PROTECTION LEVEL FREQUENCY
NOTE: It is recommended that frequency shifts occur in 15% increments only.
General Design Guide
This section is intended to provide a high-level explanation of
the steps necessary to create a multiphase power converter. It
is assumed that the reader is familiar with many of the basic
skills and techniques referenced in the following. In addition to
this guide, Intersil provides complete reference designs that
include schematics, bills of materials, and example board
layouts for all common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis, which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heatdissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(rDS(ON)). In Equation 21, IM is the maximum continuous
output current, IP-P is the peak-to-peak inductor current (see
Equation 1), and d is the duty cycle (VOUT/VIN).
I L, P-P2⋅ ( 1 – d )
⎛ I M⎞ 2
P LOW, 1 = r DS ( ON ) ⋅ ⎜ -----⎟ ⋅ ( 1 – d ) + -------------------------------------12
⎝ N⎠
31
(EQ. 21)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON), the switching
frequency, fS, and the length of dead times, tD1 and tD2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
⎛I
⎞
⎛ IM I
⎞
⎟
M I----------P LOW, 2 = V D ( ON ) ⋅ f S ⋅ ⎜ -----P-P⎟ ⋅ t
+ ⎜ -----+ ----------– P-P⎟ ⋅ t D2
2 ⎠
⎝N
2 ⎠ d1 ⎜⎝ N
(EQ. 22)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of PLOW,1 and PLOW,2.
UPPER MOSFET POWER CALCULATION
In addition to rDS(ON) losses, a large portion of the
upper-MOSFET losses are due to currents conducted
across the input voltage (VIN) during switching. Since a
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode
reverse-recovery charge, Qrr, and the upper MOSFET
rDS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 23,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
I M I P-P⎞ ⎛ t 1 ⎞
P UP,1 ≈ V IN ⋅ ⎛ ----- ⋅ ⎜ ---- ⎟ ⋅ f
⎝ N- + --------2 ⎠ ⎝ 2⎠ S
(EQ. 23)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 24, the
approximate power loss is PUP,2.
⎛ I M I P-P⎞
P UP, 2 ≈ V IN ⋅ ⎜ ----- – ----------⎟
2 ⎠
⎝N
⎛t ⎞
⋅ ⎜ ----2 ⎟ ⋅ f S
⎝ 2⎠
(EQ. 24)
A third component involves the lower MOSFET
reverse-recovery charge, Qrr. Since the inductor current has
FN6715.0
May 22, 2008
ISL6322G
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Qrr, it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is PUP,3.
P UP,3 = V IN ⋅ Q rr ⋅ f S
(EQ. 25)
Finally, the resistive part of the upper MOSFET is given in
Equation 26 as PUP,4.
2
2
I P-P
⎛ I M⎞
P UP,4 ≈ r DS ( ON ) ⋅ d ⋅ ⎜ -----⎟ + ---------12
⎝ N⎠
(EQ. 26)
In Equations 27 and 28, PQg_Q1 is the total upper gate drive
power loss and PQg_Q2 is the total lower gate drive power loss;
the gate charge (QG1 and QG2) is defined at the particular gate
to source drive voltage PVCC in the corresponding MOSFET
data sheet; IQ is the driver total quiescent current with no load
at both drive outputs; NQ1 and NQ2 are the number of upper
and lower MOSFETs per phase, respectively; NPHASE is the
number of active phases. The IQ*VCC product is the quiescent
power of the controller without capacitive load and is typically
75mW at 300kHz.
PVCC
D
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results from
Equations 23, 24, 25 and 26. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
CGD
RHI1
RG1
CDS
RGI1
CGS
Q1
S
PHASE
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three drivers
in the controller package, the total power dissipated by all three
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 36 for
thermal transfer improvement suggestions.
When designing the ISL6322G into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, PQg_TOT, due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 27 and 28, respectively.
(EQ. 27)
3
P Qg_Q1 = --- ⋅ Q G1 ⋅ PVCC ⋅ F SW ⋅ N Q1 ⋅ N PHASE
2
P Qg_Q2 = Q G2 ⋅ PVCC ⋅ F SW ⋅ N Q2 ⋅ N PHASE
.
3
+ Q G2 ⋅ N Q2⎞ ⋅ N PHASE ⋅ F SW + I Q
I DR = ⎛ --- ⋅ Q G1 ⋅ N
⎝2
⎠
Q1
(EQ. 28)
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
CGD
RHI2
LGATE
RLO2
G
RG2
CDS
RGI2
CGS
Q2
S
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, PDR_UP, the lower drive path resistance,
PDR_UP, and in the boot strap diode, PBOOT.
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ⋅ VCC )
(EQ. 29)
P Qg_Q1
P BOOT = --------------------3
R LO1
R HI1
⎛
⎞ P Qg_Q1
P DR_UP = ⎜ -------------------------------------- + ----------------------------------------⎟ ⋅ --------------------3
⎝ R HI1 + R EXT1 R LO1 + R EXT1⎠
R LO2
R HI2
⎛
⎞ P Qg_Q2
P DR_LOW = ⎜ -------------------------------------- + ----------------------------------------⎟ ⋅ --------------------R
+
R
R
+
R
2
⎝ HI2
EXT2
LO2
EXT2⎠
R GI1
R EXT1 = R G1 + ------------N
Q1
32
G
UGATE
RLO1
Package Power Dissipation
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ⋅ VCC
BOOT
R GI2
R EXT2 = R G2 + ------------N
Q2
FN6715.0
May 22, 2008
ISL6322G
The rest of the power will be dissipated by the external gate
resistors (RG1 and RG2) and the internal gate resistors
(RGI1 and RGI2) of the MOSFETs. Figures 19 and 20 show
the typical upper and lower gate drives turn-on transition
path. The total power dissipation in the controller itself, PDR,
can be roughly estimated with Equation 29.
If the desired overcurrent trip level is equal to or less
than the minimum overcurrent trip level, follow the steps
below to choose the component values for the R-C
current sensing network:
1. Choose an arbitrary value for C1. The recommended
value is 0.1µF.
Inductor DCR Current Sensing Component
Selection
The ISL6322G senses each individual channel’s inductor
current by detecting the voltage across the output inductor
DCR of that channel (as described in “Continuous Current
Sampling” on page 12). As Figure 21 illustrates, an R-C
network is required to accurately sense the inductor DCR
voltage and convert this information into a current, which is
proportional to the total output current. The time constant of
this R-C network must match the time constant of the
inductor L/DCR.
The R-C network across the inductor also sets the
overcurrent trip threshold for the regulator. Before the R-C
components can be selected, the desired overcurrent
protection level should be chosen. The minimum overcurrent
trip threshold the controller can support is dictated by the
DCR of the inductors and the number of active channels. To
calculate the minimum overcurrent trip level, IOCP,min, use
Equation 30, where N is the number of active channels, and
DCR is the individual inductor’s DCR.
0.036 ⋅ N
I OCP, min = ----------------------DCR
L
R 1 = ------------------------DCR ⋅ C 1
(EQ. 31)
I OCP = I OCP, min
3. Resistor R2 should be left unpopulated.
If the desired overcurrent trip level, IOCP, is greater than the
minimum overcurrent trip level, IOCP,min, then a resistor
divider R-C circuit should be used to set the desired trip
level.
Take the following steps to choose the component
values for the resistor divider R-C current sensing
network:
1. Choose an arbitrary value for C1. The recommended
value is 0.1µF.
2. Plug the inductor L and DCR component values, the
value for C1 chosen in step 1, the number of active
channels N, and the desired overcurrent protection level
IOCP into Equations 32 and 33 to calculate the values for
R1 and R2.
(EQ. 30)
VIN
L ⋅ I OCP
R 1 = ----------------------------------C 1 ⋅ 0.036 ⋅ N
I OCP > I OCP, min
(EQ. 32)
.
I
L
UGATE(n)
L
MOSFET
LGATE(n)
DCR
+
VL(s)
R1
COUT
VC(s)
-
+
INDUCTOR
VOUT
-
DRIVER
2. Plug the inductor L and DCR component values, and the
value for C1 chosen in step 1, into Equation 31 to
calculate the value for R1.
C1
R2*
ISL6322G INTERNAL CIRCUIT
In
L ⋅ I OCP
R 2 = -----------------------------------------------------------------------------C 1 ⋅ ( I OCP ⋅ DCR – 0.036 ⋅ N )
(EQ. 33)
IOUT Pin Resistor
A copy of the total channel sense current, ISEN1+ISEN2,
flows out of the IOUT pin, and a resistor, RIOUT, placed from
this pin to ground can be used to set the overcurrent
protection trip level. Based on the desired overcurrent trip
threshold, IOCP, the IOUT pin resistor, RIOUT, can be
calculated from Equation 34 or Equation 35, depending on
the R-C current sense circuitry being employed. If a basic
R-C sense circuit consisting of C1 and R1 is being used, use
Equation 36. If a resistor divider R-C sense circuit consisting
of R1, R2, and C1 is being used, use Equation 36.
SAMPLE
-
VC(s)
RISEN
-
+
+
ISEN-(n)
ISEN+(n)
*R2 is OPTIONAL
ISEN
600
R IOUT = -------------------------------DCR ⋅ I OCP
I OCP ≤ I OCP, min
(EQ. 34)
⎛ R 1 + R 2⎞
600
R IOUT = -------------------------------- ⋅ ⎜ ---------------------⎟
DCR ⋅ I OCP ⎝ R 2 ⎠
I OCP > I OCP, min
(EQ. 35)
FIGURE 21. DCR SENSING CONFIGURATION
33
FN6715.0
May 22, 2008
ISL6322G
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. The regulated converter is
accurately modeled as a voltage-mode regulator with two
poles at the L-C resonant frequency and a zero at the ESR
frequency. A type III controller, as shown in Figure 23,
provides the necessary compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, fHF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose fHF = 10f0, but it can be
higher if desired. Choosing fHF to be lower than 10f0 can
cause problems with too much phase shift below the system
bandwidth.
C2
RC
CC
COMP
FB
C1
ISL6322G
RFB
R1
VDIFF
FIGURE 22. COMPENSATION CIRCUIT
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 36, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 36.
C ⋅ ESR
R 1 = R FB ⋅ -------------------------------------------L ⋅ C – C ⋅ ESR
In Equation 36, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VP-P is the
peak-to-peak sawtooth signal amplitude as described in
“Electrical Specifications” on page 6.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔVMAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by the amount
specified in Equation 37.
di
ΔV ≈ ESL ⋅ ----- + ESR ⋅ ΔI
dt
(EQ. 37)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
L ⋅ C – C ⋅ ESR
C 1 = -------------------------------------------R FB
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
V IN
C 2 = ---------------------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 0 ⋅ f HF ⋅ ( L ⋅ C ) ⋅ R FB ⋅ V P-P
2
V PP ⋅ ⎛ 2π⎞ ⋅ f 0 ⋅ f HF ⋅ L ⋅ C ⋅ R FB
⎝ ⎠
R C = ---------------------------------------------------------------------------------------V IN ⋅ ( 2 ⋅ π ⋅ f HF ⋅ L ⋅ C – 1 )
V IN ⋅ ( 2 ⋅ π ⋅ f HF ⋅ L ⋅ C – 1 )
C C = ---------------------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 0 ⋅ f HF ⋅ ( L ⋅ C ) ⋅ R FB ⋅ V P-P
34
(EQ. 36)
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 10 and Equation 38), a voltage develops across the
FN6715.0
May 22, 2008
ISL6322G
⎛V – N ⋅ V
⎞
OUT⎠ ⋅ V OUT
⎝ IN
L ≥ ESR ⋅ -------------------------------------------------------------------f S ⋅ V IN ⋅ V ( P-P )( MAX )
(EQ. 38)
1000
RT (kΩ)
bulk capacitor ESR equal to IC(P-P) (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, V(P-P)(MAX), determines the lower limit on the
inductance.
100
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔVMAX. This places an upper limit on inductance.
Equation 39 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 40
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation:
L is the per-channel inductance,
C is the total output capacitance, and
N is the number of active channels.
2 ⋅ N ⋅ C ⋅ VO
L ≤ --------------------------------- ⋅ ΔV MAX – ( ΔI ⋅ ESR )
( ΔI ) 2
(EQ. 39)
1.25 ⋅ N ⋅ C- ⋅ ΔV
⎛
⎞
L ≤ ---------------------------MAX – ( ΔI ⋅ ESR ) ⋅ ⎝ V IN – V O⎠
( ΔI ) 2
(EQ. 40)
Switching frequency is determined by the selection of the
frequency-setting resistor, RT. Figure 23 and Equation 41
are provided to assist in selecting the correct value for RT.
35
10000k
FIGURE 23. RT vs SWITCHING FREQUENCY
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
For a two-phase design, use Figure 24 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (IO), and the ratio
of the peak-to-peak inductor current (IL,(P-P)) to IO.
(EQ. 41)
INPUT-CAPACITOR CURRENT (IRMS/IO)
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 31, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in
“Compensation” on page 34. Choose the lowest switching
frequency that allows the regulator to meet the
transient-response requirements.
R T = 10
100k
1000k
SWITCHING FREQUENCY (Hz)
0.3
Switching Frequency
[10.61 – ( 1.035 ⋅ log ( f S ) ) ]
10
10k
0.2
0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25x greater than the
maximum input voltage. Figure 25 provides the same input
RMS current information for single-phase designs. Use the
same approach for selecting the bulk capacitor type and
number.
FN6715.0
May 22, 2008
ISL6322G
across all power trains. Equidistant placement of the controller
to the first three power trains it controls through the integrated
drivers helps keep the gate drive traces equally short,
resulting in equal trace impedances and similar drive
capability of all sets of MOSFETs.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.6
0.4
0.2
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
When placing the MOSFETs, try to keep the source of the
upper FETs and the drain of the lower FETs as close as
thermally possible. Input Bulk capacitors should be placed
close to the drain of the upper FETs and the source of the lower
FETs. Locate the output inductors and output capacitors
between the MOSFETs and the load. The high-frequency input
and output decoupling capacitors (ceramic) should be placed
as close as practicable to the decoupling target, making use of
the shortest connection paths to any internal planes, such as
vias to GND next or on the capacitor solder pad.
DUTY CYCLE (VIN/VO)
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR SINGLE-PHASE CONVERTER
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET
turn on and off. Select low ESL ceramic capacitors and place
one as close as possible to each upper MOSFET drain to
minimize board parasitics and maximize suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
selection, layout, and placement minimizes these voltage
spikes. Consider, as an example, the turnoff transition of the
upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel-current. During the turnoff, current
stops flowing in the upper MOSFET and is picked up by the
lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using an ISL6322G controller. The power
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
The power components should be placed first, which include
the MOSFETs, input and output capacitors, and the inductors. It
is important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally
36
The critical small components include the bypass capacitors
for VCC and PVCC, and many of the components
surrounding the controller including the feedback network
and current sense components. Locate the VCC/PVCC
bypass capacitors as close to the ISL6322G as possible. It is
especially important to locate the components associated
with the feedback circuit close to their respective controller
pins, since they belong to a high-impedance circuit loop,
sensitive to EMI pick-up.
A multi-layer printed circuit board is recommended. Figure 27
shows the connections of the critical components for the
converter. Note that capacitors CxxIN and CxxOUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underneath the component side of the
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from the
PHASE terminal to output inductors short. The power plane
should support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase nodes. Use the remaining printed circuit layers for
small signal wiring.
Routing UGATE, LGATE, and PHASE Traces
Great attention should be paid to routing the UGATE, LGATE,
and PHASE traces since they drive the power train MOSFETs
using short, high current pulses. It is important to size them as
large and as short as possible to reduce their overall
impedance and inductance. They should be sized to carry at
least one ampere of current (0.02” to 0.05”). Going between
layers with vias should also be avoided, but if so, use two vias
for interconnection when possible.
Extra care should be given to the LGATE traces in particular
since keeping their impedance and inductance low helps to
significantly reduce the possibility of shoot-through. It is also
important to route each channels UGATE and PHASE traces
in as close proximity as possible to reduce their inductances.
FN6715.0
May 22, 2008
ISL6322G
Current Sense Component Placement and Trace
Routing
One of the most critical aspects of the ISL6322G regulator
layout is the placement of the inductor DCR current sense
components and traces. The R-C current sense components
must be placed as close to their respective ISEN+ and
ISEN- pins on the ISL6322G as possible.
The sense traces that connect the R-C sense components to
each side of the output inductors should be routed on the
bottom of the board, away from the noisy switching
components located on the top of the board. These traces
should be routed side by side, and they should be very thin
37
traces. It’s important to route these traces as far away from
any other noisy traces or planes as possible. These traces
should pick up as little noise as possible.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
GND pad of the ISL6322G to the ground plane with multiple
vias is recommended. This heat spreading allows the part to
achieve its full thermal potential. It is also recommended
that the controller be placed in a direct path of airflow if
possible to help thermally manage the part.
FN6715.0
May 22, 2008
ISL6322G
C3
RFB
C1
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
C2
R2
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
R1
VDIFF
FB
VIA CONNECTION TO GROUND PLANE
COMP
VSEN
+12V
RGND
+5V
CBIN1
CBOOT1
VCC
LOCATE NEAR SWITCHING TRANSISTORS;
(MINIMIZE CONNECTION PATH)
BOOT1
(CF1)
ROFS
UGATE1
OFS
PHASE1
FS
R1
REF
RT
C1
LGATE1
CREF
ISEN1ISEN1+
SCL
SDA
SS / RST / A0
RSS
(CHFOUT)
VID7
VID6
VID5
CBOUT
+12V
LOAD
VID4
VID3
ISL6322G
PVCC
(CF2)
VID2
CBIN2
CBOOT2
VID1
BOOT2
VID0
UGATE2
VRSEL
PGOOD
LOCATE NEAR LOAD;
(MINIMIZE CONNECTION
PATH)
PHASE2
EN_PH2
R1
+12V
C1
LGATE2
REN1
ISEN2ISEN2+
EN
REN2
NC
IOUT
RIOUT
GND
FIGURE 26. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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38
FN6715.0
May 22, 2008
ISL6322G
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
4 . 30 )
C
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
39
FN6715.0
May 22, 2008