ISL54503 Features The Intersil ISL54503 device is a low ON-resistance, low voltage, bidirectional, single pole/double throw (SPDT) analog switch designed to operate from a single +1.8V to +5.5V supply. Targeted applications include battery powered equipment that benefit from low ON-resistance (2.5Ω) and fast switching speeds (tON = 25ns, tOFF = 15ns). The digital logic input is 1.8V CMOS compatible when using a single +3V supply. • ON-resistance (rON) - VCC = +5.0V. . . . . . . . . . . . . . . . . . . . . 2.5Ω - VCC = +3.0V. . . . . . . . . . . . . . . . . . . . . 4.0Ω - VCC = +1.8V. . . . . . . . . . . . . . . . . . . . . 7.0Ω • rON matching between channels . . . . . . . . . . . 3mΩ • rON flatness (+4.5V Supply) . . . . . . . . . . . . . 0.6Ω • Single supply operation . . . . . . . . +1.8V to +5.5V Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to “mux-in” additional functionality while reducing ASIC design risk. The ISL54503 is offered in a 6 Ld 1.2mmx1.0mmx0.4mm pitch µTDFN package and a 6 Ld SOT-23 package, alleviating board space limitations. • Fast switching action (+4.5V Supply) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns The ISL54503 is a committed SPDT that consist of one normally open (NO) and one normally closed (NC) switch. This configuration can also be used as a 2-to-1 multiplexer. • Pb-free available (RoHS compliant) TABLE 1. FEATURES AT A GLANCE ISL54503 Number of Switches 1 SW SPDT or 2-1 MUX 1.8V rON 6Ω 1.8V tON/tOFF 65ns/40ns 3V rON 3Ω 3V tON/tOFF 30ns/20ns 5V rON 2.5Ω 5V tON/tOFF 25ns/15ns Package 6 Ld µTDFN, 6 Ld SOT-23 October 26, 2009 FN6551.2 1 • Guaranteed break-before-make • ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . 6kV • 1.8V CMOS logic compatible (+3V supply) • Available in 6 Ld µTDFN and 6 Ld SOT-23 packages Applications • Battery powered, handheld, and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops • Portable test and measurement • Medical equipment • Audio and video switching Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54503 +1.8V to +5.5V, 2.5Ω, Single SPDT Analog Switch ISL54503 Ordering Information PART NUMBER (Notes 1, 4) PART MARKING PACKAGE Tape & Reel (Pb-Free) TEMP. RANGE (°C) PKG. DWG. # ISL54503IRUZ-T (Note 2) 3 -40 to +85 6 Ld µTDFN L6.1.2x1.0A ISL54503IHZ-T (Note 3) -40 to +85 6 Ld SOT-23 MDP0038 4503 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54503. For more information on MSL please see techbrief TB363. Pin Configuration Pin Descriptions (Note 5) ISL54503 (6 LD µTDFN) TOP VIEW NAME NO 1 6 IN GND 2 5 V+ NC 3 4 COM ISL54503 (6 LD SOT-23) TOP VIEW NC 1 6 GND IN 2 5 COM NO 3 4 V+ PIN PIN µTDFN SOT-23 FUNCTION V+ 5 4 System Power Supply Input (+1.8V to +5.5V) GND 2 6 Ground Connection IN 6 2 Digital Control Input COM 4 5 Analog Switch Common Pin NO 1 3 Analog Switch Normally Open Pin NC 3 1 Analog Switch Normally Closed Pin NOTE: 5. Switches Shown for Logic “0” Input. Truth Table NOTE: LOGIC PIN NC PIN NO 0 ON OFF 1 OFF ON Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply. 2 FN6551.2 October 26, 2009 ISL54503 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . Input Voltages NO, NC, IN (Note 6) . . . . . . . . . . . -0.5V Output Voltages COM (Note 6) . . . . . . . . . . . . . . . -0.5V Continuous Current NO, NC, or COM. . . . . . Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . ESD Rating Human Body Model . . . . . . . . . . . . . . . . Machine Model . . . . . . . . . . . . . . . . . . . Charged Device Model . . . . . . . . . . . . . . . . . . -0.5 to 6.5V to ((V+) + 0.5V) to ((V+) + 0.5V) . . . . . . ±300mA . . . . . . ±500mA . . . . . . . . >6kV . . . . . . . >300V . . . . . . . >2.2kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 6 Ld µTDFN Package (Notes 7, 9). . 239.2 111.6 6 Ld SOT-23 Package (Note 8, 9) . . 260 120 Maximum Junction Temperature (Plastic Package). . +150°C Maximum Storage Temperature Range. . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions V+ (Positive DC Supply Voltage) . . . Analog Signal Range . . . . . . . . . . . VIN (Digital Logic Input Voltage (IN) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V . . . . . 0V to V+ . . . . . 0V to V+ -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 8. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP MIN (°C) (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON Full V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 14, See Figure 5) rON Matching Between Channels, ΔrON V+ = 4.5V, ICOM = 100mA, VNO or VNC = 2.5V (Note 14) rON Flatness, rFLAT(ON) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Notes 13, 14) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or VNC = 0.3V, 5V, or Floating 0 - V+ V 25 - 2.2 2.5 Ω Full - - 3 Ω 25 - 0.003 0.1 Ω Full - - 0.15 Ω 25 - 0.6 0.65 Ω Full - - 0.7 Ω 25 -25 1.5 25 nA Full -150 - 150 nA 25 -30 2.8 30 nA Full -300 - 300 nA DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1, Note 14) 25 - 25 - ns Full - 25 - ns V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1, Note 14) 25 - 15 - ns Full - 16 - ns Full - 15 - ns V+ = 5.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 3, Note 14) Charge Injection, Q VG = 0V, RG = 0Ω, CL = 1.0nF (see Figure 2) 25 - 24 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VP-P (see Figure 4) 25 - 70 - dB 3 FN6551.2 October 26, 2009 ISL54503 Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER TEST CONDITIONS TEMP MIN (°C) (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω 25 - 0.15 - % Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω 25 - 0.014 - % -3dB Bandwidth RL = 50Ω 25 - 250 - MHz NO or NC OFF Capacitance, COFF V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 7 - pF COM ON Capacitance, CCOM(ON) V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 18 - pF Full 1.65 - 5.5 V 25 - 0.028 0.1 µA Full - 1.1 2.5 µA POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Full - - 0.8 V Input Voltage High, VINH Full 2.4 - - V Full -0.1 0.053 0.1 µA Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP MIN (°C) (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Full 0 - V+ V ON-Resistance, rON µTDFN V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 14, See Figure 5) 25 - 3.3 3.5 Ω Full - - 4.5 Ω ON-Resistance, rON SOT-23 V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 14, See Figure 5) 25 - 3.3 3.6 Ω Full - - 4.5 Ω rON Matching Between Channels, ΔrON V+ = 2.7V, ICOM = 100mA, VNO or VNC = 1.5V (Note 14) 25 - 0.006 0.15 Ω Full - - 0.2 Ω rON Flatness, rFLAT(ON) µTDFN V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Notes 13, 14) 25 - 1 1.1 Ω Full - - 1.2 Ω rON Flatness, rFLAT(ON) SOT-23 V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Notes 13, 14) 25 - 1 1.2 Ω Full - - 1.3 Ω 25 - 30 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 1, Note 14) Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 1, Note 14) Break-Before-Make Time Delay, tD V+ = 3.0V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 3, Note 14) Full - 30 - ns 25 - 20 - ns Full - 20 - ns Full - 18 - ns Charge Injection, Q VG = 0V, RG = 0Ω, CL = 1.0nF (see Figure 2) 25 - 16 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 1MHz, VCOM = 1VP-P (see Figure 4) 25 - 70 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω 25 - 0.36 - % 4 FN6551.2 October 26, 2009 ISL54503 Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER TEST CONDITIONS TEMP MIN (°C) (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω 25 - 0.03 - % -3dB Bandwidth Signal = 0dBm, RL = 50Ω 25 - 250 - MHz NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 6 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 18 - pF 25 - 0.013 - µA Full - 0.7 - µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.4 - - V Full -0.1 0.058 0.1 µA Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP MIN MAX (°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON Full V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+, (Note 14, See Figure 5) 0 - V+ V 25 - 6 6.5 Ω Full - - 7 Ω DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 1, Note 14) 25 - 65 - ns Full - 95 - ns 25 - 40 - ns Turn-OFF Time, tOFF V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 1, Note 14) Full - 65 - ns Break-Before-Make Time Delay, tD V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 3, Note 14) Full - 44 - ns Charge Injection, Q VG = 0, RG = 0Ω, CL = 1.0nF (see Figure 2) 25 - 8.2 - pC DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Full - - 0.4 V Input Voltage High, VINH Full 1 - - V NOTES: 10. VIN = input voltage to perform proper function. 11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 14. Limits established by characterization and are not production tested. 5 FN6551.2 October 26, 2009 ISL54503 Test Circuits and Waveforms V+ LOGIC INPUT V+ tr < 20ns tf < 20ns 50% C 0V tOFF SWITCH INPUT VNO COM VOUT IN 90% 90% SWITCH OUTPUT VOUT NO OR NC SWITCH INPUT 0V LOGIC INPUT RL 50Ω GND CL 35pF tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (NO or NC) R + r L ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VOUT LOGIC INPUT RG ΔVOUT ON VINH ON OFF C VG GND VOUT COM NO OR NC IN CL VINL LOGIC INPUT Q = ΔVOUT x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ LOGIC INPUT V+ C NO VNX RL 50Ω 0V IN SWITCH OUTPUT VOUT 90% 0V VOUT COM NC CL 35pF GND LOGIC INPUT tD CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 6 FN6551.2 October 26, 2009 ISL54503 Test Circuits and Waveforms (Continued) V+ V+ C C SIGNAL GENERATOR rON = V1/I1 * NO OR NC NO OR NC VNX IN I1 0V OR V+ IN V1 VINL OR VINH 100mA COM COM ANALYZER GND GND RL * I = 10mA AT V+ = 1.8V 1 FIGURE 4. OFF-ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT V+ V+ C C 50Ω NO OR NC NO OR NC COM IN IN1 SIGNAL GENERATOR 0V OR V+ VINL OR VINH IMPEDANCE ANALYZER COM NC OR NO ANALYZER GND GND RL FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Description The ISL54503 is a bi-directional, single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.8V to 5.5V supply with low ON-resistance (2.5Ω) and high speed operation (tON = 25ns, tOFF = 15ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (0.15µW), low leakage currents (300nA max), and the small µTDFN and SOT-23 packages. The low ON-resistance and rON flatness provide very low insertion loss and distortion to application that require signal reproduction. FIGURE 7. CAPACITANCE TEST CIRCUIT parasitic SCR structures to turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation, the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100Ω series resistor resulting in no impact to switch operation or performance. External V+ Series Resistor For improved ESD and latch-up immunity Intersil recommends adding a 100Ω resistor in series with the V+ power supply pin of the ISL54050 IC (see Figure 8). During an overvoltage transient event (such as occurs during system level IEC 61000 ESD testing), substrate currents can be generated in the IC that can trigger 7 FN6551.2 October 26, 2009 ISL54503 V+ OPTIONAL PROTECTION RESISTOR C OPTIONAL SCHOTTKY DIODE V+ 100Ω OPTIONAL PROTECTION RESISTOR NO COM NC INX VNX VCOM IN GND OPTIONAL SCHOTTKY DIODE FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 9). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provide additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting Schottky diodes to the signal pins (as shown in Figure 9) will shunt the fault current to the supply or to ground, thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current. GND FIGURE 9. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL54503 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54503 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.8V but the part will operate with a supply below 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the “Electrical Specifications” tables starting on page 3 and the “Typical Performance Curves” starting on page 10 for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 3.6V (see Figure 16). At 3.6V the VIH level is about 0.95V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, the ISL54503 has a -3dB bandwidth of 250MHz (see Figure 17). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. 8 FN6551.2 October 26, 2009 ISL54503 An OFF switch behaves like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed-through from a switch’s input to output. Off-isolation is the resistance of this signal feed-through. Figure 18 details the high off-isolation provided by the ISL54503. At 1MHz, off-isolation is about 70dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off-isolation due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. 9 FN6551.2 October 26, 2009 ISL54503 Typical Performance Curves TA = 25°C, Unless Otherwise Specified 4.0 3.0 ICOM = 100mA 3.5 2.5 V+ = 2.7V 3.0 +85°C +25°C 2.0 rON (Ω) rON (Ω) 2.0 V+ = 3V 2.5 V+ = 4.5V 1.5 1.5 -40°C 1.0 V+ = 5V 1.0 0.0 V+ = 4.5V ICOM = 100mA 0.5 0.5 0 1 2 3 4 0.0 0 5 0.5 1.0 1.5 2.0 2.5 VCOM (V) VCOM (V) FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 3.5 4.5 8 V+ = 2.7V ICOM = 100mA 4.5 V+ = 1.8V ICOM = 10mA 7 4.0 6 +85°C 3.5 rON (Ω) +85°C 3.0 +25°C 5 +25°C 4 2.5 -40°C -40°C 3 2.0 2 1.5 1.0 4.0 FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE 5.0 rON (Ω) 3.0 0 0.5 1.0 1.5 2.0 1 2.5 0 0.2 0.4 0.6 VCOM (V) 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VCOM (V) FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE 100 70 -40°C 90 -40°C 60 80 50 70 +25°C +25°C tOFF (ns) tON (ns) 60 50 40 +85°C 40 30 +85°C 30 20 20 10 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V+ (V) FIGURE 14. TURN-ON TIME vs SUPPLY VOLTAGE 10 6.0 0 1.5 2.0 2.5 3.0 3.5 4.0 V+ (V) 4.5 5.0 5.5 6.0 FIGURE 15. TURN-OFF TIME vs SUPPLY VOLTAGE FN6551.2 October 26, 2009 ISL54503 Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 1.4 0 -1 NORMALIZED GAIN (dB) VINH AND VINL (V) V+ = 1.8V TO 5.5V VCOM = 1VP-P -2 1.2 1.0 VINH 0.8 VINL 0.6 -3 -4 -5 -6 -7 -8 -9 -10 0.4 -11 -12 0.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -13 100k 5.5 1M 10M FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE 25 V+ = 1.8V TO 5.5V 20 -40 15 -50 10 Q (pC) (dB) -60 -70 -80 5 0 V+ = 5V -5 -90 V+ = 1.8V -10 -100 V+ = 3.3V -15 -110 -120 1k 1G FIGURE 17. FREQUENCY RESPONSE -20 -30 100M FREQUENCY (Hz) V+ (V) 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 18. OFF-ISOLATION 1G -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VCOM (V) 3.5 4.0 4.5 5.0 FIGURE 19. CHARGE INJECTION vs SWITCH VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: PROCESS: Submicron CMOS 11 FN6551.2 October 26, 2009 ISL54503 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) A E L6.1.2x1.0A B 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS PIN 1 REFERENCE 2X 0.10C 2X 0.10C TOP VIEW MIN NOMINAL MAX NOTES A 0.45 0.50 0.55 - A1 - - 0.05 - A3 DETAIL A 0.10C 7X SYMBOL D A 0.08C A1 A3 SIDE VIEW C SEATING PLANE 4X e DETAIL B 1 5X L 3 L1 - 0.127 REF b 0.15 0.20 0.25 5 D 0.95 1.00 1.05 - E 1.15 1.20 1.25 - e - 0.40 BSC L 0.30 0.35 0.40 - L1 0.40 0.45 0.50 - N 6 2 Ne 3 3 θ 0 - 4 12 Rev. 2 8/06 NOTES: 6 4 BOTTOM VIEW b 6X 0.10 C A B 0.05C NOTE 3 1. Dimensioning and tolerancing conform to ASME Y14.51994. 2. N is the number of terminals. 3. Ne refers to the number of terminals on E side. 4. All dimensions are in millimeters. Angles are in degrees. 0.1x45° CHAMFER 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. A3 A1 7. Maximum package warpage is 0.05mm. DETAIL A DETAIL B PIN 1 LEAD 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 1.00 1.40 0.20 0.30 0.45 0.20 0.35 0.40 LAND PATTERN 10 12 FN6551.2 October 26, 2009 ISL54503 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 0.25 0° +3° -0° For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6551.2 October 26, 2009