INTERSIL ISL84525IU

ISL84524, ISL84525
®
Data Sheet
June 2003
Low-Voltage, Single Supply, 4 to 1
Multiplexer and DPDT Analog Switches
The Intersil ISL84524 and ISL84525 devices are precision,
bidirectional, analog switches configured as a 4 channel
multiplexer / demultiplexer (ISL84524) and a double pole /
double throw (DPDT) switch (ISL84525) designed to operate
from a single +2V to +12V supply. Both have an inhibit pin to
simultaneously open all signal paths.
ON resistance is 200Ω with a +5V supply and 500Ω with a
+3V supply. Each switch can handle rail to rail analog
signals. The off-leakage current is only 1nA at +25oC or
25nA at +85oC.
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single +5V
supply.
The ISL84524 is a 4 to 1 multiplexer device. The ISL84525 is
a DPDT, which is perfect for use in 2-to-1 multiplexer
applications.
Table 1 summarizes the performance of this family. For
higher performance, see the ISL43640 and ISL43410 data
sheets.
TABLE 1. FEATURES AT A GLANCE
RON & tON / tOFF
3V RON
3V tON / tOFF
ISL84524
4:1 MUX
ISL84525
DPDT
190Ω
190Ω
170ns / 50ns
170ns / 50ns
92Ω
92Ω
90ns / 40ns
90ns / 40ns
5V RON
5V tON / tOFF
PACKAGE
10 Ld MSOP
FN6042.1
Features
• Drop-in Replacements for MAX4524 and MAX4525
• ON Resistance (RON) Max, VS = 5V . . . . . . . . . . . . 200Ω
• ON Resistance (RON) Max, VS = 3V . . . . . . . . . . . . 500Ω
• RON Matching Between Channels. . . . . . . . . . . . . . . . . . <8Ω
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)
• Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<3µW
• Fast Switching Action (VS = 5V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
• Guaranteed Max Off-leakage @ 5V . . . . . . . . . . . . . . 25nA
• Guaranteed Break-Before-Make
• TTL, CMOS Compatible
• Available in 10 Ld MSOP Package
Applications
• Battery Powered, Handheld, and Portable Equipment
• Communications Systems
- Radios
- Telecom Infrastructure
- ADSL, VDSL Modems
• Test Equipment
- Medical Ultrasound
- Magnetic Resonance Image
- CT and PET Scanners
- ATE
- Electrocardiograph
• Audio and Video Signal Routing
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84524, ISL84525
Pinouts
(Note 1)
ISL84524 (MSOP)
TOP VIEW
ISL84525 (MSOP)
TOP VIEW
10 V+
NO2 1
10 V+
NO1 1
NO3 2
9 COM
COM1 2
NO1 3
8 NO0
NC1 3
8 NO2
7 ADD1
INH 4
7 NC2
6 ADD2
GND 5
INH 4
LOGIC
GND 5
9 COM2
LOGIC
4:1 MUX
6 ADD
DPDT
NOTE:
1. Switches Shown for Logic “0” Inputs.
Truth Tables
Ordering Information
ISL84524
INH
ADD2
ADD1
SWITCH ON
1
X
X
NONE
0
0
0
NO0
0
0
1
NO1
0
1
0
NO2
0
1
1
NO3
ISL84525
INH
ADD
SWITCH ON
1
X
NONE
0
0
NCX
0
1
NOX
NOTE:
11V.
Logic “0” ≤0.8V. Logic “1” ≥2.4V, with VS between 3V and
Pin Descriptions
PIN
V+
FUNCTION
System Power Supply Input (+2V to +12V)
GND
Ground Connection
INH
Digital Control Input. Connect to GND for Normal
Operation. Connect to V+ to turn all switches off.
COM
Analog Switch Common Pin
NOX
Analog Switch Normally Open Pin
NCX
Analog Switch Normally Closed Pin
ADDX
Address Input Pin
2
PART NO.
(BRAND)
TEMP.
RANGE (oC)
PACKAGE
PKG. DWG. #
ISL84524IU
(524I)
-40 to 85
10 Ld MSOP
M10.118
ISL84525IU
(525I)
-40 to 85
10 Ld MSOP
M10.118
NOTE: Most surface mount devices are available on tape and reel;
add “-T” to suffix.
ISL84524, ISL84525
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
Input Voltages
INH, NO, NC, ADD (Note 2) . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 40mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . .
190
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Moisture Sensitivity (See Technical Brief TB363)
10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Storage Temperature Range. . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(Lead Tips Only)
Operating Conditions
Temperature Range
ISL8452XIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current
ratings.
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications +5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(oC)
(NOTE 5)
MIN
TYP
Full
0
-
V+
V
25
-
-
150
Ω
Full
-
-
200
Ω
25
-
2
8
Ω
Full
-
-
15
Ω
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V
(See Figure 5)
RON Matching Between Channels,
∆RON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V (Note 7)
RON Flatness, RFLAT(ON)
V+ = 5.5V, ICOM = 1.0mA, VNO or VNC = 1.5V, 2.5V,
3.5V (Note 8)
Full
-
-
15.5
Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V
(Note 6)
25
-1
-
1
nA
Full
-10
-
10
nA
COM OFF Leakage Current,
ICOM(OFF)
V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V
(Note 6)
25
-1
-
1
nA
Full
-25
-
25
nA
COM ON Leakage Current,
ICOM(ON)
V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V,
4.5V, or Floating (Note 6)
25
-1
-
1
nA
Full
-25
-
25
nA
Input Voltage High, VINH
Full
2.4
1.5
-
V
Input Voltage Low, VINL
Full
-
1.5
0.8
V
V+ = 5.5V, VIN = 0V or V+
Full
-1
-
1
µA
VNO or VNC = 3V, RL =300Ω, CL = 35pF, VIN = 0 to 3
(See Figure 1)
25
-
90
150
ns
Full
-
-
200
ns
25
-
40
120
ns
Full
-
-
180
ns
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, tON
Inhibit Turn-OFF Time, tOFF
VNO or VNC = 3V, RL =300Ω, CL = 35pF, VIN = 0 to 3
(See Figure 1)
3
ISL84524, ISL84525
Electrical Specifications +5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
Address Transition Time, tTRANS
VNO or VNC = 3V, RL =300Ω, CL = 35pF,
VIN = 0 to 3 (See Figure 1)
TEMP
(oC)
(NOTE 5)
MIN
TYP
25
-
90
150
ns
Full
-
-
200
ns
(NOTE 5)
MAX
UNITS
Break-Before-Make Time Delay, tD
RL = 300Ω, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3
(See Figure 3)
25
5
20
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2)
25
-
0.8
5
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 1MHz (See Figure 4)
25
-
75
-
dB
Crosstalk (Channel-to-Channel),
(ISL84525)
RL = 50Ω, CL = 5pF, f = 1MHz (See Figure 6)
25
-
-85
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
4
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84524
25
-
14
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84525
25
-
6
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84524
25
-
20
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84525
25
-
12
-
pF
Full
2
-
12
V
25
-1
-
1
µA
Full
-10
-
10
µA
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, VIN = 0V or V+, all channels on or off
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC.
7. ∆RON = RON (MAX) - RON (MIN).
8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
Electrical Specifications +3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 4),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(oC)
(NOTE 5)
MIN
TYP
Full
0
-
V+
V
25
-
-
400
Ω
Full
-
-
500
Ω
25
-1
-
1
nA
Full
-10
-
10
nA
25
-1
-
1
nA
Full
-25
-
25
nA
25
-1
-
1
nA
Full
-25
-
25
nA
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 1.0mA, VNO or VNC = 1.5V
(See Figure 5)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V
(Note 6)
COM OFF Leakage Current,
ICOM(OFF)
V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V
(Note 6)
COM ON Leakage Current,
ICOM(ON)
V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V,
or floating (Note 6)
4
ISL84524, ISL84525
Electrical Specifications +3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 4),
Unless Otherwise Specified (Continued)
TEMP
(oC)
(NOTE 5)
MIN
TYP
Input Voltage High, VINH
Full
2.0
1.0
-
V
Input Voltage Low, VINL
Full
-
1.0
0.5
V
V+ = 3.6V, VIN = 0V or V+
Full
-1
-
1
µA
VNO or VNC = 1.5V, RL =300Ω, CL = 35pF,
VIN = 0 to 3 (See Figure 1)
25
-
170
300
ns
Full
-
-
400
ns
25
-
50
200
ns
Full
-
-
300
ns
25
-
130
300
ns
Full
-
-
400
ns
PARAMETER
TEST CONDITIONS
(NOTE 5)
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, tON
VNO or VNC = 1.5V, RL =300Ω, CL = 35pF,
VIN = 0 to 3 (See Figure 1)
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
VNO or VNC = 1.5V, RL =300Ω, CL = 35pF,
VIN = 0 to 3 (See Figure 1)
Break-Before-Make Time Delay, tD
RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V,
VIN = 0 to 3 (See Figure 3)
Full
5
40
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (See Figure 2)
25
-
0.8
1
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 1MHz (See Figure 4)
25
-
75
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 1MHz (See Figure 6)
25
-
-85
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
4
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84524
25
-
14
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84525
25
-
6
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84524
25
-
20
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
ISL84525
25
-
12
-
pF
25
-1
-
1
µA
Full
-10
-
10
µA
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
V+ = 3.6V, VIN = 0V or V+, all channels on or off
Positive Supply Current, I+
5
ISL84524, ISL84525
Test Circuits and Waveforms
V+
C
V+
NO0
ISL84524
NO1-NO3
INH
3V
LOGIC
INPUT
tr < 20ns
tf < 20ns
50%
LOGIC
INPUT
COM
ADD1,
GND ADD2
V+
C
90%
VOUT
RL
300Ω
CL
35pF
C
90%
V+
0V
NC
ISL84525
NO
tOFF
INH
COM
GND ADD
LOGIC
INPUT
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
V+
50%
CL
35pF
NO0
C
ISL84524
NO1-NO3
tr < 20ns
tf < 20ns
RL
300Ω
FIGURE 1B. INHIBIT TEST CIRCUIT
C
3V
VOUT
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
-----------------------------V OUT = V
(NO or NC) R + R
L
( ON )
FIGURE 1A. INHIBIT MEASUREMENT POINTS
LOGIC
INPUT
VOUT
0V
tON
SWITCH
OUTPUT
C
ADD1
ADD2
COM
GND
INH
LOGIC
INPUT
VOUT
RL
300Ω
CL
35pF
0V
tTRANS
V+
C
90%
SWITCH
OUTPUT
VOUT
C
90%
V+
0V
NC
ISL84525
NO
COM
VOUT
tTRANS
ADD
GND
LOGIC
INPUT
Logic input waveform is inverted for switches that have the opposite
logic sense.
RL
300Ω
CL
35pF
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------------R L + R ( ON )
FIGURE 1D. ADDRESS TEST CIRCUIT
FIGURE 1C. ADDRESS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
6
INH
ISL84524, ISL84525
Test Circuits and Waveforms (Continued)
V+
C
3V
OFF
OFF
LOGIC
INPUT
VOUT
RG
ON
COM
NO or NC
0V
ADDX
SWITCH
OUTPUT
VOUT
∆VOUT
VG
INH
GND
CL
LOGIC
INPUT
Q = ∆VOUT x CL
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
C
VOUT
NO0-NO3
V+
ADD1
COM
ISL84524
RL
300Ω
CL
35pF
ADD2
tr < 20ns
tf < 20ns
3V
LOGIC
INPUT
GND
LOGIC
INPUT
INH
0V
V+
C
80%
SWITCH
OUTPUT
VOUT
0V
V+
tD
C
VOUT
NO
NC
COM
ISL84525
RL
300Ω
ADD
LOGIC
INPUT
GND
INH
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME
7
FIGURE 3B. TEST CIRCUIT
CL
35pF
ISL84524, ISL84525
Test Circuits and Waveforms (Continued)
V+
V+
C
C
SIGNAL
GENERATOR
RON = V1/1mA
NO or NC
NO or NC
VNX
0V or V+
1mA
ADDX
0V or V+
V1
ADDX
0V or V+
ANALYZER
COM
INH
GND
COM
RL
GND
INH
FIGURE 5. RON TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
V+
V+
C
SIGNAL
GENERATOR
C
50Ω
NO1 or NC1
NO or NC
COM1
ISL84525
0V or V+
ADD
0V or V+
NO2 or NC2
ANALYZER
ADDX
IMPEDANCE
ANALYZER
COM2
GND
NC
COM
GND
INH
INH
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
8
FIGURE 7. CAPACITANCE TEST CIRCUIT
ISL84524, ISL84525
Detailed Description
Power-Supply Considerations
The ISL84524 and ISL84525 operate from a single 2V to
12V supply with low on-resistance and high speed operation.
The devices are especially well suited to portable battery
powered equipment thanks to the low operating supply
voltage (2.7V), low power consumption (3µW), low leakage
currents (25nA max), and the tiny MSOP packaging. High
frequency applications also benefit from the wide bandwidth,
and the very high off isolation (75 dB) and crosstalk rejection
(-85dB).
The ISL8452X construction is typical of most CMOS analog
switches, except that they have only two supply pins: V+ and
GND. V+ and GND drive the internal CMOS switches and
set their analog voltage limits. Unlike switches with a 13V
maximum supply voltage, the ISL8452X 15V maximum
supply voltage provides plenty of room for the 10% tolerance
of 12V supplies, as well as room for overshoot and noise
spikes.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1kΩ
OPTIONAL PROTECTION
DIODE
V+
ADDX
1kΩ
INH
VNO or NC
VCOM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
9
The minimum recommended supply voltage is 2V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a
supply range of 2V to 11V. At 12V the VIH level is about
2.5V. This is still below the TTL guaranteed high output
minimum level of 2.8V, but noise margin is reduced. For best
results with a 12V supply, use a logic family that provides a
VOH greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figure 13). Figure 13 also illustrates that the
frequency response is very consistent over varying analog
signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another. Figure
14 details the high Off Isolation and Crosstalk rejection
provided by this family. At 10MHz, Off Isolation is about
55dB in 50Ω systems, decreasing approximately 20dB per
decade as frequency increases. Higher load impedances
decrease Off Isolation and Crosstalk rejection due to the
voltage divider action of the switch OFF impedance and the
load impedance.
ISL84524, ISL84525
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Typical Performance Curves TA = 25oC, Unless Otherwise Specified
250
225
VCOM = (V+) - 1V
V+ = 3.3V
200
ICOM = 1mA
85oC
175
200
25oC
150
125
85oC
RON (Ω)
RON (Ω)
25oC
100
-40oC
0
5
6
7
8
V+ (V)
9
10
11
12
75
140
120
85oC
100
25oC
80
-40oC
60
80
70 85oC
60
50
40 -40oC
30
0
50
4
-40oC
100
150
3
ICOM = 1mA
13
V+ = 5V
25oC
V+ = 12V
4
2
6
VCOM (V)
8
10
12
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
120
350
VCOM = (V+) - 1V
VCOM = (V+) - 1V
110
300
100
90
250
tOFF (ns)
tON (ns)
80
200
85oC
150
70
60
85oC
50
25oC
100
-40oC
50
25oC
40
30
-40oC
20
0
10
2
3
4
5
6
7
V+ (V)
8
9
10
FIGURE 11. TURN - ON TIME vs SUPPLY VOLTAGE
10
11
12
2
3
4
5
6
7
V+ (V)
8
9
10
FIGURE 12. TURN - OFF TIME vs SUPPLY VOLTAGE
11
12
ISL84524, ISL84525
0
VIN = 5VP-P
GAIN
0
PHASE
45
VIN = 5VP-P
90
135
CROSSTALK (dB)
-3
-30
30
-40
40
-50
50
-60
70
-70
80
-90
90
-100
100
-110
1k
600
10k
100k
FREQUENCY (MHz)
0.75
V+ = 5V
Q (pC)
0.5
0.25
V+ = 3.3V
0
-0.25
-0.5
0
1
2
3
4
VCOM (V)
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
ISL84524: 193
ISL84525: 193
PROCESS:
Si Gate CMOS
11
10M
110
100M 500M
FIGURE 14. CROSSTALK AND OFF ISOLATION
1
TRANSISTOR COUNT:
1M
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE
GND
60
ISOLATION
CROSSTALK
180
100
20
-80
RL = 50Ω
10
-20
OFF ISOLATION (dB)
V+ = 3V to 12V
VIN = 0.2VP-P
+3
1
10
-10
V+ = 5V
PHASE (DEGREES)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
5
ISL84524, ISL84525
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X θ
A2
A1
b
-H-
0.10 (0.004)
L
SEATING
PLANE
C
MIN
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
-A-
0.50 BSC
E
L1
e
D
SYMBOL
e
L1
MILLIMETERS
0.95 REF
10
R
0.003
R1
-
10
-
0.07
0.003
-
θ
5o
15o
α
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 0 12/02
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
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12