CFT Series Synthesizer Draft Rev‐B CFT Series Synthesizer Users Guide 1 | P a g e CFT Series Synthesizer Draft Rev‐B CONTENTS: Warranty CFT Series Synthesizer Overview Features Specification Mounting Connectors Power Requirements P2 Signal Table Hardware Functionality Introduction RF Firmware Status and Control Interface Standard Parallel Electrical Interface P1 Signal Table Standard Parallel Logical Interface Read/Write Timing Detailed Register Decode Ethernet Interface (To Be Implemented) Control Structure Hardware Ethernet‐IP‐UDP Stack Operation Frequency Tuning Manual Tuning Step Sweep List Sweep (To Be Implemented) Pulse Modulation External Internal Exponential Modulation (To Be Implemented) Acceptance Test Plan Frequency Accuracy Tuning Speed Amplitude Accuracy Amplitude Settling and Pulse Modulation Spectral Purity RF Isolation Power Consumption Reference Mechanical Testing Matrix Test Data Sheets 2 | P a g e CFT Series Synthesizer Draft Rev‐B WARRANTY AND SERVICE Service The CFT synthesizer contains no user‐serviceable parts. If you believe the synthesizer is malfunctioning, damaged, or not operating properly, discontinue use and contact API Defense. Warranty and Repair API Defense does warrant and guarantee to the purchaser the quality of workmanship and materials used to provide satisfactory performance for a period of not less than one year from the date of delivery. During this one year (12 month) warranty period, API Defense will repair items excluding instances of accidental damage, abuse or subjection to potential greater than specified. Return shipping costs will be covered under a warranty repair. The warranty shall cover a period of 12 months from the time of receipt of the product. Extended warranties beyond this one year period can be purchased by contacting API Defense at 814‐467‐7693. COMPACT FAST TUNING (CFT) SYNTHESIZER FEATURES: CFT series synthesizers offer high performance signal generation in a small footprint. A rugged compact package and low power consumption are ideal for mobile applications as well as lab needs where fast tuning and spectral purity are required. This class of synthesizer can also be customized simplifying system integration by removing any additional glue logic. • 1.60 – 18.0GHz Coverage • 100MHz internal reference (+/‐ 50 parts per billion (ppb)) • Switchable reference output • 10/100/1000Base‐T Ethernet interface (RJ‐45) • Programmable Pulse Width (PW) and Pulse Repetition Interval (PRI) • Exponential Modulation (Frequency and Phase) • 2us Switching Speed • Flexible control interface • Automatic Level Control • Phase Lock Status output bit • Continuous Wave, Sweep and List mode frequency control • Available internal user programmable logic, PowerPC, and memory 3 | P a g e CFT Series Synthesizer Draft Rev‐B CFT SERIES SYNTHESIZER SPECIFICATIONS: Specification Parameter Frequency Switching Speed Spurious Harmonics Sub‐harmonics Internal Reference Frequency Stability Power (J2) Phase Noise (10 GHz) 1kHz 10kHz 100kHz 1MHz Temperature Output Power Response On to Off Isolation Rise Time (Off to On) Fall Time (On to Off) Min Pulse Width Power +12Vdc +5Vdc ‐12Vdc Weight Size Value 1.60 – 18.0 2 ‐60 ‐30 ‐60 Units GHz μs dBc dBc dBc 100 +/‐ 100 0 MHz ppb dBm ‐70 ‐105 ‐110 ‐118 ‐30 to +75 +8 +/‐1 >70 <10 <10 10 <27 1000 2000 400 <1.5 5.5x5.5x2 dBc/Hz dBc/Hz dBc/Hz dBc/Hz C (Case Temp) dBm dB dB ns ns ns W mA mA mA kg inches Table 1 CFT SERIES SYNTHESIZER MOUNTING/INSTALLATION: The synthesizer housing is machined from solid aluminum stock with front panel, top and bottom dust covers securely attached. All housing components are nickel plated, and with exception to the bottom dust cover, all exterior surfaces are black powder coated. It is intended that the bottom cover be the mounting surface. Four #6‐32 spring loaded captive screws are provided for attachment. 4 | P a g e CFT Series Synthesizer Draft Rev‐B Captive Screws Figure 1 Captive Screw Detail Figure 2 5 | P a g e CFT Series Synthesizer Draft Rev‐B While not required, it is suggested that the bottom cover make a good thermal interface to some form of “chill plate”. Mounting to a heat sink such as a system chassis will minimize temperature gradient between ambient air and synthesizer housing, in turn, maximizing ambient operating temperature range. At 25C in “dead air”, the temperature gradient from ambient to synthesizer housing is approximately 18C. Specified operational temperature is based on unit case temperature. Standard connectors are used for power, RF, and digital control interfaces as listed in table 2. Connectors Designator J1 Ethernet J2 Reference J3 RF Out P1 Status/Control P2 Power Function 10/100/1000 Base‐T Interface Reference Output/Input RF Output Digital Status and Control Power Connector Type RJ‐45 SMA Female (Note 1) Field Replaceable SMA Female DSub High Density44(DB44HDM) DSub 9 Pin Plug (DE9M) Table 2 Front Panel Connectors Power Rear Panel Connector Figure3 Figure4 POWER REQUIREMENTS The CFT Synthesizer requires three dc supply potentials. Supply Requirements Volts Min (V) Max (V) Max Current (mA) +5 4.75 5.25 2100 +12 10 16 1100 ‐12 ‐16 ‐10 475 Table 3 6 | P a g e CFT Series Synthesizer Draft Rev‐B J2 Pinout Table Signal Name +5Vdc +5Vdc Rtn Chassis Gnd +12Vdc +12Vdc Rtn Chassis Gnd Chassis Gnd ‐12Vdc Rtn ‐12Vdc J1‐Pin 1 2 3 4 5 6 7 8 9 Table 4 CFT SERIES SYNTHESIZER FUNCTIONAL DESCRIPTION: The CFT series synthesizer performs frequency synthesis over the 1.60 to 18.0GHz range. However, the fundamental frequency bandwidth is 1.60 to 3.20GHz. The remaining (3.20 – 18.0GHz) is comprised of sub‐octave bands generated by a series of frequency doublers and filters. Synthesizer tuning speed is not a function of absolute or differential frequency. RF Bands Band Range (GHz) Multiplier 0 1.60 ‐ 2.25 1 1 2.25 ‐ 3.20 1 2 3.20 – 4.50 2 3 4.50 – 6.40 2 4 6.40 – 9.00 4 5 9.00 – 12.8 4 6 12.8 – 18.0 8 Table 5 The standard output power level is +8dBm and is maintained by a digitally controlled Automatic Level Control (ALC) circuit. The ALC loop settles in less than 2us; power leveling is maintained during pulse modulation. A Xilinx Virtex‐4 Field Programmable Gate Array (FPGA) manages synthesizer operation, communications, and provides user programmable resources. FPGA configuration files are loaded via P1 Status/Control JTAG interface using standard Xilinx configuration tools. The JTAG chain consists of the Platform Memory and FPGA as shown below. 7 | P a g e CFT Series Synthesizer Draft Rev‐B Simplified Block Diagram Figure 5 Frequency Synthesis A Voltage Controlled Oscillator (VCO) covering the fundamental frequency range is ultimately phase locked to a 100MHz Oven Controlled Crystal Oscillator (OCXO) through the use of a unique hybrid Phase Lock Loop (PLL). The standard unit employs an internal high performance OCXO with +/‐50ppb long term stability over the operating temperature range. The 100MHz internal reference is available on J2 (SMA female). The 100MHz reference output can be switched off. 8 | P a g e CFT Series Synthesizer Draft Rev‐B Internal Reference Output: Reference Output Specification Parameter Value Tolerance Frequency 100MHz +/‐ 50 ppb Power 0dBm +/‐ 1dB Waveform Sine‐Wave Harmonics ‐50dBc Max Spurious ‐100dBc Max Phase Noise (Offset) Max ‐120dBc/Hz 100Hz Max ‐150dBc/Hz 1kHz Max ‐155dBc/Hz 10kHz Warm Up Time 60 Seconds Max To <.1ppm On/Off Isolation 60dB Min Table 6 CFT synthesizers can be factory configured to accept an external source of many standard reference frequencies. Note that the RF phase noise to an offset of approximately 5 kHz is a function of the input reference phase noise. The PLL can achieve a frequency resolution of (.1164Hz). However, the effective resolution is 8 times greater due to frequency multiplication. This also represents the intrinsic frequency error of the PLL. The maximum intrinsic frequency error is approximately .9313Hz. Frequency tuning is guaranteed to be monotonic in all tuning modes. STATUS AND CONTROL ARCHITECTURE Control and status monitoring can be performed over the Ethernet Port, Parallel Port or both. While CFT synthesizers ship with a standard interface, depending on available skill sets, the interface and synthesizer control architecture can be modified to suit a particular system design or implement custom algorithms. Hardware resources have also been set aside for customer use. A VHDL development model is available with simplified interfaces implemented as records. Standard Parallel Electrical Interface The parallel interface is on the P1 Status/Control connector. Electrically the interface consists of a 27‐bit bi‐directional bus, 2 dedicated output bits and 2 dedicated input bits. The bi‐directional bus is constituted by three, 8‐bit banks and a single, 3‐bit bank. The direction of each bank is controlled by a direction bit sourced from the FPGA as shown in figure 6. 9 | P a g e CFT Series Synthesizer Draft Rev‐B Bi‐directional Configuration Figure 6 The three dedicated input bits are terminated with a resistor network with a Thevenin impedance of 121 Ohms as shown in figure7. Input only with resistive termination +3.3V P1 Status/Control 221 Input Buffered Input FPGA 270 GND Figure 7 3-bits input Two output only bits are also available. Output only signaling Figure 8 The parallel port can interface to +3.3V as well as +5V systems and will accept inputs of up to +7V without damage. DC Control Levels Parameter Min Max Absolute DC Input Voltage ‐0.5V +7.0V High‐ Input Level +2.2V Low‐ Input Level +0.8V High‐ Output Level +2.6V Low‐ Output Level +0.1V Table 7 10 | P a g e CFT Series Synthesizer Draft Rev‐B J1 Status/Control Electrical J1‐Pin 1 2 3 4 6 7 8 9 11 12 13 14 16 17 18 19 21 22 23 24 26 27 28 29 31 32 33 34 36 37 38 39 40 41 42 43 44 5 10 15 20 25 30 35 Mode Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Output Input Input Input Input Input Output Input Output Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Termination 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up 1k Pull‐Up none none 270 Ohm Thevenin 270 Ohm Thevenin 270 Ohm Thevenin 4.7k Pull‐Up 4.7k Pull‐Up 4.7k Pull‐Up 4.7k Pull‐Up N/A N/A N/A N/A N/A N/A N/A N/A Table 8 Standard Parallel Logical Interface The standard logical interface consists of the following signals: • 16‐Data Bits (Data(16:0)) • 8‐Address Bits (Address(6:0)) • Data OE# • Data Strobe • RF OE# • REF OE# • Phase Lock # • Multiplexed Output 11 | P a g e CFT Series Synthesizer Draft Rev‐B Parallel Logical Signal Listing Signal Mode Data(15:0) Bi‐Directional Address(6:0) Input Data OE# Input Data Strobe Input RF OE# Input REF OE# Input Phase Lock# Output Multiplexed Output Output Table 9 J1 Status/Control Logical Signal Name Data 0 Data 1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15 Address0 Address1 Address2 Address3 Address4 Address5 Address6 Address7 Data OE# SPARE SPARE Mux Output Phase Lock# Ref OE# RF OE# Data Strobe JTAG TMS JTAG TDI JTAG TDO JTAG TCK JTAG +3.3V Digital Rtn Digital Rtn Digital Rtn Digital Rtn Digital Rtn Digital Rtn Digital Rtn J1‐Pin 1 2 3 4 6 7 8 9 11 12 13 14 16 17 18 19 21 22 23 24 26 27 28 29 31 32 33 34 36 37 38 39 40 41 42 43 44 5 10 15 20 25 30 35 Description Read/Write Data Lines Address Lines Output Enable (Active low) Dynamic Latch (Falling Edge) Microwave Output Enable (Active low) 100MHz Reference Output Enable (Active low) Synthesizer Phase Lock Status (Lock = low) Configurable Output Pin Description Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 0) Data Bit, 1k Pull‐UP (Bank 1) Data Bit, 1k Pull‐UP (Bank 1) Data Bit, 1k Pull‐UP (Bank 1) Data Bit, 1k Pull‐UP (Bank 1) Data Bit, 1k Pull‐UP (Bank 1) Data Bit, 1k Pull‐UP (Bank 1) Data Bit, 1k Pull‐UP (Bank 1) Data Bit, 1k Pull‐UP (Bank 1) Address Bit, 1k Pull (Bank 2) Address Bit, 1k Pull (Bank 2) Address Bit, 1k Pull (Bank 2) Address Bit, 1k Pull (Bank 2) Address Bit, 1k Pull (Bank 2) Address Bit, 1k Pull (Bank 2) Address Bit, 1k Pull (Bank 2) Address Bit, 1k Pull (Bank 2) Transceiver Direction Spare Bit, 1k Pull (Bank 3) Spare Bit, 1k Pull (Bank 3) Multiplexed Output 1k Pull‐up Phase Lock Indicator Lock = '0' , 1k Pull‐up 100MHz Reference Control ON = '0', 270 Thevenin RF Output Control ON = '0', 270 Thevenin Dynamic Latch On Falling Edge, 270 Thevenin JTAG Test Mode Select, 4.7k Pull‐up JTAG Test Data Input, 4.7k Pull‐up JTAG Test Data Output, 4.7k Pull‐up JTAG Test Clock, 4.7k Pull‐up JTAG Supply Voltage, +3.3V Supply Rail Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Digital Signal Return Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Input Input Input Input Input Output Output Input Input Input Input Input Input Input Output GND GND GND GND GND GND GND Table 10 Synthesizer parameters such as frequency, pulse width and pulse repetition interval are set by internal register values. To change a register value, the data and address bus is driven with the appropriate signals, Data OE# is driven high and data strobe is pulsed low. Data is latched into a register on the falling edge of the data strobe. Register values can be read by driving the address lines and Data OE# low. 12 | P a g e CFT Series Synthesizer Draft Rev‐B Simplified Control Architecture Note: For simplification not all registers are illustrated. Figure 9 13 | P a g e CFT Series Synthesizer Draft Rev‐B Registers 16‐Bit Register Address (hex) Mode Description Firmware Version 00 Read Only FPGA Image Version IP Address(1) 01 Read/Write IP address upper 16‐bits IP Address(0) 02 Read/Write IP address lower 16‐bits UDP Local Source Port 03 Read/Write Local UDP port number UDP Destination Port 04 Read/Write Destination UDP port number MAC Physical Address(2) 05 Read Only MAC address bits 47 down to 32 MAC Physical Address(1) 06 Read Only MAC address bits 31 down to 16 MAC Physical Address(0) 07 Read Only MAC address bits 15 down to 0 Pulse Width(1) 08 Read/Write Pulse Width upper 16‐bits Pulse Width(0) 09 Read/Write Pulse Width lower 16‐bits Pulse Repetition Interval(1) 0A Read/Write PRI upper 16‐bits Pulse Repetition Interval(0) 0B Read/Write PRI lower 16‐bits Temperature 0C Read Only Temperature 12‐bits Control 0D Read/Write Synthesizer Control bits Start Frequency 0E Read/Write Sweep Start Frequency Stop Frequency 0F Read/Write Sweep Stop Frequency Step Size 10 Read/Write Sweep Frequency Step Size Dwell Time(1) 11 Read/Write Sweep Dwell Time upper 16‐bits Dwell Time(0) 12 Read/Write Sweep Dwell Time lower 16‐bits Current Frequency FF Read/Write Current Frequency Value Table 11 Note that since all data, address and bus direction lines are terminated with pull‐up resistors, the bus default address and mode is Current Frequency, Write. Read/Write Timing Register Write Timing Diagram thz twsu twhd twsw Figure 10 14 | P a g e CFT Series Synthesizer Draft Rev‐B Write Timing Requirements Parameter Write Setup Symbol t wsu Specification 21.5ns Min Write Hold t whd 21.5ns Min OE# high to 3‐State Output t hz 20ns Max Minimum Strobe Width t wsw 20ns Min Table 12 Register Read Timing Diagram t oe t rad trar Figure 11 Read Timing Requirements Parameter Symbol OE# low to Active Output t oe Specification 35ns Max Read Address to Data t rad 35ns Max Read Address Rate t rar 35ns Min Table 13 Detailed Register Decode Firmware Register Address: x”00” Mode: Read Only Default: Current Firmware Version Description: This 16‐bit register is factory set containing the FPGA image revision code used for configuration management. The firmware register is read only. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FW5 FW14 FW13 FW12 FW11 FW10 FW9 FW8 FW7 FW6 FW5 FW4 FW3 FW2 FW1 FW0 D(15:0) : Firmware Version Number; FW(15:0) . 15 | P a g e CFT Series Synthesizer Draft Rev‐B IP Address MSB Address: x”01” Mode: Read/Write Default: TBD Description: This register contains the upper 16‐bits of the local IP address. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 LIP31 LIP30 LIP29 LIP28 LIP27 LIP26 LIP25 LIP24 LIP23 LIP22 LIP21 LIP20 D3 LIP19 D2 LIP18 D1 D0 LIP17 LIP16 D(15:0): Local IP Address upper 16‐bits; LIP(31:16). IP Address LSB Address: x”02” Mode: Read/Write Default: TBD Description: This register contains the lower 16‐bits of the local IP address. D15 D14 D13 D12 D11 D10 D9 D8 LIP15 LIP14 LIP13 LIP12 LIP11 LIP10 LIP9 LIP8 D7 D6 D5 D4 LIP7 LIP6 LIP5 LIP4 D3 LIP3 D2 LIP2 D1 LIP1 D0 LIP0 D(15:0): Local IP Address lower 16‐bits; LIP(15:0). UDP Local Source Port Number Address: x”03” Mode: Read/Write Default: TBD Description: This register contains the local UDP port number. D15 D14 LP15 LP14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LP13 LP12 LP11 LP10 LP9 LP8 LP7 LP6 LP5 LP4 LP3 LP2 LP1 LP0 D(15:0): Local UDP Port Number; LP(15:0). UDP Destination Port Number Address: x”04” Mode: Read/Write Default: TBD Description: This register contains the destination UDP port number. D15 D14 DP15 DP14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0 D(15:0): Destination UDP Port Number; DP(15:0). 16 | P a g e CFT Series Synthesizer Draft Rev‐B MAC Address(2) Address: x”05” Mode: Read Only Default: TBD Description: This register contains the upper physical address bytes. D15 D14 PH47 PH46 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 PH45 PH44 PH43 PH42 PH41 PH40 PH39 PH38 PH37 PH36 PH35 D2 PH34 PH18 D1 PH33 PH17 D0 PH32 PH16 D(15:0): Physical MAC Address; PH(47:32). MAC Address(1) Address: x”06” Mode: Read Only Default: TBD Description: This register contains the center physical address bytes. D15 D14 PH31 PH30 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 PH29 PH28 PH27 PH26 PH25 PH24 PH23 PH22 PH21 PH20 PH19 D2 D1 D0 D(15:0): Physical MAC Address; PH(31:16). MAC Address(0) Address: x”07” Mode: Read Only Default: TBD Description: This register contains upper physical address bytes. D15 D14 PH15 PH14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PH13 PH12 PH11 PH10 PH9 PH8 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 D(15:0): Physical MAC Address; PH(31:0). Pulse Width(1) Address: x”08” Mode: Read/Write Default: TBD Description: This register contains upper pulse width bytes. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PW31 PW30 PW29 PW28 PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20 PW19 PW18 PW17 PW16 D(15:0): Pulse Width; PW(31:16). 17 | P a g e CFT Series Synthesizer Draft Rev‐B Pulse Width(0) Address: x”09” Mode: Read/Write Default: TBD Description: This register contains lower pulse width bytes. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PW15 PW14 PW13 PW12 PW11 PW10 PW9 PW8 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 D(15:0): Pulse Width; PW(15:0). Decode: 31: 0 10 Pulse Repetition Interval(1) Address: x”0A” Mode: Read/Write Default: TBD Description: This register contains upper pulse repetition interval bytes. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PR31 PR30 PR29 PR28 PR27 PR26 PR25 PR24 PR23 PR22 PR21 PR20 PR19 PR18 PR17 PR16 D(15:0): Pulse Repetition Interval; PR(31:16). Pulse Repetition Interval(0) Address: x”0B” Mode: Read/Write Default: TBD Description: This register contains lower pulse repetition interval bytes. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 31: 0 10 D(15:0): Pulse Repetition Interval; PR(15:0). Decode: 18 | P a g e CFT Series Synthesizer Draft Rev‐B Temperature Address: Mode: Default: Description: x”0C” Read Only TBD This register contains current 12‐bit internal synthesizer temperature. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NU NU NU NU T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 D(15:0): Temperature; PR(11:0). Decode: 11: 0 .038 55 Control Register Address: x”0D” Mode: Read/Write Default: TBD Description: This register contains synthesizer configuration control register. D15 D14 D13 D12 D11 NU NU NU NU NU D10 NU D9 NU D8 NU D7 NU D6 NU D5 D4 D3 SWEN FRSC1 FSRC0 D2 REFEN D1 D0 RFEN PEN D(0): PEN; Enables internal pulse modulator Active high. D(1): RFEN; Master RF output Enable bit Active high. D(2): REFEN; Master Reference output Enable bit Active high. D(4:3); FRSC(1:0); Current Frequency Register source. D(5); SWEN; Sweep Enable Active high. FRSC(1:0) Decode: “00” = Parallel Port “01” = RAM “10” = Sweep Counter Start Frequency Address: x”0E” Mode: Read/Write Default: TBD Description: This register contains frequency sweep start frequency. D15 SF15 D14 SF14 D13 SF13 D12 SF12 D11 SF11 D10 SF10 D9 SF9 D(15:0): Sweep Start Frequency; SF(15:0). Decode: D8 SF8 D7 SF7 15: 0 D6 SF6 .5 D5 SF5 D3 D4 SF4 1600 SF3 D2 SF2 D1 SF1 D0 SF0 19 | P a g e CFT Series Synthesizer Draft Rev‐B Stop Frequency Address: x”0F” Mode: Read/Write Default: TBD Description: This register contains frequency sweep start frequency. D15 D14 STF15 STF14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 STF13 STF12 STF11 STF10 STF9 STF8 STF7 STF6 STF5 STF4 STF3 STF2 D(15:0): Sweep Stop Frequency; SF(15:0). Decode: 15: 0 .5 1600 Step Size Address: x”10” Mode: Read/Write Default: TBD Description: This register contains frequency sweep step size. D15 D14 STP15 STP14 D13 STP13 D12 STP12 D11 STP11 D0 STF0 D10 D9 D8 D7 D6 D5 D4 D3 D2 STP10 STP9 STP8 STP7 STP6 STP5 STP4 STP3 STP2 D1 STF1 D1 STP1 D0 STP0 D(15:0): Frequency sweep step size; STP(14:0). Decode: 15: 0 .5 Dwell Time(1) Address: x”11” Mode: Read/Write Default: TBD Description: This register contains upper bytes of sweep dwell time per unit frequency step. D15 D14 DT30 DT31 D13 DT29 D12 DT28 D11 DT27 D10 DT26 D9 D8 D7 D6 D5 D4 D3 D2 DT25 DT24 DT23 DT22 DT21 DT20 DT19 DT18 D1 DT7 D0 DT16 D(15:0): Step dwell time; DT(31:16). 20 | P a g e CFT Series Synthesizer Draft Rev‐B Dwell Time(0) Address: Mode: Default: Description: D15 D14 DT14 DT15 x”12” Read/Write TBD This register contains lower bytes of sweep dwell time per unit frequency step. D13 DT13 D12 DT12 D11 DT11 D10 DT10 D9 D8 D7 D6 D5 D4 DT9 DT8 DT7 DT6 DT5 DT4 D3 DT3 D2 DT2 D1 DT1 D0 DT0 D(15:0): Step dwell time; DT(15:0). Decode: 31: 0 10 Current Frequency Address: x”FF” Mode: Read/Write Default: TBD Description: This register contains currently tuned frequency. D15 CF15 D14 CF14 D13 CF13 D12 CF12 D11 CF11 D10 CF10 D9 CF9 D8 CF8 D7 CF7 D6 CF6 D5 CF5 D4 CF4 D3 CF3 D2 CF2 D1 CF1 D0 CF0 D(15:0): Sweep Stop Frequency; SF(15:0). Decode: 15: 0 .5 1600 OPERATION: Frequency Tuning Manual Tuning Manual frequency tuning is accomplished by driving the address /data lines and pulling the tune strobe low. The data strobe line is sampled and the detection of a falling edge launches the tuning process. The output is blanked for 2us during tuning. Any falling edge of the tuning strobe during the tuning period will not initiate a new tuning process but will update the current frequency register. The addressing of Current Frequency Register (x”FF”) notes special consideration. Since all the parallel inputs are pulled‐ up, DATA OE# and the Address(7:0) need not be driven. In other words, the default mode of operation is register write to address x”FF” the Current Frequency Register. 21 | P a g e CFT Series Synthesizer Draft Rev‐B Frequency Tuning Timing t rfOff t rfOn tstr Figure 12 Tune Timing Specification Parameter Tune Strobe to RF Off Symbol t rfOff Min 55ns Max 70ns Tune Strobe to RF On/Phase Lock t rfOn 1.950us 2.000us Frequency strobe update t str 2.00us **** Table 14 Frequency Sweep Frequency step sweeping is accomplished by loading the Start Frequency (x”0E”), Stop Frequency (x”0F”), Step Size (x”10”) and Dwell Time (x”11”, x”12”) registers and setting Control (x”0D”) register bit SWEN (D5) high. This will cause the synthesizer to sweep from the ”Start Frequency” to the “Stop Frequency” in steps of “Step Size” with a delay at each frequency point of “Dwell Time”. The dwell is the time after frequency lock. Other modulation techniques are compatible with the frequency sweep where each of the modulation state machines are reset during the tuning interval and released after locking period of 2us. Sweep Diagram with Stop Frequency greater than Start Frequency Figure 13 22 | P a g e CFT Series Synthesizer Draft Rev‐B The relative magnitude of the start and stop frequencies will determine step direction as illustrated in figure 13 and 14 Sweep Diagram with Stop Frequency less than Start Frequency Figure 14 During frequency sweep, the Current Frequency register (x”FF”) is updated allowing for determination of the currently tuned frequency by performing a register read by addressing and pulling DATAOE# to a logical low. Phase lock can be used as a latching signal. List Mode Functionality To Be Added Pulse Modulation The CFT synthesizer has a fast and high isolation switch on its output allowing for pulse modulation. The switch provides greater than 70dB isolation with <10ns rise/fall times. Pulse Modulation can be performed manually through RFOE# or internally through the internal pulse modulation machine. Note that even when in internal modulation, RFOE# will disable the RF output signal. External Pulse Modulation Timing t OErf t rtrf Figure 15 t ftrf 23 | P a g e CFT Series Synthesizer Draft Rev‐B Pulse Modulation Timing Specification Parameter Symbol RFOE# Low to 90% RF Output tOErf Specification <45 ns RF rise time 10% to 90% t rtrf <10ns RF fall time 90% to 10% t ftrf <10ns Table 15 The pulse modulation machine is held reset by a frequency tuning event until the 2us tuning period ends. For example, the number of pulses per frequency point can be controlled. Consider the following settings: Pulse Width: 1us Pulse Repetition Interval: 3us Start Frequency: 1600MHz Stop Frequency: 18000MHz Dwell Time: 6us These settings will result in a train of 1us pulses with a 3us interval where the frequency changes every 2nd pulse as shown below in figure 16. Pulse Train Generation Figure 16 Digital Exponential Modulation Functionality To Be Added 24 | P a g e CFT Series Synthesizer Draft Rev‐B ACCEPTATNCE TEST PLAN: Procedure 1.1 Frequency Accuracy: The synthesizer is manually tuned under software control from 1600MHz to 18000MHz in 25MHz steps for a total of 657 points. At each point, frequency error is recorded and plotted with frequency on x‐axis and error in ppb (parts per billion) on y‐axis. The frequency sweep engine will be exercised to verify operation. Specification: Frequency Accuracy: +/‐ 100ppb Frequency Accuracy Test Configuration Bench Power Supplies P1 Personal Computer USB Test Fixture P2 J3 UUT Spectrum Analyzer Router Figure 17 25 | P a g e CFT Series Synthesizer Draft Rev‐B Procedure 1.2 Tuning Speed: The synthesizer is manually tuned over the fundamental frequency range to ensure switching speed of less than 2us. The particular start frequencies and stop frequencies are listed below. This test performs an autocorrelation of the output RF signal as illustrated. The oscilloscope is triggered on the falling edge of tune strobe. The correlated video is to settle less than 2us from the falling edge of the tune strobe. Specification: Switching Speed: <2us Tuning Speed Test Configuration Figure 18 Tuning Test Locations Run # Start Frequency (MHz) Stop Frequency(MHz) 1 1600 3200 2 3200 1600 3 1600 2400 4 2400 1600 5 2400 3200 6 3200 2400 Table 16 26 | P a g e CFT Series Synthesizer Draft Rev‐B Procedure 1.3 Amplitude Accuracy: The synthesizer is manually tuned under software control from 1600MHz to 18000MHz in 25MHz steps for a total of 657 points. At each point, amplitude error is recorded and plotted with frequency on x‐axis and error in dB on the y‐axis. Specification: Output Amplitude: +8dBm, +/‐ 1dB Power Accuracy Test Configuration Bench Power Supplies P1 Personal Computer Figure 19 USB Test Fixture P2 J3 UUT USB Power Sensor 27 | P a g e CFT Series Synthesizer Draft Rev‐B Procedure 1.4 Amplitude Settling and Pulse Modulation: The synthesizer is manually tuned in frequency according to the table17. At each step, the settling of amplitude video is noted to ensuring output power settling in 2us. This procedure will also verify RF output rise and fall times and latency of RF OE# to 10 and 90% amplitude video levels. The internal pulse modulation engine will be exercised to verify operation. Specification: Amplitude settling : 2us Rise Time: <10ns Fall Time: <10ns RF OE# Delay: <45 ns Amplitude settling and pulse modulation configuration Bench Power Supplies P1 Personal Computer USB Test Fixture 15dB Ampitude Video J3 P2 UUT Detector Diode 4-Channel Oscilloscope Tune Strobe RfOe Figure 20 Amplitude Test Frequencies Run # Start Frequency (MHz) Stop Frequency(MHz) 1 1600 18000 2 18000 6400 3 6400 12800 4 12800 2250 Table 17 At each of the start frequencies according to table 17, RF OE# will be toggled with 50% duty cycle and a pulse width of 1us. The amplitude video rise and fall times will be noted. 28 | P a g e CFT Series Synthesizer Draft Rev‐B Procedure 1.5 Spectral Purity: The synthesizer is manually tuned according to table 18. At each point, spurious/harmonic content and phase noise are measured. Specification: Spurious Content: <‐60dBc Harmonic Content: < ‐30dBc Phase Noise: (see note below) 1kHz : ‐70dBc/Hz 10kHz: ‐105dBc/Hz 100kHz: ‐110dBc/Hz 1MHz: ‐118dBc/Hz Note: The phase noise specification is referenced at 10GHz. Phase noise of this synthesizer is a function of frequency and phase noise translation factor must be summed to the specified frequency phase noise at each offset. The function is given below. 20 log Spectral purity test configuration Bench Power Supplies P1 Personal Computer USB Test Fixture J3 P2 UUT Spectrum Analyzer Router Figure 21 Spectral Purity Test Frequencies Run # Test Frequency (MHz) 1 1600 29 | P a g e CFT Series Synthesizer Draft Rev‐B 2 2250 3 3200 4 4500 5 5450 6 6400 7 7700 8 9000 9 10900 10 12800 11 15400 12 18000 Table 18 Procedure 1.6 On to Off RF Isolation: The synthesizer is manually tuned in frequency according to the table 18. At each point using spectral purity test configuration, the on to off RF isolation is measured. Specification: On to Off Isolation: >70dB Procedure 1.7 Power Consumption: The synthesizer is manually tuning to the frequency points listed in table 19. At each point, the +12Vdc, ‐ 12Vdc and +5Vdc power line currents are measured. The RF and Reference outputs will be enabled and terminated. Specification: Max Current +12Vdc: 1100mA Max Current ‐12Vdc: 475mA Max Current +5Vdc: 2100mA Power Consumption Test Frequencies Run # Test Frequency (MHz) 1 1600 2 9800 3 18000 Table 19 30 | P a g e CFT Series Synthesizer Draft Rev‐B Procedure 1.8 Reference Output: The reference output power, frequency, spurious/harmonic content and on to off isolation is measured. Specification: Output Power: 0dBm +/‐ 1dB Frequency Accuracy: +/‐100ppb Harmonics: <‐50dBc Spurious: <‐90dBc On/Off Isolation: >60dB Reference Test Configuration Bench Power Supplies P1 Personal Computer USB Test Fixture P2 J2 UUT Spectrum Analyzer Router Figure 22 Procedure 1.9 Mechanical The synthesizer is to be inspected to ensure all hardware is installed and tightened accordingly. The appearance is to be new free of scratches or any other blemishes. The mechanical dimensions according to Drawing (TBD) are to be measured. The unit is to be weighed. Specification: Appearance: Mint/New Weight: <1.5kg Dimensions: See Drawing(TBD) 31 | P a g e CFT Series Synthesizer Draft Rev‐B Testing Matrix: Testing will be performed according to table20. Any major revision as determined by Kuchera Engineering, will require Engineering testing as listed in the testing matrix. Additional testing beyond the standard may be ordered. Testing Matrix Procedure ‐30C +25C +70C 1.1 Frequency Accuracy S S S 1.2 Switching Speed E,O S E,O 1.3 Amplitude Accuracy S S S 1.4 Amplitude Settling E,O S E,O 1.5 Spectral Purity E,O S E,O 1.6 RF On/Off Isolation E,O S E,O 1.7 Power Consumption E,O S E,O 1.8 Reference Performance E,O S E,O Table 20 Testing Key E = Major Revision/Engineering Test S = Standard Testing O= Optional Testing 32 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 1 of 11 Procedure 1.1 Frequency Accuracy ‐30C Pass Fail _________________ Initials Comments: Paste Data Plots Below. SN: ________________ Date: ________________ +25C +70C Pass Fail Pass _________________ Initials _________________ Initials Fail 33 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 2 of 11 SN: ________________ Procedure 1.2 Date: ________________ Tuning Speed ‐30C +25C +70C Run#1 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#2 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#3 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#4 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#5 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#6 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Comments: 34 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 3 of 11 Procedure 1.3 Amplitude Accuracy ‐30C Pass Fail _________________ Initials Comments: Paste Data Plots Below. SN: ________________ Date: ________________ +25C +70C Pass Fail Pass _________________ Initials _________________ Initials Fail 35 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 4 of 11 SN: ________________ Procedure 1.4 Date: ________________ Amplitude Settling and Pulse Modulation ‐30C +25C +70C Run#1 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#2 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#3 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#4 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials Comments: 36 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 5 of 11 SN: ________________ Procedure 1.5 Date: ________________ Spectral Purity ‐30C +25C +70C Run#1 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#2 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#3 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#4 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#5 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#6 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials Comments: 37 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 6 of 11 SN: ________________ Procedure 1.5( Sheet 2) Date: ________________ Spectral Purity ‐30C +25C +70C Run#7 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#8 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#9 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#10 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#11 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#12 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials Comments: 38 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 7 of 11 SN: ________________ Procedure 1.6 Date: ________________ Isolation ‐30C +25C +70C Run#1 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#2 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#3 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#4 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#5 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#6 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials Comments: 39 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 8 of 11 SN: ________________ Procedure 1.6( Sheet 2) Date: ________________ Spectral Purity ‐30C +25C +70C Run#7 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#8 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#9 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#10 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#11 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Run#12 Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials Comments: 40 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 9 of 11 SN: ________________ Procedure 1.8 Date: ________________ Power Consumption ‐30C +25C +70C +12Vdc Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Current (mA) Current (mA) Current (mA) _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ ‐12Vdc Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Current (mA) Current (mA) Current (mA) _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ +5Vdc Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Current (mA) Current (mA) Current (mA) _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Comments: 41 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 10 of 11 SN: ________________ Procedure 1.8 Date: ________________ Reference ‐30C +25C +70C Output Pass Fail Pass Fail Pass Fail Power _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Frequency Pass Fail Pass Fail Pass Fail Accuracy _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Harmonics Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Spurious Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Isolation Pass Fail Pass Fail Pass Fail _________________ _________________ _________________ Initials Initials Initials ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Comments: 42 | P a g e CFT Series Synthesizer Draft Rev‐B Test Data Sheet 11 of 11 Procedure 1.9 Mechanical Inspection Appearance SN: ________________ Date: ________________ Pass Fail _________________ Initials ____________________________________________ Hardware Pass Fail _________________ Initials ____________________________________________ Weight Pass Fail _________________ Initials ____________________________________________ Dimensions Pass Fail _________________ Initials ____________________________________________ Comments: 43 | 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