EL5285 T NT DUC PRO LACEME r at E T e E P t L n E O R Ce OBS ENDED port .com/tsc p u M S l i l M nica nters ECO Sheet January 18, 2002 Tech r www.i NO RData r u o o act ERSIL t n o c 8-INT 1-88 ® Dual 4ns High-Speed Comparator Features The EL5285 comparator is designed for operation in single supply and dual supply applications with 5V to 12V between VS+ and VS-. For single supplies, the inputs can operate from 0.1V below ground for use in ground sensing applications. • 4ns typ. propagation delay FN7190 • 5V to 12V input supply • +2.7V to +5V output supply • True-to-ground input • Rail-to-rail outputs The output side of the comparators can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. The latch input of the EL5285 can be used to hold the comparator output value by applying a low logic level to the pin. The EL5285 features two separate comparators The EL5285 is available in the 14-pin SO package and is specified for operation over the full -40°C to +85°C temperature range. Also available are a single (EL5185), window comparator (EL5287), and quad versions (EL5485 and EL5486). • Active low latch • Single available (EL5185) • Window available (EL5287) • Quad available (EL5485 & EL5486) • Pin-compatible 8ns family available (EL5x81, EL5283 & EL5482) Applications • Threshold detection • High speed sampling circuits • High speed triggers Pinout • Line receivers EL5285 (14-PIN SO) TOP VIEW • PWM circuits • High speed V/F converters VS+ 1 INA+ 2 14 VSD + - 13 OUTA INA- 3 12 LATCHA NC 4 PART NUMBER PACKAGE TAPE & REEL PKG. NO. EL5285CS 14-Pin SO - MDP0027 EL5285CS-T7 14-Pin SO 7” MDP0027 EL5285CS-T13 14-Pin SO 13” MDP0027 11 NC INB+ 5 INB- 6 Ordering Information 10 LATCHB + - 9 OUTB VS- 7 8 GND 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL5285 Absolute Maximum Ratings (TA = 25°C) Analog Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . +12.6V Digital Supply Voltage (VSD to GND). . . . . . . . . . . . . . . . . . . . . .+7V Differential Input Voltage . . . . . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V] Common-mode Input Voltage . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V] Latch Input Voltage . . . . . . . . . . . . . . . . . . . . -0.2V to [(VSD) +0.2V] Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS = ±5V, VSD = 5V, RL = 2.3kΩ, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 1 4 mV INPUT VOS Input Offset Voltage IB Input Bias Current CIN Input Capacitance IOS Input Offset Current VCM Input Voltage Range CMRR Common-mode Rejection Ratio -5.1V < VCM < +2.75V VOH Output High Voltage VIN > 250mV VOL Output Low Voltage VIN > 250mV VCM = 0V, VO = 2.5V -10 VCM = 0V, VO = 2.5V -2.5 -5 µA 5 pF 0.5 (VS-) - 0.1 2.5 µA (VS+) - 2.25 V 65 90 dB VSD - 0.6 VSD - 0.4 V OUTPUT GND + 0.25 GND + 0.5 V DYNAMIC PERFORMANCE tpd+ Positive Going Delay Time VIN = 1VP-P, VOD = 50mV 4 6 ns tpd- Negative Going Delay Time VIN = 1VP-P, VOD = 50mV 4 6 ns IS+ Positive Analog Supply Current Per comparator 12 13.5 mA IS- Negative Analog Supply Current Per comparator 7.5 8.5 mA ISD Digital Supply Current at No Load Per comparator, output high 5.5 6.5 mA 0.9 1.2 mA SUPPLY Per comparator, output low PSRR Power Supply Rejection Ratio 55 80 dB LATCH VLH Latch Input Voltage High VLL Latch Input Voltage Low ILH Latch Input Current High VLH = 3.0V -30 -18 µA ILL Latch Input Current Low VLL = 0.3V -30 -24 µA td + Latch Disable to High Delay 6 ns td - Latch Disable to Low Delay 6 ns ts Minimum Setup Time 2 ns th Minimum Hold Time 1 ns tpw(D) Minimum Latch Disable Pulse Width 10 ns 2 2.0 0.8 V V EL5285 Typical Performance Curves Supply Current vs Supply Voltage Output High Voltage vs Temperature 14 5 VIN=-50mV RL=2.3kΩ 12 4.8 IS (mA) VOH (V) IS+ 10 8 IS- 6 4.6 4.4 4 4.2 2 0 0 1 2 3 4 5 4 -50 6 -30 -10 ±VS (V) 10 30 50 70 90 50 70 90 Temperature (°C) Offset Voltage vs Temperature Input Bias Current vs Temperature 2.5 9 8 2 7 6 IB (µA) VOS (mV) 1.5 1 5 4 0.5 3 0 2 -0.5 -50 -30 -10 10 30 50 70 1 -50 90 -30 -10 Temperature (°C) 10 30 Temperature (°C) Output Low Voltage vs Temperature Supply Current vs Temperature (per comparator) 0.4 14 Supply Current (mA) 12 VOL (V) 0.3 0.2 IS+ 10 8 IS- 6 4 2 0.1 -50 -30 -10 10 30 Temperature (°C) 3 50 70 90 0 -50 -30 -10 10 30 Temperature (°C) 50 70 90 EL5285 Typical Performance Curves 4.2 (Continued) Propagation Delay vs Overdrive VIN=1VSTEP Propagation Delay vs Supply Voltage 4.5 VS=±5V VSD=5V RL=2.3kΩ 4 4.3 TPD+ 3.9 3.8 TPD- 3.7 VSD=VS+ VOD=50mV RL=2.2kΩ 4.4 Delay Time (ns) Delay Time (ns) 4.1 4.2 TPD+ 4.1 4 TPD- 3.9 3.8 3.7 3.6 3.6 3.5 50 100 150 200 250 300 350 400 450 500 550 600 3.5 4 4.2 4.6 4.4 4.8 VOD (mV) 6.8 Propagation Delay vs Overdrive VIN=3VSTEP 5.2 5.4 5.6 5.8 6 Digital Supply Current vs Switching Frequency (per comparator) 25 VS=±5V VSD=5V RL=2.3kΩ 6.6 6.4 VS=±5V TA=25°C RL=2.3kΩ 20 6.2 ISD (mA) Delay Time (ns) 5 ±VS (V) TPD+ 6 5.8 TPD- 5.6 5.4 15 VSD=5V 10 VSD=3V 5 5.2 5 0.2 0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 2 20 10 7.2 Propagation Delay vs Overdrive VIN=5VSTEP 16 VS=±5V VSD=5V RL=2.3kΩ TPD+ 6.8 TPD- 6.6 50 6.4 6.2 Propagation Delay vs Source Resistance VIN=1VSTEP VS=±5V VSD=5mV VOD=50mV RL=2.3kΩ 14 Delay Time (ns) Delay Time (ns) 7 40 30 Frequency (MHz) VOD (V) 12 TPD+ TPD- 10 8 6 6 5.8 0.2 0.4 0.6 0.8 4 1 1.2 1.4 1.6 1.8 VOD (V) 4 2 2.2 2.4 2.6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Source Resistance (kΩ) 1.6 1.8 2 EL5285 Typical Performance Curves 0.9 VS=±5V VSD=5V VOD=50mV RL=2.3kΩ 7 Delay Time (ns) Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board Propagation Delay vs Load Capacitance VIN=1VSTEP 6.5 0.8 Power Dissipation (W) 7.5 (Continued) TPD+ 6 TPD- 5.5 5 4.5 0.6 SO 14 °C /W 0.5 0.4 0.3 0.2 0 0 10 20 30 40 50 60 70 80 90 100 0 CLOAD (pF) Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 88 SO 1 °C 4 /W Output (5ns/div, 2V/div) 0.6 0.4 Input (5ns/div, 0.5V/div) 0.2 0 0 25 50 75 85 100 Ambient Temperature (°C) Output with 50MHz Input VIN=3VP-P Output (5ns/div, 2V/div) Input (5ns/div, 2V/div) 5 50 Output with 50MHz Input VIN=1VP-P 1 0.8 25 75 85 Ambient Temperature (°C) 1.2 1.136W Power Dissipation (W) 12 0 0.1 4 1.4 833mW 0.7 125 150 100 125 EL5285 Pin Descriptions PIN NUMBER PIN NAME FUNCTION 1 VS+ Positive supply current 2 INA+ Positive input, channel A EQUIVALENT CIRCUIT VS+ IN- IN+ VSCircuit 1 3 INA- Negative input, channel A (Reference Circuit 1) 4, 11 NC Not connected 5 INB+ Negative input, channel B (Reference Circuit 1) 6 INB- Positive input, channel B (Reference Circuit 1) 7 VS- Negative supply voltage 8 GND Ground 9 OUTB Output, channel B VSD VS+ OUT VSCircuit 2 10 LATCHB Latch input, channel B VS+ VSD VSD LATCH VSCircuit 3 12 LATCHA 13 OUTA 14 VSD Latch input, channel A (Reference Circuit 3) Output, channel A (Reference Circuit 2) Digital supply voltage 6 EL5285 Timing Diagram Compare Compare Latch Enable Input 1.4V Latch Latch Differenti al Input Voltage ts Latch th tpw(D) VIN VOS VOD tpd- td+ Comparator Output 2.4V Definition of Terms TERM DEFINITION VOS Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output VIN Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications VOD Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications tpd+ Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output low to high transition tpd- Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output high to low transition td + Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a low to high transition td- Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a high to low transition ts Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in order to be acquired and held at the outputs th Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in order to be acquired and held at the output tpw (D) Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal change Applications Information Power Supplies and Circuit Layout The EL5285 comparator operates with single and dual supply with 5V to 12V between VS+ and VS-. The output side of the comparator is supplied by a single supply from 2.7V to 5V. The rail to rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. As with many high speed devices, the supplies must be well bypassed. Elantec recommends a 4.7µF tantalum in parallel with a 0.1µF ceramic. These should be placed as 7 close as possible to the supply pins. Keep all leads short to reduce stray capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the comparator. The device should be soldered directly to the PC board instead of using a socket. Use a PC board with a good, unbroken low inductance ground plane. Good ground plane construction techniques enhance stability of the comparators. Input Voltage Considerations The EL5285’s input range is specified from 0.1V below VSto 2.25V below VS+. The criterion for the input limit is that EL5285 the output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in a significant increase of input bias current. If one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. However, the propagation delay will increase. When both inputs are outside the input voltage range, the output becomes unpredictable. Large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage. Inputs of unused channels should not be left floating. They should be driven to a known state. For example, one input can be tied to ground and the other input can be connected to some voltage reference (like ±100mV) to avoid oscillation in the output due to unwanted output to input feedback. Inverting comparator with hysteresis: VREF R1 VIN + - R3 adds a portion of the output to the threshold set by R1 and R2. The calculation of the resistor values are as follows: Select the threshold voltage VTH and calculate R1 and R2. The current through R1/R2 bias string must be many times greater than the input bias current of the comparator: R1 V TH = V REF × --------------------R +R 1 2 Let the hysteresis be VH, and calculate R3: VO R 3 = -------- × ( R 1 || R 2 ) VH Input Slew Rate Most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. For clean output waveform, the input must meet certain minimum slew rate requirements. In some applications, it may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. For the EL5285, the propagation delay increases when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay does not change much with the input slew rate. R3 R2 where: VO=VSD-0.8V (swing of the output) Recalculate R2 to maintain the same value of VTH: V TH V TH – 0.5V SD R 2 1 = ( V REF – V TH ) ÷ ----------- + -------------------------------------- R3 R1 Non inverting comparator with hysteresis: R3 VIN R1 VREF + - Latch Pin Dynamics The EL5285 contains a “transparent” latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch’s high-to-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. When the latch goes high, the new data will appear at the output in approximately 4ns (latch propagation delay). Hysteresis Hysteresis can be added externally. The following two methods can be used to add hysteresis. 8 R3 adds a portion of the output to the positive input. Note that the current through R3 should be much greater than the input bias current in order to minimize errors. The calculation of the resistor values as follows: Pick the value of R1. R1 should be small (less than 1kΩ) in order to minimize the propagation delay time. Choose the hysteresis VH and calculate R3: R1 R 3 = ( V SD – 0.8 ) × -------V H Check the current through R3 and make sure that it is much greater than the input bias current as follows: 0.5V SD – V REF I = ----------------------------------------R3 EL5285 These two methods will generate hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to affect the bias string and adjustment of R1 may be required. changes state. The non-inverting and inverting inputs may be reversed. + - VIN VREF Power Dissipation When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. For reliable operation, the junction temperature must be kept below TJMAX (125°C). An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the load is very small: P DISS = ( V S × I S + V SD × I SD ) × N where: VS is the analog supply voltage from VS+ to VSIS is the analog quiescent supply current per comparator VSD is the digital supply voltage from VSD to ground ISD is the digital supply current per comparator N is the number of comparators in the package ISD strongly depends on the input switching frequency. Please refer to the performance curve to choose the input driving frequency. Having obtained the power dissipation, the maximum junction temperature can be determined as follows: T JMAX = T MAX + Θ JA × P DISS VOUT Crystal Oscillator A simple crystal oscillator using one comparator of an EL5285 is shown below. The resistors R1 and R2 set the bias point at the comparator's non-inverting input. Resistors R3, R4, and C1 set the inverting input node at an appropriate DC average voltage based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the EL5285 will give the correct logic output when an input is outside the common mode range, additional delays may occur when it is so operated. Therefore, the DC bias voltages at the inputs are set about 500mV below the center of the common mode range and the 200Ω resistor attenuates the feedback to the non-inverting input. The circuit will operate with most AT-cut crystal from 1MHz to 8MHz over a 2V to 7V supply range. The output duty cycle for this circuit is roughly 50% at 5V VCC, but it is affected by the tolerances of the resistors. The duty cycle can be adjusted by changing VCC value. 5V 200Ω R1 5kΩ R2 1.5kΩ 1MHz to 8MHz + VOUT R3 C1 R4 0.01µF 2kΩ 2kΩ where: TMAX is the maximum ambient temperature θJA is the thermal resistance of the package Threshold Detector The inverting input is connected to a reference voltage and the non-inverting input is connected to the input. As the input passes the VREF threshold, the comparator's output All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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