Application Note 1643 Author: Yi Tian ISL97646 Evaluation Board Application Manual Description Features The ISL97646IRZ-EVALZ is an evaluation board for the ISL97646, which is a DC/DC voltage regulator for TFT-LCD displays with screen sizes up to 20". ISL97646 integrates a boost converter, a VON slice circuit, an LDO and a high performance VCOM amplifier. This evaluation board is designed to: • A complete TFT-LCD PMIC evaluation platform for the ISL97646 1. Deliver up to 0.8A current for AVDD supply to the source/column driver ICs 3. Modulate VGH_M output for gate high voltage with desired delay time and discharge slope using the VON slice circuit 4. The high performance amplifier generates the LCD pixel common bias voltage (VCOM) 5. The LDO outputs up to 350mA for external digital circuitry The ISL97646 evaluation board provides a dip switch that allows users to select either 650kHz or 1.2MHz and the enable signal to enable or disable the IC. ISL97646 (24 LD 4x4 QFN) VGH RE CE PGND FB ENABLE TOP VIEW 24 23 22 21 20 19 VFLK 3 16 FREQ VDPM 4 15 COMP VDD_1 5 14 SS VDD_2 6 13 VIN_1 July 1, 2011 AN1643.0 1 10 11 12 LDO_OUT VIN_2 ADJ 17 AGND 2 POS VGH_M NEG 18 OUT 1 9 • LDO for external digital circuitry supply • Op Amp follower for VCOM • Layout Guidelines • RoHS compliant What is Needed • The following instruments will be needed to perform testing: - Power supplies - DC Electronic load - Multimeters - Oscilloscope - Resistors - Cables and wires PART # LX 8 • VON and VOFF charge pumps for gate driver IC supplies Ordering Information GND 7 • Non-synchronous boost for AVDD supply • VON slice circuit for VGH_M 2. Generate different VON (gate high) and VOFF (gate low) Pin Configuration • Input voltage: 2.7V to 5.5V ISL97646IRZ-EVALZ DESCRIPTION Evaluation Board for ISL97646 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1643 Quick Setup Guide TABLE 1. TYPICAL MAXIMUM OUTPUT CURRENT Step 1: Connect the power supply between the headers of VIN and VIN_GND. The positive output of the power supply should be connected to the VIN header. Set the power supply voltage between 2.7V and 5.5V, and the current limit at 4A. Step 2: Connect the positive and negative inputs of the Electronic load to the AVDD header and the AVDD_GND header, respectively. The load current should not exceed the maximum output current listed in Table 1. Step 3: Set S1 towards the direction of the arrow in order to tie the FREQ pin to VIN, which will set 1.2MHz switching frequency; set S1 towards the reverse direction of the arrow to pull FREQ to ground with R16, to set the frequency to 650kHz. Step 4: Set S2 towards the direction of the arrow in order to tie the ENABLE pin to VIN, which will enable the part; set S2 towards the reverse direction of the arrow in order to pull Enable to ground with R17, to disable the part. Step 5: Connect pin 2 of JP4 to pin 3 of JP4 to enable LDO; connect pin 2 of JP4 to pin 1 of JP4 to disable LDO. Step 6: Connect pin 2 of JP5 to pin 3 of JP5 to enable Gate Pulse Modulation (VGH_M); connect pin 2 of JP5 to pin 1 of JP5 to disable VGH_M. Step 7: Connect the positive and negative inputs of the electronic load to the LDO_OUT header and the LDO_GND header, respectively. VIN (V) VOUT (V) IOMAX (mA) 3.3 8 800 3.3 12 480 5 8 1370 5 12 850 NOTES: 1. Table 1 shows typical maximum output current values for 1.2MHz switching frequency and 10µH inductor. 2. Maximum current values in actual application may vary with component variance. 3. Feedback compensation parameters and input and output capacitance of the boost may need to be modified to keep good stability with maximum peak inductor current of 2.6A. Gate Pulse Modulator Timing Diagram The ISL97646 evaluation board can generate a modulated VGH_M with a fixed power-on delay time, a discharging slope and a delay time to the falling edge of VFLK. The waveform of VGH_M is shown in Figure 1. Step 8: Connect the Electronic load between the headers of VON and Vin_GND. The positive input of the E-load should be connected to the VON header; the negative input of the E-load should be connected to Vin_GND. Connect the E-load between the headers of VOFF and Vin_GND. The positive input of the E-load should be connected to Vin_GND header; the negative input of the E-load should be connected to VOFF. Set the current values of the E-load. The values of VON and VOFF at different loadings are shown in Table 2. Step 9: Connect the header of VON to the VGH pin. Step 10: Connect the input from the signal generator between the headers of VFLK and SGND. Select square waveform with an amplitude of 3.3V and a frequency of 50kHz. Step 11: Connect the power supply between the headers of POS and SGND. Set the power supply voltage at the desired VCOM value. Step 12: Make sure all the connections on the EVB are correct, then turn on the power supply and E-loads. The part will start to operate. Maximum Boost Output Current The MOSFET current limit is 2.6A. This limits the maximum output current that ISL97646 can drive. Table 1 shows the maximum output current IOMAX at different input and output voltages. 2 FIGURE 1. POWER ON DELAY TIME LDO Output Voltages The output voltage is adjusted by the connection of the ADJ pin. When ADJ is connected to ground, the output voltage is set to 3.3V; when ADJ pin is floating, the output voltage is set to 2.85V; and when ADJ pin is connected to LDO_OUT pin, the output voltage is set to 2.5V. AN1643.0 July 1, 2011 Application Note 1643 VON and VOFF at Different Loadings 4. The feedback network should sense the output voltage directly from the point of load, and should be placed to the IC and as far away from LX node as possible. The boost converter integrated in ISL97646 is capable of outputting up to 20V AVDD. This ISL97646 evaluation board generates VON and VOFF based on the output AVDD designed. Table 2 shows different values of VON and VOFF at different AVDD and different loadings for 1.2MHz switching frequency. By removing R18 and adding C24 and D3 into the circuit, the charge pump is able to deliver a VON higher than 2*AVDD. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point at the exposed die plate, underneath the package. Recommended Layout The device performance, including efficiency, output noise, transient response and control loop stability, is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. Following are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VIN and VDD bypass capacitors close to the pins. 3. Reduce the loop area with large AC amplitudes and fast slew rate. 6. The exposed die plate should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separated from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for control circuit. 9. Minimize feedback input track lengths to avoid switching noise pick-up. The EVB board layout shown on page 5 to page 7 is available to illustrate the proper layout implementation. TABLE 2. TYPICAL VON AND VOFF FOR DIFFERENT LOADING VON (V) VOFF (V) ILOADING AVDD = 8V Single Stage AVDD = 8V Two Stages AVDD = 12V Single Stage AVDD = 8V AVDD = 12V 1mA 15.2 23.4 23.8 4.3 4.4 5mA 15.1 23.2 23.3 4.3 4.3 10mA 14.7 23.0 23.2 4.2 4.3 3 AN1643.0 July 1, 2011 Evaluation Board Design Schematic D4 BAT54S Q1 MMBT3906 P16 2 AVDD 1 2 2 C23 0.1uF/25V 3 R4 1K 1 3 C27 0.1uF/25V Voff C11 1uF/16V 1 C26 0.1uF/25V C25 1uF/25V C22 0.1uF/25V 4 Z1 MMSZ 5231B P15 Von 3 P17 0 R18 D3 OPEN D2 BAT54S C24 OPEN S1 1 2 VGH 4 3 SW DIP-2 R17 10K R16 10K R3 10 P1 P2 AVDD_GND LDO_GND P3 P4 VIN_GND SGND 10 P14 L1 10uH C19 0.47u/40V 5 JP5 SHDN FB PGND CE COMP VDD1 SS 6 VDD2 C20 0.47u/16V VIN1 D1 MBRM120T3 VIN P13 18 17 AVDD C3 10uF/25V C17 1uF 16 C10 15 2.2nF 14 13 R14 0 C16 0.1uF C4 10uF/25V C5 10uF/25V C6 10uF/25V AVDD R1 10K R5 C7 OPEN 10K C9 10nF R2 1.3K 12 11 10 9 8 7 ISL97644 3 P8 R9 100K C8 OPEN 2 R7 0 VS_GPM 1 VS_AMP R8 OPEN R13 0 R12 0 P5 C15 R10 0 R11 OPEN 100K AN1643.0 July 1, 2011 P7 OUT JP4 3 P9 RE VGH VDPM NEG 2 1 VIN2 FREQ OUT C18 0.47u/16V VFLK LX VFLK LDO-OUT 4 P11 VGH_M ADJ 3 AGND 2 C14 open VGH_M GND POS P12 C2 10uF/6.3V 19 21 20 22 23 24 U1 1 C1 10uF/6.3V R6 2K C13 470p POS C12 4.7uF/6.3V C21 0.1uF LDO_OUT Application Note 1643 R15 Application Note 1643 Evaluation Board Layout FIGURE 2. EVB ASSEMBLY LAYER 5 AN1643.0 July 1, 2011 Application Note 1643 Evaluation Board Layout (Continued) FIGURE 3. TOP LAYER 6 AN1643.0 July 1, 2011 Application Note 1643 Evaluation Board Layout (Continued) FIGURE 4. BOTTOM LAYER 7 AN1643.0 July 1, 2011 Application Note 1643 Bill of Materials for ISL97646 Evaluation Board PART TYPE DESIGNATOR FOOTPRINT 10k R1 0603 1.3k R2 0603 10 R3 0603 1k R4 0603 10k R5 0603 2k R6 0603 0 R7 0603 OPEN R8 0603 100k R9 0603 0 R10 0603 100k R11 0603 0 R12 0603 0 R13 0603 0 R14 0603 10 R15 0603 10k R16 0603 10k R17 0603 0 R18 0603 10µF/6.3V C1 0805 10µF/6.3V C2 0805 10µF/25V C3 1210 10µF/25V C4 1210 10µF/25V C5 1210 10µF/25V C6 1210 OPEN C7 0603 OPEN C8 0603 10nF/25V C9 0603 2.2nF/25V C10 0603 1µF/16V C11 0603 4.7µF/6.3V C12 0805 470pF C13 0603 OPEN C14 1206 OPEN C15 0603 0.1µF/25V C16 0603 1µF C17 0603 0.47µF/16V C18 0603 0.47µF/50V C19 0805 0.47µF/16V C20 0603 0.1µF/6.3V C21 0603 8 AN1643.0 July 1, 2011 Application Note 1643 Bill of Materials for ISL97646 Evaluation Board (Continued) PART TYPE DESIGNATOR FOOTPRINT 0.1µF/25V C22 0603 0.1µF/25V C23 0603 OPEN C24 0603 1µF/25V C25 0603 0.1µF/25V C26 0603 0.1µF/25V C27 0603 1µF/16V C28 0603 MBRM120T3 D1 Case457 BAT54S D2 SOT-23 OPEN D3 SOT-23 BAT54S D4 SOT-23 ADJ JP JP4 JUMPER-3PIN VDPM JP JP5 JUMPER-3PIN 10µH L1 RLF7030 AVDD_GND P1 POWERPOST LDO_GND P2 POWERPOST VIN_GND P3 POWERPOST SGND P4 POWERPOST VDIV P5 POWERPOST POS P6 POWERPOST OUT P7 POWERPOST VS_AMP P8 POWERPOST VS_GPM P9 POWERPOST VFLK P11 POWERPOST VGH_M P12 POWERPOST AVDD P13 POWERPOST VIN P14 POWERPOST VGH P15 POWERPOST VON P16 POWERPOST VOFF P17 POWERPOST MMBT3906 Q1 SOT-23 SW DIP-2 S1 DIP4 ISL97646 U1 24 LD 4X4 QFN MMSZ 5233B Z1 SOD-123 Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 9 AN1643.0 July 1, 2011