NS ESIG D W T R NE NT PAR O F E D C EM Digitally Controlled Potentiometer NDE M M E D R EPL A O C E E 0 R 1 D 53 NOT OMMEN Data September 5, 2006 ISL9 Sheet R EC ISL95711 (XDCP™) FN8241.3 Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface Features The Intersil ISL95711 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a I2C interface. • I2C Serial Interface with Hardwire Slave Address Allows Up to Four Devices per bus The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. The wiper terminal can be connected to either end of the resistor array or at any one of the Tap Positions in between, providing 128 steps of resolution between RL and RH. The “position” of the wiper is determined by the value assigned to the volatile Wiper Register (WR). This register has an associated non-volatile Initial Value Register (IVR). The value stored in the IVR will be written into the WR at power-up, allowing wiper position recall after power interruption. The WR and the IVR can be directly written to and read from using standard I2C interface protocol. The device is available in either a 10kor 50k version. • 128 Wiper Tap Points - Wiper position can be stored in nonvolatile memory and recalled on power-up The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: • High Reliability - Endurance, 200,000 data changes per bit - Register data retention, 50 years • Industrial and automotive control • RTOTAL Values = 10k50k • Parameter and bias adjustments • Package - 10 Ld MSOP - Pb-free plus anneal (RoHS compliant) • Non-Volatile Solid-State Potentiometer • Amplifier bias and control Pinout • DCP Terminal Voltage, from V- to VCC • 127 Resistive Elements - Typical Rtotal tempco ±50ppm/°C - Ratiometric Tempco ±4ppm/°C - End to end resistance range ±20% • Low Power CMOS - Standby current, 1µA - Active current, 200A max - VCC = 2.7V to 5.5V - V- = -2.7V to -5.5V ISL95711 (10 LD MSOP) TOP VIEW SDA 1 10 SCL V- 2 9 VCC GND 3 8 RL A1 4 7 RW 5 6 RH A0 Ordering Information PART NUMBER (Notes 1, 2) PART MARKING RESISTANCE OPTION () TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL95711WIU10Z AKO 10k -40 to +85 10 Ld MSOP M10.118 ISL95711UIU10Z AKQ 50k -40 to +85 10 Ld MSOP M10.118 NOTES: 1. Add “-T” suffix for tape and reel. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL95711 Block Diagram SDA SCL GND VCC 7-BIT WIPER REGISTER (VOLATILE) RH 127 126 SDA 125 RH SCL CONTROL AND MEMORY A1 7-BIT NONVOLATILE MEMORY RW A0 124 ONE OF 128 TRANSFER GATES RESISTOR ARRAY DECODER RL 2 STORE AND RECALL CONTROL CIRCUITRY VSIMPLE BLOCK DIAGRAM A1 A0 1 0 RL RW SLAVE ADDRESS DECODE DETAILED BLOCK DIAGRAM Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION Open drain Data I/O for I2C serial interface 1 SDA 2 V- 3 GND 4 A1 A1 and A0 are address select pins used to set the slave address for the I2C serial interface 5 A0 A1 and A0 are address select pins used to set the slave address for the I2C serial interface 6 RH A fixed terminal for one end of the potentiometer resistor. 7 RW The wiper terminal which is equivalent to the movable terminal of a potentiometer. 8 RL A fixed terminal for one end of the potentiometer resistor. 9 VCC Positive logic supply voltage 10 SCL Clock input for the I2C serial interface Negative supply voltage for the potentiometer wiper control Ground 2 FN8241.3 September 5, 2006 ISL95711 Absolute Maximum Ratings Thermal Information Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on SDA, SCL, A0, and A1 with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VCC+0.3V Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V V = |V(RH)-V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -.03V to 6V RH, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC ESD (Mil-Std 883, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . .>2kV ESD Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V Thermal Resistance (Typical, Note 3) JA (°C/W) MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . +170 Recommended Operating Conditions Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to -5.5V CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. PARAMETER RH to RL resistance TEST CONDITIONS RH,RL RW CH/CL/CW ILkgDCP UNIT k U option 50 k -20 IDCP = 1mA T = -40°C to +85°C +20 ±50 VV- = -5.5V; VCC = +5.5V, wiper current = (VCC-V-)/RTOTAL 70 Potentiometer Capacitance (Note 13) Leakage on RH, RL, RW pins MAX 10 RH,RL terminal voltage Wiper resistance TYP (Note 1) W option RH to RL resistance tolerance TCR Resistance Temperature Coefficient (Notes 12, 13) MIN ppm/°C VCC V 200 10/10/ 25 Voltage at pins; V- to VCC % 0.1 pF 1 µA -1 1 LSB (Note 6) -0.5 0.5 LSB (Note 2) LSB (Note 2) VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = VRW unloaded) INL (Note 6) Integral non-linearity DNL (Note 5) Differential non-linearity W, U options ZSerror (Note 3) Zero-scale error W option 0 1 4 U option 0 0.5 2 FSerror (Note 4) Full-scale error W option -4 -1 0 U option -2 -1 0 TCV (Notes 7, 13) Ratiometric Temperature Coefficient DCP Register set at 63d, T = -40°C to +85°C ±4 LSB (Note 2) ppm/°C RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 11) Integral non-linearity DCP register set between 20 hex and 7F hex. Monotonic over all tap positions RDNL (Note 10) Differential non-linearity W and U options Roffset (Note 9) Offset DCP Register set to 00 hex, W option 0 DCP Register set to 00 hex, U option 0 3 -1 1 MI (Note 8) -0.5 0.5 MI (Note 8) 2 5 0.5 2 MI (Note 8) FN8241.3 September 5, 2006 ISL95711 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNITS 200 µA ICC1 VCC supply current, volatile write/read fSCL = 400kHz;SDA = Open; (for I2C, Active, Read and Volatile Write States only) IV-1 V- supply current, volatile write/read fSCL = 400kHz;SDA = Open; (for I2C, Active, Read and Volatile Write States only) ICC2 VCC supply current, non volatile write fSCL = 400kHz; SDA = Open; (for I2C, Active, Nonvolatile Write State only) IV-2 V- supply current, nonvolatile write fSCL = 400kHz; SDA = Open; (for I2C, Active, Nonvolatile Write State only) VCC current (standby) VCC = +5.5V, I2C Interface in Standby State 1 µA 1 µA V- current (standby) VCC = +3.6V, I2C Interface in Standby State V- = -5.5V, I2C Interface in Standby State ICCSB IV-SB ILkgDig tDCP (Note 13) Vpor A -100 200 -3 mA -5 V- = -3.6V, I2C Interface in Standby State -2 Leakage current, at pins SDA, SCL, A0, and A1 Voltage at pin from GND to VCC -10 DCP wiper response time SCL falling edge of last bit of DCP Data Byte to wiper change Power-on recall for both V- and VCC V- µA µA 10 1 V- ramp rate tD (Note 13) Power-up delay V 2.5 0.2 V V/ms 3 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state µA µs -2.5 VCC V-Ramp µA ms EEPROM SPECS EEPROM Endurance EEPROM Retention Temperature +75°C 200,000 Cycles 50 Years SERIAL INTERFACE SPECS VIL A0, A1, SDA, and SCL input buffer LOW voltage -0.3 0.3*VCC V VIH A0, A1, SDA, and SCL input buffer HIGH voltage 0.7*VCC VCC+ 0.3 V Hysteresis VOL Cpin (Note 15) fSCL SDA and SCL input buffer hysteresis 0.05* VCC SDA output buffer LOW voltage, sinking 4mA 0 V 0.4 V A0, A1, SDA, and SCL pin capacitance 10 pF SCL frequency 400 kHz tIN Pulse width suppression time at SDA and SCL inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL falling edge to SDA output data valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. 900 ns tBUF Time the bus must be free before the start of a new transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. 1300 ns tLOW Clock LOW time Measured at the 30% of VCC crossing. 1300 ns tHIGH Clock HIGH time Measured at the 70% of VCC crossing. 600 ns START condition setup time SCL rising edge to SDA falling edge. Both crossing 70% of VCC. 600 ns tSU:STA 4 FN8241.3 September 5, 2006 ISL95711 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNITS tHD:STA START condition hold time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. 600 ns tSU:DAT Input data setup time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input data hold time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. 0 ns tSU:STO STOP condition setup time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. 600 ns tHD:STO STOP condition setup time From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. 600 ns Output data hold time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. 0 ns tR (Note 15) SDA and SCL rise time From 30% to 70% of VCC 20 + 0.1 * Cb 250 ns tF (Note 15) SDA and SCL fall time From 70% to 30% of VCC 20 + 0.1 * Cb 250 ns Cb (Note 15) Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF Rpu (Note 15) SDA and SCL bus pull-up resistor offchip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k. For Cb = 40pF, max is about 15~20k. 1 tWC (Notes 14) Non-volatile Write cycle time tDH k 12 20 ms tSU:A A0, A1 setup time Before START condition 600 ns tHD:A A0, A1 hold time After STOP condition 600 ns NOTES: 1. Typical values are for TA = +25°C and ±5V supply voltage. 2. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = (V(RW)0 – V-)/LSB. 4. FS error = [V(RW)127 – VCC]/LSB. 5. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 6. INL = V(RW)i – (i • LSB – V(RW)0)/LSB for i = 1 to 127. Max V RW i – Min V RW i 10 6 7. TC V = ---------------------------------------------------------------------------------------------- ---------------- Max V RW i + Min V RW i 2 125°C for i = 16 to 120 decimal. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = |R127 – R0|/127. R127 and R0 are the measured resistances for the DCP register set to 127d and 0 respectively. 9. Roffset = R0/MI, when measuring between RW and RL. Roffset = R127/MI, when measuring between RW and RH. 10. RDNL = (Ri – Ri-1)/MI - 1, for i = 16 to 127. 11. RINL = [Ri – (MI • i) – R0]/MI, for i = 16 to 127. 6 Max Ri – Min Ri 10 12. TC R = ---------------------------------------------------------------- ---------------- Max Ri + Min Ri 2 125°C for i = 16 to 127d. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range. 13. This parameter is not 100% tested. 14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification. 5 FN8241.3 September 5, 2006 ISL95711 SDA vs SCL Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1 Pin Timing STOP START SCL Clk 1 SDA IN tHD:A tSU:A A0, A1 Test Circuit Equivalent Circuit TEST POINT RTOTAL RL RH CW CH RW CL FORCE CURRENT RW wiper register address and data from a I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. Pin Descriptions Potentiometer Pins RH AND RL SDA requires an external pull-up resistor, since it’s an open drain input/output. The high (RH) and low (RL) terminals of the ISL95711 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RH are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 127, the wiper will be closest to RH, and with the WR set to 00, the wiper is closest to RL SCL requires an external pull-up resistor, since it’s an open drain input. RW DEVICE ADDRESS (A1-A0) Rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR. The Address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must be made with the Address input pins in order to initiate communication with the ISL95711. A maximum of 4 ISL95711 devices may occupy the I2C serial bus. Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. The SDA is a bidirectional serial data input/output pin for the I2C interface. It receives device address, operation code, 6 FN8241.3 September 5, 2006 ISL95711 Typical Performance Curves 120 Irw=0.6mA T=85ºC T = 85ºC 0.6 80 60 Isb (µA) WIPER RESISTANCE () 100 T=25ºC 40 20 T=-40ºC 20 40 60 80 100 T = 25ºC T = -40ºC 0.4 0.3 2.7 0 0 0.5 120 3.2 3.7 4.2 FIGURE 2. STANDBY ICC vs VCC 0.2 0.2 Vrh=5.5V, Vrl=-5.5V Vrh=5.5V, Vrl=-5.5V 0.1 0.1 INL (LSB) DNL (LSB) 5.2 Vcc, V TAP POSITION (DECIMAL) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC/RTOTAL] for 10k (W) 0 -0.1 0 -0.1 Vrh=2.7V, Vrl=-2.7V Vrh=2.7V, Vrl=-2.7V -0.2 -0.2 0 20 40 60 80 100 120 0 20 TAP POSITION (DECIMAL) 40 60 80 100 120 TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) 0 1.6 Vrh=2.7V, Vrl=-2.7V, 10k -0.4 FSerror (LSB) 1.2 ZSerror (LSB) 4.7 0.8 Vrh=5.5V, Vrl=-5.5V, 10k 0.4 Vrh=5.5V, Vrl=-5.5V, 10k -0.8 -1.2 -1.6 Vrh=2.7V, Vrl=-2.7V, 10k 0 -40 -20 0 20 40 60 TEMPERATURE (C) FIGURE 5. ZSerror vs TEMPERATURE 7 80 -2 -40 -20 0 20 40 60 80 TEMPERATURE (C) FIGURE 6. FSerror vs TEMPERATURE FN8241.3 September 5, 2006 ISL95711 Typical Performance Curves (Continued) 0.1 1 T=25ºC T=25ºC Vcc=2.7V, V-=-2.7V 0.8 Vcc=2.7V, V-=-2.7V RINL (LSB) RDNL (LSB) 0.05 0 0.6 0.4 0.2 -0.05 0 Vcc=5.5V, V-=-5.5V -0.1 Vcc=5.5V, V-=-5.5V -0.2 0 20 40 60 80 100 120 0 20 TAP POSITION (DECIMAL) 60 80 100 120 TAP POSITION (DECIMAL) FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) 1 100 Idcp= 0.57mA 80 0.5 TCv (ppm/°C) END TO END RTOTAL CHANGE (%) 40 0 Idcp= 1.16mA -0.5 60 40 10k 20 50k -1 -40 0 -20 0 20 40 60 80 TEMPERATURE (ºC) 16 36 56 76 96 116 TAP POSITION (DECIMAL) FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE 200 10k TCr (ppm/°C) 150 100 50 50k 0 16 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm 8 FIGURE 12. FREQUENCY RESPONSE (1.8MHz) FN8241.3 September 5, 2006 ISL95711 Typical Performance Curves (Continued) FIGURE 13. WIPER MOVEMENT FIGURE 14. LARGE SIGNAL SETTLING TIME Principles of Operation DCP Description The ISL95711 is an integrated circuit incorporating one DCP with it’s associated register, non-volatile memory, and the I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal is controlled by a 7-bit volatile Wiper Register (WR). When the WR contains all zeroes (00h), the wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR contains all ones (7Fh), the wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (7Fh), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered-down, the last value stored in the IVR will be maintained in the nonvolatile memory. When power is restored, the contents of the IVR are recalled and the wiper is set to that value. The ISL95711 has dual supplies, VCC and V-. For proper operation of the chip, it is recommended both power supplies ramp up simultaneously to their final values within 20ms. The chip design gives priority to the V- supply stabilization and then looks at VCC stabilization. As the Vsupply goes below -2.5V, the RW pin goes to the default code of 64. As VCC also exceeds 2.5V (after V- < -2.5V), the RW pin goes to the code stored in the EEPROM memory value (this is referred as power on recall). While the ISL95711 is being powered up, the WR is reset to 40h (64 decimal), which locates the RW at the center between RL and RH. Soon after the power supply voltage becomes large enough for reliable non-volatile memory reading (~ ±2.5V), the ISL95711 reads the value stored on a non-volatile Initial Value Register (IVR) and loads it into the WR. The WR and IVR can be read or written directly using the I2C serial interface as described in the following sections. Memory Description The ISL95711 contains 1 non-volatile byte know as the Initial Value Register (IVR). It is accessed by the I2C interface operations with Address 00h. The IVR contains the value which is loaded into the Volatile Wiper Register (WR) at power-up. The volatile WR, and the non-volatile IVR of a DCP are accessed with the same address. 9 FN8241.3 September 5, 2006 ISL95711 The Access Control Register (ACR) determines which byte at address 00h is accessed (IVR or WR). The volatile ACR must be set as follows: When the ACR is all zeroes, which is the default at power-up: • A read operation to address 0 outputs the value of the non-volatile IVR. • A write operation to address 0 writes the same value to the WR and IVR of the corresponding DCP. When the ACR is 80h: • A read operation to address 0 outputs the value of the volatile WR. • A write operation to address 0 only writes to the corresponding volatile WR. It is not possible to write to an IVR without writing the same value to its corresponding WR. 00h and 80h are the only values that should be written to address 2. All other values are reserved and must not be written to address 2. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 2 - ACR 1 0 Reserved IVR WR WR: Wiper Register, IVR: Initial value Register. The ISL95711 is pre-programmed with 40h in the IVR. and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 15). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 15). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 16). The ISL95711 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL95711 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 01010 as the five MSBs, and the following two bits matching the logic values present at pins A1, and A0. The LSB is in the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation. (See Table 2.) TABLE 2. IDENTIFICATION BYTE FORMAT Logic values at pins A1, and A0 respectively I2C Serial Interface The ISL95711 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL95711 operates as a slave device in all applications. 0 1 0 (MSB) 1 0 A1 A0 R/W (LSB) Write Operation Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 15). On power-up of the ISL95711 the SDA pin is in the input mode. A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL95711 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95711 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95711 enters its standby state (See Figure 17). All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL95711 continuously monitors the SDA The byte at address 02h determines if the Data Byte is to be written to volatile or both volatile and non-volatile. (See “Memory Description” on page 9.) All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions 10 FN8241.3 September 5, 2006 ISL95711 Data Protection Read Operation A STOP condition acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0 or 2, the Data Byte is transferred to the Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory. A Read operation consists of a three byte instruction followed by one or more Data Bytes (See Figure 18). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL95711 responds with an ACK; then the ISL95711 transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (See Figure 18). The byte at address 02h determines if the Data Bytes being read are from volatile or non-volatile memory. (See “Memory Description”.) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE ISL95711 S T A R T IDENTIFICATION BYTE ADDRESS BYTE 0 1 0 1 0 A1 A0 0 0 0 0 0 0 0 S T O P DATA BYTE 0 A C K A C K A C K FIGURE 17. BYTE WRITE SEQUENCE 11 FN8241.3 September 5, 2006 ISL95711 S T A R T SIGNALS FROM THE MASTER IDENTIFICATION BYTE WITH R/W=0 ADDRESS BYTE 0 1 0 1 0 A1 A0 0 SIGNAL AT SDA S T A IDENTIFICATION R BYTE WITH T R/W=1 A C K SIGNALS FROM THE SLAVE S T O P A C K 0 1 0 1 0 A1 A0 1 0 0 0 0 0 0 0 A C K A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 18. READ SEQUENCE Communicating with the ISL95711 Register Description: IVR and WR There are 3 register addresses in the ISL95711, of which two can be used. Address 00h and address 02h are used to control the device. Address 01h is reserved and should not be used. Address 00h contains the non-volatile Initial Value Register (IVR), and the volatile Wiper Register (WR). Address 02h contains only a volatile word and is used as a pointer to either the IVR or WR. See Table 1. The ISL95711 has a single potentiometer. The wiper of the potentiometer is controlled directly by the WR. Writes and reads can be made directly to this register to control and monitor the wiper position without any non-volatile memory changes. This is done by setting address 02h to data 80h, then writing the data. The non-volatile IVR stores the power-up value of the wiper. On power-up, the contents of the IVR are transferred to the WR. Register Descriptions: Access Control The Access Control Register (ACR) is volatile and is at address 02h. It is 8-bits, and only the MSB is significant, all other bits should be zero (0). The ACR controls which word is accessed at register 00h as follows: To write to the IVR, first address 02h is set to data 00h, then the data is written. Writing a new value to the IVR register will set a new power-up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. So, if a new value is loaded into the IVR, not only will the non-volatile IVR change, but the WR will also contain the same value after the write, and the wiper position will change. Reading from the IVR will not change the WR, if its contents are different. 00h = Nonvolatile IVR 80h = Volatile WR All other bits of the ACR should be written to as zeros. Only the MSB can be either 0 or 1. Power-up default for this address is 00h. Example 1 Writing a new value (77h) to the IVR: Write to ACR first 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A 0 0 0 A 0 0 0 0 0 0 0 0 A 0 1 1 1 0 1 1 1 A 0 0 0 0 0 0 A Then, write to IVR 0 1 0 1 0 NOTE: The WR will also reflect this new value since both registers get written to at the same time) Example 2 Reading from the WR: Write to the ACR first (to index the WR) 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A A 1 0 Then, Set the WR address 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 0 0 1 A x x x x x x x x Read from the WR 0 1 0 1 0 NOTE: A = acknowledge, x = data bit read 12 FN8241.3 September 5, 2006 ISL95711 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X 0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X A2 A1 b -H- 0.10 (0.004) L SEATING PLANE C -A- e D 0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- MILLIMETERS MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e L1 MIN 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - 0.07 - - R1 0.003 - 0.07 - - 5o 15o 5o 15o - 0o 6o 0o 6o - END VIEW Rev. 0 12/02 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN8241.3 September 5, 2006