X9410
Low Noise/Low Power/SPI Bus
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X 9418
October 12, 2006
Dual Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Two potentiometers per package
• SPI serial interface
• Register oriented format
- Direct read/write/transfer wiper positions
- Store as many as four positions per
potentiometer
• Power supplies
- VCC = 2.7V to 5.5V
- V+ = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• Low power CMOS
- Standby current < 1µA
- High reliability
- Endurance - 100,000 data changes per bit per
register
- Register data retention - 100 years
• 8-bytes of nonvolatile EEPROM memory
• 10kresistor arrays
• Resolution: 64 taps each pot
• 24 Ld SOIC, 24 Ld TSSOP, and 24 Ld plastic DIP
packages
• Pb-free plus anneal available (RoHS compliant)
FN8193.2
DESCRIPTION
The X9410 integrates two digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
Pot 0
VSS
R0 R1
V+
VR2 R3
HOLD
CS
SCK
SO
SI
A0
A1
WP
VL0/RL0
VW0/RW0
Interface
and
Control
Circuitry
8
VW1/RW1
Pot 1
Data
R0 R1
R2 R3
1
VH0/RH0
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9410
Ordering Information
PART NUMBER
VCC LIMITS
(V)
PART MARKING
X9410YS24I
X9410YS I
X9410YS24IZ (Note)
X9410YS ZI
X9410WP24I
X9410WP I
X9410WS24I*
POTENTIOMETER
ORGANIZATION TEMP RANGE
(k)
(°C)
5 ±10%
PKG. DWG. #
-40 to 85
24 Ld SOIC (300 mil)
M24.3
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
MDP0027
-40 to 85
24 Ld PDIP
E24.6
X9410WS I
-40 to 85
24 Ld SOIC (300 mil)
M24.3
X9410WS24IZ* (Note)
X9410WS ZI
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
MDP0027
X9410WV24I*
X9410WV I
-40 to 85
24 Ld TSSOP (4.4mm)
MDP0044
X9410WV24IZ* (Note)
X9410WV ZI
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9410YS24I-2.7
X9410YS G
-40 to 85
24 Ld SOIC (300 mil)
M24.3
X9410YS24IZ-2.7 (Note)
X9410YS ZG
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
MDP0027
X9410WP24I-2.7
X9410WP G
-40 to 85
24 Ld PDIP
E24.6
X9410WS24I-2.7*
X9410WS G
-40 to 85
24 Ld SOIC (300 mil)
M24.3
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
MDP0027
0 to 70
24 Ld TSSOP (4.4mm)
MDP0044
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
10
2.7 to 5.5
X9410WS24IZ-2.7* (Note) X9410WS ZG
X9410WV24-2.7*
X9410WV F
X9410WV24Z-2.7* (Note) X9410WV ZF
X9410WV24I-2.7*
2.5
PACKAGE
X9410WV G
X9410WV24IZ-2.7* (Note) X9410WV ZG
2.5
10
-40 to 85
24 Ld TSSOP (4.4mm)
MDP0044
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9410.
Chip Select (CS)
When CS is HIGH, the X9410 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9410, placing it
2
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A0 - A1)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9410. A maximum of 4 devices may occupy the
SPI serial bus.
FN8193.2
October 12, 2006
X9410
PIN NAMES
Potentiometer Pins
VH/RH (VH0/RH0 - VH1/RH1), VL/RL (VL0/RL0 - VL1/RL1)
Symbol
Description
The VH/RH and VL/RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
SCK
Serial Clock
SI, SO
Serial Data
VW/RW (VW0/RW0 - VW1/RW1)
A0 - A1
Device Address
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
VH0/RH0 - VH1/RH1,
VL0/RL0 - VL1/RL1
Potentiometer Pins
(terminal equivalent)
VW0/RW0 - VW1/RW1
Potentiometer Pin
(wiper equivalent)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
WP
Hardware Write Protection
V+,V-
Analog Supplies
Analog Supplies (V+, V-)
VCC
System Supply Voltage
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
VSS
System Ground
NC
No Connection
Hardware Write Protect Input (WP)
PIN CONFIGURATION
DEVICE DESCRIPTION
DIP/SOIC
VCC
1
24
V+
The X9410 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
VL0/RL0
2
23
NC
VH0/RH0
3
22
NC
VW0/RW0
4
21
NC
Serial Interface
CS
5
20
A0
WP
6
19
SO
SI
7
18
HOLD
A1
8
17
SCK
VL1/RL1
9
16
NC
The X9410 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
X9410
VH1/RH1
10
15
NC
VW1/RW1
11
14
NC
VSS
12
13
V-
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
TSSOP
SI
1
24
WP
A1
2
23
CS
VL1/RL1
3
22
VW0/RW0
VH1/RH1
4
21
VH0/RH0
VW1/RW1
VSS
5
20
VL0/RL0
19
VCC
6
X9410
NC
7
18
NC
NC
8
17
NC
NC
9
16
NC
V-
10
15
V+
SCK
11
14
A0
HOLD
12
13
SO
3
The X9410 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
FN8193.2
October 12, 2006
X9410
Wiper Counter Register (WCR)
Data Registers
The X9410 contains two Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent
to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can be
altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data Register
instructions (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data Register
zero (DR0) upon power-up.
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9410 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
(LSB)
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
Figure 1. Detailed Potentiometer Block Diagram
(One of Two Arrays)
Serial Data Path
Serial
Bus
Input
From Interface
Circuitry
Register 0
Register 1
8
Register 2
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 3
VH/RH
C
o
u
n
t
e
r
D
e
c
o
d
e
INC/DEC
Logic
UP/DN
Modified SCL
UP/DN
CLK
VL/RL
VW/RW
4
FN8193.2
October 12, 2006
X9410
Figure 3. Instruction Byte Format
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9410 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9410 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9410 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9410 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
The remaining two bits in the ID byte must be set to 0.
Figure 2. Identification Byte Format
1
0
I3
I2
I1
Instructions
I0
R1
R0
0
P0
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last bit (P0)
selects which one of the two potentiometers is to be
affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter Register to the specified associated Data Register.
– Global XFR Data Register to Counter Register—This
transfers the contents of both specified Data Registers
to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of both Wiper
Counter Registers to the specified associated Data
Registers.
Device Type
Identifier
0
Register
Select
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9410 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 3.
5
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between both potentiometers and
one associated register.
FN8193.2
October 12, 2006
X9410
The sequence of these operations is shown in Figure 5
and Figure 6.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9410; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
The final command is Increment/Decrement. It is
different from the other commands because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps, thereby providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figure 7 and Figure 8.
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1 R0
0
P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
1
0
1
0
0
A1 A0
I3
I2
I1 I0
R1 R0
0 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
1
0
0
A1 A0
I3
I2
I1 I0
R1 R0 0
P0
S0
0
6
0
D5 D4 D3 D2 D1 D0
FN8193.2
October 12, 2006
X9410
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3
I2
I1
I0
0
0
0
P0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW/RW
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction
Read Wiper Counter Register
I3
1
I2
0
Instruction Set
I1
I0 R1 R0
0
1
0
0
Write Wiper Counter Register
1
0
1
0
0
0
0
Read Data Register
1
0
1
1
R1
R0
0
Write Data Register
1
1
0
0
R1
R0
0
XFR Data Register to Wiper
Counter Register
1
1
0
1
R1
R0
0
XFR Wiper Counter Register
to Data Register
1
1
1
0
R1
R0
0
Global XFR Data Register to
Wiper Counter Register
0
0
0
1
R1
R0
0
Global XFR Wiper Counter
Register to Data Register
1
0
0
0
R1
R0
0
Increment/Decrement Wiper
Counter Register
Read Status (WIP bit)
0
0
1
0
0
0
0
0
1
0
1
0
0
0
7
P1
0
P0
Operation
P0 Read the contents of the Wiper Counter
Register pointed to by P0
P0 Write new value to the Wiper Counter Register
pointed to by P0
P0 Read the contents of the Data Register pointed
to by P0 and R1 - R0
P0 Write new value to the Data Register pointed to
by P0 and R1 - R0
P0 Transfer the contents of the Data Register
pointed to by R1 - R0 to the Wiper Counter
Register pointed to by P0
P0 Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Register
pointed to by R1 - R0
0 Transfer the contents of the Data Registers
pointed to by R1 - R0 of both pots to their
respective Wiper Counter Register
0 Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1 - R0 of both pots
P0 Enable Increment/decrement of the Wiper
Counter Register pointed to by P0
1 Read the status of the internal write cycle, by
checking the WIP bit.
FN8193.2
October 12, 2006
X9410
Instruction Format
Notes: (1)
(2)
(2)
(3)
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9410 on SO)
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
instruction
opcode
DR and WCR
addresses
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 0 0 A A 1 0 0 1 0 0 0 P 0 0 P P P P P P Edge
1 0
0
5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 0 0 A A 1 0 1 0 0 0 0 P 0 0 P P P P P P Edge
1 0
0
5 4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 0 1 1 R R
1 0
1 0
0
Data Byte
(sent by X9410 on SO)
CS
W W W W W W Rising
P
0 0 P P P P P P Edge
0
5 4 3 2 1 0
Write Data Register(DR)
device type
device
identifier
addresses
instruction
opcode
DR and WCR
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 1 0 0 R
1 0
1
R
0
0
P
0
Data Byte
(sent by host on SI)
CS
W W W W W W Rising
0 0 P P P P P P Edge
5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 0 1 R R 0 P Edge
1 0
1 0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction DR and WCR
identifier
addresses
opcode
addresses
CS
CS
Falling
Rising
D D
Edge 0 1 0 1 0 0 A A 1 1 1 0 R R 0 P Edge
1 0
0
1 0
8
HIGH-VOLTAGE
WRITE CYCLE
FN8193.2
October 12, 2006
X9410
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
WCR
increment/decrement
CS
CS
identifier
addresses
opcode
addresses (sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 1 0 X X 0 P I/ I/ . . . . I/ I/ Edge
1 0
0 D D
D D
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge
1 0
1 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge
1 0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9410 on SO)
CS
CS
Falling
W Rising
Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
1 0
P
9
FN8193.2
October 12, 2006
X9410
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature.......................... -65C to +150C
Voltage on SCK, SCL or any address
input with respect to VSS ......................... -1V to +7V
Voltage on V+ (referenced to VSS) ........................ 10V
Voltage on V- (referenced to VSS).........................-10V
(V+) - (V-)............................................................... 12V
Any VH .....................................................................V+
Any VL ...................................................................... VLead temperature (soldering, 10s) .................. +300°C
IW (10s) ............................................................ ±12mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9410
X9410-2.7
Supply Voltage (VCC) Limits
5V 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Max.
Unit
End to end resistance
±20
%
Power rating
50
mW
IW
Wiper current
±6
mA
RW
Wiper resistance
150
250
Wiper Current = 1mA,
VCC = 3V
40
100
Wiper Current = 1mA,
VCC = 5V
V
RTOTAL
Vv+
VvVTERM
Parameter
Voltage on V+ Pin
Voltage on V- Pin
+4.5
+5.5
X9410-2.7
+2.7
+5.5
X9410
-5.5
-4.5
X9410-2.7
-5.5
-2.7
V-
V+
Noise
(4)
Absolute
linearity (1)
Relative
linearity (2)
Typ.
X9410
Voltage on any VH/RH or VL/RL Pin
Resolution
Min.
Temperature coefficient of RTOTAL
Potentiometer capacitances
V
dBV
1.6
%
Ref: 1kHz
±1
MI(3)
Rw(n)(actual) - Rw(n)(expected)
±0.2
MI(3)
Rw(n + 1) - [Rw(n) + MI]
300
ppm/C
±20
10/10/25
+25°C, each pot
V
-120
Ratiometric temp. coefficient
CH/CL/CW
Test Conditions
ppm/°C
pF
See Circuit #3
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
(4) Individual array resolution
10
FN8193.2
October 12, 2006
X9410
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC1
VCC supply current (Active)
ICC2
VCC supply current (Nonvolatile
Write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
-0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
COUT
CIN
(5)
(5)
Test
Max.
Unit
Test Conditions
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, A1, SI, and SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tPUR
(6)
(6)
tPUW
tR VCC
Parameter
Min.
Max.
Unit
Power-up to initiation of read operation
1
1
ms
Power-up to initiation of write operation
5
5
ms
0.2
50
V/msec
VCC Power-up ramp
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or powerdown sequencing of the bias supplies VCC, V+, and Vprovided that all three supplies reach their final values
within 1msec of each other. However, at all times, the
voltages on the potentiometer pins must be less than
V+ and more than V-. The recall of the wiper position
from nonvolatile memory is not in effect until all
supplies reach their final value.
11
EQUIVALENT A.C. LOAD CIRCUIT
5V
2.7V
1533
SDA Output
100pF
100pF
FN8193.2
October 12, 2006
X9410
A.C. TEST CONDITIONS
Test Circuit #3 SPICE Macro Model
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
RTOTAL
RH
VCC x 0.5
CL
CH
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the
third (last) power supply (VCC, V+ or V-) is stable until
the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.
CW
10pF
RL
10pF
25pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
50
500
ns
tH
SI, SCK, HOLD and CS input hold time
tRI
SI, SCK, HOLD and CS input rise time
2
µs
tFI
SI, SCK, HOLD and CS input fall time
2
µs
500
ns
100
ns
tDIS
SO output disable time
0
ns
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
0
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
tHZ
HOLD low to output in High Z
100
ns
tLZ
HOLD high to output in Low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
tCS
CS deselect time
2
µs
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
12
ns
20
ns
FN8193.2
October 12, 2006
X9410
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
Typ.
Max.
Unit
5
10
ms
High-voltage write cycle time (store instructions)
XDCP TIMING
Symbol
tWRPO
Parameter
Min. Max.
Unit
Wiper response time after the third (last) power supply is stable
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
ns
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
tCS
CS
SCK
...
tSU
SI
SO
tLAG
tCYC
tLEAD
tH
MSB
tWL
tWH
...
tRI
tFI
LSB
High Impedance
13
FN8193.2
October 12, 2006
X9410
Output Timing
CS
SCK
...
tV
tHO
tDIS
...
MSB
SO
LSB
ADDR
SI
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
SI
MSB
...
LSB
VW/RW
SO
High Impedance
14
FN8193.2
October 12, 2006
X9410
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VW/RW
ADDR
SI
Inc/Dec
Inc/Dec
...
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
15
FN8193.2
October 12, 2006
X9410
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
VR
VR
VW/RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
NONINVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
–
+
VO
100k
–
VO
+
}
}
TL072
R1
R2
10k
10k
+12V
10k
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
16
FN8193.2
October 12, 2006
X9410
Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
+
R2
R1
–
–
VS
R
VO
+
R3
R4
R2
All RS = 10k
R1
GO = 1 + R2/R1
fc = 1/(2RC)
V O = G VS
-1/2 G +1/2
R1
R2
}
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
V O = G VS
G = -R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
+
R1
–
} RA
+
} RB
frequency R1, R2, C
amplitude RA, RB
17
FN8193.2
October 12, 2006
X9410
Dual-In-Line Plastic Packages (PDIP)
E24.6 (JEDEC MS-011-AA ISSUE B)
N
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
-C-
A2
SEATING
PLANE
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MAX
-
0.250
-
-
0.39
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
D
1.150
1.290
D1
0.005
-
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
6.35
NOTES
0.015
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
29.3
4
-
4
32.7
5
-
5
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
N
24
24
9
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
18
FN8193.2
October 12, 2006
X9410
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS
24
0°
24
8°
0°
7
8°
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
19
FN8193.2
October 12, 2006
X9410
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
20
FN8193.2
October 12, 2006
X9410
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
(N/2)+1
N
PIN #1 I.D.
E
E1
0.20 C B A
1
(N/2)
B
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. E 12/02
NOTES:
SEATING
PLANE
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
c
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8193.2
October 12, 2006