81314LDxx

GS81314LD18/36GK-133/120/106
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaQuad-IVe™
Burst of 4 Multi-Bank ECCRAM™
Up to 1333 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
Clocking and Addressing Schemes
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The GS81314LD18/36GK SigmaQuad-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
4Mb x 36 and 8Mb x 18 organizations available
Organized as 8 logical memory banks
1333 MHz maximum operating frequency
1.333 BT/s peak transaction rate (in billions per second)
192 Gb/s peak data bandwidth (in x36 devices)
Separate I/O DDR Data Buses
Non-multiplexed SDR Address Bus
One operation - Read or Write - per clock cycle
Certain address/bank restrictions on Read and Write ops
Burst of 4 Read and Write operations
6 cycle Read Latency
On-chip ECC with virtually zero SER
Loopback signal timing training capability
1.25V ~ 1.3V nominal core voltage
1.2V ~ 1.3V HSTL I/O interface
Configuration registers
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IVe™ Family Overview
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IVe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g. the 8M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Parameter Synopsis
Speed Grade
Max Operating Frequency
Read Latency
VDD
-133
1333 MHz
6 cycles
1.2V to 1.35V
-120
1200 MHz
6 cycles
1.2V to 1.35V
-106
1066 MHz
6 cycles
1.2V to 1.35V
Rev: 1.09 5/2016
1/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
8M x 18 Pinout (Top View)
5
6
7
8
1
2
3
4
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCH
(CFG)
MRW
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
NUO
VSS
NUI
MCL
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS
Q0
VSS
C
Q17
VDDQ
D17
VDDQ
VSS
SA13
VDD
SA14
VSS
VDDQ
NUI
VDDQ
NUO
D
VSS
NUO
VSS
NUI
SA19
VDDQ
NC
(288 Mb)
VDDQ
SA20
D1
VSS
Q1
VSS
E
Q16
VDDQ
D16
VDD
VSS
SA11
VSS
SA12
VSS
VDD
NUI
VDDQ
NUO
F
VSS
NUO
VSS
NUI
SA17
VDD
VDDQ
VDD
SA18
D2
VSS
Q2
VSS
G
Q15
NUO
D15
NUI
VSS
SA9
MZT1
SA10
VSS
D3
NUI
Q3
NUO
H
Q14
VDDQ
D14
VDDQ
SA15
VDDQ
W
VDDQ
SA16
VDDQ
NUI
VDDQ
NUO
J
VSS
NUO
VSS
NUI
VSS
SA7
VSS
SA8
VSS
D4
VSS
Q4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
Vss
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
Q13
VSS
D13
VSS
SA5
VSS
SA6
VSS
NUI
VSS
NUO
VSS
N
NUO
VDDQ
NUI
VDDQ
PLL
VDDQ
R
VDDQ
MCL
VDDQ
D5
VDDQ
Q5
P
NUO
Q12
NUI
D12
VSS
SA3
MZT0
SA4
VSS
NUI
D6
NUO
Q6
R
VSS
Q11
VSS
D11
MCH
VDD
VDDQ
VDD
RST
NUI
VSS
NUO
VSS
T
NUO
VDDQ
NUI
VDD
VSS
SA1
VSS
SA2
VSS
VDD
D7
VDDQ
Q7
U
VSS
Q10
VSS
D10
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
NUI
VSS
NUO
VSS
V
NUO
VDDQ
NUI
VDDQ
VSS
SA21
(x18)
VDD
NUI
(B2)
VSS
VDDQ
D8
VDDQ
Q8
W
VSS
Q9
VSS
D9
TCK
MCL
RCS
MCL
TMS
NUI
VSS
NUO
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.09 5/2016
2/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
4M x 36 Pinout (Top View)
5
6
7
8
1
2
3
4
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCL
(CFG)
MRW
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
Q35
VSS
D35
MCL
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS
Q0
VSS
C
Q26
VDDQ
D26
VDDQ
VSS
SA13
VDD
SA14
VSS
VDDQ
D9
VDDQ
Q9
D
VSS
Q34
VSS
D34
SA19
VDDQ
NC
(288 Mb)
VDDQ
SA20
D1
VSS
Q1
VSS
E
Q25
VDDQ
D25
VDD
VSS
SA11
VSS
SA12
VSS
VDD
D10
VDDQ
Q10
F
VSS
Q33
VSS
D33
SA17
VDD
VDDQ
VDD
SA18
D2
VSS
Q2
VSS
G
Q24
Q32
D24
D32
VSS
SA9
MZT1
SA10
VSS
D3
D11
Q3
Q11
H
Q23
VDDQ
D23
VDDQ
SA15
VDDQ
W
VDDQ
SA16
VDDQ
D12
VDDQ
Q12
J
VSS
Q31
VSS
D31
VSS
SA7
VSS
SA8
VSS
D4
VSS
Q4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
VSS
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
Q22
VSS
D22
VSS
SA5
VSS
SA6
VSS
D13
VSS
Q13
VSS
N
Q30
VDDQ
D30
VDDQ
PLL
VDDQ
R
VDDQ
MCL
VDDQ
D5
VDDQ
Q5
P
Q29
Q21
D29
D21
VSS
SA3
MZT0
SA4
VSS
D14
D6
Q14
Q6
R
VSS
Q20
VSS
D20
MCH
VDD
VDDQ
VDD
RST
D15
VSS
Q15
VSS
T
Q28
VDDQ
D28
VDD
VSS
SA1
VSS
SA2
VSS
VDD
D7
VDDQ
Q7
U
VSS
Q19
VSS
D19
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
D16
VSS
Q16
VSS
V
Q27
VDDQ
D27
VDDQ
VSS
NUI
(x18)
VDD
NUI
(B2)
VSS
VDDQ
D8
VDDQ
Q8
W
VSS
Q18
VSS
D18
TCK
MCL
RCS
MCL
TMS
D17
VSS
Q17
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.09 5/2016
3/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Pin Description
Symbol
Description
Type
SA[21:1]
Address — Read or write address is registered on CK.
Input
D[35:0]
Write Data — Registered on KD and KD during Write operations.
D[17:0] - x18 and x36.
D[35:18] - x36 only.
Input
Q[35:0]
Read Data — Aligned with CQ and CQ during Read operations.
Q[17:0] - x18 and x36.
Q[35:18] - x36 only.
Output
Read Data Valid — Driven high one half cycle before valid read data.
Output
QVLD[1:0]
CK, CK
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Input
KD[1:0],
KD[1:0]
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch D[17:0] in x36, and D[8:0] in x18.
KD1, KD1: latch D[35:18] in x36, and D[17:9] in x18.
Input
CQ[1:0],
CQ[1:0]
Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
CQ0, CQ0: align with Q[17:0] in x36, and Q[8:0] in x18.
CQ1, CQ1: align with Q[35:18] in x36, and Q[17:9] in x18.
Output
R
Read Enable — Registered on CK. See the Clock Truth Table for functionality.
Input
W
Write Enable — Registered on CK. See the Clock Truth Table for functionality.
Input
MRW
Mode Register Write — Registered onCK. Can be used synchronously or asynchronously to enable Register Write Mode. See the State and Clock Truth Tables for functionality.
Input
PLL
PLL Enable — Weakly pulled High internally.
PLL = 0: disables internal PLL.
PLL = 1: enables internal PLL.
Input
RST
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Input
ZQ
Driver Impedance Control Resistor Input — Must be connected to VSS through an external resistor RQ to
program driver impedance.
Input
ZT
ODT Impedance Control Resistor Input — Must be connected to VSS through an external resistor RT to
program ODT impedance.
Input
RCS
Current Source Resistor Input — Must be connected to VSS through an external 2K resistor to provide
an accurate current source for the PLL.
Input
Rev: 1.09 5/2016
4/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Symbol
Description
Type
MZT[1:0]
ODT Mode Select — Set the default ODT state globally for all input groups during power-up and reset. Must
be tied High or Low.
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 11: reserved.
Note: The ODT state for each input group can be changed at any time via the Configuration Registers.
Input
PZT[1:0]
ODT Configuration Select — Set the default ODT state for various combinations of input groups during
power-up and reset, when MZT[1:0] = 01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Note: The ODT state for each input group can be changed at any time via the Configuration Registers.
Input
VDD
Core Power Supply
—
VDDQ
I/O Power Supply
—
VREF
Input Reference Voltage — Input buffer reference voltage.
—
VSS
Ground
—
TCK
JTAG Clock — Weakly pulled Low internally.
Input
TMS
JTAG Mode Select — Weakly pulled High internally.
Input
TDI
JTAG Data Input — Weakly pulled High internally.
Input
TDO
JTAG Data Output
MCH
Must Connect High — May be tied to VDDQ directly or via a 1k resistor.
Input
MCL
Must Connect Low — May be tied to VSS directly or via a 1k resistor.
Input
NC
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
NUI
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Input
NUO
Not Used Output — There is an internal chip connection to these output pins, but they are unused by the
device. The drivers are tri-stated internally. They should be left unconnected.
Output
Rev: 1.09 5/2016
Output
5/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
—
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Initialization Summary
Prior to functional use, these devices must first be initialized and configured. The steps described below will ensure that the
internal logic has been properly reset, and that functional timing parameters have been configured.
Flow Chart
Notes:
1. MZT[1:0] and PZT[1:0] mode pins are used to set the default ODT state of all
input groups at power-up, and whenever RST is asserted High. The ODT state
for each input group can be changed any time thereafter using Register Write
Mode to program certain bits in the Configuration Registers.
Power-Up
Reset SRAM
2.
Calibrations are performed for driver impedance, ODT impedance, and the PLL
current source immediately after RST is de-asserted Low. The calibrations can
take up to 384K cycles total. See the Power-Up and Reset Requirements section
for more information.
3.
The PLL can be enabled by the PLL pin, or by the PLL Enable (PLE) bit in the
Configuration Registers. See the PLL Operation section for more information.
4.
If the PLE register bit is used to enable the PLL, then Register Write Mode will
likely have to be utilized in the “Asynchronous, Pre-Input Training” method in
order to change the state of the bit, since Address / Control Input Training has
not yet been performed. See the Configuration Registers section for more information.
5.
It can take up to 64K cycles for the PLL to lock after it has been enabled.
6.
Special Loopback Modes are available in these devices to perform Address /
Control Input Training; they are selected and enabled via the Loopback Mode
Select (LBK[1:0]) and Loopback Mode Enable (LBKE) bits in the Configuration
Registers.
7.
If Loopback Modes are used to perform Address / Control Input Training, then
Register Write Mode will likely have to be utilized in the “Asynchronous,
Pre-Input Training” method in order to change the states of the LBK[1:0] and
LBKE register bits.
8.
Loopback Modes can also be used for Read Data Output Training, if desired.
See the Signal Timing Training and Loopback Mode sections for more information.
9.
“Additional Configuration” includes any other configuration changes required by
the system. Since this step is performed after Address / Control Input Training,
Register Write Mode can be utilized in the “Asynchronous, Post-Input Training”
method (or perhaps the “Synchronous” method, if the synchronous timing
requirements can be met at the particular operating frequency).
Wait for Calibrations
Enable PLL,
Wait for Lock
Training
Required?
No
Yes
Address / Control
Input Training
Read Data
Output Training
Write Data
Input Training
Additional
Configuration
Normal Operation
10. It is up to the system to determine if/when re-training is necessary.
Yes
Rev: 1.09 5/2016
Train
Again?
No
6/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1: Assert RST High for at least 1ms.
While RST is asserted high:
• The PLL is disabled.
• The states of R, W, and MRW control inputs are ignored.
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• Q are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low.
Step 5: Wait at least 384K (393,216) cycles.
During this time:
• Driver and ODT impedances are calibrated. Can take up to 320K cycles.
• The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles.
Step 6: Enable the PLL.
Step 7: Wait at least 64K (65,536) cycles for the PLL to lock.
After the PLL has locked:
• CQ, CQ begin toggling within specification.
Step 8: Continue initialization (see the Initialization Flow Chart).
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low, as in step 4 above, steps 5~7 above must be followed before normal operation is resumed. It is up the system to determine
whether further re-initialization beyond step 7 (as outlined in the Initialization Flow Chart) is required before normal operation is
resumed.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.09 5/2016
7/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
PLL Operation
A PLL is implemented in these devices to control all output timing. It uses the CK input clock as a source, and is enabled when all
of the following conditions are met:
1. RST is de-asserted Low, and
2. Either the PLL Enable pin (PLL) or the PLL Enable register bit (PLE) is asserted High, and
3. CK cycle time  tKHKH (max), as specified in the AC Timing Specifications section.
Once enabled, the PLL requires 64K stable clock cycles in order to lock/synchronize properly.
When the PLL is enabled, it aligns output clocks and read data to input clocks (with some fixed delay), and it generates all
mid-cycle output timing. See the Output Timing section for more information.
The PLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the PLL to lose lock/
synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see “tKJITcc” in the AC Timing Specifications section
for more information). However, the PLL must be resynchronized (i.e. disabled and then re-enabled) whenever the nominal input
clock frequency is changed.
The PLL is disabled when any of the following conditions are met:
1. RST is asserted High, or
2. Both the PLL Enable pin (PLL) and the PLL Enable register bit (PLE) are deasserted Low, or
3. CK is stopped for at least 30ns, or CK cycle time  30ns.
On-Chip Error Correction
These devices implement a single-error correct, single-error detect (SEC-SED) ECC algorithm (specifically, a Hamming Code) on
each 18-bit data word transmitted in DDR fashion on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/Q[26:18],
and D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to the
user). As such, these devices actually comprise 184Mb of memory, of which 144Mb are visible to the user.
The ECC algorithm cannot detect multi-bit errors. However, these devices are architected in such a way that a single SER event
very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit” represents the data
transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-bit errors results in
the SER mentioned previously (i.e., <0.002 FITs/Mb, measured at sea level).
Not only does the on-chip ECC significantly improve SER performance, but it can also free up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit
“data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction).
Depending on the application, such error-bit allocation may be unnecessary in these devices, in which case the entire memory array
can be utilized for data storage, effectively providing 12.5% greater storage capacity compared to SRAMs of the same density not
equipped with on-chip ECC.
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Configuration Registers
These devices utilize a set of registers for device configuration. The configuration registers are written via Register Write Mode,
which is initiated by asserting MRW High and R Low. When Register Write Mode is utilized, up to sixteen distinct 6-bit registers
can be programmed using SDR timing on the SA[10:1] address input pins. The D data input pins are not used.
Note: Register Write Mode only provides the ability to write the configuration registers. The ability to read the configuration registers is provided via a private JTAG instruction and register. Please contact GSI for more information.
Register Write Mode can be utilized in two ways:
1. Asynchronous Method: MRW is driven asynchronously, such that is does not meet setup and hold time specs to CK.
2. Synchronous Method: MRW is driven synchronously, such that is meets setup and hold time specs to CK.
Regardless how Register Write Mode is utilized, at least 16 NOPs must be initiated before beginning a Register Write sequence, to
ensure any previous Read and Write operations are completed before the sequence begins. And, at least 16 NOPs must be initiated
after completing a Register Write sequence and before initiating Read and Write operations, and before utilizing Loopback Mode,
to allow sufficient time for the newly programmed register settings to take effect.
Register Write Mode Utilization - Asynchronous Method
Register Write Mode can be utilized asynchronously up to the full operating speed of the device. When Register Write Mode is utilized asynchronously, there are two cases to consider:
1. Pre Input Training: SA[10:1], R, W are driven such that they do not meet setup and hold time specs to CK.
2. Post Input Training: SA[10:1], R, W are driven such that they meet setup and hold time specs to CK.
Each case is examined separately below.
Pre Input Training Requirements
In this case, MRW, R, W, and SA[10:1] are all driven asynchronously. When Register Write Mode is utilized in this manner, only
one register can be programmed during any particular instance that MRW is asserted High.
The requirements for this usage case are as follows:
• At least 16 NOPs must be initiated before and after the Register Write sequence.
• MRW High must meet minimum pulse width requirements (tMRWPW).
• R Low and SA[10:1] Valid must meet minimum setup time requirements (tMRWS) to MRW High.
• R Low and SA[10:1] Valid must meet minimum hold time requirements (tMRWH) from MRW Low.
• W High must also meet minimum setup time requirements (tMRWS) to MRW High, if inadvertent memory writes are to be prevented during the Register Write process. Otherwise, W state is “don’t care”.
• W High must also meet minimum hold time requirements (tMRWH) from MRW Low, if inadvertent memory writes are to be
prevented during the Register Write process. Otherwise, W state is “don’t care”.
Note: tMRWPW = tMRWS = tMRWH = 4 cycles (minimum).
Note: Inadvertent memory reads will occur while MRW and R are Low during the Register Write process. The memory reads are
harmless, and can be ignored.
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Post Input Training Requirements
In this case, MRW is driven asynchronously, whereas R, W, and SA[10:1] are all driven synchronously (i.e. they all meet setup and
hold time specs to CK). When Register Write Mode is utilized in this manner, multiple registers can be programmed during any
particular instance that MRW is asserted High. The timing diagrams below arbitrarily show four registers programmed while MRW
is asserted High, but in practice it can be any number greater than or equal to one.
The requirements for this usage case are as follows:
• At least 16 NOPs must be initiated before and after the Register Write(s).
• MRW High must meet minimum setup time requirements (tMRWS) to the CK that generates the first Register Write.
• MRW High must meet minimum hold time requirements (tMRWH) from the CK that generates the first NOP after the last Register Write.
• R must be driven Low (synchronously) and SA[10:1] must be driven Valid (synchronously) for each Register Write.
• W state is a “don’t care” (synchronously) for each Register Write.
Note: tMRWS = tMRWH = 4 cycles (minimum).
Asynchronous Register Write Timing Diagram - Pre Input Training
16 NOPs
Register Write Mode
16 NOPs
CK
tMRWS
tMRWPW
SA[10:1]
tMRWH
Register #n
W
Must be “high” to prevent memory write; “don’t care” otherwise
R
MRW
Asynchronous Register Write Timing Diagram - Post Input Training
Read / Write
16 NOPs
16 NOPs
Register Write Mode
Read / Write
CK
tIVKH tKHIX
SA[10:1]
V
Reg #a
Reg #b
Reg #c
Reg #d
V
V
W
V
X
X
X
X
V
V
R
V
V
V
tMRWS
tMRWH
MRW
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Register Write Mode Utilization - Synchronous Method
Register Write Mode can also be utilized synchronously up to the full operating speed of the device. However, MRW cannot be
trained using Loopback Mode, so the ability to use it synchronously may be limited to slower operating frequencies where the lack
of training capability is less problematic for the user.
In this case, MRW, R, W, and SA[10:1] are all driven synchronously (i.e. they all meet setup and hold time specs to CK). When
Register Write Mode is utilized in this manner, multiple registers can be programmed in successive cycles. The timing diagrams
below arbitrarily show four registers programmed in successive cycles, but in practice it can be any number greater than or equal to
one.
The requirements for this usage case are as follows:
• At least 16 NOPs must be initiated before and after the Register Write(s).
• MRW must be driven High (synchronously), R must be driven Low (synchronously), and SA[10:1] must be driven Valid (synchronously) for each Register Write.
• W state is a “don’t care” (synchronously) for each Register Write.
Synchronous Register Write Timing Diagram
Read / Write
16 NOPs
Register Write Mode
16 NOPs
Read / Write
CK
tIVKH tKHIX
SA[10:1]
V
Reg #a
Reg #b
Reg #c
Reg #d
V
V
W
V
X
X
X
X
V
V
R
V
V
V
tRVKH tKHRX
MRW
Rev: 1.09 5/2016
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Register Description
As described previously, Register Write Mode provides the ability to program up to sixteen distinct 6-bit configuration registers using SDR timing on the SA[10:1] address input pins. Specifically, SA[4:1] are used to select one of the sixteen distinct registers, and
SA[10:5] are used to program the six data bits of the selected register.
The registers are defined as follows:
Address
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
Pin
8G
6G
8J
6J
8M
6M
8P
6P
8T
6T
Reg #
Bit Usage
Register Data Bits
Register Select Bits
Active
Active
RSVD[2:0]
Active
LBK[1:0]
Active
DZT[1:0]
Active
RLM
0
0
0
0
0
PLE
0
0
0
1
1
LBKE
0
0
1
0
2
KDZT[1:0]
CKZT[1:0]
0
0
1
1
3
CZT[1:0]
AZT[1:0]
0
1
0
0
4
Unused
All Others except “111X”
Active
Reserved for GSI Internal Use Only
1
1
1
5 ~ 13
X
14 ~ 15
Notes:
1. Unused/unlabeled register bits should be written to “0”.
2. The RSVD[2:0] bits in Register #1 should be written to “100”.
3. Registers #14 and #15 are reserved for GSI internal use only. Users should not access these registers.
Register Bit Definitions
PLL Enable
Read Latency Select
RLM
PLE
0
reserved
0
Disable PLL, if PLL pin = 0
1
Read Latency = 6 cycles
1
Enable PLL
1
POR/RST Default
0
POR/RST Default
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Loopback Mode Enable
Loopback Mode Select
LBKE
LBK[1:0]
0
Disable Loopback Mode
0
0
XOR Loopback Mode, input group #1
1
Enable Loopback Mode
0
1
XOR Loopback Mode, input group #2
0
POR/RST Default
1
0
INV Loopback Mode, input group #1
1
1
INV Loopback Mode, input group #2
0
0
POR/RST Default
Note: In the ODT Control register bit definitions below, MZT[1:0] and PZT[1:0] pins set the default state of the register bits at power-up and whenever RST is asserted High. The register bits can then be overwritten (via Register Write Mode), while RST is de-asserted Low, to change the state of the feature controlled by the register bits.
Input Clock ODT Control
Address & Control ODT Control
CKZT1
CKZT0
AZT1
AZT0
KDZT1
KDZT0
CZT1
CZT0
0
0
disabled
0
0
disabled
0
1
enabled: PU = PD = RT
0
1
enabled: PU = PD = RT
1
0
enabled: PU = PD = 2*RT
1
0
enabled: PU = PD = 2*RT
1
1
reserved
1
1
reserved
00, if MZT[1:0] = 00 or PZT0 = 0
01, if MZT[1:0] = 01 and PZT0 = 1
10, if MZT[1:0] = 10 and PZT0 = 1
11, if MZT[1:0] = 11 and PZT0 = 1
00, if MZT[1:0] = 00 or PZT1 = 0
01, if MZT[1:0] = 01 and PZT1 = 1
10, if MZT[1:0] = 10 and PZT1 = 1
11, if MZT[1:0] = 11 and PZT1 = 1
POR/RST Default
POR/RST Default
Write Data ODT Control
DZT1
DZT0
0
0
disabled
0
1
enabled: PU = PD = RT
1
0
enabled: PU = PD = 2*RT
1
1
reserved
00, if MZT[1:0] = 00
01, if MZT[1:0] = 01
10, if MZT[1:0] = 10
11, if MZT[1:0] = 11
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POR/RST Default
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Signal Timing Training
Signal timing training (aka “deskew”) is often required for reliable signal transmission between components at the I/O speeds
supported by these devices. Typically, the timing training is performed in the following sequence:
Step 1: Address / Control input training.
These devices support a special Loopback Mode of operation to facilitate address / control input training.
Step 2: Read Data output training.
These devices support a special Loopback Mode of operation to facilitate read data output training.
Alternatively, slow-frequency Memory Write operations can be used to store DDR data patterns in the memory array
reliably (full-frequency Memory Write operations cannot be used because write data signals have not been trained yet),
and full-frequency Memory Read operations can then be used to train the read data output signals.
Step 3: Write Data input training.
Since address, control, and read data signals have already been trained at this point, full-frequency Memory Write and
Read operations can then be used to train the write data inputs.
Loopback Mode
These devices support two distinct Loopback Modes of operation, which can be used to:
1. Perform per-pin training on the address (SA), control (R, W), and write data clock (KD, KD) inputs.
2. Perform per-pin training on the read data (Q) outputs.
In both cases, SA, R, W, KD, KD input pin values are sampled, logically manipulated, and looped back to Q output pins.
Register bit LBKE is used to enable/disable Loopback Mode. When LBKE = 1 and MRW = 0, Loopback Mode is enabled, and
Memory Read and Write operations are blocked regardless of the states of R and W. When LBKE = 0 or MRW = 1, Loopback
Mode is disabled. See the State Truth Table for more information.
Register bits LBK[1:0] are used to select between the two distinct Loopback Modes supported by the design (controlled by LBK1),
and between the two groups of inputs used during the selected Loopback Mode (controlled by LBK0), as follows:
•
•
•
•
LBK[1:0] = 00: selects XOR LBK Mode using Input Group 1. Loopback Mode “00”.
LBK[1:0] = 01: selects XOR LBK Mode using Input Group 2. Loopback Mode “01”.
LBK[1:0] = 10: selects INV LBK Mode using Input Group 1. Loopback Mode “10”.
LBK[1:0] = 11: selects INV LBK Mode using Input Group 2. Loopback Mode “11”.
Note: For convenience, KD clocks have been included in the group of inputs that can be trained via Loopback Mode. However, 
the timing requirement for KD clocks is that their edges be tightly aligned to CK clock edges, unlike the timing requirement for
address/control signals, whose edges must be centered (approximately) between CK edges in order to optimize setup and hold
times to those CK edges. Consequently, it is questionable whether Loopback Mode can be used to train KD clocks effectively.
Loopback Latency
Loopback Latency (“LBKL”) - i.e. the number of cycles from when the inputs are sampled to when the proper result appears on the
output pins, is equal to 7 cycles.
Enabling Loopback Mode
Loopback Mode is enabled as follows:
Step 1: Initiate a Register Write operation with SA[10:1] = “000ab1.0010” to select Register #2, set LBKE = 1 to enable
Loopback Mode, and set LBK[1:0] to “ab” to select Loopback Mode “ab”.
Step 2: Wait 16 cycles for new register settings to take effect.
Loopback Mode “ab” is enabled after step 2 because MRW = 0, LBKE = 1, and LBK[1:0] = “ab”.
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Changing Loopback Modes
Once enabled, Loopback Mode can be changed as follows
Step 1: Initiate a Register Write operation with SA[10:1] = “000cd1.0010” to select Register #2, keep LBKE = 1 to keep
Loopback Mode enabled, and set LBK[1:0] to “cd” to select Loopback Mode “cd”.
Step 2: Wait 16 cycles for new register settings to take effect.
Loopback Mode “cd” is enabled after step 2 because MRW = 0, LBKE = 1, and LBK[1:0] = “cd”.
Disabling Loopback Mode
Loopback Mode is disabled as follows:
Step 1: Initiate a Register Write operation with SA[10:1] = “000xx0.0010” to select Register #2 and set LBKE = 0 to disable
Loopback Mode.
Step 2: Wait 16 cycles for new register settings to take effect.
Loopback Mode is disabled after step 2 because LBKE = 0.
XOR LBK Mode
XOR LBK Mode is for address/control input training. It is defined as follows:
• Each input pin of the selected input group is sampled on CK and CK.
• For each input sampled, the value sampled on CK is XORed with the value sampled on CK.
• For each input sampled, the XOR result is subsequently driven out on its associated output pin (concurrently with CQ) for one
full clock cycle, beginning “LBKL” cycles after the input is sampled.
Consequently, the output data pattern is always SDR regardless of the input data pattern, and regardless whether the SRAM
samples the inputs correctly or not. The SDR output data pattern enables address/control inputs to be trained before data outputs.
XOR LBK Mode enables the controller to input various SDR and DDR data patterns on a particular input, and then determine
whether the SRAM sampled them correctly or not by observing SDR data patterns on the associated output. Via multiple iterations
of this process, the controller can adjust its output timing (in order to adjust the SRAM input timing) until optimum setup and hold
margin at both SRAM input sample points is achieved, thereby individually “training” each address/control input pin.
INV LBK Mode
INV LBK Mode is primarily for read data output training. It is defined as follows:
• Each input pin of the selected input group is sampled on CK and CK.
• For each input sampled, the value sampled on CK is subsequently driven out on its associated output pin (concurrently with
CQ) for half a clock cycle, beginning “LBKL” cycles after the input is sampled.
• For each input sampled, the value sampled on CK is inverted and then subsequently driven out on its associated output pin (concurrently with CQ) for half a clock cycle, beginning “LBKL + 0.5” cycles after the input is sampled.
Consequently, the output data pattern is DDR if the input data pattern is SDR (and vice versa), provided the SRAM samples the
inputs correctly. Therefore, to ensure deterministic output behavior, address/control inputs should be trained before data outputs.
INV LBK Mode enables the controller to input various SDR (or DDR) data patterns on a particular input, to generate deterministic
DDR (or SDR) data patterns on a particular output. The controller latches the output as it would during a normal Read operation,
and verifies whether it received the expected values or not. Via multiple iterations of this process, the controller can adjust its input
timing until optimum setup and hold margin at both controller input sample points is achieved, thereby individually “training” each
read data output pin.
Note: INV LBK Mode can be used for address/control input training, if desired. However, such usage can be problematic because
the output data pattern may be erroneous (i.e. it could be SDR or DDR regardless of the input pattern) if the SRAM samples the
input incorrectly. In which case the controller may have difficulty detecting the erroneous behavior, and/or interpreting it.
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Entering XOR LBK Mode
16 NOPs
Register Write Mode
(Enable XOR LBK)
16 NOPs
XOR LBK Mode
(first 6 cycles of 11, for example)
CK
Input
CQ
Output
NOP State
Undefined
Output begins reflecting XOR LBK result ...
Exiting XOR LBK Mode
XOR LBK Mode continued
(last 5 cycles of 11, for example)
Register Write Mode
(Disable XOR LBK)
16 NOPs
Read / Write
CK
Input
CQ
Output
... after Loopback Latency
Undefined
NOP State
Note: “Input” represents any loop-backed input pin. “Output” represents the output pin on which “Input” is looped back.
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Entering INV LBK Mode
16 NOPs
Register Write Mode
(Enable INV LBK)
16 NOPs
INV LBK Mode
(first 6 cycles of 11, for example)
CK
Input
CQ
Output
NOP State
Undefined
Output begins reflecting INV LBK result ...
Exiting INV LBK Mode
INV LBK Mode continued
(last 5 cycles of 11, for example)
Register Write Mode
(Disable INV LBK)
16 NOPs
Read / Write
CK
Input
CQ
Output
... after Loopback Latency
Undefined
NOP State
Note: “Input” represents any loop-backed input pin. “Output” represents the output pin on which “Input” is looped back.
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Loopback Mode Input Group Definition and Input-to-Output Pin Mapping
Inputs are divided into 2 groups because there are up to 28 inputs to train (22 address, 2 control, and 4 KD clocks), but as few as 18
outputs available to loop them back to (in x18 devices).
There are 18 inputs per group - one per Q output in x18 devices, and one per two Q outputs in x36 devices.
Input Signals
Output Pins
Output Signals
GP1
GP2
GP1
GP2
x18
x36
x18
x36
1
8P
8V
SA4
NU
13V
13V, 12W
Q8
Q8, Q17
2
8M
8T
SA6
SA2
13T
13T, 12U
Q7
Q7, Q16
3
8J
---
SA8
RSVD
13P
13P, 12R
Q6
Q6, Q15
4
9H
9L
SA16
KD0
13N
13N, 12P
Q5
Q5, Q14
5
8G
9K
SA10
KD0
12J
12J, 12M
Q4
Q4, Q13
6
9F
7H
SA18
W
12G
12G, 13H
Q3
Q3, Q12
7
8E
---
SA12
RSVD
12F
12F, 13G
Q2
Q2, Q11
8
9D
---
SA20
RSVD
12D
12D, 13E
Q1
Q1, Q10
9
8C
---
SA14
RSVD
12B
12B, 13C
Q0
Q0, Q9
10
6T
---
SA1
RSVD
2W
2W, 1V
Q9
Q18, Q27
11
6P
6V
SA3
SA21
2U
2U, 1T
Q10
Q19, Q28
12
6M
---
SA5
RSVD
2R
2R, 1P
Q11
Q20, Q29
13
6J
7N
SA7
R
2P
2P, 1N
Q12
Q21, Q30
14
5H
5L
SA15
KD1
2M
2M, 2J
Q13
Q22, Q31
15
6G
5K
SA9
KD1
1H
1H, 2G
Q14
Q23, Q32
16
5F
---
SA17
RSVD
1G
1G, 2F
Q15
Q24, Q33
17
6E
---
SA11
RSVD
1E
1E, 2D
Q16
Q25, Q34
18
5D
6C
SA19
SA13
1C
1C, 2B
Q17
Q26, Q35
Right Side Output Data Byte(s)
Input Pins
Left Side Output Data Byte(s)
Bit #
Notes:
1. Blue shading indicates input pins that are unused (NU) in certain device configurations. During Loopback Mode, the associated
output pins loop back the states of those input pins regardless whether they are used or unused.
2. Gray shading indicates Group 2 inputs that are reserved (RSVD) for future use. During Loopback Mode, the associated output
pins act as if they were looping back input pins tied Low.
3. The 18 unused Q in x18 devices remain in their “NU” states during Loopback Mode.
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Address Bus Utilization and Bank Access Restrictions
The address bus is a non-multiplexed SDR bus. One memory address may be loaded per cycle - a read address at CK or a write
address at CK; consequently only one memory operation - a Read or a Write - may be initiated per clock cycle. The address bus is
also sampled at CK during a Register Write operation.
Address Bit Encoding
Command
SA Address Bits
Addr
Device
Load
21 20 19 18 17 16 15 14 13 12 11 10 9 8
Read
CK
Write
CK
Register
Write
CK
x36
NU
Address
x18
x36
Address
NU
Address
x18
x36
x18
Address
NU X
X
X
7
6
5
4
3
2
1
0
BA
Address
BA NU
BA
Address
BA NU
BA
Address
BA NU
BA
Address
BA NU
X
X
X
X
X
X
X
X
X
Register Data
Register #
NU
X
X
X
X
X
X
X
X
X
Register Data
Register #
NU
Note: BA = Bank Address
Bank Access Restrictions
1. In all devices, Read in cycle “n” must be to a different bank than Write in cycle “n-4” (due to Write Buffering).
Note: Bank restriction #1 (the only restriction in SIO-B4 devices) can be avoided by always initiating Reads “in phase” - that is, by
always initiating Reads an even number of cycles apart.
Consider a typical sequence of alternating Read and Write operations:
R -> W -> R -> W -> R -> W -> R -> W -> R -> W -> R -> W.
In this case the Reads are always “in phase” because they always occur 2 cycles apart. Consequently, when a Read occurs in cycle
“n”, the operation in cycle “n-4” is always a Read, and therefore this bank restriction is automatically avoided.
Now consider the following sequence, where NOPs replace Read and Write operations in the typical sequence:
R -> W -> NOP -> W -> R -> NOP -> R -> NOP -> NOP -> W -> R -> W.
In this case the Reads stay “in phase” because they occur 2 or 4 cycles apart. Consequently, when a Read occurs in cycle “n”, the
operation in cycle “n-4” is always a Read or NOP, and therefore this bank restriction is automatically avoided.
Now consider the following sequence, where an even number of NOPs are inserted into the typical sequence:
R -> W -> NOP -> NOP -> R-> W -> R -> NOP -> NOP -> W -> R -> W -> R -> W -> R -> W.
In this case the Reads stay “in phase” because they occur 2 or 4 cycles apart. Consequently, when a Read occurs in cycle “n”, the
operation in cycle “n-4” is always a Read or NOP, and therefore this bank restriction is automatically avoided.
Now consider the following sequence, where an odd number of NOPs are inserted into the typical sequence:
R -> W -> NOP -> R -> W -> R -> W -> R -> NOP -> W -> R -> W -> NOP -> NOP -> NOP -> R -> W.
In this case the Reads become “out of phase” because they sometimes occur 3 or 5 cycles apart. Consequently, when a Read occurs
in cycle “n”, the operation in cycle “n-4” is sometimes a Write (see the red bolded Reads for examples where this occurs), and therefore this bank restriction must be taken into consideration when the Reads are initiated.
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Read Latency
Read Latency (i.e. the number of cycles from read command input to first read data output) is specified as follows:
Read Latency
Comment
6 cycles
First read data output 6 cycles after read command input
Note: The RLM register bit must remain “1” in these devices while initiating Read operations, to keep Read Latency = 6 cycles.
Write Latency
Write Latency (i.e. the number of cycles from write command input to first write data input) is specified as follows:
Write Latency
Comment
-1 cycle
First write date input 1 cycle before write command input
Read / Write Coherency
These devices are fully coherent. That is, Read operations always return the most recently written data to a particular address, even
when a Read operation to a particular address occurs one cycle after a Write operation to the same address.
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State Truth Table
RST
MRW LBKE
R
W
SA
D
SRAM State
Q
1
X
X
X
X
X
X
Reset
NOP State
0
1
X
0
X
V
X
Register Write Mode
Undefined
0
0
1
X
X
X
X
Loopback Mode
Loopback
0
1
X
1
0
0
0
X
Memory Mode
(Read, Write, NOP)
See Clock Truth
Table
See Clock Truth Table
Note: 1 = High; 0 = Low; V = Valid; X = don’t care.
Clock Truth Table
SA
MRW
R
W
Previous
Operation
Current
Operation
CK
(tn)
CK
(tn)
CK
(tn)
CK
(tn)
(tn–1)
(tn)
KD
(tn-1)
KD
(tn-½)
X
0
1
1
NOP
NOP
X
X
—
0
—
X
0
1
X
Write
NOP
D3
D4
—
0
—
X
0
X
1
Read
NOP
X
X
—
V
0
1
0
NOP
Write
D1
D2
D3
D4
V
0
X
0
Read
Write
D1
D2
D3
D4
V
0
0
X
NOP
Read
X
X
V
0
0
X
Write
Read
D3
V
1
0
X
NOP
Register Write
1
1
X
NOP
NOP
D
Q
KD
(tn)
KD
(tn+½)
CQ
(tn+6)
CQ
(tn+6½)
Q3
CQ
(tn+7)
Q4
CQ
(tn+7½)
—
0
—
Q3
Q4
—
—
Q1
Q2
Q3
Q4
D4
—
Q1
Q2
Q3
Q4
X
X
—
Undefined
Undefined
X
X
—
0
—
Notes:
1. 1 = High; 0 = Low; V = Valid; X = don’t care.
2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of write data transferred during Write operations.
3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of read data transferred during Read operations.
4. Q pins are driven Low for one cycle in response to NOP and Write commands, 6 cycles after the command is sampled, except when preceded by a Read command.
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Input Timing
These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various
synchronous inputs. Specifically:
During Memory Mode, CK latches address (SA) inputs, and CK latches control (R, W, MRW) inputs.
During Register Write Mode, CK latches address and control inputs.
During Loopback Mode, CK and CK latch address, control, and write data clock (KD, KD) inputs.
During Memory Mode, KD[1:0] and KD[1:0] latch particular write data (D) inputs, as follows:
• KD0 and KD0 latch D[17:0] in x36 devices, and D[8:0] in x18 devices.
• KD1 and KD1 latch D[35:18] in x36 devices, and D[17:9] in x18 devices.
Output Timing
These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is
tightly aligned with read data in order to enable reliable source-synchronous data transmission.
These devices utilize a PLL to control output timing. When the PLL is enabled, it generates 0 and 180 phase clocks from CK
that control read data output clock (CQ, CQ), read data (Q), and read data valid (QVLD) output timing, as follows:
• CK+0 generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive.
• CK+180 generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive.
Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations.
When the PLL is enabled, CQ is aligned to an internally-delayed version of CK. See the AC Timing Specifications for more
information.
CQ[1:0] and CQ[1:0] align with particular Q and QVLD outputs, as follows:
• CQ0 and CQ0 align with Q[17:0], QVLD0 in x36 devices, and Q[8:0], QVLD0 in x18 devices.
• CQ1 and CQ1 align with Q[35:18], QVLD1 in x36 devices, and Q[17:9], QVLD0 in x18 devices.
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Driver Impedance Control
Programmable Driver Impedance is implemented on the following output signals:
• CQ, CQ, Q, QVLD.
Driver impedance is programmed by connecting an external resistor RQ between the ZQ pin and VSS.
Driver impedance is set to the programmed value within 320K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.
Output Signal
Pull-Down Impedance (ROUTL)
Pull-Up Impedance (ROUTH)
CQ, CQ, Q, QVLD
RQ*0.2  15%
RQ*0.2  15%
Notes:
1. ROUTL and ROUTH apply when 175 RQ  225.
2. The mismatch between ROUTL and ROUTH is less than 10%, guaranteed by design.
ODT Impedance Control
Programmable ODT Impedance is implemented on the following input signals:
• CK, CK, KD, KD, SA, R, W, MRW, D.
ODT impedance is programmed by connecting an external resistor RT between the ZT pin and VSS.
ODT impedance is set to the programmed value within 320K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.
Input Signal
CK, CK
KD, KD
SA
Rev: 1.09 5/2016
Register Bits
Pull-Down Impedance (RINL)
Pull-Up Impedance (RINH)
CKZT[1:0] = 00
off
off
CKZT[1:0] = 01
RT  15%
RT  15%
CKZT[1:0] = 10
RT*2  20%
RT*2  20%
CKZT[1:0] = 11
reserved
reserved
KDZT[1:0] = 00
off
off
KDZT[1:0] = 01
RT  15%
RT  15%
KDZT[1:0] = 10
RT*2  20%
RT*2  20%
KDZT[1:0] = 11
reserved
reserved
AZT[1:0] = 00
off
off
AZT[1:0] = 01
RT  15%
RT  15%
AZT[1:0] = 10
RT*2  20%
RT*2  20%
AZT[1:0] = 11
reserved
reserved
23/40
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Input Signal
R, W, MRW
D
Register Bits
Pull-Down Impedance (RINL)
Pull-Up Impedance (RINH)
CZT[1:0] = 00
off
off
CZT[1:0] = 01
RT  15%
RT  15%
CZT[1:0] = 10
RT*2  20%
RT*2  20%
CZT[1:0] = 11
reserved
reserved
DZT[1:0] = 00
off
off
DZT[1:0] = 01
RT  15%
RT  15%
DZT[1:0] = 10
RT*2  20%
RT*2  20%
DZT[1:0] = 11
reserved
reserved
Notes:
1. RINL and RINH apply when 105 RT  135
2. The mismatch between RINL and RINH is less than 10%, guaranteed by design.
3. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.
Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be
tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to VDDQ / 2 (i.e., to the switch point of the
diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.
This could result in the device’s operating currents being higher.
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Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Core Supply Voltage
VDD
-0.3 to +1.4
V
I/O Supply Voltage
VDDQ
-0.3 to VDD
V
VIN1
-0.3 to VDDQ + 0.3
VIN2
VDDQ - 1.5 to +1.7
Input Voltage (LS)
VIN3
Junction Temperature
Storage Temperature
Input Voltage (HS)
Notes
V
2
-0.3 to VDDQ + 0.3
V
3
TJ
0 to 125
C
TSTG
-55 to 125
C
Notes:
1. Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time
may affect reliability of this component.
2. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W, MRW. VIN1 and VIN2 must both be met.
3. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Core Supply Voltage
VDD
1.2
1.25
1.35
V
I/O Supply Voltage
VDDQ
1.15
1.2
VDD
V
Commercial Junction Temperature
TJC
0
—
85
C
Industrial Junction Temperature
TJI
-40
—
100
C
Notes
Note: For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF, and Inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
Thermal Impedances
Package
JA (C°/W)
Airflow = 0 m/s
 JA (C°/W)
Airflow = 1 m/s
 JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
 JC (C°/W)
FBGA
13.67
10.28
9.31
3.08
0.13
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I/O Capacitance
Parameter
Symbol
Min
Max
Units
Notes
Input Capacitance
CIN
—
5.0
pF
1, 3
Output Capacitance
COUT
—
5.5
pF
2, 3
Notes:
1. VIN = VDDQ/2.
2. VOUT = VDDQ/2.
3. TA = 25C, f = 1 MHz.
Input Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Notes
DC Input Reference Voltage
VREFdc
0.48 * VDDQ
0.50 * VDDQ
0.52 * VDDQ
V
—
DC Input High Voltage (HS)
VIH1dc
VREF + 0.08
0.80 * VDDQ
VDDQ + 0.15
V
1, 6
DC Input Low Voltage (HS)
VIL1dc
-0.15
0.20 * VDDQ
VREF - 0.08
V
2, 6
DC Input High Voltage (LS)
VIH2dc
0.75 * VDDQ
VDDQ
VDDQ + 0.15
V
7
DC Input Low Voltage (LS)
VIL2dc
-0.15
0
0.25 * VDDQ
V
7
AC Input Reference Voltage
VREFac
0.47 * VDDQ
0.50 * VDDQ
0.53 * VDDQ
V
3
AC Input High Voltage (HS)
VIH1ac
VREF + 0.15
0.80 * VDDQ
VDDQ + 0.25
V
1, 4~6
AC Input Low Voltage (HS)
VIL1ac
-0.25
0.20 * VDDQ
VREF - 0.15
V
2, 4~6
AC Input High Voltage (LS)
VIH2ac
VDDQ - 0.2
VDDQ
VDDQ + 0.25
V
4, 7
AC Input Low Voltage (LS)
VIL2ac
-0.25
0
0.2
V
4, 7
Notes:
1. “Typ” parameter applies when Controller ROUTH = 40 and SRAM RINH = RINL = 120.
2. “Typ” parameter applies when Controller ROUTL = 40 and SRAM RINH = RINL = 120.
3. VREFac is equal to VREFdc plus noise.
4. VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
5. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
6. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W, MRW.
7. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.
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Output Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Notes
DC Output High Voltage
VOHdc
—
0.80 * VDDQ
VDDQ + 0.15
V
1, 3
DC Output Low Voltage
VOLdc
-0.15
0.20 * VDDQ
—
V
2, 3
AC Output High Voltage
VOHac
—
0.80 * VDDQ
VDDQ + 0.25
V
1, 3
AC Output Low Voltage
VOLac
-0.25
0.20 * VDDQ
—
V
2, 3
Note:
1. “Typ” parameter applies when SRAM ROUTH = 40 and Controller RINH = RINL = 120.
2. “Typ” parameter applies when SRAM ROUTL = 40 and Controller RINH = RINL = 120.
3. Parameters apply to: CQ, CQ, Q, QVLD.
Leakage Currents
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Min
Max
Units
Notes
ILI1
-2
2
uA
1, 2
ILI2
-20
2
uA
1, 3
ILI3
-2
20
uA
1, 4
ILO
-2
2
uA
5, 6
Notes:
1. VIN = VSS to VDDQ.
2. Parameters apply to CK, CK, KD, KD, SA, D, R, W, MRW when ODT is disabled.
Parameters apply to MZT, PZT.
3. Parameters apply to PLL, TMS, TDI (weakly pulled up).
4. Parameters apply to RST, TCK (weakly pulled down).
5. VOUT = VSS to VDDQ.
6. Parameters apply to CQ, CQ, Q, QVLD, TDO.
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Operating Currents
Parameter
Symbol
VDD (nom)
1066 MHz
1200 MHz
1333 MHz
Units
x18 Operating Current
IDD
1.25V
2300
2500
2700
mA
x36 Operating Current
IDD
1.25V
3000
3200
3400
mA
Notes:
1. IOUT = 0 mA; VIN = VIH or VIL.
2. Applies at 100% alternating Reads and Writes.
AC Test Conditions
Parameter
Symbol
Conditions
Units
Core Supply Voltage
VDD
1.2 to 1.35
V
I/O Supply Voltage
VDDQ
1.15 to 1.25
V
Input Reference Voltage
VREF
0.6
V
Input High Level
VIH
0.9
V
Input Low Level
VIL
0.3
V
Input Rise and Fall Time
—
2.0
V/ns
Input and Output Reference Level
—
0.6
V
Note: Output Load Conditions RQ = 200. Refer to figure below.
AC Test Output Load
50
Output
50
VDDQ/2
5 pF
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AC Timing Specifications (independent of device speed grade)
Parameter
Symbol
Min
Max
Units Notes
Input Clock Timing
Clk High Pulse Width
tKHKL
0.45
—
cycles
1
Clk Low Pulse Width
tKLKH
0.45
—
cycles
1
Clk High to Clk High
tKHKH
0.45
0.55
cycles
2
Clk High to Write Data Clk High
tKHKDH
-200
+200
ps
3
Clk Cycle-to-Cycle Jitter
tKJITcc
—
60
ps
1,4,5
PLL Lock Time
tKlock
65,536
—
cycles
6
Clk Static to PLL Reset
tKreset
30
—
ns
7,12
Output Timing
Clk High to Output Valid / Hold
tKHQV/X
+0.4
+1.2
ns
8
Clk High to Echo Clock High
tKHCQH
+0.4
+1.2
ns
9
Echo Clk High to Output Valid / Hold
tCQHQV/X
-75
+75
ps
10,12
Echo Clk High to Echo Clock High
tCQHCQH
0.5*tKHKH (nom) - 25
0.5*tKHKH (nom) + 25
ps
11,12
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameter specifiesCK CK and KD KD requirements.
3. Parameter specifies CK KD and CK KD requirements.
4. Parameter specifies Cycle-to-Cycle (C2C) Jitter (i.e. the maximum variation from clock rising edge to the next clock rising edge). 
As such, it limits Period Jitter (i.e. the maximum variation in clock cycle time from nominal) to  30ps. 
And as such, it limits Absolute Jitter (i.e. the maximum variation in clock rising edge from its nominal position) to  15ps.
5. The device can tolerated C2C Jitter greater than 60ps, up to a maximum of 200ps. However, when using a device from a particular speed
grade, tKHKH (min) of that speed grade must be derated (increased) by half the difference between the actual C2C Jitter and 60ps. For
example, if the actual C2C Jitter is 100ps, then tKHKH (min) for the -133 speed grade is derated to 0.77ns (0.75ns + 0.5*(100ps - 60ps)).
6. VDD slew rate must be < 0.1V DC per 50ns for PLL lock retention. PLL lock time begins once VDD and input clock are stable.
7. Parameter applies to CK.
8. Parameters apply to Q, and are referenced to CK.
9. Parameter specifies CK CQ timing.
10. Parameters apply to Q, QVLD and are referenced to CQ & CQ.
11. Parameter specifies CQ CQ timing. tKHKH (nom) is the nominal input clock cycle time applied to the device.
12. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
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AC Timing Specifications (variable with device speed grade)
Parameter
Symbol
–133
Min
–120
Max
Min
–106
Units Notes
Max
Min
Max
6.0
0.9375
6.0
ns
Input Clock Timing
Clk Cycle Time
tKHKH
0.75
6.0
0.83
1
Input Setup & Hold Timing
Input Valid to Clk High
tIVKH
150
—
150
—
150
—
ps
Clk High to Input Hold
tKHIX
150
—
150
—
150
—
ps
Input Pulse Width
tIPW
200
—
200
—
200
—
ps
MRW Valid to Clk High
tRVKH
150
—
150
—
150
—
ps
Clk High to MRW Hold
tKHRX
150
—
150
—
150
—
ps
2
3
4
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameters apply to SA, and are referenced to CK (and to CK during Loopback Mode).
Parameters apply to R, W, and are referenced to CK (and to CK during Loopback Mode).
Parameters apply to D, and are referenced to KD & KD.
Parameters apply to KD, KD, and are referenced to CK & CK during Loopback Mode.
3. Parameter specifies the input pulse width requirements for each individual address, control, and data input. Per-pin deskew must be performed, to center the valid window of each individual input around the clock edge that latches it, in order for this parameter to be relevant
to the application. The parameter is not tested; it is guaranteed by design and verified through extensive corner-lot characterization.
4. Parameters apply to MRW, and are referenced to CK. Applicable when Register Write Mode is utilized synchronously.
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Memory Read and Write Timing Diagram
Read
Write
Read
NOP
NOP
Write
Read
Write
Read
Write
NOP
KD
tKHKH
tKHKL tKLKH tKHKH
KD
tIVKH
D
D21
tKHKDH
D22
D23
D24
tIVKH
tKHIX
D41
D42
D43
D44
D61
tKHIX
D62
D63
D64
D81
D82
D83
D84
tKHKDH
CK
tKHKH
tKHKL tKLKH tKHKH
CK
tIVKH tKHIX
SA A1
A2
A3
A4
A5
A6
A7
A8
tIVKH tKHIX
R
W
tKHQX
tKHQV
Q
Q11
Q12
Q13
Q14
Q31
Q32
Q33
Q34
QVLD
tCQHQX
tKHCQH
tCQHQV
tCQHQX
tCQHQV
CQ
tCQHCQH
CQ
Note: MRW=0 (not shown).
Rev: 1.09 5/2016
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JTAG Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller,
etc.), ECCRAM, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices
contain a TAP Controller and multiple TAP Registers. The TAP Registers consist of one Instruction Register and multiple Data
Registers.
The TAP consists of the following four signals:
Pin
Pin Name
I/O
Description
TCK
Test Clock
I
Induces (clocks) TAP Controller state transitions.
TMS
Test Mode Select
I
Inputs commands to the TAP Controller.
Sampled on the rising edge of TCK.
TDI
Test Data In
I
Inputs data serially to the TAP Registers.
Sampled on the rising edge of TCK.
TDO
Test Data Out
O
Outputs data serially from the TAP Registers.
Driven from the falling edge of TCK.
Concurrent TAP and Normal ECCRAM Operation
According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only
exceptions are EXTEST and SAMPLE-Z. See the Tap Registers section for more information.
Disabling the TAP
When JTAG is not used, TCK should be tied Low to prevent clocking the ECCRAM. TMS and TDI should either be tied High
through a pull-up resistor or left unconnected. TDO should be left unconnected.
JTAG DC Operating Conditions
Parameter
Symbol
Min
Max
Units
Notes
JTAG Input High Voltage
VTIH
0.75 * VDDQ
VDDQ + 0.15
V
1
JTAG Input Low Voltage
VTIL
–0.15
0.25 * VDDQ
V
1
JTAG Output High Voltage
VTOH
VDDQ – 0.2
—
V
2, 3
JTAG Output Low Voltage
VTOL
—
0.2
V
2, 4
Notes:
1. Parameters apply to TCK, TMS, and TDI.
2. Parameters apply to TDO.
3. ITOH = –2.0 mA.
4. ITOL = 2.0 mA.
Rev: 1.09 5/2016
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
JTAG AC Timing Specifications
Parameter
Symbol
Min
Max
Units
TCK Cycle Time
tTHTH
50
—
ns
TCK High Pulse Width
tTHTL
20
—
ns
TCK Low Pulse Width
tTLTH
20
—
ns
TMS Setup Time
tMVTH
10
—
ns
TMS Hold Time
tTHMX
10
—
ns
TDI Setup Time
tDVTH
10
—
ns
TDI Hold Time
tTHDX
10
—
ns
Capture Setup Time (Address, Control, Data, Clock)
tCS
10
—
ns
Capture Hold Time (Address, Control, Data, Clock)
tCH
10
—
ns
TCK Low to TDO Valid
tTLQV
—
10
ns
TCK Low to TDO Hold
tTLQX
0
—
ns
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV
tTLQX
TDO
Rev: 1.09 5/2016
33/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the Test-Logic Reset state in one of two ways:
1. At power up.
2. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
TAP Controller State Diagram
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
Update-DR
Rev: 1.09 5/2016
0
34/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0
1
1
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP
Controller.
Instruction Register (IR - 3 bits)
The Instruction Register stores the various TAP Instructions supported by ECCRAM. It is loaded with the IDCODE instruction
(logic 001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI
and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
Instruction
Description
EXTEST
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with output signals (Q, QVLD,
CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan Register
contents do not appear at the output pins until the TAP Controller has reached the Update-DR state.
Also disables all ODT.
See the Boundary Scan Register description for more information.
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register when the
TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO when the
TAP Controller is in the Shift-DR state.
See the ID Register description for more information.
010
SAMPLE-Z
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also disables all ODT.
Also forces Q output drivers to a High-Z state.
See the Boundary Scan Register description for more information.
011
PRIVATE
Reserved for manufacturer use only.
100
SAMPLE
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Boundary Scan Register description for more information.
101
PRIVATE
Reserved for manufacturer use only.
110
PRIVATE
Reserved for manufacturer use only.
111
BYPASS
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and
inserts the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Bypass Register description for more information.
000
001
Rev: 1.09 5/2016
35/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Bypass Register (DR - 1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP
Controller is in the Shift-DR state.
ID Register (DR - 32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the
Shift-DR state.
The ID Register is 32 bits wide, and is encoded as follows:
See BSDL Model
(31:12)
GSI ID
(11:1)
Start Bit
(0)
XXXX XXXX XXXX XXXX XXXX
0001 1011 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,
and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR - 129 bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the ECCRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all
signals composing the ECCRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.
Additionally, the contents of the Boundary Scan Register associated with the ECCRAM outputs (Q, QVLD, CQ, CQ) are driven
directly to the corresponding ECCRAM output pins when the EXTEST instruction is selected. However, after the EXTEST
instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state
does not appear at the output pins until the TAP Controller has reached the Update-DR state.
The value captured in the boundary scan register for NU pins is determined by the external pin state. The value captured in the
boundary scan register for NC pins is 0 regardless of the external pin state. The value captured in the Internal Cell (Bit 129) is 1.
Output Driver State During EXTEST
EXTEST allows the Internal Cell (Bit 129) in the Boundary Scan Register to control the state of Q drivers. That is, when Bit 129 =
1, Q drivers are enabled (i.e., driving High or Low), and when Bit 129 = 0, Q drivers are disabled (i.e., forced to High-Z state). See
the Boundary Scan Register section for more information.
ODT State During EXTEST and SAMPLE-Z
ODT on all inputs is disabled during EXTEST and SAMPLE-Z.
Rev: 1.09 5/2016
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Boundary Scan Register Bit Order Assignment
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and Bit 129 is the
MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out
through TDO.
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
1
7L
29
12F
57
12W
85
1T
113
1C
2
7K
30
11G
58
10W
86
4R
114
3C
3
9L
31
13G
59
8V
87
2R
115
2B
4
9K
32
10G
60
9U
88
3P
116
4B
5
8J
33
12G
61
8T
89
1P
117
5A
6
7H
34
11H
62
9R
90
4P
118
6A
7
9H
35
13H
63
8P
91
2P
119
6B
8
7G
36
10J
64
9N
92
3N
120
6C
9
8G
37
12J
65
8M
93
1N
121
5D
10
9F
38
13K
66
6M
94
4M
122
6E
11
8E
39
13L
67
7N
95
2M
123
5F
12
7D
40
11L
68
5N
96
3L
124
6G
13
9D
41
12M
69
7P
97
1L
125
5H
14
8C
42
10M
70
6P
98
1K
126
6J
15
7B
43
13N
71
5R
99
2J
127
5K
16
8B
44
11N
72
6T
100
4J
128
5L
17
9B
45
12P
73
7U
101
1H
129
Internal
18
7A
46
10P
74
5U
102
3H
19
9A
47
13P
75
6V
103
2G
20
10B
48
11P
76
6W
104
4G
21
12B
49
12R
77
7Y
105
1G
22
11C
50
10R
78
4W
106
3G
23
13C
51
13T
79
2W
107
2F
24
10D
52
11T
80
3V
108
4F
25
12D
53
12U
81
1V
109
1E
26
11E
54
10U
82
4U
110
3E
27
13E
55
13V
83
2U
111
2D
28
10F
56
11V
84
3T
112
4D
Rev: 1.09 5/2016
37/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
260-Pin BGA Package Drawing (Package GK)
0.08 S C
0.22 S C A S B S
Ø
Ø
Ø
0.50~Ø0.70(260x)
13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
19.00
17.40  0.05
22.00  0.05
1.00
PIN #1 CORNER
13.20  0.05
B
A
1.00
14.00  0.05
12.00
Rev: 1.09 5/2016
C
0.15
0.05
SEATING PLANE
0.40~0.60
0.51 REF
C
4–R0.5 (MAX)
0.50 + 0.03
0.10
HEAT SPREADER
//
1.09 REF
C
2.10 + 0.2/–0.3
0.06
0.05(4X)
Ball Pitch:
1.00 Substrate Thickness:
Ball Diameter:
0.60 Mold Thickness:
0.51
—
38/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Ordering Information — GSI SigmaQuad-IVe ECCRAM
Org
Part Number
Type
Package
Speed
(MHz)
TA
8M x 18
GS81314LD18GK-133
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1333
C
8M x 18
GS81314LD18GK-120
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1200
C
8M x 18
GS81314LD18GK-106
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1066
C
8M x 18
GS81314LD18GK-133I
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1333
I
8M x 18
GS81314LD18GK-120I
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1200
I
8M x 18
GS81314LD18GK-106I
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1066
I
4M x 36
GS81314LD36GK-133
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1333
C
4M x 36
GS81314LD36GK-120
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1200
C
4M x 36
GS81314LD36GK-106
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1066
C
4M x 36
GS81314LD36GK-133I
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1333
I
4M x 36
GS81314LD36GK-120I
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1200
I
4M x 36
GS81314LD36GK-106I
SigmaQuad-IVe B4
ROHS-Compliant 260-Pin BGA
1066
I
Note: C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.09 5/2016
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
GS81314LD18/36GK-133/120/106
Revision History
Rev. Code
Types of Changes
Format or Content
GS81314LD1836GK_r1
—
GS81314LD1836GK_r1.01
Content
• Changed Loopback Latency to 7 cycles, regardless of Read Latency.
GS81314LD1836GK_r1.02
Content
• Removed leaded BGA package support.
GS81314LD1836GK_r1.03
Content
• Removed 4th digit from all speed bins.
GS81314LD1836GK_r1.04
Content
• Redefined Bank Address pins.
Content
•
•
•
•
•
•
•
•
GS81314LD1836GK_r1.06
Content
• Add IDD specifications.
• Changed -125 speed bin to -120. Changed -110 speed bin to -106.
Removed -100 speed bin.
• Removed RL=5 support (created new RL=5 -specific datasheet with
no bank restrictions; see GS81314LD1937GK).
GS81314LD1836GK_r1.07
Content
• Reduced VDD (min) requirement for -120 speed bin to 1.15V, to allow
for 1.2V nominal VDD.
GS81314LD1836GK_r1.08
Content
• Removed “Preliminary” from data sheets.
GS81314LD1836GK_r1.09
Content
• Increased VDD (min) to 1.2V for 1066 MHz and 1200 MHz speed
bins. VDD (min) is now the same value for all speed bins.
GS81314LD1836GK_r1.05
Rev: 1.09 5/2016
Revisions
• Creation of new datasheet
Increased VDD (max) to 1.35V.
Added package thermal impedances.
Redefined OFR[2:0] bits in Configuration Reg #1 as RSVD[2:0].
Revised tKHKDH specs.
Revised tKHQV, tKHQX, and tKHCQH specs.
Revised tCQHQV and tCQHQX specs.
Revised tIPW specs.
Banner changed to “Preliminary”, to reflect ES status.
40/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology