New Product SiS407DN Vishay Siliconix P-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY RDS(on) () ID (A)e, f 0.0095 at VGS = - 4.5 V - 25 0.0138 at VGS = - 2.5 V - 25 0.0195 at VGS = - 1.8 V - 25 VDS (V) - 20 Qg (Typ.) 38 nC PowerPAK 1212-8 S 3.30 mm S 3.30 mm 1 APPLICATIONS S 2 S 3 • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • Low Thermal Resistance PowerPAK® Package with Small Size and Low 1.07 mm Profile • 100% Rg Tested • 100% UIS Tested • Compliant to RoHS Directive 2002/95/EC • Load Switch • Battery Switch G 4 G D 8 D 7 D 6 D 5 D Bottom View P-Channel MOSFET Ordering Information: SiS407DN-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Symbol Limit Drain-Source Voltage VDS - 20 Gate-Source Voltage VGS ±8 TC = 70 °C TA = 25 °C ID Continuous Source-Drain Diode Current Avalanche Current Single Pulse Avalanche Energy IDM TC = 25 °C TA = 70 °C L = 0.1 mH IS TC = 70 °C TA = 25 °C Soldering Recommendations (Peak Temperature)b, c - 40 - 3.0a, b EAS 20 33 PD A - 25e - 20 21 mJ W 3.6a, b 2.3a, b TA = 70 °C Operating Junction and Storage Temperature Range - 15.4a, b IAS TC = 25 °C Maximum Power Dissipation - 25e - 12.3a, b TA = 70 °C Pulsed Drain Current V - 25e TC = 25 °C Continuous Drain Current (TJ = 150 °C)a Unit TJ, Tstg - 55 to 150 260 °C Notes: a. Surface mounted on 1" x 1" FR4 board. b. t = 10 s. c. See solder profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. e. Package limited. f. TC = 25 °C. Document Number: 65942 S10-2022-Rev. B, 06-Sep-10 www.vishay.com 1 New Product SiS407DN Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Symbol Maximum t 10 s RthJA 28 35 RthJC 2.9 3.8 Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) Typical Steady State a, b Unit °C/W Notes: a. Surface mounted on 1" x 1" FR4 board. b. Maximum under steady state conditions is 81 °C/W. SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = - 250 µA - 20 Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS/TJ VDS Temperature Coefficient VGS(th) Temperature Coefficient VGS(th)/TJ Gate-Source Threshold Voltage V - 13 ID = - 250 µA mV/°C 2.6 VGS(th) VDS = VGS, ID = - 250 µA -1 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 8 V ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = - 20 V, VGS = 0 V -1 VDS = - 20 V, VGS = 0 V, TJ = 55 °C - 10 On-State Drain Currenta ID(on) Drain-Source On-State Resistancea Forward Transconductancea RDS(on) gfs VDS - 5 V, VGS = - 10 V - 0.4 - 40 µA A VGS = - 4.5 V, ID = - 15.3 A 0.0082 VGS = - 2.5 V, ID = - 13.1 A 0.0115 0.0095 0.0138 VGS = - 1.8 V, ID = - 5 A 0.0156 0.0195 VDS = - 10 V, ID = - 15.3 A 60 S Dynamicb Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time Rise Time Turn-Off DelayTime Fall Time 2760 VDS = - 10 V, VGS = 0 V, f = 1 MHz VDS = - 10 V, VGS = - 8 V, ID = - 10 A VDS = - 10 V, VGS = - 4.5 V, ID = - 10 A td(off) pF 62.5 93.8 38 57 4 nC 10 f = 1 MHz td(on) tr 405 370 VDD = - 10 V, RL = 1 ID - 10 A, VGEN = - 4.5 V, Rg = 1 tf 0.9 4.4 8.8 23 35 28 42 92 138 38 57 ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C - 25 - 40 IS = - 10 A IF = - 10 A, dI/dt = 100 A/µs, TJ = 25 °C A - 0.82 - 1.2 V 56 80 ns 50 75 nC 25 31 ns Notes: a. Pulse test; pulse width 300 µs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 65942 S10-2022-Rev. B, 06-Sep-10 New Product SiS407DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 40 V GS = 10 V thru 2 V 8 I D - Drain Current (A) I D - Drain Current (A) 30 V GS = 1.8 V 20 6 4 T C = 25 °C 10 2 T C = 125 °C 0.5 1.0 1.5 2.0 2.5 3.0 0.4 1.2 V GS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 5000 0.024 4000 V GS = 1.8 V V GS = 2.5 V 0.012 Ciss 2000 Coss 1000 Crss 0 0 0 10 20 30 1.6 3000 V GS = 4.5 V 0.006 0 40 5 10 15 20 V DS - Drain-to-Source Voltage (V) ID - Drain Current (A) Capacitance On-Resistance vs. Drain Current 1.6 8 ID = 15.3 A ID = 15.3 A V GS = 4.5 V 6 V DS = 10 V V DS = 16 V V DS = 5 V 4 2 (Normalized) 1.4 R DS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 0.8 V DS - Drain-to-Source Voltage (V) 0.030 0.018 T C = - 55 °C 0 0.0 C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 0 0.0 V GS = 2.5 V 1.2 1.0 0.8 0 0 15 30 45 60 75 0.6 - 50 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) T J - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 65942 S10-2022-Rev. B, 06-Sep-10 150 www.vishay.com 3 New Product SiS407DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 0.03 R DS(on) - On-Resistance (Ω) I S - Source Current (A) ID = 15.3 A T J = 150 °C 10 T J = 25 °C 1 0.02 T J = 125 °C 0.01 T J = 25 °C 0 0.1 0.0 0.2 0.4 0.6 0.8 0 1.0 2 V SD - Source-to-Drain Voltage (V) 4 6 8 V GS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage - 0.2 50 - 0.3 40 ID = 250 μA Power (W) VGS(th) (V) - 0.4 - 0.5 30 20 - 0.6 10 - 0.7 - 0.8 - 50 - 25 0 25 50 75 100 125 0 0.01 150 0.1 1 10 100 T J - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 600 100 Limited by R DS(on)* 100 μA I D - Drain Current (A) 10 1 ms 10 ms 1 100 ms 1s 10 s 0.1 TA = 25 °C Single Pulse DC BVDSS Limited 0.01 0.1 1 10 100 V DS - Drain-to-Source Voltage (V) * V GS > minimum VGS at which R DS(on) is specified Safe Operating Area, Junction-to-Ambient www.vishay.com 4 Document Number: 65942 S10-2022-Rev. B, 06-Sep-10 New Product SiS407DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 60 I D - Drain Current (A) 45 30 Package Limited 15 0 0 25 50 75 100 125 150 T C - Case Temperature (°C) 40 2.0 30 1.5 Power (W) Power (W) Current Derating* 20 1.0 0.5 10 0.0 0 0 25 50 75 100 125 150 0 25 50 75 100 125 T C - Case Temperature (°C) TA - Ambient Temperature (°C) Power, Junction-to-Case Power, Junction-to-Ambient 150 * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 65942 S10-2022-Rev. B, 06-Sep-10 www.vishay.com 5 New Product SiS407DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = R thJA = 81 °C/W 3. T JM - TA = PDMZthJA(t) Single Pulse 0.01 10-4 4. Surface Mounted 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65942. www.vishay.com 6 Document Number: 65942 S10-2022-Rev. B, 06-Sep-10 Package Information www.vishay.com Vishay Siliconix D4 PowerPAK® 1212-8, (Single / Dual) W H E2 E4 L K M θ e 1 Z D5 D D2 2 2 D1 8 1 5 4 θ 4 b 3 L1 E3 A1 Backside view of single pad H 2 E1 E Detail Z L K E2 E4 D2 D3(2x) D4 c A H 1 D1 2 K1 Notes 1. Inch will govern 2 Dimensions exclusive of mold gate burrs 3. Dimensions exclusive of mold flash and cutting burrs D2 3 4 b θ D5 θ E3 Backside view of dual pad DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.97 1.04 1.12 0.038 0.041 0.044 A1 0.00 - 0.05 0.000 - 0.002 b 0.23 0.30 0.41 0.009 0.012 0.016 c 0.23 0.28 0.33 0.009 0.011 0.013 D 3.20 3.0 3.40 0.126 0.130 0.134 D1 2.95 3.05 3.15 0.116 0.120 0.124 D2 1.98 2.11 2.24 0.078 0.083 0.088 D3 0.48 - 0.89 0.019 - 0.035 D4 0.47 typ. D5 2.3 typ. 0.0185 typ 0.090 typ E 3.20 3.30 3.40 0.126 0.130 0.134 E1 2.95 3.05 3.15 0.116 0.120 0.124 E2 1.47 1.60 1.73 0.058 0.063 0.068 E3 1.75 1.85 1.98 0.069 0.073 0.078 E4 0.034 typ. 0.013 typ. e 0.65 BSC 0.026 BSC K 0.86 typ. K1 0.35 - 0.034 typ. - 0.014 - - H 0.30 0.41 0.51 0.012 0.016 0.020 L 0.30 0.43 0.56 0.012 0.017 0.022 L1 0.06 0.13 0.20 0.002 0.005 0.008 0° - 12° 0° - 12° W 0.15 0.25 0.36 0.006 0.010 0.014 M 0.125 typ. 0.005 typ. ECN: T16-0287-Rev. L, 06-Jun-16 DWG: 5882 Revison: 06-Jun-16 Document Number: 71656 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 AN822 Vishay Siliconix PowerPAK® 1212 Mounting and Thermal Considerations Johnson Zhao MOSFETs for switching applications are now available with die on resistances around 1 mΩ and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed. THE PowerPAK PACKAGE The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note “PowerPAK SO-8 Mounting and Thermal Considerations.”) The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option. Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints. PowerPAK 1212 SINGLE MOUNTING To take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance. Figure 1. PowerPAK 1212 Devices Document Number 71681 03-Mar-06 www.vishay.com 1 AN822 Vishay Siliconix PowerPAK 1212 DUAL To take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document. The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance. ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://www.vishay.com/ doc?73257. REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera- Ramp-Up Rate + 6 °C /Second Maximum Temperature at 155 ± 15 °C 120 Seconds Maximum Temperature Above 180 °C 70 - 180 Seconds Maximum Temperature 240 + 5/- 0 °C Time at Maximum Temperature 20 - 40 Seconds Ramp-Down Rate + 6 °C/Second Maximum Figure 2. Solder Reflow Temperature Profile 10 s (max) 210 - 220 °C 3 ° C/s (max) 4 ° C/s (max) 183 °C 140 - 170 °C 50 s (max) 3° C/s (max) 60 s (min) Pre-Heating Zone Reflow Zone Maximum peak temperature at 240 °C is allowed. Figure 3. Solder Reflow Temperatures and Time Durations www.vishay.com 2 Document Number 71681 03-Mar-06 AN822 Vishay Siliconix TABLE 1: EQIVALENT STEADY STATE PERFORMANCE Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8 Configuration Single Dual Single Dual Single Dual Single Dual Single Dual Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90 2.4 5.5 1.8 5.5 PowerPAK 1212 Standard SO-8 49.8 °C 2.4 °C/W Standard TSSOP-8 85 °C 20 °C/W TSOP-6 149 °C 52 °C/W 125 °C 40 °C/W PC Board at 45 °C Figure 4. Temperature of Devices on a PC Board THERMAL PERFORMANCE Introduction Spreading Copper A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rθjc, or the junction to- foot thermal resistance, Rθjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance. By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on rDS(ON) whereas a rise of over 40 °C will cause an increase in rDS(ON) as high as 20 %. Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed. Document Number 71681 03-Mar-06 www.vishay.com 3 AN822 Vishay Siliconix 130 105 Spreading Copper (sq. in.) Spreading Copper (sq. in.) 120 95 110 100 RthJ A (°C/W) RthJA (°C/W) 85 75 65 90 80 50 % 100 % 70 100 % 55 0% 60 50 % 0% 50 45 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance CONCLUSIONS As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8. Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package. The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages. www.vishay.com 4 Document Number 71681 03-Mar-06 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single 0.152 (3.860) 0.039 0.068 (0.990) (1.725) 0.010 (0.255) (2.390) 0.094 0.088 (2.235) 0.016 (0.405) 0.026 (0.660) 0.025 0.030 (0.635) (0.760) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72597 Revision: 21-Jan-08 www.vishay.com 7 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000