DATASHEET

DATASHEET
Quad Lane Extender
ISL36411
Features
The ISL36411 is a quad receive-side equalizer with extended
functionality for advanced protocols operating with line rates
up to 11.1Gbps. It integrates a driver/limiting amplifier with a
programmable equalizer to compensate for the frequency
dependent attenuation of PCB traces and twin-axial cables.
The ISL36411 is capable of extending signal reach up to 10m
on 28AWG cable. Supported protocols include 4k/8k video
capable DisplayPort v1.3 (HBR1/2/3), USB 3.1 Gen 2 at
10Gbps. InfiniBand (QDR), 40G Ethernet (40GBASECR4/SR4),
and 10G SFP+ specification (SFF-8431).
• Supports four channels with data rates up to 11.1Gbps
The small form factor, highly-integrated quad design is ideal
for high-density data transmission applications including
active copper cable assemblies. The four equalizing filters
within the ISL36411 can each be set to provide optimal signal
fidelity for a given media and length. The compensation level
for the filters is set by two external control pins.
• Line silence preservation and individual lane LOS support
Operating on a single 1.2V power supply, the ISL36411
enables per channel throughputs of up to 11.1Gbps while
passing USB3.x LFPS signals as low as 100kHz. High data
rates are achieved by using Current Mode Logic (CML) inputs
and outputs and is packaged in a 4mmx7mm 46 Ld QFN.
Individual lane LOS support is included for module
applications.
Related Literature
• AN1573, “ISL36411 Evaluation Board User Guide”
• Low power (~110mW per channel)
• Low latency (<500ps)
• Four equalizers in 4mmx7mm QFN package for straight
route-through architecture and simplified routing
• Equalizer boost is pin selectable
• Pin selectable equalizer boosts
• Supports 64b/66b encoded data - long run lengths
• 1.2V power supply
• LOS support
Applications
• DisplayPort v1.3 active copper cable modules
• QSFP active copper cable modules
• InfiniBand QDR
• 40G ethernet (40GBase-CR4/SR4)
• 100G ethernet (100GBase-CR10/SR10)
• High-speed Printed Circuit Board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach 3x
• Improved BER
ACTIVE COPPER CABLE ASSEMBLY
1.2V
HOST CHANNEL
ADAPTER
10nF
1.2V
100pF
VDD
10nF
0.1˩)
100pF
IN1[P,N]
OUT1[P,N]
IN2[P,N]
OUT2[P,N]
0.1˩)
0.1˩)
0.1˩)
Tx4[P,N]
0.1˩)
IN4[P,N]
OUT3[P,N]
100pF
FABRIC SWITCH
1.2V
OUT4[P,N]
DT
OUT2[P,N]
Rx1[P,N]
Rx2[P,N]
1.2V
ืP$:*
IN3[P,N]
IN4[P,N]
OUT3[P,N]
OUT4[P,N]
0.1˩)
0.1˩)
Rx3[P,N]
Rx4[P,N]
DT
10nF
IN3[P,N]
IN2[P,N]
0.1˩)
ISL36411
ISL35411
Tx3[P,N]
0.1˩)
10nF
HOST ASIC
0.1˩)
VDD
0.1˩)
HOST ASIC
Tx2[P,N]
DE
OUT1[P,N]
100pF
0.1˩)
Tx1[P,N]
TDSBL
8-PAIR DIFFERENTIAL 100˖
7:,1$;,$/&$%/(
CP LOSB
IN1[P,N]
CONNECTOR PADDLE CARD
CONNECTOR PADDLE CARD
FIGURE 1. TYPICAL APPLICATION CIRCUIT
June 21, 2016
FN6965.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2016. All Rights Reserved
Intersil (and design) and Q:ACTIVE are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL36411
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
ISL36411DRZ-TS
ISL36411DRZ
0 to +85
100 (Sample Reel)
46 Ld QFN
L46.4x7
ISL36411DRZ-T7
ISL36411DRZ
0 to +85
1k
46 Ld QFN
L46.4x7
ISL36411DRZ-EVALZ
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL36411. For more information on MSL, please see tech brief TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
DATA
RATE
(Gb/s)
MAXIMUM
CABLE
LENGTH DIFFERENTIAL
POWER
DEO/P SWING
NUMBER OF CONSUMPTION (24AWG)
EMPHASIS EQUALIZATION
(mVP-P)
(m)
(mW)
Tx OR Rx
(dB)
(dB)
DIFFERENCES
BETWEEN QLX
PARTS
TARGET
MARKET
ISL36411
11
4x Rx
440
20
650
N/A
30
N/A
DP1.3, 40GbE,
QSFP+
ISL35411
11
4x Tx
340
20
600
4
N/A
N/A
DP1.3, 40GbE,
QSFP+
QLX4600-SL30
6.25
4x Rx
312
30
600
N/A
30
4 pins for Loss of DP1.2, SAS-6Gb,
Signal (LOS) PCIe 2.0
QLX4600-S30
6.25
4x Rx
312
30
600
N/A
30
DP1.2, SAS-6Gb,
4 pins for
PCIe 2.0
Impedance
Selection
(= Power Down)
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FN6965.2
June 21, 2016
ISL36411
Pin Configuration
VDD
GND
NC
CP1A
CP1B
DT1
NC
GND
ISL36411
(46 LD QFN)
TOP VIEW
46 45 44 43 42 41 40 39
VDD 1
38 OUT1[P]
IN1[P] 2
37 OUT1[N]
IN1[N] 3
36 VDD
LOSB1 4
35 VDD
VDD 5
34 OUT2[P]
IN2[P] 6
33 OUT2[N]
IN2[N] 7
32 VDD
EXPOSED PAD
(GND)
LOSB2 8
VDD 9
31 VDD
30 OUT3[P]
IN3[P] 10
29 OUT3[N]
IN3[N] 11
28 VDD
LOSB3 12
27 VDD
VDD 13
26 OUT4[P]
IN4[P] 14
25 OUT4[N]
IN4[N] 15
24 VDD
GND
NC
NC
CP2B
CP2A
DT2
GND
LOSB4
16 17 18 19 20 21 22 23
Pin Descriptions
PIN NAME
VDD
PIN NUMBER
DESCRIPTION
1, 5, 9, 13, 24, 27, Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground is
28, 31, 32, 35, 36, recommended for each of these pins for broad high frequency noise suppression.
39
IN1[P, N]
2, 3
LOSB1
4
IN2[P, N]
6, 7
LOSB2
8
IN3[P, N]
10, 11
LOSB3
12
IN4[P, N]
14, 15
LOSB4
16
GND
17, 23, 40, 46
DT2
18
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Equalizer 1 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
LOS BAR indicator 1. Low output when IN1 signal is below DT threshold.
Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
LOS BAR indicator 2. Low output when IN2 signal is below DT threshold.
Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
LOS BAR indicator 3. Low output when IN3 signal is below DT threshold.
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
LOS BAR indicator 4. Low output when IN4 signal is below DT threshold.
These pins should be grounded.
Detection Threshold for equalizers 3 and 4. Reference DC voltage threshold for input signal power detection. Data
output OUT3 and OUT4 are muted when the power of IN3 and IN4, respectively, fall below the threshold. Tie to
ground to disable electrical idle preservation and always enable the limiting amplifier.
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FN6965.2
June 21, 2016
ISL36411
Pin Descriptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
CP2[A,B]
19, 20
Control pins for setting equalizers 3 and 4. CMOS logic inputs. Pins are read as a 2-digit number to set the boost
level. A is the MSB and B is the LSB. Pins are internally pulled down through a 25kΩ resistor.
NC
21, 22, 41, 45
OUT4[N, P]
25, 26
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
OUT3[N, P]
29, 30
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
OUT2[N, P]
33, 34
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
OUT1[N, P]
37, 38
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency
response is recommended.
CP1[B, A]
42, 43
Control pins for setting equalizers 1 and 2. CMOS logic inputs. Pins are read as a 2-digit number to set the boost
level. A is the MSB and B is the LSB. Pins are internally pulled down through a 25kΩ resistor.
DT1
44
Detection Threshold for equalizers 1 and 2. Reference DC voltage threshold for input signal power detection. Data
output OUT1 and OUT2 are muted when the power of IN1 and IN2, respectively, fall below the threshold. Tie to
ground to disable electrical idle preservation and always enable the limiting amplifier.
Exposed Pad
-
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not connected: do not make any connections to these pins.
Exposed ground pad. For proper electrical and thermal performance, this pad should be connected to the PCB
ground plane.
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FN6965.2
June 21, 2016
ISL36411
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1.5V
Voltage at All Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1.5V
ESD Ratings
Human Body Model
High-Speed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5kV
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
46 Ld QFN Package (Notes 4, 5) . . . . . . . .
33
2.8
Operating Ambient Temperature Range . . . . . . . . . . . . . . . . .0°C to +85°C
Storage Ambient Temperature Range. . . . . . . . . . . . . . . . -55°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Operating Conditions
PARAMETER
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
VDD
1.1
1.2
1.3
V
TA
0
25
85
°C
11.1
Gbps
MAX
(Note 6)
UNIT
SYMBOL
Supply Voltage
Operating Ambient Temperature
Bit Rate
TEST CONDITION
NRZ data applied to any channel
2.5
Control Pin CharacteristicsVDD = 1.2V, TA = +25°C and VIN = 600mVP-P, unless otherwise noted.
PARAMETER
SYMBOL
TEST CONDITION
MIN
(Note 6)
TYP
Output LOW Logic Level
VOL
LOS[k]
0
250
mV
Output HIGH Logic Level
VOH
LOS[k]
750
VDD
mV
200
µA
Input Current
Current draw on digital pin, i.e., CP[k][A,B]
100
Electrical Specifications VDD = 1.2V, TA = +25°C and VIN = 600mVP-P, unless otherwise noted.
PARAMETERS
SYMBOL
Supply Current
IDD
Cable Input Amplitude Range
VIN
TEST CONDITION
MIN
(Note 6)
600
DC Differential Input
Resistance
Measured on input channel IN[k]
80
DC Single-Ended Input
Resistance
Measured on input channel IN[k]P or IN[k]N,
with respect to VDD
40
SDD11
Input Return Loss Limit
(Common-Mode)
SCC11
Input Return Loss Limit
(Common-Mode to Differential
Conversion)
SDC11
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5
MAX
(Note 6)
368
Measured differentially at data source before
encountering channel loss; Up to 10m 28AWG
standard twin-axial cable (approx. -27dB at
5GHz)
Input Return Loss Limit
(Differential)
TYP
UNIT
NOTES
mA
1600
mVP-P
100
120
Ω
50
60
Ω
7
100MHz to 4.1GHz
Note 8
dB
8
4.1GHz to 11.1GHz
Note 9
dB
9
100MHz to 2.5GHz
Note 10
dB
10
2.5GHz to 11.1GHz
-3
dB
15
100MHz to 11.1GHz
-10
dB
15
FN6965.2
June 21, 2016
ISL36411
Electrical Specifications VDD = 1.2V, TA = +25°C and VIN = 600mVP-P, unless otherwise noted. (Continued)
PARAMETERS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
Measured differentially at OUT[k]P and
OUT[k]N with 50Ω load on both output pins
450
600
850
mVP-P
Measured on OUT[k]
80
105
120
Ω
SYMBOL
Output Amplitude Range
VOUT
Differential Output Impedance
Output Return Loss Limit
(Differential)
SDD22
Output Return Loss Limit
(Common-Mode)
SCC22
Output Return Loss Limit
(Common-Mode to Differential
Conversion)
SDC22
Output Residual Jitter
Output Transition Time
tr, tf
TEST CONDITION
NOTES
100MHz to 4.1GHz
Note 8
dB
8
4.1MHz to 11.1GHz
Note 9
dB
9
100MHz to 2.5GHz
Note 10
dB
10
2.5MHz to 11.1GHz
-3
dB
15
100MHz to 11.1GHz
-10
dB
15
10Gbps; Up to 10m 28AWG std twin-axial cable
(~ -27dB at 5GHz); 1200mVP-P ≤ VIN ≤
1600mVP-P
0.35
UI
7, 11, 12
32
ps
13
50
ps
15
20% to 80%
Lane-to-Lane Skew
Propagation Delay
From IN[k] to OUT[k]
500
ps
15
LOS Assert Time
Time to assert loss-of-signal indicator when
transitioning from active data mode to line
silence mode
50
µs
14
LOS Deassert Time
Time to assert loss-of-signal indicator when
transitioning from line silence mode to active
data mode
50
µs
14
Data-to-Line Silence Response
Time
K28.5 data pattern at 10Gbps
100
µs
14
Data-to-Line Silence Response
Time
K28.5 data pattern at 10Gbps
100
µs
14
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. After channel loss, differential amplitudes at ISL36411 inputs must meet the input voltage range specified in “Absolute Maximum Ratings” on
page 5.
8. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*(f), with f in GHz. Established by characterization and not production tested.
9. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3+13Log10(f/5.5), with f in GHz. Established by characterization and not
production tested.
10. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not production tested.
11. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured
at the input to the channel). Total jitter (TJ) is DJP-P + 14.1 x RJRMS.
12. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only.
13. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
14. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude is 20mVP-P
(differential) or less. Established by characterization and not production tested.
15. Limits established by characterization and are not production tested.
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FN6965.2
June 21, 2016
ISL36411
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched into the twin-axial cable using an
SMA adapter card. The chip evaluation board is connected to the output of the cable through another adapter card. The ISL36411 output signal is then
visualized on a scope to determine signal integrity parameters such as jitter.
PATTERN
GENERATOR
SMA
ADAPTER
CARD
100TWIN-AXIAL
CABLE
SMA
ADAPTER
CARD
ISL36411 EVAL
BOARD
OSCILLOSCOPE
FIGURE 2. DEVICE CHARACTERIZATION SET UP
FIGURE 3. ISL36411 10.3125Gb/s OUTPUT FOR A 10M 28AWG CABLE
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FN6965.2
June 21, 2016
ISL36411
CPA CPB
LIMITING
AMPLIFIER
IN[P]
OUTPUT
DRIVER
OUT[P]
ADJUSTABLE
EQUALIZER
IN[N]
OUT[N]
SIGNAL
DETECTOR
DT
LOSB
FIGURE 4. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE ISL36411
Operation
The ISL36411 is an advanced quad lane-extender for high-speed
interconnects. A functional diagram of one of the four channels
in the ISL36411 is shown in Figure 4. In addition to a robust
equalization filter to compensate for channel loss and restore
signal fidelity, the ISL36411 contains unique integrated features
to preserve special signaling protocols typically broken by other
equalizers. The signal detect function is used to mute the
channel output when the equalized signal falls below the level
determined by the Detection Threshold (DT) pin voltage. This
function is intended to preserve periods of line silence
(“quiescent state” in InfiniBand contexts). Furthermore, the
output of the signal detect/DT comparator is used as a Loss Of
Signal (LOS) indicator to indicate the absence of a received
signal.
As illustrated in Figure 4, the core of each high-speed signal path
in the ISL36411 is a sophisticated equalizer followed by a
limiting amplifier. The equalizer compensates for skin loss,
dielectric loss and impedance discontinuities in the transmission
channel. Each equalizer is followed by a limiting amplification
stage that provides a clean output signal with full amplitude
swing and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
Adjustable Equalization Boost
Control Pin Boost Setting
The connectivity of the CP pins is used to determine the boost
level of each pair of channels. CP1 controls the boost of channels
1 and 2, CP2 controls the boosts of channels 3 and 4. Table 2
defines the mapping from the 2-bit CP word to the 8 possible
boost levels.
TABLE 2. MAPPING BETWEEN BOOST LEVEL AND CP-PIN
CONNECTIVITY
CPA
CPB
BOOST LEVEL
Float
Float
0
Float
GND
1
GND
VDD
2
Float
VDD
3
VDD
Float
4
GND
Float
5
GND
GND
6
VDD
GND
7
VDD
VDD
8
Each channel in the ISL36411 features a settable (in pairs)
equalizer for custom signal restoration. The flexibility of this
adjustable compensation architecture enables signal fidelity to
be optimized on a channel-by-channel basis, providing support
for a wide variety of channel characteristics and data rates
ranging from 2.5Gbps to 11.1Gbps. Because the boost level is
externally set rather than internally adapted, the ISL36411
provides reliable communication from the very first bit
transmitted. There is no time needed for adaptation and control
loop convergence. Furthermore, there are no pathological data
patterns that will cause the ISL36411 to move to an incorrect
boost level.
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FN6965.2
June 21, 2016
ISL36411
ISL36411 CML Input and Output Buffers
LOS Bar Indicator
The input and output buffers for the high-speed data channels in
the ISL36411 are implemented using CML (shown in Figures 5
and 6).
Pins LOSB[k] are used to output the state of the muting circuitry
to serve as a loss of signal indicator for channel k. This signal is
directly derived from the muting signal off the DT-threshold
signal detector output. The LOS signal goes LOW when the power
signal is below the DT threshold and HIGH when the power goes
above the DT threshold. This feature is meant to be used in
optical systems (e.g. QSFP) where there are no quiescent or
electrical-idle states. In these cases, the DT threshold is used to
determine the sensitivity of the LOS indicator.
VDD
IN[P]
50
Detection Thereshold (DT) Pin Functionality
1ST Filter
STAGE
50
IN[N]
FIGURE 5. CML INPUT EQUIVALENT CIRCUIT
VDD
The ISL36411 is capable of maintaining periods of line silence by
monitoring the channel for Loss Of Signal (LOS) conditions and
subsequently muting the output driver when such a condition is
detected. A reference voltage applied to the Detection Threshold
(DT) pins is used to set the LOS threshold of the internal signal
detection circuitry (one pin for a pair of channels). The DT voltage
is set with an external pull-up resistor, RDT. For typical
applications, a 15kΩ resistor is recommended for channels with
loss greater than 12dB at 5GHz and a 0.9kΩ resistor is
recommended for lower loss channels. Other values of the
resistor may also be applicable; therefore DT settings should be
verified on an application-specific basis.
PCB Layout Considerations
50Ω
50Ω
OUT[P]
OUT[N]
Because of the high speed of the ISL36411 signals, careful PCB
layout is critical to maximize performance. The following
guidelines should be adhered to as closely as possible:
• All high speed differential pair traces should have a
characteristic impedance of 50Ω with respect to ground plane
and 100Ω with respect to each other.
• Avoid using vias for high speed traces as this will create
discontinuity in the traces’ characteristic impedance.
• Input and output traces need to have DC blocking capacitors
(100nF). Capacitors should be placed as close to the chip as
possible.
FIGURE 6. CML OUTPUT EQUIVALENT CIRCUIT
LINE SILENCE/QUIESCENT MODE
Line silence is commonly broken by the limiting amplification in
other equalizers. This disruption can be detrimental in many
systems that rely on line silence as part of the protocol. The
ISL36411 contains special lane management capabilities to
detect and preserve periods of line silence while still providing
the fidelity-enhancing benefits of limiting amplification during
active data transmission. Line silence is detected by measuring
the amplitude of the equalized signal and comparing that to a
threshold set by the voltage at the DT pin. When the amplitude
falls below the threshold, the output driver stages are muted and
held at their nominal common-mode voltage.
NOTE: The output common-mode voltage remains constant during both
active data transmission and output muting modes.
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9
• For each differential pair, the positive trace and the negative
trace need to be of the same length in order to avoid intra-pair
skew. A Serpentine technique may be used to match trace
lengths.
• Maintain a constant solid ground plane underneath the
high-speed differential traces.
• Each VDD pin should be connected to 1.2V and also bypassed
to ground through a 10nF and a 100pF capacitor in parallel.
Minimize the trace length and avoid vias between the VDD pin
and the bypass capacitors in order to maximize the power
supply noise rejection.
• If 4 channels of the device are set to the same boost, then the
quantity of CP resistors can be reduced by tying both CP pins
together.
FN6965.2
June 21, 2016
ISL36411
Application Information
1.2V
IN3[P]
IN3[N]
LOSB3
1.2V
IN4[P]
1.2V
GND
NC
NC
5
34
6
33
ISL36411
1.2V
1.2V
OUT2[P]
OUT2[N]
1.2V
7
32
8
31
9
30
10
29
11
28
12
27
13
26
OUT4[P]
14
25
OUT4[N]
15
24
1.2V
OUT3[P]
OUT3[N]
LOSB4
16
IN4[N]
35
OUT1[N]
1.2V
1.2V
1.2V
GND
LOSB2
4
NC
IN2[N]
36
NC
IN2[P]
3
OUT1[P]
19
1.2V
37
18
LOSB1
38
2
17
IN1[N]
A
1
DT2
IN1[P]
GND
1.2V
DT1
GND
EQ BOOST
CONTROL
FOR CHANNELS
1 AND 2
1.2V
10nF
100pF*
EQ BOOST
CONTROL
FOR CHANNELS
3 AND 4
ISL36411
LANE EXTENDER
BYPASS CIRCUIT FOR EACH VDD PIN
00pF CAPACITOR SHOULD BE POSITIONED CLOSEST TO THE PIN)
A) DC BLOCKING CAPACITORS = X7R or COG
0.1˩)>6GHz BANDWIDTH)
NOTES:
16. See “Control Pin Boost Setting” on page 8 for information on how to connect the CP pins.
17. See “Detection Thereshold (DT) Pin Functionality” on page 9 for details on DT pin operation.
FIGURE 7. TYPICAL APPLICATION REFERENCE SCHEMATIC
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL36411
About Q:ACTIVE™ Technology
Intersil has long realized that to enable the complex server
clusters of next generation data centers, it is critical to manage
the signal integrity issues of electrical interconnects. To address
this, Intersil has developed its groundbreaking Q:ACTIVE™
product line. By integrating its analog ICs inside cabling
interconnects, Intersil is able to achieve unsurpassed
improvements in reach, power consumption, latency and cable
gauge size as well as increased airflow in tomorrow’s data
centers. This new technology transforms passive cabling into
intelligent “roadways” that yield lower operating expenses and
capital expenditures for the expanding data center.
Intersil Lane Extenders allow greater reach over existing cabling
while reducing the need for thicker cables. This significantly
reduces cable weight and clutter, increases airflow and improves
power consumption.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
June 21, 2016
FN6965.2
Updated page 1 description of part.
Added applications bullet “DisplayPort v1.3 active copper cable modules”.
Removed “High-speed active cable assemblies” application bullet.
Added Related Literature section on page 1.
Added Table 1 on page 2.
Added Note 6 on page 6 and referenced in specification tables.
Replaced Products section with the About Intersil section.
Updated POD L46.4x7 to the latest revision changes are as follows:
-3/15/13 Side view, changed pkg thickness from 0.70+/-0.05 to 0.75+/-0.05 Detail x, changed from 0.152
REF to 0.203 REF.
March 16, 2010
FN6965.1
page 5
Control pin characteristics:
VOL: delete typical “0”
Input current: max 200, typ 100
page 6
Output res jitter: 0.35
In Entries from Lane-to-Lane Skew all the way down, all the numbers should move to typ column
Added High-Speed pins to ESD Ratings as follows to Abs Max Ratings:
ESD Ratings
Human Body Model
High-Speed Pins 1.5kV
All Other Pins 2kV
Removed board footprint from page 10 due to information covered in outline drawing.
February 8, 2010
FN6965.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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ISL36411
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN)
Rev 1, 3/13
2.80
4.00
42X 0.40
A
B
6
PIN 1
INDEX AREA
38
7.00
(4X)
46
39
6
PIN 1
INDEX AREA
1
5.50 ±0.1
Exp. DAP
5.60
15
24
0.05
46X 0.20 4
0.10 M C A B
SIDE VIEW
TOP VIEW
16
23
2.50 ±0.1
Exp. DAP
46X 0.40
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.75 ±0.05
C
SEATING PLANE
0.05 C
SIDE VIEW
C
0.203 REF
5
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
( 6.80 )
( 42X 0.40)
( 5.50 )
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(46X 0.20)
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
( 46 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
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