Si5440DC www.vishay.com Vishay Siliconix N-Channel 30 V (D-S) MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) ID (A) a 0.019 at VGS = 10 V 6 0.024 at VGS = 4.5 V 6 VDS (V) 30 • TrenchFET® power MOSFET Qg (TYP.) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 9 nC APPLICATIONS 1206-8 ChipFET® Single D D 8 D 7 S 6 5 1. 9 m m 1 3.0 mm Top View • Load switches - Notebook PC D 1 2 D 3 D 4 D G G Bottom View Marking Code: AI N-Channel MOSFET Ordering Information: Si5440DC-T1-GE3 (lead (Pb)-free and halogen-free) S ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 30 Gate-Source Voltage VGS ± 20 TC = 70 °C 6a ID TA = 25 °C 6 a, b, c 6 a, b, c TA = 70 °C Pulsed Drain Current IDM TC = 25 °C Continuous Source-Drain Diode Current 5.2 2.1 b, c TC = 25 °C 6.3 TC = 70 °C 4 PD TA = 25 °C W 2.5 b, c 1.6 b, c TA = 70 °C Operating Junction and Storage Temperature Range A 30 IS TA = 25 °C Maximum Power Dissipation V 6a TC = 25 °C Continuous Drain Current (TJ = 150 °C) UNIT TJ, Tstg -55 to +150 Soldering Recommendations (Peak Temperature) e, f °C 260 THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient a, c, d Maximum Junction-to-Foot (Drain) SYMBOL TYPICAL MAXIMUM t≤5s RthJA 40 50 Steady State RthJF 15 20 UNIT °C/W Notes a. Package limited, TC = 25 °C. b. Surface mounted on 1" x 1" FR4 board. c. t = 10 s d. Maximum under steady state conditions is 95 °C/W. e. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. S15-2143-Rev. B, 07-Sep-15 Document Number: 69056 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5440DC www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 30 - - V - 31 - - -5.1 - Static Drain-Source Breakdown Voltage VDS Temperature Coefficient ΔVDS /TJ ID = 250 μA mV/°C VGS(th) Temperature Coefficient ΔVGS(th)/TJ Gate-Source Threshold Voltage VGS(th) VDS = VGS , ID = 250 μA 1.2 - 2.5 V IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA VDS = 30 V, VGS = 0 V - - 1 VDS = 30 V, VGS = 0 V, TJ = 55 °C - - 5 Gate-Source Leakage Zero Gate Voltage Drain Current IDSS On-State Drain Current a ID(on) Drain-Source On-State Resistance a Forward Transconductance a RDS(on) gfs VDS ≥ 5 V, VGS = 10 V 20 - - VGS = 10 V, ID = 9.1 A - 0.016 0.019 VGS = 4.5 V, ID = 8.1 A - 0.019 0.024 VDS = 15 V, ID = 9.1 A - 30 - - 1200 - μA A Ω S Dynamic b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time VDS = 10 V, VGS = 0 V, f = 1 MHz VDS = 10 V, VGS = 10 V, ID = 9.1 A VDS = 10 V, VGS = 4.5 V, ID = 9.1 A f = 1 MHz td(on) VDD = 15 V, RL = 2.1 Ω ID ≅ 7.3 A, VGEN = 4.5 V, Rg = 1 Ω tr - 180 - - 80 - - 19 29 - 9 14 - 3.5 - - 2.3 - - 3 - - 20 30 - 12 20 - 20 30 tf - 10 15 td(on) - 10 15 td(off) VDD = 15 V, RL = 2.1 Ω ID ≅ 7.3 A, VGEN = 10 V, Rg = 1 Ω tr td(off) tf pF nC Ω ns - 10 15 - 20 30 - 10 15 - - 5.2 - - 30 - 0.8 1.2 V - 20 40 ns - 10 20 nC - 11 - - 9 - Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C IS = 7.3 A, VGS = 0 V IF = 7.3 A, dI/dt = 100 A/μs, TJ = 25 °C A ns Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S15-2143-Rev. B, 07-Sep-15 Document Number: 69056 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5440DC www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 30 10 VGS = 10 V thru 4 V TC = - 55 °C 8 I D - Drain Current (A) I D - Drain Current (A) 25 20 15 VGS = 3 V 10 6 4 TC = 25 °C 2 5 TC = 125 °C VGS = 2 V 0 0.0 0 0.5 1.0 1.5 2.0 2.5 VDS - Drain-to-Source Voltage (V) 0.0 3.0 0.5 Output Characteristics 1500 Ciss 0.022 C - Capacitance (pF) 1200 0.020 VGS = 4.5 V 0.018 VGS = 10 V 0.016 900 600 Coss 300 0.014 0.012 Crss 0 0 5 10 15 20 ID - Drain Current (A) 25 0 30 5 10 15 20 25 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current 30 Capacitance 1.6 10 R DS(on) - On-Resistance (Normalized) ID = 9.1 A VGS - Gate-to-Source Voltage (V) 3.0 Transfer Characteristics 0.024 R DS(on) - On-Resistance (Ω) 1.0 1.5 2.0 2.5 VGS - Gate-to-Source Voltage (V) 8 VDS = 15 V 6 VDS = 24 V 4 2 0 0 4 8 12 16 Qg - Total Gate Charge (nC) Gate Charge S15-2143-Rev. B, 07-Sep-15 20 ID = 9.1 A 1.4 VGS = 10 V, 4.5 V 1.2 1.0 0.8 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature Document Number: 69056 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5440DC www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.05 100 TJ = 150 °C R DS(on) - On-Resistance (Ω) I S - Source Current (A) ID = 9.1 A TJ = 25 °C 10 1 0.0 0.04 0.03 TJ = 125 °C 0.02 TJ = 25 °C 0.01 0 0.2 0.4 0.6 0.8 1.0 VSD - Source-to-Drain Voltage (V) 0 1.2 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 2.2 50 2.0 40 ID = 250 µA Power (W) VGS(th) (V) 1.8 1.6 30 20 1.4 10 1.2 1.0 - 50 - 25 0 25 50 75 100 TJ - Temperature (°C) 125 0 10 -3 150 10 -2 Threshold Voltage 10 -1 1 Time (s) 10 100 600 Single Pulse Power 100 Limited by RDS(on)* 100 µs I D - Drain Current (A) 10 1 ms 1 10 ms 0.1 TA = 25 °C Single Pulse 0.01 0.01 BVDSS Limited 100 ms 1s 10 s DC 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient S15-2143-Rev. B, 07-Sep-15 Document Number: 69056 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5440DC www.vishay.com Vishay Siliconix 16 8 12 6 Power (W) I D - Drain Current (A) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 8 Package Limited 4 2 4 0 0 0 25 50 75 100 TC - Case Temperature (°C) Current Derating a 125 150 25 50 75 100 125 150 TC - Case Temperature (°C) Power Derating Note a. The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S15-2143-Rev. B, 07-Sep-15 Document Number: 69056 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5440DC www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 95 °C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69056. S15-2143-Rev. B, 07-Sep-15 Document Number: 69056 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix 1206-8 ChipFETR 4 L D 8 7 6 5 4 1 S 2 e 3 E1 5 6 7 8 4 3 2 1 E 4 b x c Backside View 2X 0.10/0.13 R C1 A DETAIL X NOTES: 1. All dimensions are in millimeaters. 2. Mold gate burrs shall not exceed 0.13 mm per side. 3. Leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 4. Dimensions exclusive of mold gate burrs. 5. No mold flash allowed on the top and bottom lead surface. MILLIMETERS Dim A b c c1 D E E1 e L S INCHES Min Nom Max Min Nom Max 1.00 − 1.10 0.039 − 0.043 0.25 0.30 0.35 0.010 0.012 0.014 0.1 0.15 0.20 0.004 0.006 0.008 0 − 0.038 0 − 0.0015 2.95 3.05 3.10 0.116 0.120 0.122 1.825 1.90 1.975 0.072 0.075 0.078 1.55 1.65 1.70 0.061 0.065 0.067 0.65 BSC 0.28 − 0.0256 BSC 0.42 0.011 − 0.55 BSC 0.022 BSC 5_Nom 5_Nom 0.017 ECN: C-03528—Rev. F, 19-Jan-04 DWG: 5547 Document Number: 71151 15-Jan-04 www.vishay.com 1 AN811 Vishay Siliconix Single-Channel 1206-8 ChipFETr Power MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION New Vishay Siliconix ChipFETs in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206-8 ChipFET has the same footprint as the body of the LITTLE FOOTR TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger SO-8. 80 mil 68 mil This technical note discusses the single-channel ChipFET 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. 28 mil 26 mil PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the single-channel 1206-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. Single 1206-8 ChipFET 1 D D D D The pad pattern with copper spreading shown in Figure 2 improves the thermal area of the drain connections (pins 1,2,3,6.7,8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Vishay Siliconix Evaluation Board described in the next section (Figure 3). D D G S Bottom View FIGURE 1. For package dimensions see the 1206-8 ChipFET package outline drawing (http://www.vishay.com/doc?71151). BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. Document Number: 71126 12-Dec-03 FIGURE 2. Footprint With Copper Spreading THE VISHAY SILICONIX EVALUATION BOARD FOR THE SINGLE 1206-8 The ChipFET 1206-08 evaluation board measures 0.6 in by 0.5 in. Its copper pad pattern consists of an increased pad area around the six drain leads on the top-side—approximately 0.0482 sq. in. 31.1 sq. mm—and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. The outer package outline is for the 8-pin DIP, which will allow test sockets to be used to assist in testing. The thermal performance of the 1206-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board. www.vishay.com 1 AN811 Vishay Siliconix Front of Board Back of Board ChipFETr vishay.com FIGURE 3. Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 15_C/W typical, 20_C/W maximum for the single device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the SO-8 package RQjf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The typical RQja for the single-channel 1206-8 ChipFET is 80_C/W steady state, compared with 68_C/W for the SO-8. Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W for the SO-8. The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 45_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33_C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square pcb. 160 Thermal Resistance (C/W) THERMAL PERFORMANCE 120 Single EVB Min. Footprint 80 1” Square PCB 40 Testing To aid comparison further, Figure 4 illustrates ChipFET 1206-8 thermal performance on two different board sizes and three different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of RQja for the single 1206-8 ChipFET are : 1) Minimum recommended pad pattern (see Figure 2) on the evaluation board size of 0.5 in x 0.6 in. 156_C/W 2) The evaluation board with the pad pattern described on Figure 3. 111_C/W 3) Industry standard 1” square pcb with maximum copper both sides. 78_C/W www.vishay.com 2 0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000 Time (Secs) FIGURE 4. Single 1206−8 ChipFET SUMMARY The thermal results for the single-channel 1206-8 ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size. ASSOCIATED DOCUMENT 1206-8 ChipFET Dual Thermal performance, AN812 (http://www.vishay.com/doc?71127). Document Number: 71126 12-Dec-03 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET® 0.093 0.026 0.016 0.010 (0.650) (0.406) (0.244) 0.036 (0.914) 0.022 (0.559) (2.032) 0.080 (2.357) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 2 Document Number: 72593 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000