ISL9222AEVAL1Z Evaluation Board Application Manual ® Application Note December 4, 2008 AN1445.0 Introduction What is Needed The ISL9222AEVAL1Z is an evaluation tool for the ISL9222A single-cell Li-ion battery charger. The evaluation tool provides a complete evaluation platform addressing all data sheet specifications and functionality. The jumpers on the board facilitate the programming of the charge current, different charging conditions, and can be used to make other necessary connections, such as current measurement. The following instruments will be needed to perform testing: The ISL9222A adds an additional feature in providing a limited amount of current to system architecture while protecting the system from destructively high voltage. • Multimeters • Power supplies: - PS1: DC 30V/2A - PS2: DC 10V/2A - PS3: DC 10V/2A • DC Electronic load: 20V/2A • Oscilloscope • Cables and wires ISL9222A (8 LD TDFN) TOP VIEW Quick Setup Guide (Refer to Figure 1) Note: Do Not Apply Power Until Step 6 VIN 1 8 BAT 1. Connect a 5V supply PS1 to VDC input (J1, upper +) with the current limit set at 1.3A PPR 2 7 IREF JIGON 3 6 JIGIN 2. Connect a 3.5V supply PS2 to BAT output (J2, upper +) with the current limit set at 1.3A EN 4 5 GND 3. Connect a current meter to JP6 as shown in Figure 1 4. Connect the DC electronic load of 1.2A to VBAT (J2, upper +) Ordering Information PART NUMBER ISL9222AEVAL1Z 5. Insert a jumper shunt on JP3; all other jumper shunts are not installed DESCRIPTION 6. Turn on Power Supplies and DC electronic load, adjust the power supply PS2 such that the voltmeter V2 reads 3.5V Evaluation Board for ISL9222A Features • A Complete Evaluation Platform for the ISL9222A Charger • Both Inputs Accept Voltage up to 28V • Flexible Power Connectors Each with a Hook and a Solder Pad Providing Variety to Users 7. Voltmeter V3 at JIGON pin reads the voltage almost the same as voltmeter V2 reads. JIGON is the output of OR gate with VBAT as supply. JIGON will be pulled up to VBAT if the POR of the part is reached. Refer to the JIGON states table in the data sheet. 8. The LED should be on, indicating power on. • USB Port On-Board Accepts Power Directly From USB Cable • Convenient Jumpers for Programming the Charge Current, Charge Mode, and for Current Measurement • 3.5x2.5 Square Inches Board Size Handy for Evaluation • Thermal Vias in the Thermal Pad Similar To Customers’ Thermally Enhanced Environment • On-Board LEDs for Input PPR and CHG State Indication 9. The current meter I2 should read about 0.25A as the charging current 10. Insert a jumper shunt on JP5 and the current meter I2 should read about 0.5A charging current 11. Insert a jumper shunt on both JP5 and JP7. The current meter I2 should read about 0.65A charging current 12. Reduce the voltage at PS2 to 2.0V for trickle charge currents. Repeat steps 8, 9 and 10. The current reading should be 50mA, 100mA and 190mA for steps 8, 9 and 10, respectively • RoHS compliant 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1445 I1 V1 I2 V2 PS1 - PS2 + - + - + E - Load2 V3 FIGURE 1. CONNECTION OF EQUIPMENT Description of Jumper Settings JP1 - Connects the EN pin to a pull-up voltage or GND. The pull-up voltage is either from the BAT voltage (when a shunt is installed on JP3) or from an external power supply. If there is no shunt installed on JP1, the EN pin is internally pulled down to logic LOW to enable the charger. If a shunt is installed across the two jumper pins labeled as “Enable”, the EN pin is driven to logic LOW, the charger is enabled, same as floating. If the shunt is installed across the two jumper pins labeled as “Disable”, the EN pin is driven to logic HIGH to disable the charger. JP6 - A shunt installed on JP6 connects the BAT pin to the output connector J2 if output current measurement is not needed. The shunt can be replaced by a current meter if output current measurement is needed. JP7 - Parallels an additional 48.7k resistor to the IREF pin such that the cradle charge current will be increased by 0.25A. TABLE 1. JUMPER SETTING SUMMARY JUMPER POSITION FUNCTION JP2 - A shunt installed on JP1 connects the input source from connector J1 to the circuit if input current measurement is not needed. The shunt can be replaced by a current meter if input current measurement is needed, as shown in Figure 1. JP1 Shunt installed 3-pin jumper. Installing shunt on the upper 2 pins connects EN pin to HI. Installing shunt on the lower 2 pins connecting EN pin to LOW. JP2 Shunt installed Connects input source from VIN connector to VIN pin. JP3 - Selects the power source for EN pin pull-up and LED supply. If a shunt is installed, the BAT voltage is selected to be the source, if not, an external power supply of 3.3V can be connected to upper pin to provide pull-up and LED supply voltage. JP3 Shunt installed Connects cathode of D2 to VBAT for POR indication. JP5 Shunt installed Sets charge current to 0.5A if JP7 is not installed. JP6 Shunt installed Connects J2 to VBAT pin. JP7 Shunt installed Sets charge current to 0.5A if JP5 is not installed. JP5 - Parallels an additional 48.7k resistor to the IREF pin such that the cradle charge current will be increased by 0.25A (RIREF = 48.7k and the charge current is 0.25A if the shunts on both JP5 and JP7 are removed) 2 AN1445.0 December 4, 2008 Application Note 1445 Board Design Schematic VIN GND1 JP2 2 1 1 2 1 C8 C1 C3 4.7µF 10µF JP3 C2 JIGIN C4 0.1µF R2 470 2 1 J2 U1 1 VIN 2 PPR 1µF IREF R5 1k BAT 8 IREF 7 2 3 JIGON JIGIN 6 4 EN GND 5 JP5 1 ISL9222A DISABLE 2 C6 47µF 2 D2 RED EN JIGON PPR 1uF C5 47µF JP6 2 1 JP7 1 J1 GND2 V_BAT ENABLE JP1 C7 1 2 3 R1 100k R4 48.7k R6 48.7k R7 48.7k 0.1µF FIGURE 2. SCHEMATIC TABLE 2. ISL9222AEVAL1Z BILL OF MATERIALS ITEM QTY REFERENCE PART DESCRIPTION PART NO. VENDOR 1 1 C1 4.7µF, 35V Panasonic 2 3 C2, C4, C7 0.1µF, 50V Panasonic 3 1 C3 10µF, 6.3µF Panasonic 4 1 C8 1µF, 10V Panasonic 5 2 C5, C6 47µF, 6.3V Panasonic 6 1 D2 RED 7 2 VIN, VBAT Test Point, Red 8 5 9 SML-LXT0805GW-TR Lumex 5010 Keystone PPR, JIGON, JIG IN, IREF, EN Test Point, Yellow 5014 Keystone 1 GND Test Point, Black 5011 Keystone 10 1 JP1 2.54mm Header, 3CKT 22-88-4030 Molex 11 5 JP2, JP3, JP5, JP6, JP7 2.54mm Header, 2CKT 22-28-4020 Molex 12 2 J1, J2 2.54mm Header, 2CKT 22-11-2022 Molex 13 1 R1 100k Panasonic 14 1 R2 470 Panasonic 15 3 R4, R6, R7 48.7k Panasonic 16 1 R5 1k Panasonic 17 1 U1 ISL9222A 3 DFN 8L 2x3 Intersil AN1445.0 December 4, 2008 Application Note 1445 PCB Layout FIGURE 3. SILK LAYER FIGURE 4. TOP LAYER 4 AN1445.0 December 4, 2008 Application Note 1445 PCB Layout (Continued) FIGURE 5. BOTTOM LAYER Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 5 AN1445.0 December 4, 2008