sta7132mc ds en

Unipolar 2-Phase Stepper Motor
Driver ICs
STA7130MC Series
Datasheet
June, 2016 Rev.4.1
This document describes the STA7130MC series, which are unipolar
2-phase stepping motor driver ICs.
This document contains preliminary information on the products
under development. If you have any questions, including information on
options, please contact your nearest sales or representative office.
Table of Contents
1. General Description ..................................................................................... 2
2. Features and Benefits.................................................................................. 2
3. Part Numbers and Rated Currents ............................................................ 2
4. Specifications ................................................................................................ 3
5. Power Derating Chart ................................................................................. 6
6. Package Outline Drawing ........................................................................... 6
7. Functional Block Diagram and Pin Assignment ....................................... 7
8. Application Example .................................................................................... 8
9. Truth Tables ................................................................................................. 9
10. Logic Input Pins ......................................................................................... 10
11. Logic Input Timing .................................................................................... 11
12. Step Sequence Diagrams ........................................................................... 12
13. Individual Circuit Descriptions ................................................................ 18
14. Functional Descriptions............................................................................. 20
15. Application Information ............................................................................ 27
16. Thermal Design Information .................................................................... 32
17. Characteristics Data .................................................................................. 34
Important Notes ............................................................................................... 35
Sanken Electric Co., Ltd.
http://www.sanken-ele.co.jp/en/
1 / 36
STA7130MC Series Datasheet Rev.4.1
1. General Description
Thank you for your long years of patronage for each series of our unipolar 2-phase
stepping motor driver ICs. The STA7130MC series is our latest release.
This document describes summaries of our latest products.
2. Features and Benefits
(1)
(2)
(3)
(4)
Load (motor supply) voltages, VM: 35 V (max.), 0 to 33 V normal operating range
Main power supply voltages, VBB: 46 V (max.), 10 to 44 V normal operating range
Maximum output currents, IO(max): 2.0 A, 3.0 A
Clock-in stepping control that allows full-, half-, quarter-, eighth-, and
sixteenth-step excitation driving
(5) Built-in “sense resistor” detects motor current
(6) All variants are pin-compatible for enhanced design flexibility
(7) ZIP type 18-pin molded package (STA package)
(8) Self-excitation PWM current control with fixed OFF-time
 OFF-time adjusted automatically by step reference current ratio (3 levels)
(9) Built-in synchronous rectifying circuit reduces power dissipation at PWM-OFF
(10) Synchronous PWM chopping function prevents motor noise in the Hold mode
(11) The Standby mode to reduce IC input current in stand-by state
(12) Built-in protection circuitry against motor coil opens/shorts and thermal shutdown
protection
(13) The following functional options are available:
● Blanking Time
• Standard type:
1.5 µs (typ.)
• Optional type B:
3.0 µs (typ.)
NOTE: “Optional type B” is abbreviated and referred to as “B” as the letter used for
product branding codes. This term and abbreviation are also used throughout this
document. See also Section 6 for more details.
3. Part Numbers and Rated Currents
Table 3-1 provides product part numbers and rated currents available in the STA7130MC
series.
Table 3-1. Part Numbers and Rated Currents
Part Number
STA7132MC
STA7133MC
Rated Current
(Maximum Setting Value)
2.0 A
3.0 A
Sanken Electric Co., Ltd.
2 / 36
STA7130MC Series Datasheet Rev.4.1
4. Specifications
Table 4-1. Absolute Maximum Ratings
Unless specifically noted, TA = 25 °C
Characteristic
Symbol
Rating
Unit
Load (Motor Supply) Voltage
VM
35
V
Main Power Supply Voltage
VBB
46
V
2.0
A
STA7132MC
3.0
A
STA7133MC
Output Current
IO
Logic Input Voltage
VLI
−0.3 to 5.5
V
Logic Output Voltage
VLO
5.5
V
REF Input Voltage
VREF
−0.3 to 5.5
V
Detection Voltage
VRS
±1
V
Power Dissipation
PD
3.5
W
Junction Temperature
TJ
150
°C
Ambient Temperature
TA
−20 to 80
°C
Remarks
Control
current
value
FLAG, MO pins
Without heatsink
Storage Temperature
Tstg
−30 to 150
°C
NOTE: Output current ratings may be limited by duty cycles, ambient temperatures, and heat
sinking conditions. Do not exceed the maximum output current and the maximum junction
temperature (TJ) given above, under any conditions of use.
Table 4-2. Recommended Operating Conditions
Unless specifically noted, TA = 25 °C
Standard Value
Min.
Max.
33
Characteristic
Load (Motor Supply) Voltage
Symbol
VM
Main Power Supply Voltage
VBB
10
44
V
VIN(Logic)
0
5.5
V
Logic Input Voltage
Unit
V
Remarks
Control current accuracy
degrades at a voltage of
0.1 V or less
Measured at Pin 10 (lead
Case Temperature
TC
85
°C
portion), without heatsink
NOTE: As the motor supply voltage, VM, becomes higher, it also approaches the breakdown
voltage of the OUTx pins (75 V min.); and breakdown will be more likely to happen. Even if
one of the OUTx pins breaks down (due to surge noise or other factors), the STA7130MC
series will recognize it as abnormality (coil open) and will run appropriate protection
functions. Therefore, a thorough evaluation is recommended.
REF Input Voltage
VREF
0.1
0.9
Sanken Electric Co., Ltd.
V
3 / 36
STA7130MC Series Datasheet Rev.4.1
Table 4-3. Electrical Characteristics
Unless specifically noted, TA = 25 °C, VBB = 24 V
Characteristic
Symbol
IBB
IBBS
Min.
MOSFET Breakdown
Voltage
VDSS
75
MOSFET On-Resistance
RDS(on)
Main Power Supply Current
MOSFET Body Diode
Forward Voltage
Maximum Response
Frequency
Logic Input Voltage
Logic Input Current
Logic Output Voltage
Logic Output Current
REF Input Voltage
REF Input Current
Step Reference Current
Ratio
SENSE Detection Voltage
fCLK
250
VLIL
VLIH
ILIL
ILIH
VLOL
ILOL
VREF
VREFS
IREF
0
2.3
Max.
15
3
0.24
0.18
1.2
1.3
0.7
5.5
0.5
3
0.9
5.5
0.1
2.0
±10
100
98.1
95.7
92.4
88.2
83.1
77.3
70.7
63.4
55.5
47.1
38.2
29
19.5
9.8
VREF × 1/3
– 0.03
Ω
V
kHz
±1
±1
Mode F
Mode E
Mode D
Mode C
Mode B
Mode A
Mode 9
Mode 8
Mode 7
Mode 6
Mode 5
Mode 4
Mode 3
Mode 2
Mode 1
Unit
mA
mA
V
0.18
0.12
0.85
0.9
VF
VSENSE
Rating
Typ.
VREF × 1/3
VREF × 1/3
+ 0.03
V
V
µA
µA
V
mA
V
V
µA
Conditions
Normal mode
Standby mode
ID = 1 mA
STA7132MC
STA7133MC
STA7132MC
STA7133MC
Clock duty cycle =
50%
VLIL = 0 V
VLIH = 5 V
ILOL = 3 mA
VLOL = 0.5 V
Standby11)
VREF = 0.1 to 5 V
%
VREF = 0.1 to 0.9 V
V
VREF = 0.6 V, Mode F
NOTE: Unless specifically noted, negative current is defined as output current flow from a
specified pin.
1)
In a state of: IBBS, output OFF, and sequencer enabled.
Sanken Electric Co., Ltd.
4 / 36
STA7130MC Series Datasheet Rev.4.1
Table 4-3. Electrical Characteristics (continued)
Unless specifically noted, TA = 25 °C, VBB = 24 V
Characteristic
Sense Resistor1)
Minimum PWM ON-Time
PWM OFF-Time
Standby-Enable Recovery
Time
Switching Time
Overcurrent Detection
Voltage2)
Overcurrent Detection
Current (VSOC / RS)
Load Disconnection
Undetected Time
Overheat Protection
Temperature
1)
Min.
Symbol
RS
tON(min)
tOFF1
tOFF2
tOFF3
tSE
Rating
Typ.
0.15
0.1
1.5
3.0
12
9
7
Max.
Unit
µs
µs
µs
µs
µs
Conditions
STA7132MC
STA7133MC
Standard type
Optional type B
Mode 8 to Mode F
Mode 4 to Mode 7
Mode 1 = Mode 3
µs
Standby1, Standby2
Ω
100
tCON
tCOFF
1.6
0.9
µs
µs
VSOC
0.45
V
IOCP
3
4.5
A
A
Clock  Output ON
Clock  Output OFF
SENSE Terminal
Voltage
STA7132MC
STA7133MC
tOPP
2
µs
From PWM-OFF
TTSD
125
°C
Measured at back of
device case (after
heat has saturated)
Protection circuit operates when VSENSE > VSOC.
Figure 4-1. Setting Range of Reference Voltage, VREF
5.5 V
Standby1 Set Range_
2.0 V
1.35 V (Typ)
(Mode F)
Prohibition_
Zone
OCP
0.9 V
Motor Current Set Range_
0.1 V
NOTE: Extra attentions should be paid to the changeover between the motor current setting
range and the Standby1 set range. If the changeover takes too long, OCP operation will start
when VSENSE > VSOC, depending on the step reference current ratio (Mode) selected.
Sanken Electric Co., Ltd.
5 / 36
STA7130MC Series Datasheet Rev.4.1
5. Power Derating Chart
Figure 5-1. Power Derating Chart
6. Package Outline Drawing
NOTES:
● Dimensions in millimeters
● Pin material: Cu
● Pin plating:
Solder plating (Pb-free)
● Branding codes:
Part number: STA713xMC
• The lowercase letter x represents a number of either of 2 or 3, according to current
ratings. See also Table 3-1, which lists the part numbers and corresponding
current ratings.
• Optional type B has the suffix letter B at the end of its part number.
Lot number: YMDD
• Y is the last digit of the year of manufacture
• M is the month of the year (1 to 9, O, N, or D)
• DD is the day of the month (01 to 31)
Sanken Electric Co., Ltd.
6 / 36
STA7130MC Series Datasheet Rev.4.1
7. Functional Block Diagram and Pin Assignment
8 12
9
MIC
17
OUTB
OUTB
7 13
VBB
6
RESET
5
CLOCK
CW/CCW
M3
4
M1
15
M2
11
FLAG
2
MO
OUTA
1
REF/STANDBY1
OUTA
Figure 7-1. Functional Block Diagram
18
Reg.
÷3
PreDriver
PreDriver
Sequencer
&
Standby Circuit
Protection
Protection
DAC
TSD
+
SENSEA
Synchro
Control
Comp
3
PWM
Control
-
Rs
DAC
+
Comp
PWM
Control
OSC
OSC
Pin No.
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
OUTA
OUTA
SENSEA
MO
M1
M2
M3
CLOCK
VBB
GND
REF/STANDBY1
RESET
CW/CCW
SYNC
FLAG
SENSEB
___________
OUTB
OUTB
___________
14
10
SYNC
GND
16
-
SENSEB
Rs
Function
Phase A___output
Phase A output
Phase A current sensing
Output from 2-phase excitation status monitor
Input for excitation mode & Standby2 setting
Step clock input
Main power supply voltage
Ground
Input for control current / Standby1 setting
Reset input for internal logic
Forward / reverse input
Synchronous PMW control switch input
Output from protection circuits monitor
Phase B___current sensing
Phase B output
Phase B output
Sanken Electric Co., Ltd.
7 / 36
STA7130MC Series Datasheet Rev.4.1
8. Application Example
Figure 8-1. Application Example
VM = 10 to 33 V
VDD = 3.0 to 5.5 V
+
Q1
STANDBY
R11
R1
C1
OUTA
OUTA
VBB
OUTB
OUTB
CA
R10
RESET
CLOCK
CW/CCW
M1
STA7130MC Series
M2
M3
SYNC
MO
FLAG
REF/STANDBY1
SENSEA
SENSEB
GND
+
CB
MicroController
R4 to R9
R2
R3
C2
Single-Point
Ground
Logic Ground
Power Ground
Constants, for reference use only:
R1 = 10 kΩ
R4 to R9 = 1 to 10 kΩ (Not required if input state does not reach indefinite.)
R2 = 1 kΩ (VR)
R10 to R11 = 5.1 to 10 kΩ
R3 = 10 kΩ
NOTES:
● Take precautions to avoid noise on the VDD line; noise levels greater than 0.5 V on the VDD
line may cause device malfunction. Noise can be reduced by separating the logic ground
and the power ground on a PCB from the GND pin (Pin 10).
● Unused logic input pins (CW/CCW, M1, M2, M3, RESET, and SYNC) must be pulled up or
down to VDD or ground. If those unused pins are left open, the device may malfunction.
● Unused logic output pins (MO, FLAG) must be kept open.
Sanken Electric Co., Ltd.
8 / 36
STA7130MC Series Datasheet Rev.4.1
9. Truth Tables
(1) Input Pins
Table 9-1. Truth Table for Common Input Pins
Pin Name
Low Level
High Level
Clock
RESET
CW/CCW
M1
M2
M3
REF/STANDBY1
Normal operation
Forward (CW)
Logic reset
Reverse (CCW)
—
Excitation mode setting &
Standby2 (Protection Release)1)
Enable
Non-sync PWM
SYNC
control
1) See Table 9-2 below.
Standby1
—
Sync PWM control
—
Voltage across the REF/STANDBY1 pin controls PWM currents and the Standby1
function. The threshold voltage of this pin is set to approximately 1.75 V.
• When VREF ≤ 1.5 V (low level), the REF/STANDBY1 pin functions as the reference
voltage input for normal operation.
• When VREF ≥ 2.0 V (high level), the REF/STANDBY1 pin disables all outputs and
then puts the IC into the Standby1 mode. This Standby1 mode disables internal
linear circuitry and minimizes the main power supply current, IBB. Although much of
the internal circuitry is disabled, the logic circuit is still active. If an input signal on
the CLOCK pin is asserted, the internal sequencer/translator circuit reacts and sets
a step starting point for the next operation.
The Reset function is asynchronous. If an input on the RESET pin is high, the internal
logic circuit is reset. Note that a signal on the RESET pin cannot control an output
disable command. If not the Standby state, outputs turn on at the starting point of
excitation.
The Sync function runs only at “2-phase excitation timing." (2-phase excitation timing
is a point where the step reference current ratio of both phases A and B is either of Mode
8 or F.) If this function is used at other than the 2-phase excitation timing, an overall
balance might collapse because PWM OFF-times and setting currents are different in
each of phase A and phase B control scenario. (If this function is used at a point of 1-phase
excitation, it does not react as the Sync function does. But there is no problem.)
Table 9-2. Commutation & Standby2 Truth Table for Common Input Pins
Pin Name
Excitation Mode
M1
M2
M3
Remarks
L
L
L
Mode 8 fixed
Full step (2 Phase)
H
L
L
Mode F fixed
L
H
L
Mode 8, and F
Half step (1-2 Phase)
H
H
L
Mode F fixed
Quarter step (W1-2 Phase)
L
L
H
Mode 4, 8, C, and F
Eighth step (2W1-2 Phase)
H
L
H
Mode 2, 4, 6, 8, A, C, E, and F
Sixteenth step (4W1-2 Phase)
L
H
H
Mode 1 to F
Standby2
H
H
H
Output Disable & Protection Release
The Standby2 function operates in the same way as the Standby1 function does, except
that the internal logic circuit enters the Hold mode. Therefore, in the Standby2 mode, the
internal sequencer/translator circuit is not activated even if a step command signal
occurs on the CLOCK input pin.
The Standby2 function can release the state in which the Protection function is active
(i.e., Protection Release).
Sanken Electric Co., Ltd.
9 / 36
STA7130MC Series Datasheet Rev.4.1
(2) Output Pins
Table 9-3. Truth Table for Monitor Output Pins
Pin Name
Low Level
High Level (Hi-Z)
MO
FLAG
Other than 2-phase excitation timing
Normal operation
2-phase excitation timing
Protection circuit operation
“2-phase excitation timing” is a point where the step reference current ratio of both
phases A and B is either of Mode 8 or F.
Each monitor output pin is an open-drain type configuration. When using these pins,
add a pull-up resistor of approximately 5.1 to 10 kΩ.
The outputs turn off when the protection circuit starts operating. To release the
protection state, re-input the main power supply voltage (VBB) or put the IC into the
Standby2 mode.
10. Logic Input Pins
The low pass filter (LPF) incorporated with the logic input pins (CLOCK, RESET,
CW/CCW, M1, M2, M3, and SYNC) improves noise rejection.
The logic inputs are MOS input compatible; therefore, they are in a high impedance state.
Note that the IC should be used at a fixed input level, either low or high.
If there is a possibility that signals from the microcontroller are in high impedance, add a
pull-up/-down resistor. Since outputs from the logic input pins, which function as output
ON/OFF controllers, may result in abnormal oscillation, leading to MOSFET breakdown as
the worst-case scenario.
Sanken Electric Co., Ltd.
10 / 36
STA7130MC Series Datasheet Rev.4.1
11. Logic Input Timing
(1) Clock Signal
a. A low-to-high transition on the CLOCK input signal advances the sequencer/translator.
Clock pulse width should be set at 2 μs or longer in both positive and negative polarities.
Therefore, clock response frequency is set to 250 kHz.
b. Clock Edge Timing
With regard to the input logic of the CW/CCW, M1, M2, and M3 pins, a 1 μs delay
should occur both before and after a pulse edge, as setup and hold times (see Figure
11-1). The sequencer logic circuitry might malfunction if the logic polarity is changed
during these setup and hold times.
Figure 11-1. Input Signal Timing
Reset
2 µs (min)
5 µs (min)
4 µs (min)
2 µs (min)
Clock
2 µs (min)
CW/CCW
M1
M2
M3
1 µs (min) 1 µs (min)
1 µs (min) 1 µs (min)
NOTE: When awaking from the Standby1 or Standby2 mode, a delay of 100 µs or longer
before sending a clock pulse is recommended.
(2) Reset Signal
a. Reset Signal Pulse Width
Reset pulse width is equivalent to the hold time of a high level input. It should be 2 µs
or longer, same as the clock pulse width.
b. Reset Release and Clock Input Timing
When the timing of a reset release (falling edge) and a clock edge is simultaneous, the
internal logic might result in an unexpected operation. Therefore, a greater than 5 µs
delay is required between the falling edge of the RESET input signal and the next rising
edge of the CLOCK input signal (see Figure 11-1).
(3) Logic Level Change
Logic level inputs on CW/CCW, M1, M2, and M3 set the translator step direction
(CW/CCW) and step mode (M1, M2, and M3; see also Table 9-2, the commutation truth
table). Changes to those inputs do not take effect until the rising edge of an input signal on
the CLOCK pin. However, depending on the type and state of a motor, there may be errors
in motor operation such as step-out. A thorough evaluation on the changes of sequence
should be carried out.
Sanken Electric Co., Ltd.
11 / 36
STA7130MC Series Datasheet Rev.4.1
12. Step Sequence Diagrams
Figure 12-1. Full Step (2 Phase Excitation)
M1: L, M2: L, M3: L (Mode 8)
RESET
…
CLOCK
0
2
1
B
CW
A
A
0
70.7
0
70.7
CCW
B
M1: H, M2: L, M3: L (Mode F)
RESET
…
CLOCK
0
1
2
B
CW
A
0
0
CCW
10
0
A
B
Sanken Electric Co., Ltd.
12 / 36
STA7130MC Series Datasheet Rev.4.1
Figure 12-2. Half Step (1-2 Phase Excitation)
M1: L, M2: H, M3: L (1 Phase: Mode F / 2 Phase: Mode 8)
RESET
…
CLOCK
0
1
2
3
4
3
4
B
CW
A
A
0
70.7
0
10
0
70.7
CCW
B
M1: H, M2: H, M3: L (Mode F)
RESET
…
CLOCK
0
1
2
B
CW
A
0
0
CCW
10
0
A
B
Sanken Electric Co., Ltd.
13 / 36
STA7130MC Series Datasheet Rev.4.1
Figure 12-3. Quarter Step (W1-2 Phase Excitation)
M1: L, M2: L, M3: H
RESET
…
CLOCK
0
1
2
3
4
5
6
7
8
B
CW
A
0
38.2
70.7
CCW
0
38.2
70.7
92.4
92.4
10
0
A
B
Sanken Electric Co., Ltd.
14 / 36
STA7130MC Series Datasheet Rev.4.1
Figure 12-4. Eighth Step (2W1-2 Phase Excitation)
M1: H, M2: L, M3: H
RESET
…
CLOCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
B
CW
A
0
19.5
38.2
55.5
70.7
83.1
CCW
0
19.5
38.2
55.5
70.7
83.1
92.4
92.4
98.1
10
0
98.1
A
B
Sanken Electric Co., Ltd.
15 / 36
STA7130MC Series Datasheet Rev.4.1
Figure 12-5. Sixteenth Step (4W1-2 Phase Excitation)
M1: L, M2: H, M3: H
RESET
…
CLOCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
B
CW
A
A
0
9.8
19.5
29.0
38.2
47.1
55.5
63.4
70.7
77.3
83.1
88.2
CCW
92.4
0
9.8
19.5
29.0
38.2
47.1
55.5
63.4
70.7
77.3
88.2
83.1
10
0
95.7
95.7
98.1
98.1
92.4
B
Sanken Electric Co., Ltd.
16 / 36
STA7130MC Series Datasheet Rev.4.1
Excitation Change Sequence
The change of excitation modes is determined by the settings of the excitation pins (M1, M2,
and M3) before and after a step signal. Table 12-1 shows each excitation mode state setting.
Table 12-1. Excitation Mode States
Direction
CCW
CW
1)
2)
Internal Sequence State1)
Phase A
Phase B
2 Phase (Full Step)
Step Sequencing2)
1-2 Phase (Half Step)
PWM
Mode
PWM
Mode
Mode 8
Mode F
Mode 8/F
Mode F
W1-2 Phase
(1/4 Step)
A
A
A
A
A
A
A
A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
B
B
B
B
B
B
B
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
X
XX
X
XX
X
2W1-2
Phase
(1/8 Step)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XX
X
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XX
X
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XX
X
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4W1-2
Phase
(1/16 Step
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Each mode is defined accordingly to the SLA7070MPRT series.
XX indicates that sequence state is Mode 8; but step reference current ratio is Mode F.
Mode F has a step reference current ratio of 100%, and a PWM OFF-time of 12 μs.
Sanken Electric Co., Ltd.
17 / 36
STA7130MC Series Datasheet Rev.4.1
13. Individual Circuit Descriptions
(1) Monolithic IC (MIC)
• Sequencer Logic
A single clock strategy is employed for step timing. An input on the CW/CCW pin
determines the direction of motor rotation. Excitation mode is controlled by the
combination of the M1, M2, and M3 input logic levels. See Section 9 for truth tables, and
Section 11 for input timings.
• DAC (D-to-A Converter)
DACs that generate the reference voltage for controlling current. In microstep
sequencing, the current at each step is set by the values of a sense resistor (RS), a
reference voltage (VREF), the output voltage of the DACs, controlled by the output of the
sequencer/translator circuit.
Internal Reference Voltage = Reference Voltage / 3  Step Reference Current Ratio
For the step reference current ratios, see the electrical characteristics tables given in
Section 4.
• PWM Control
Circuits that allow self-excitation PWM current controlling with a fixed OFF-time are
used in this series. Each built-in oscillator (OSC) determines an OFF-time and a
blanking time for proper PWM operation. The operation mechanism of the PWM control
circuitry is identical to that of the STA7130M family. For more detailed functional
descriptions, see Section 14.
• Synchronous Control
A synchronous chopping circuit that prevents occasional motor noise during a hold
state which normally results from the asynchronous PWM operation of both motor
phases. When the SYNC input pin is set to logic high, the circuit sends a timing signal
that simultaneously turns off the chopping of phases A and B.
This function adopts the same operation mechanism applied to the STA7130M series.
Therefore, the use of the synchronous control during normal stepping is not
recommended, because it produces less motor torque or may cause motor vibration due
to staircase current.
The use of the synchronous control when the motor is not in operation is only allowed
in 2-phase excitation timing, because the differences in current control values and PWM
OFF-times between phases A and B exist at other excitation timings; otherwise, these
two phases may not be synchronized or may be greatly disrupted in their current control
values.
• Regulator Circuit
An integrated regulator circuit is used for powering the output MOSFET gate drive
circuit (pre-driver) and other internal linear circuits.
• Protection Circuit
Built-in protection circuits against motor coil opens or shorts are provided. This
protection is activated by sensing the voltage across internal sense resistors, RS.
Therefore, an overcurrent condition cannot be detected which results from the OUTx
pins or SENSEx pins, or both, shorting to GND. The protection against motor coil opens
is available only during PWM operation; therefore, it does not work at constant voltage
driving, when the motor is rotating at a high speed.
The operation of the protection circuit disables all outputs and reduces the circuit
current to approximately one-third. To return from the Protection mode, perform the
following steps:
1) Cycle the main power supply, VBB.
2) Release the protection state by setting logic input pins (M1, M2, and M3) high to
change into the Standby2 mode.
Sanken Electric Co., Ltd.
18 / 36
STA7130MC Series Datasheet Rev.4.1
• TSD Circuit
A TSD circuit that protects a driver by shifting an output to the Disable mode is
incorporated. When the temperature of the product control IC (MIC) rises and becomes
higher than its threshold, the circuit starts operating.
To reset the function, perform the same steps as described in the Protection Circuit
description.
(2) Output MOSFET Chip
The type of MOSFET chips to be mounted varies according to which of the two different
output current ratings has been selected. For specifications, see Table 4-3.
(3) Sense Resistor
Sense resistors are incorporated in this series to detect motor current. The resistance of
these varies according to which of the two different output current ratings has been
selected. For specifications, see Table 4-3.
Sanken Electric Co., Ltd.
19 / 36
STA7130MC Series Datasheet Rev.4.1
14. Functional Descriptions
(1) PWM Current Control
[1] Blanking Time
An actual operating waveform on the SENSEx pin when driving a motor is shown in
Figure 14-1.
Figure 14-1. Operating Waveform on SENSEx Pin during PWM Chopping
(Circled area of the left panel is shown in expanded scale in the right panel)
Immediately after a PWM turns off, ringing (or spike) noise on the SENSEx pin is
observed for a period of a few microseconds. Ringing noise can be generated by various
causes, such as capacitance between motor coils or inappropriate motor wiring.
Each pair of outputs is controlled by a fixed OFF-time PWM current-control circuit
that limits the load current to a target value, ITRIP. Initially, an output is enabled and
then currents flow through the motor winding and the current sense resistors. When
the voltage across the current sense resistors equals the DAC output voltage, VTRIP,
the current sense comparator resets a PWM latch. This turns off the driver for the
fixed OFF-time, during which the load inductance causes the current to recirculate for
the OFF-time period. Therefore, if the ringing noise on the sense resistor(s) equals and
surpasses VTRIP, the PWM turns off (i.e., a hunting phenomenon).
To prevent this phenomenon, a blanking time is set to override signals from the
current sense comparator for a certain period immediately after the PWM turns on
(Figure 14-2).
Figure 14-2. SENSEx Pin Waveform Pattern during PMW Control
PWM Pulse Width
ON
OFF (Fixed)
ITRIP
A
0
A
Blanking Time
Sanken Electric Co., Ltd.
20 / 36
STA7130MC Series Datasheet Rev.4.1
[2] Blanking Time and Hunting Phenomenon
Although current control can be improved by
shortening a blanking time, the degree of
margin to a ringing noise decreases
simultaneously. For this reason, when a motor
is driven by the device, a hunting phenomenon
may occur. Figure 14-3 shows an example of the
waveform pattern when the phenomenon
occurs.
In order to overcome this problem, Sanken
has released a new option, “type B”, which
offers a longer blanking time. Having the
longer banking time, the optional type B can
improve problems such as torque reduction and
huge motor noise that are occasionally found
during the hunting phenomenon.
Figure 14-3. Example of SENSEx Pin
Waveform during Hunting
Phenomenon
[3] Blanking Time Difference
Table 14-1 shows characteristic differences between two blanking times, shorter and
longer blanking periods.
This comparison is based on the case where drive conditions, such as a motor, motor
power supply voltage, REF input voltage, and circuit constant were kept the same
while only the indicated parameters were changed.
Table 14-1. Characteristic Comparison of Difference in Blanking Time
Parameter
Better Performance
Internal blanking time
Short
Long
Minimum PWM ON-time
Small
Ringing noise suppression
Minimum coil current
Large
Small
Coil current waveform
distortion at a high rotation
(mainly microstep)
Large
Brief descriptions for each parameter are as follows:
• Minimum PWM ON-time, tON(min)
This series has a blanking time that is effectively selected and fixed by the
PWM control. Therefore, even if an application attempts to shorten its ON-time
for limiting currents, it would not go below the fixed blanking time. Minimum
PWM ON-time refers to the time when an output is on during this blanking time
period, that is, when an output MOSFET is actually turned on. In other words, a
blanking time determines a minimum ON-time (“Small” in Table 14-1).
• Minimum Coil Current
This refers to the coil current when the PWM control is performed during a
minimum PWM ON-time. In other words, the device with a shorter blanking time
can reduce more coil current.
• Coil Current Waveform Distortion during High-Velocity Revolution
While a microstep drive is active, the ITRIP value changes to a predetermined
value in accordance with a clock input. The ITRIP value (internal reference voltage
splitting ratio) is then set up to be a sine wave. Because the PWM control of motor
coil current is set according to the ITRIP value, (the envelope of) the motor coil
current will also be controlled to be sine wave-like.
Sanken Electric Co., Ltd.
21 / 36
STA7130MC Series Datasheet Rev.4.1
In fact, due to the inductance characteristic of the coil, the device requires some
time to bring the coil current completely to a targeted value (ITRIP).
Roughly, the relationship between the convergence time (tconv), a time until the
coil current settles to its ITRIP value, and the duty cycle (tclk) of an input clock pulse
in any mode is
t CONV  t clk ,
where the coil current waveform amplitude serves as the limit for ITRIP.
When the current attempts to increase, the full limit of tconv is determined by
power supply voltage and the time constant of the motor coil used. While the
current attempts to decrease, the full limit is determined by the power supply
voltage, the damping time constant of the motor coil used, and the minimum
ON-time.
The duty cycle (tclk) is determined by the frequency of an input clock. It becomes
smaller as the frequency of the input clock increases. When the frequency of the
input clock is raised, because tclk becomes small, it is normal that the coil current
cannot be raised to the ITRIP value within a single clock period. In this situation,
the waveform amplitude of the coil current degenerates from the sine wave,
referred to as “waveform distortion.”
Figure 14-4 illustrates the comparison result of waveform distortions. Devices
with different blanking times were compared under the operating conditions that
power supply voltages, current preset values, motors, and so forth were kept the
same.
As shown in the areas circled (blanking times) in the figure below, the
amplitude envelope of the SENSEx pin waveform in the 1.5 µs case, which is the
same as the current waveform, has become sine wave-like whereas the waveform
in the 3.0 µs blanking time case has degenerated from an ideal sine wave.
The meaning of the team "Large" in Table 14-1 is as follows: if making a
comparison under the same operating conditions, the device with a longer
blanking time will result in less waveform distortion due to a lower clock
frequency. But if the clock frequency is the same, waveform distortion will be
larger due to a shorter blanking time. Even if such distortion is observed, it does
not always mean that the motor characteristics will be negatively affected.
Therefore, thorough evaluations should be carried out to make an informed
decision.
Figure 14-4. Comparison of SENSEx Pin Waveforms during High-Speed Revolution
Sanken Electric Co., Ltd.
22 / 36
STA7130MC Series Datasheet Rev.4.1
[4] PWM OFF-time
PWM OFF-time for the STA7130MC series is controlled at a fixed time generated by
the corresponding internal oscillator. It also is switched in three levels by step current
reference ratios. (See Table 4-3 for more details.)
In addition, the STA7130MC series provides a function that decreases power losses
occurring when the PWM turns off. This function dissipates the back EMF stored in
the motor coil at MOSFET turn-on, as well as at PWM turn-on (synchronous
rectification operation).
Figure 14-5 explains differences between two back EMF generation mechanisms.
Whereas the older version of our product series only performs ON/OFF operations
using a MOSFET on the PWM-ON side, the STA7130MC series can perform ON/OFF
operations using a MOSFET on the PWM-OFF side.
To prevent simultaneous switching of the MOSFETs at the synchronous rectification
operation, the IC has a dead time of approximately 0.5 μs. During the dead time, the
back EMF flows through the body diodes of the MOSFETs.
Figure 14-5. Difference in Back EMF Generation
Vcc
Normal Rectification Operation
Ion
Vcc
Synchronous Rectification Operation
Ion
Ioff
Ioff
SPM
Vg
SPM
Vg
Vrs
PWM ON
Rs
PWM OFF
Vg
Vg
Vrs
PWM ON
PWM ON
Rs
PWM OFF
Back EMF at Dead Time
PWM ON
Dead Time
FET Gate Signal
Vg
0
FET Gate Signal
Vg
VREF
Sense Voltage
0
VRS
FET Gate Signal
Vg
0
FET Gate Signal
Vg
VREF
Sense Voltage
0
VRS
Back EMF flows through the body diode of MOFSET during dead time .
Sanken Electric Co., Ltd.
23 / 36
STA7130MC Series Datasheet Rev.4.1
(2) Protection Functions
The STA7130MC series includes a motor coil short protection circuit, a motor coil open
protection circuit, and an overheat protection circuit. Detailed explanations of each
protection circuit are provided below.
[1] Motor Coil Short Circuit Protection (Load Short) Circuit
This protection circuit, embedded in the STA7130MC series, begins to operate when
the device detects an increase in the sense resistor voltage level, VRS. The threshold
voltage of this protection circuit, VSOC, is set to approximately 0.45 V. Outputs are
disabled at the time the protection circuit starts, where VRS exceeds VSOC.
Figure 14-6. Motor Coil Short Protection Circuit Operation
VM
Coil Short Circuit
SPM
Coil Short
Circuit
VOCP
Normal Operation
VREF
Vg
VRS
Rs
VRS
0

Output Disable
NOTE: Overcurrent that flows without passing the sense resister is undetectable.
[2] Motor Coil Open Protection Circuit (Patent acquired)
Driver destruction can occur when one output pin (motor coil) is disconnected in
unipolar drive operation. This is because a MOSFET connected after disconnection
will be in an avalanche breakdown state, where very high energy is added with back
EMF when PWM is off. With the avalanche state, an output cancels the energy stored
in the motor coil where the resisting pressure between the drain and source of the
MOSFET is reached (i.e., the condition in which the breakdown occurred).
Although MOSFETs with a certain amount of an avalanche energy tolerance rating
are used in the STA7130MC series, the avalanche energy tolerance falls as a
temperature increases.
Because high energy is added repeatedly whenever PWM operation disconnects the
MOSFET, the temperature of the MOSFET rises; and when the applied energy
exceeds the tolerance, the driver will be destroyed. Therefore, a circuit which detects
this avalanche state and protects the driver is added in the STA7130MC series.
As explained above, when the motor coil is disconnected, accumulated voltage in the
MOSFET causes a reverse current to flow during a PWM OFF-time. For this reason,
VRS that is negative during a PWM OFF-time in a normal operation becomes positive
when the motor coil is disconnected. Thus, the disconnected motor is detectable by
sensing that VRS in the PWM OFF-time is positive.
Sanken Electric Co., Ltd.
24 / 36
STA7130MC Series Datasheet Rev.4.1
In order to avoid detection malfunctions, the STA7130MC series actuates a
dedicated protection function, the motor coil open protection circuit, when the motor
disconnection state is detected three times continuously (see Figure 14-7).
Figure 14-7. Coil Open Protection Operation
PWM Operation
at Normal Device Operation
PWM Operation
at Motor Disconnection
VM
SPM
VM
SPM
Ion
Ioff
Disconnecton
Vg
Vg
Vout
Vout
Vrs
Rs
Vrs
Rs
Motor
Disconnection
FET Gate Signal
Vg
0
FET Gate Signal
Vg
0
VDSS
Vout
2 VM
VM
Vout
0
0
VREF
VRS
0
Breakdown (Avalanche State)
VREF
VRS
0
Motor Disconnection Detectable
NOTE: In addition to requiring three breakdown cycles to confirm the open circuit
condition, the STA7130MC series provides a fixed delay, an overload disconnection
undetected time (topp), before the protection is activated. This is to avoid false
detections, which can be occurred by surge noise after PWM turn-off, causing an
unwanted operation of the function even when the load is not actually disconnected.
The figure below describes alternative topp scenarios. If a total period of breakdown
time exceeds topp, the device shuts down the output. If this is the case, check the motor
and wiring layout to reduce surge noise. Shortening the breakdown time will allow the
protection circuit to function properly. (Variation among device variants and
applications should be taken into consideration.) When there is no actual breakdown,
normal operations will continue. One possible solution is adding a capacitor between
the OUTx and GND pins, which could damp the surge noise sufficiently.
Sanken Electric Co., Ltd.
25 / 36
STA7130MC Series Datasheet Rev.4.1
Surge remains under VDSS
VDSS
VOUT
(A) Breakdown confirmed
after 3 cycles
Breakdown ends w/in topp
VDSS
VOUT
(B) No effect on operations
Breakdown continues after topp
VDSS
VOUT
(C) Generates false detections
[3] Overheat Protection Circuit
When a product temperature rises and exceeds Ttsd, this protection circuit starts
operating and sets all outputs to be disabled.
NOTE: This product series has multichip composition (one IC for control, four
MOSFETs, and two chip resistors). Although main heat sources are the MOSFETs and
chip resisters, the location which actually detects temperature is the control IC (MIC).
Separated from these main heat sources, the control IC cannot detect a rapid
temperature change. Accordingly, perform worst-case thermal evaluations, in which
junction temperatures must not exceed a guaranteed value of 150 °C, in your
application design phase.
Sanken Electric Co., Ltd.
26 / 36
STA7130MC Series Datasheet Rev.4.1
15. Application Information
(1) Motor Current Ratio Setting
The motor current, IO (Mode F, 100%), for the STA7130MC series is determined by the
values chosen for the external components, R1, R2, and the current sense resistors, RS, in
the case of the sample application circuit shown in Figure 8-1. The formula to calculate IO is
shown below:
Io 
R2
1
 VDD  / Rs .
R1  R 2
3
(1)
The double-underlined term represents the reference voltage, VREF.
If VREF is set below 0.1 V, the accuracy of IO setting is more likely to be degraded due to
the variation between individual devices and/or the impedance of application trace layout.
The standard voltage for current ITRIP that the STA7130MC series controls is partially
divided by internal DACs:
I TRIP 
VREF 1
  ( Mode Proportion ) .
RS 3
(2)
(2) Lower Limit of Control Current
The STA7130MC series uses a self-oscillating PWM current-control topology in which an
OFF-time is fixed. As energy stored in motor coil is eliminated within the fixed PWM
OFF-time, coil current flows intermittently, as shown in Figure 15-1. Thus, average current
decreases as well as motor torque decreases. The point at which current starts flowing to
the coil is considered as the lower limit of the control current, IO(min), where IOUT is a target
current level.
The lower limit of control current differs by application conditions of the motor or other
factors, but it can be calculated from the following formula:
I O min 



V M 
1

 1 ,
R 
t
 
 exp  OFF t  
C

 

Lm
, and
R
R  Rm  RDS ( on)  RS .
with t C 
(3)
Where:
VM is the motor supply voltage,
RDS(on) is the MOS FET on-resistance,
Rm is the motor winding resistance,
Lm is the motor winding inductance,
tOFF is the PWM OFF-time, and
RS is the current sense resistor.
Even if the control current value is set at less than its lower limit, there is no setting at
which the IC fails to operate. However, the control current will worsen against its target
current.
Figure 15-1. Model Waveform of Control Current Lower Limit
ITRIP (Large)
A
ITRIP (Small)
0
A
The circled area indicates interval when the coil current generated is 0 A.
Sanken Electric Co., Ltd.
27 / 36
STA7130MC Series Datasheet Rev.4.1
(3) Avalanche Energy
In the unipolar topology of the STA7130MC series, a surge voltage (ringing noise) that
exceeds the MOSFET capacity to withstand might be applied to the IC. To prevent
damage, the STA7130MC series is designed with built-in MOSFETs having sufficient
avalanche resistance to withstand this surge voltage.
VM
Therefore, even if surge voltages occur, users will be able to
use the IC without any problems.
SPM
However, in case the motor harness used is too long or the
IC is used above its rated current or voltage, there is a
ID
possibility that an avalanche energy could be applied that
exceeds Sanken design expectations. Thus, users must test
VDS(AV)
the avalanche energy applied to the IC under actual
application conditions.
The following procedure can be used to check the
avalanche energy in an application. Figure 15-2 and Figure
Rs
15-3 show test points and waveform characteristics resultant,
respectively.
Figure 15-2. Test Points
From the waveform test result shown in Figure 15-3:
VDS(AV) = 80 V,
ID = 1 A, and
t = 0.5 µs.
VDS(AV)
The avalanche energy, EAV, then can be calculated using
the following formula:
EAV ≈ VDS(AV) × 1/2 × ID × t
(4)
= 80 (V) × 1/2 × 1 (A) × 0.5 × 10-6 (μs)
= 0.02 (mJ).
By comparing the calculated EAV values with the graph
shown in Figure 15-4, the application can be evaluated if it is
safe for the IC by being within the avalanche
energy-tolerated dose range of the MOFSETs.
ID
t
Figure 15-3. Waveform at
Avalanche Breakdown
Figure 15-4. Iterated Avalanche Energy Tolerated Level, EAV
20
STA7133MC
EAV (mJ)
[mJ]
Eav
16
12
8
STA7132MC
4
0
0
25
50
75
100
125
150
製品温度
Tc[℃]
Product
Temperature,
TC (°C)
Sanken Electric Co., Ltd.
28 / 36
STA7130MC Series Datasheet Rev.4.1
(4) Motor Supply Voltage (VM) and Main Power Supply Voltage (VBB)
Because the STA7130MC series has a structure that separates the control IC (MIC)
and the power MOSFETs as shown in Figure 7-1, the motor supply and main power
supply are electrically separated. Therefore, it is possible to drive the IC with using
different power supplies and different voltages for the motor supply and the main power
supply. However, extra caution is required because the supply voltage ranges differ
among power supplies.
(5) Internal Logic Circuits
a. Reset for the Internal Sequencer
The sequencer/translator circuit embedded in this product series is initialized by the
built-in power-on reset function, which is activated at a time when the main power
supply (VBB) is applied. Therefore, the output immediately after power-on indicates a
status that the power circuits are in the home state.
When the sequencer/translator must be reset after the motor has been operating, a
signal must be input on the RESET pin. In a case in which external reset control is not
necessary and the RESET pin is not used, the RESET pin must be pulled to logic low
on the application circuit board. When external reset controlling is not necessary and
the RESET pin is not used, the RESET pin must be pulled to logic low on an
application circuit board.
b. Clock Input
The STA7130MC series is designed to move one sequence increment at a time,
according to the current stepping mode, when a positive clock pulse edge is detected.
When a clock input signal stops, the present excitation state enters a motor hold
state. At this time, there is no difference to the IC if the clock input signal is at low
level or high level.
c. Chopping Synchronous Circuit
The STA7130MC series has a chopping synchronous function to protect from
abnormal noises that may occasionally occur during the motor Hold mode. This
function can be operated by setting the SYNC pin at high level. However, if this
function is used during motor rotation, control current does not stabilize; and that may
result in reduced motor torque and/or increased vibration.
Note that the synchronous circuit should be disabled to control the motor current
properly even when it is used in other than the 2-phase excitation state (Modes 8 and
F) or the 1-phase excitation hold state.
In
normal
operation,
an
external
Figure 15-5. Clock Signal Shutoff
microcomputer sends an input signal for
Detection Circuit
switching. However, in applications where any
Vcc
input
signals
cannot
be
transmitted
adequately due to a limited number of ports,
CLOCK
SYNC
the following method can be taken to use the
function.
74HC14
The schematic diagram in Figure 15-5 shows
R
C
how the IC is designed so that a signal on the
SYNC pin can be determined by an input
signal on the CLOCK pin.
Figure 15-6. Clock Signal Edge
Detection Circuit
Step
Clock
Sanken Electric Co., Ltd.
a
Edge
Clock
29 / 36
STA7130MC Series Datasheet Rev.4.1
When the CLOCK pin receives a logic high signal, the internal capacitor, C, is
charged, and the SYNC pin signal is set to logic low. However, if the input signal on
the CLOCK pin cannot rise above a logic low level, the capacitor is discharged by the
internal resistor, R, and the SYNC pin signal is set to logic high, causing the IC to shift
to the synchronous mode. RC time constant in the circuit should be determined by the
minimum clock frequency used.
When using a sequence that keeps an input signal on the CLOCK pin at logic high,
an inverter circuit must be added.
When the CLOCK pin signal is set at an undetermined level, an edge detection
circuit (Figure 15-6) can be added to prepare a proper clock input signal, allowing
correct processing by the circuit illustrated in Figure 15-5.
d. Output Disable Circuits (Standby1 and Standy2)
There are two methods to set the IC to a motor free-state (coast, with outputs
disabled). One is to set the REF pin to more than 2 V (Standby1). And the other is to
set all the excitation mode setting pins (M1, M2, and M3) to high (Standby2). In either
way, the IC is put into the Standby mode, which stops the main power supply and
reduces circuit current.
The difference between the two methods is that the Standby1 keeps the internal
sequencer enabled, whereas the Standby2 puts the internal sequencer into a hold
state. That is to say, in the Standby2 mode, the excitation sequence remains in the
hold state even after a signal is input on the CLOCK pin. The Standby2 also works as
a function to return from the state in which the protection function is activated.
When awaking to normal operation mode (motor rotation) from the Disable
(Standby1 or Standby2) mode, set an appropriate delay time, i.e., a time period from
cancellation of the Disable mode to an initial clock input edge. In doing so, consider not
only a rise time for the IC, but also a rise time for the motor excitation current (Figure
15-7).
Figure 15-7. Timing Delay between Disable Mode
Cancellation and the Next Clock Input
REF/STANDBY1 or
M1, M2, and M3
100 µs(min)
Clock Signal
e. REF/STANDBY1 Pin
The REF pin provides access to the following functions:
[1] Reference voltage setting for output current setting: Low level (VREF ≤ 0.9 V)
[2] Output Enable-Disable control input: High level (VREF ≥ 2.0 V)
These functions are further described in Section 9, and in the discussion of output
disabling, above. Moreover, the threshold voltage to switch the output enable-disable
signals is set to approximately 1.75 V.
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STA7130MC Series Datasheet Rev.4.1
To control the REF voltage, pay attention to the following points:
Range A – Control current value varies in accordance with VREF, not only within
the range specified in [1], but also within the range from [1] to the threshold
voltage (typically 1.75 V). Therefore, power dissipation in the IC and the sense
resistors must be given extra consideration. In addition, note that OCP operation
may start depending on the reference voltage splitting ratio.
Range B – In this range, the voltage that switches output enable and disable
exists. At enable, the same cautions apply as in Range A. For some cases, there
are possibilities that an output status will become unstable as a result of
iterations between enable and disable states.
f. Logic Input Pins (CLOCK, RESET, CW/CCW, M1, M2, M3, and SYNC)
When a logic input pin (CLOCK, RESET, CW/CCW, M1, M2, M3, or SYNC) is not
used, the pin must be tied to VDD or GND.
Do not leave any of these pins floating, because there is possibility of undefined
effects on IC performance if they are left open.
g. Monitor Output Pins (MO and FLAG)
The MO and FLAG output pins are designed as monitor outputs. Moreover, the IC
consists of an open-drain output configuration, as shown in Figure 15-8. When using
the monitor output pin, add a pull-up resistor of approximately 5.1 to 10 kΩ. Therefore,
let these output pins open when they are not used.
Figure 15-8. MO/FLAG Pin General Internal Circuit Layout
Static Electricity
Protection Circuit
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MO or
FLAG
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STA7130MC Series Datasheet Rev.4.1
16. Thermal Design Information
It is not practical to calculate the power dissipation of the STA7130MC series accurately,
because that would require factors that are variable during operation, such as time periods
and excitation modes during motor rotation, input frequencies and sequences, and so forth.
Given this situation, it is preferable to perform approximate calculations at worst
conditions. The following is a simplified formula for the calculation of power dissipation using
extracted minimum necessary parameters:
P  I 2  (R DS(on)+Rs)  2 ,
where:
P is the power dissipation in the IC,
I is the operation current (≈ Io),
RDS(on) is the on-resistance of the output MOSFET, and
Rs is the current sense resistance.
Based on the power dissipation in the IC calculated using the above formula, the expected
increase in operating junction temperature, ΔTJ, of the IC can be estimated using Figure 16-1.
This result should be added to the worst-case ambient temperature when operating, TA(max).
Based on the calculation, there is no problem unless TA(max) + ΔTJ > 150 °C. However, final
confirmation should be made by measuring the IC temperature during operation and then
verifying power dissipation and junction temperature in the corresponding graph in Figure
16-1.
Figure 16-1. Temperature Increase
Increase in Temperature, ΔT (°C)
150
ΔTJ-A = 35.7 × PD
125
100
75
50
ΔTC-A = 22.9 × PD
25
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Allowable Package Power Dissipation, PD (W)
When the IC is used with a heatsink mounted, product package thermal resistance, θJ-A, is
a variable used in calculating ΔTJ-A. The value of θJ-A is calculated from the following
formula:
θJ-A ≈ θJ-C + θFIN = (θJ-A – θC-A) + θFIN ,
where θFIN is the thermal resistance of the heatsink. Then, ΔTJ-A can be calculated with using
the value of θJ-A.
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STA7130MC Series Datasheet Rev.4.1
The following procedure should be used to measure product temperature and to estimate
junction temperature in actual operation.
First, measure a temperature rise in the center of backside of mold resin used for the
device (ΔTC-A).
Second, estimate power dissipation (P) and junction temperature (TJ) from the
temperature rise with reference to Figure 16-1, the Temperature Increase graph. At this
point, the device temperature rise (ΔTC-A) and the junction temperature rise (TJ) become
almost equivalent in the following formula:
ΔTJ ≈ ΔTC-A + P × θJ-C .
CAUTION
The STA7130MC series is designed as a multichip, consisting of four separate power
elements (MOSFETs), one control IC (MIC), and two sense resistors. Moreover, because the
control IC cannot accurately detect the temperature of the built-in power elements, which are
the primary sources of heat, the STA7130MC series does not provide a protection function
against overheating. For thermal protection, users must conduct sufficient thermal
evaluations to ensure that the junction temperature of the IC does not exceed a guaranteed
level of 150 °C.
This thermal design information is provided for preliminary design estimations only.
Before operating the IC in an application, users must experimentally determine its actual
thermal performance (the case temperature of Pin 10). The maximum recommended case
temperatures (Pin 10) for the IC are:
● With no external heatsink connection: 85 °C
● With external heatsink connection:
75 °C
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STA7130MC Series Datasheet Rev.4.1
17. Characteristics Data
(1) Output MOSFET On-Voltage, VDS(on)
(2) Output MOSFET Body Diodes Forward Voltage, VF
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STA7130MC Series Datasheet Rev.4.1
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STA7130MC Series Datasheet Rev.4.1
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DSGN-CEZ-16001
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