CA3262A, CA3262 Quad-Gated, Inverting Power Drivers August 1997 Features Description • • • • • • The CA3262 and CA3262A are used to interface low-level logic to high current loads. Each Power Driver has four inverting switches consisting of a non-inverting logic input stage and an inverting low-side driver output stage. All inputs are 5V TTL/CMOS logic compatible and have a common Enable input. Each output device has independent current limiting (ILIM) and thermal limiting (TLIM) for protection from over-load conditions. Steering diodes connected from each output (in pairs) to the Clamp pins may be used in conjunction with external zener diodes to protect the IC against over-voltage transients that result from inductive load switching. Independent Over-Current Limiting On Each Output Independent Over-Temperature Limiting On Each Output Output Drivers Capable of Switching 700mA Load Inputs Compatible With TTL or 5V CMOS Logic Suitable For Resistive, Lamp or Inductive Loads Power-Frame Package Construction For Good Heat Dissipation • Operating Temperature Ranges - CA3262A . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC - CA3262 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Applications System Applications • • • • • • • • • • Solenoids Relays Lamps Steppers Small Motors Displays To allow for maximum heat transfer from the chip, all ground pins on the DIP, PLCC and SOIC packages are directly connected to the mounting pad of the chip. Integral heat spreading lead frames directly connect the bond pads and ground leads to conduct heat from the chip junction to the PC Board for good heat dissipation. Automotive Appliances Industrial Controls Robotics The CA3262 and CA3262A can drive four incandescent lamp loads without modulating their brilliance when the “cold” lamps are energized. Outputs may be parallel connected to drive high current loads. The maximum output current of each output is determined by the over-current limiting threshold which is typically 1.2A but may be as low as 0.7A. Ordering Information PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE CA3262E -40 to 85 16 Ld PDIP E16.3 CA3262AE -40 to 125 16 Ld PDIP E16.3 CA3262AQ -40 to 125 28 Ld PLCC N28.45 CA3262AM -40 to 125 24 Ld SOIC (W) M24.3 Pinouts 15 IN B OUT B 3 14 ENABLE GND 4 13 GND INDEX 4 3 2 1 CA3262A (SOIC) TOP VIEW PRELIMINARY ENABLE 2 IN B CLAMP IN A IN A OUT A 16 NC 1 CLAMP OUT A CA3262A (PLCC) TOP VIEW OUT B CA3262, CA3262A (PDIP) TOP VIEW 28 27 26 25 GND GND 5 OUT A 1 24 IN A CLAMP 2 23 IN B OUT B 3 22 ENABLE NC 4 21 NC 20 GND GND 5 12 GND GND 6 24 GND GND 5 OUT C 6 11 VCC GND 7 23 GND GND 6 19 GND GND 7 18 GND GND 8 17 GND NC 9 16 NC GND 9 21 GND GND 10 20 GND GND 11 19 GND OUT C 10 15 VCC CLAMP 11 14 IN C OUT D 12 13 IN D VCC IN C 12 13 14 15 16 17 18 IN D IN D 22 GND GND 8 NC 9 IN C OUT D 8 10 OUT C OUT D 7 CLAMP CLAMP File Number 1 1836.6 CA3262A, CA3262 Functional Block Diagram VCC VCC V+ CONSTANT CURRENT SOURCES OUT D TLIM IN D CLAMP ILIM TLIM OUT C IN C REFERENCE VOLTAGE 1.2V INPUT ILIM ENABLE OUT B TLIM ENABLE TO SUBSEQUENT STAGES IN B CLAMP ILIM TLIM FIGURE 1. CA3262A EQUIVALENT SCHEMATIC OF ONE INPUT STAGE OUT A IN A ILIM TRUTH TABLE (Each Output) ENABLE IN OUT H H L H L H L X H H = High, L = Low, X = Don’t Care VCC +5V P.S. V+ RELAY OUT D IN D TLIM CLAMP VBATT ILIM OUT C IN C TTL OR CMOS LOGIC LEVEL INPUTS SOLENOID TLIM VBATT ENABLE ILIM OUT B IN B HIGH CURRENT HIGH SIDE DR TLIM CLAMP MOTOR ILIM VBATT OUT A IN A TLIM LAMP ILIM FIGURE 2. QUAD INVERTING POWER DRIVER (QDR) SHOWN WITH TYPICAL APPLICATION LOADS 2 CA3262A, CA3262 Absolute Maximum Ratings Thermal Information Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Logic Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Output Voltage, VCEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V Output Sustaining Voltage, VCE(SUS) . . . . . . . . . . . . . . . . . . . . 40V Output Transient Current . . . . . . . . . . . . . . . . . . . . . . . . . . (Note 1) Output Load Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Note 2) Thermal Resistance (Typical, Note 3) θJA (oC/W) For PC Mount Without Added Copper Ground Area CA3262E (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . 60 CA3262AE (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . 60 CA3262AQ (PLCC) . . . . . . . . . . . . . . . . . . . . . . . 45 CA3262AM (SOIC) . . . . . . . . . . . . . . . . . . . . . . . 60 For PC Mount With 2 sq. in. of Added Copper Ground Area CA3262E (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . 40 CA3262AE (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . 40 CA3262AQ (PLCC) . . . . . . . . . . . . . . . . . . . . . . . 36 CA3262AM (SOIC) . . . . . . . . . . . . . . . . . . . . . . . 36 See Maximum Power Dissipation vs Temperature curves, Figures 6A and 6B. Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 265oC Operating Conditions Temperature Range CA3262AE, CA3262AQ, CA3262AM . . . . . . . . . . -40oC to 125oC CA3262E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications VCC = 5.5V, TA = -40oC to 125oC for CA3262A and VCC = 5.5V, TA = -40oC to 85oC for CA3262 Unless Otherwise Specified CA3262 PARAMETER Output Leakage Current SYMBOL ICEX TEST CONDITIONS VCE = 60V, VENABLE = 0.8V Output Sustaining Voltage VCE(SUS) Note 5 Collector Emitter Saturation Voltage (See Figures 4B and 5B) VCE(SAT) VIN = 2V, VCC = 4.75V CA3262A MIN TYP MAX MIN TYP MAX UNITS - - 100 - 0.6 50 µA 40 - - 40 - - V IC = 100mA - - 0.25 - 0.05 0.15 V IC = 200mA - - - - - 0.2 V IC = 300mA - - - - - 0.25 V IC = 400mA - - 0.4 - 0.2 0.3 V IC = 500mA - - - - - 0.4 V IC = 600mA - - 0.6 - - 0.5 V IC = 700mA, TA = -40oC - - 0.6 - - 0.5 V Input Low Voltage VIL - - 0.8 - - 0.8 V Input High Voltage VIH 2 - - 2 - - V Input Low Current IIL VIN = 0.8V - - 10 - 0.75 10 µA Input High Current IIH VIN = VENABLE = 5.5V, IC = 600mA - - 10 - - 10 µA VIN = 2V, VENABLE = 5.5V, IOUTA = 250mA, IOUTB = 250mA, IOUTC = 250mA, IOUTD = 250mA - - 70 - (Note 4) 55 mA - - 5 - (Note 4) 5 mA - - 100 - - 50 µA Supply Current, All Outputs ON, (See Figures 4A and 5A) ICC(ON) Supply Current, All Outputs OFF, (See Figures 4A and 5A) ICC(OFF) VIN = 0V Clamp Diode Leakage Current IR Clamp Diode Forward Voltage, (See Figures 4D and 5D) VF Turn-On Delay, (See Figures 4C and 5C) Over Current Limiting VR = 60V IF = 1A, VIN = 0V - - 1.7 - - 1.7 V IF = 1.5A, VIN = 0V - - 2.1 - - 2.1 V - - 8 - - 8 µs 0.7 - (Note 1) 0.7 - (Note 1) A - 155 - - 155 - oC tPHL, tPLH IOUT = 500mA ILIM VOUT = 2V, VIN = 5.5V, VENABLE = 5.5V DESIGN PARAMETERS Over Temperature Limiting (Junction Temperature) TLIM 3 CA3262A, CA3262 Electrical Specifications VCC = 5.5V, TA = -40oC to 125oC for CA3262A and VCC = 5.5V, TA = -40oC to 85oC for CA3262 Unless Otherwise Specified (Continued) CA3262 PARAMETER SYMBOL TEST CONDITIONS CA3262A MIN TYP MAX MIN TYP MAX UNITS - - - 3 - pF - - 4.4 - pF Input Capacitance, Input CIN - Enable Capacitance CEN - NOTES: 1. The CA3262 and CA3262A have on-chip limiting for transient peak currents. Under short-circuit conditions with voltage applied to the collector of the output transistor and with the output transistor turned ON, the current will increase to 1.2A, typical. Over-Current Limiting protects a short circuit condition for a normal operating range of output supply voltage. During a short circuit condition, the output driver will shortly thereafter (approx. 5ms) go into Over-Temperature Limiting. While Over-Current Limiting may range to peak currents greater than 2A, each output will typically withstand a direct short circuit up to supply voltage levels of 16V. Excessive dissipation before thermal limiting occurs may cause damage to the chip for supply voltages greater than 18V. The CA3262 and CA3262A are rated to withstand peak current, cold turn-on conditions of #168 or #194 lamp loads. 2. The total DC current for the CA3262 and CA3262A with all 4 outputs ON should not exceed the total of (4 x 0.7A + Max. ICC) ~ 2.85A. This level of current will significantly increase the chip temperature due to increased dissipation and may cause thermal shutdown in high ambient temperature conditions (See Absolute Maximum Ratings for Dissipation). Any one output may be allowed to exceed 0.7A but may be subject to Over-Current Limiting above the ILIM min. limit of 0.7A. As a practical limit, no single output should be loaded to more than 1A (Max). 3. Normal applications require a surface mount of the 28 lead PLCC and 24 lead SOIC packages on a PC Board. The PLCC, SOIC and PDIP packages have power lead frame construction through the ground pins to conduct heat from the frame to the PC Board ground area. Thermal resistance, θJA, is given for a surface mount of the 28 lead PLCC and the 24 lead SOIC packages on a 1 oz. copper PC board with minimal ground area and with 2 square inches of ground area. 4. ICC varies with temperature. Typically, ICC(ON) is 18mA at 125oC and 41mA at -40oC. Typically, ICC(OFF) is 2.2mA at 125oC and 1.2mA at -40oC. 5. Tested with a switched-off 500mA Load of 120mH (with 24Ω series resistance), VBATT = 12V and the outputs (VCE) clamped to +40V maximum with an external zener diode. Applications Typical circuit configurations for applying the CA3262 and CA3262A are shown in the application circuit of Figure 2. To their rated capabilities, both circuits can be used to drive inductive, resistive and lamp loads. The CA3262A has a lower VSAT than the CA3262 and is rated for 125oC ambient temperature applications. The CA3262 data sheet rating is 85oC. Otherwise, the protection features described apply to both the CA3262 and CA3262A. The maximum voltage for full load current switching is the output sustaining voltage, VCE(SUS) which should not exceed 40V. To provide a means of over-voltage protection, on-chip steering diodes are connected from each output to one of two CLAMP pins. Over-voltage pulses may be generated from inductive load switching and must be clamped or limited to a peak voltage less than VCE(SUS) . To limit an inductive voltage pulse, a zener diode should be connected to the appropriate CLAMP pin. When the voltage pulse exceeds the zener threshold, the excess energy is dumped to ground via the on-chip steering diode and the external zener diode. The on-chip diodes may be used in a free-wheeling mode by connecting the CLAMP pins to an external clamp supply voltage. Zener diode clamp protection is preferred over the power supply clamp option, primarily because the power supplies may be subject to large transient changes; including turn-ON and turn-OFF conditions where non-tracking conditions between supplies could allow forward conduction through the steering diodes. For all transient conditions of either method, the clamp voltage should greater than the maximum supply voltage of the switching outputs and less than VCE(SUS) . Note that the rate of change of the output current during load switching is fast. Therefore, even small values of inductance, including the inductance of a few meters of hook-up wire to the load circuit, can generate voltage spikes of considerable amplitude at the output terminals and may require clamping to protect the device ratings. Current-limiting is provided as protection for shorted or overloaded output conditions. Voltage is sampled across a small metal resistor in the emitter of each output stage. When the voltage exceeds a preset comparator level, drive is reduced to the output. Current limiting is sustained unless thermal conditions exceed the preset thermal shutdown temperature of 155oC. If an output is shorted, the remaining three outputs will continue to function normally unless the continued heat spreading is sufficient to raise the junction temperature at any other output to a level greater than 155oC. High ambient temperature conditions may allow this to happen. The degree of interaction is minimized at chip layout design by separating the output devices, each to a separate corner of the chip. As noted, the thermal resistance values of the PDIP, PLCC and SOIC packages are improved by direct connection of the leads to the chip mounting pad. For a normal PC Board application, the thermal resistance coefficient for each package can be significantly lowered by increasing ground copper area on the PC board next to the ground pins of the IC. 4 CA3262A, CA3262 IB TEMP. SENSE CURRENT AMPLIFIER BANDGAP VOLT. REF. CURRENT SENSE FIGURE 3. EACH OUTPUT POWER DRIVER IS A COMPOSITE CIRCUIT WITH OVER-TEMPERATURE SENSE FOR THERMAL LIMITING AND OVER-CURRENT SENSE TO PROVIDE CURRENT LIMITING Typical Performance Curves 80 SUPPLY VOLTAGE (VCC) = 4.75V 0.7 60 0.6 COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) SUPPLY CURRENT (mA) SUPPLY VOLTAGE (VCC) = 5.5V 70 50 VIN = 2V, IOUT = 250mA (EACH) 40 30 20 THERMAL SHUTDOWN 0.5 IC = 700mA 0.4 0.3 0.2 0.1 10 VIN = 0V, IOUT = 0mA 0 -40 -20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (oC) -40 140 FIGURE 4A. TYPICAL SUPPLY CURRENT (PIN 11) CHARACTERISTICS -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (oC) FIGURE 4B. TYPICAL COLLECTOR-TO-EMITTER SATURATION VOLTAGE CHARACTERISTICS IN QUAD-GATED INVERTING POWER DRIVER OUTPUT 4 4 CLAMP DIODE FORWARD VOLTAGE (V) PROPAGATION DELAY TIME (µs) IC = 600mA 3 tPHL VIN 2 9, 10, 15, 16 (16) (17) (27) (28) VOUT 1, 3, 6, 8 (2) (4) (12) (14) 1 50% 50% tPLH tPHL (ON) (OFF) 50% 50% tPLH 0 3 2 IF = 1.5A IF = 1A 1 0 -40 -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (oC) -40 FIGURE 4C. TYPICAL PROPAGATION DELAY TIME CHARACTERISTICS -20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (oC) 140 FIGURE 4D. TYPICAL CLAMP-DIODE FORWARD VOLTAGE CHARACTERISTICS FIGURE 4. TYPICAL CHARACTERISTICS OF THE CA3262E 5 CA3262A, CA3262 Typical Performance Curves (Continued) 80 SUPPLY VOLTAGE (VCC) = 5.5V 0.7 COLLECTOR-TO-EMITTER SATURATION VOLTAGE (V) SUPPLY CURRENT (mA) 70 60 50 VIN HIGH IOUT = 500mA (EACH) 40 30 20 VIN LOW IOUT = 0mA 10 SUPPLY VOLTAGE (VCC) = 4.75 IOUT = 600mA 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 -20 0 20 40 60 80 100 120 -40 140 -20 0 FIGURE 5A. TYPICAL SUPPLY CURRENT (PIN 11) CHARACTERISTICS 40 60 80 100 120 140 FIGURE 5B. TYPICAL COLLECTOR-TO-EMITTER SATURATION VOLTAGE CHARACTERISTICS IN QUAD-GATED INVERTING POWER DRIVER OUTPUTS 4 CLAMP DIODE FORWARD VOLTAGE (V) 4 PROPAGATION DELAY TIME (µs) 20 AMBIENT TEMPERATURE (oC) AMBIENT TEMPERATURE (oC) tPHL 3 2 tPLH 9, 10, 15, 16 (16) (17) (27) (28) 1 VIN 50% tPLH tPHL 1, 3, 6, 8 VOUT (ON) (2) (4) (12) (14) (OFF) 50% 0 3 IF = 1.5A 2 IF = 1A 1 0 -40 -20 0 20 40 60 80 100 120 -40 140 AMBIENT TEMPERATURE (oC) -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (oC) FIGURE 5C. TYPICAL PROPAGATION DELAY TIME CHARACTERISTICS FIGURE 5D. TYPICAL CLAMP-DIODE FORWARD VOLTAGE CHARACTERISTICS FIGURE 5. TYPICAL CHARACTERISTICS OF THE CA3262AE AND CA3262AQ 2 1 1 0.5 3 2 1 1.5 PACKAGE DISSIPATION (W) PACKAGE DISSIPATION (W) 1.5 PACKAGE DERATING WITHOUT HEAT SINK 1 - CA3262AQ (PLCC) 2 - CA3262AE (PDIP), CA3262AM (SOIC) 1 PACKAGE DERATING WITH 2 SQ INCHES OF COPPPER PC BOARD HEAT SINK AREA 0.5 1 - CA3262AQ (PLCC) 2 - CA3262AM (SOIC) 3 - CA3262AE (PDIP) 0 0 -50 0 50 100 150 -50 AMBIENT TEMPERATURE (oC) 0 50 100 150 AMBIENT TEMPERATURE (oC) FIGURE 6A. DISSIPATION RATING CHART FOR PLCC, PDIP AND SOIC PACKAGES WITHOUT ADDITIONAL HEAT SINKS FIGURE 6B. DISSIPATION RATING CHART FOR PLCC, PDIP AND SOIC PACKAGES WITH 2 SQ. IN. OF COPPER PC BOARD HEAT SINKING 6 CA3262A, CA3262 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- A2 -C- SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.210 - 5.33 4 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 D1 0.005 - 0.13 A L D1 MIN A E D MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. - 5 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 19.68 16 16 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 7 CA3262A, CA3262 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) PIN (1) IDENTIFIER 0.004 (0.10) N28.45 (JEDEC MS-018AB ISSUE A) C 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L INCHES D2/E2 E1 E C L D2/E2 VIEW “A” D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN A1 A 0.045 (1.14) MIN MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 6 Rev. 1 3/95 -C- SEATING PLANE 0.026 (0.66) 0.032 (0.81) MILLIMETERS SYMBOL 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 8 CA3262A, CA3262 Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α NOTES: MILLIMETERS MAX A1 e α MIN 24 0o 24 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 9