DATASHEET

HIP4020
Data Sheet
September 17, 2015
Half Amp Full Bridge Power Driver for
Small 3V, 5V and 12V DC Motors
In the Functional Block Diagram of the HIP4020, the four
switches and a load are arranged in an H-Configuration so
that the drive voltage from terminals OUTA and OUTB can
be cross-switched to change the direction of current flow in
the load. This is commonly known as 4-quadrant load
control. As shown in the Block Diagram, switches Q1 and Q4
are conducting or in an ON state when current flows from
VDD through Q1 to the load, and then through Q4 to terminal
VSSB; where load terminal OUTA is at a positive potential
with respect to OUTB. Switches Q1 and Q4 are operated
synchronously by the control logic. The control logic
switches Q3 and Q2 to an open or OFF state when Q1 and
Q4 are switched ON. To reverse the current flow in the load,
the switch states are reversed where Q1 and Q4 are OFF
while Q2 and Q3 are ON. Consequently, current then flows
from VDD through Q3, through the load, and through Q2 to
terminal VSSA, and load terminal OUTB is then at a positive
potential with respect to OUTA.
Terminals ENA and ENB are ENABLE Inputs for the Logic A
and B Input Controls. The ILF output is an Overcurrent Limit
Fault Flag Output and indicates a fault condition for either
Output A or B or both. The VDD and VSS are the Power
Supply reference terminals for the A and B Control Logic
Inputs and ILF Output. While the VDD positive power supply
terminal is internally connected to each bridge driver, the
VSSA and VSSB Power Supply terminals are separate and
independent from VSS and may be more negative than the
VSS ground reference terminal. The use of level shifters in
the gate drive circuitry to the NMOS (low-side) output stages
FN3976.4
allows controlled level shifting of the output drive relative to
ground.
Features
• Two Independent Controlled Complementary MOS Power
Output Half H-Drivers (Full-Bridge) for Nominal 3V to 12V
Power Supply Operation
• Split Voltage Power Supply Option for Output Drivers
• Load Switching Capabilities to 0.5A
• Single Supply Range +2.5V to +15V
• Low Standby Current
• CMOS/TTL Compatible Input Logic
• Over-Temperature Shutdown Protection
• Overcurrent Limit Protection
• Overcurrent Fault Flag Output
• Direction, Braking and PWM Control
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• DC Motor Driver
• Relay and Solenoid Drivers
• Stepper Motor Controller
• Air Core Gauge Instrument Driver
• Speedometer Displays
• Tachometer Displays
• Remote Power Switch
• Battery Operated Switch Circuits
• Logic and Microcontroller Operated Switch
Ordering Information
PART NUMBER
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
PKG. DWG. #
HIP4020IB (No longer available, HIP4020IB
recommended replacement:
HIP4020IBZ)
-40 to 85
20 Ld SOIC
M20.3
HIP4020IBZ (Note)
HIP4020IBZ
-40 to 85
20 Ld SOIC (Pb-free)
M20.3
HIP4020IBZT (Note)
HIP4020IBZ
-40 to 85
20 Ld SOIC Tape and Reel (Pbfree)
M20.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC1997, 2005, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP4020
Block Diagram
HIP4020 (SOIC)
TOP VIEW
20 NC
2
19 VDD
B2
3
18 NC
ENB
4
17 OUTB
B1
5
16 VSSB
VSS 6
B1
B2
ENB
15 VSSA
A1
ENA
7
14 OUTA
A2
A1
8
13 NC
A2
9
12 VDD
NC 10
11 NC
ENA
ILF
OVER TEMP. AND CURRENT LIMIT,
LEVEL SHIFT, DRIVE CONTROL
1
CONTROL CONTROL
LOGIC A
LOGIC B
NC
ILF
VDD
VSS
2
ISENSE
ISENSE
Q3
Q1
OUTB
OUTA
TSENSE
LOAD
Pinout
Q2
Q4
ISENSE
VSSA
ISENSE
VSSB
FN3976.4
September 17, 2015
HIP4020
Absolute Maximum Ratings
Thermal Information
Supply Voltage; VDD to VSS or VSSA or VSSB . . . . . . . . . . . . .+15V
Neg. Output Supply Voltage, (VSSA, VSSB) . . . . . . . . . . . . (Note 1)
DC Logic Input Voltage (Each Input) . . . (VSS -0.5V) to (VDD +0.5V)
DC Logic Input Current (Each Input)  15mA
ILF Fault Output Current  15mA
Output Load Current, (Self Limiting, See Elec. Spec.)IO(LIMIT)
Thermal Resistance (Typical, Note 2)
JA (°C/W)
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . .
105
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions TA = 25°C
Typical Operating Supply Voltage Range, VDD . . . . . . . +3 to +12V
Low Voltage Logic Retention, Min. VDD. . . . . . . . . . . . . . . . . . . .+2V
Idle Supply Current; No Load, VDD = +5V. . . . . . . . . . . . . . . .0.8mA
Typical P+N Channel rDS(ON) , VDD = +5V, 0.5A Load . . . . . . . . 2
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. VSS is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in reference
to the VSS common ground by using a split supply for VDD (positive) to VSSA and VSSB (negative). For an uneven split in the supply voltage,
the Maximum Negative Output Supply Voltage for VSSA and VSSB is limited by the Maximum VDD to VSSA or VSSB ratings. Since the VDD pins
are internally tied together, the voltage on each VDD pins must be equal and common.
2. JA is measured with the component mounted on an evaluation PC board in free air.
3. Refer to the Truth Table and the VEN to VOUT Switching Waveforms. Current, IO refers to IOUTA or IOUTB as the Output Load current. Note that
ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1, A2, ENA or B1, B2, ENB
inputs. Refer to the Terminal Information Table for external pin connections to establish mode control switching. Figure 1 shows a typical
application circuit used to control a DC Motor.
Electrical Specifications
TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified
PARAMETER
SYMBOL
Input Leakage Current
ILEAK
TEST CONDITIONS
VDD = +15V
MIN
TYP
MAX
UNITS
-
-
25
nA
Low Level Input Voltage
VIL
VSS
-
0.8
V
High Level Input Voltage
VIH
2
-
VDD
V
ILF Output Low, Sink Current
IOH
VOUT = 0.4V, VDD = +12V
15
-
-
mA
ILF Output High, Source Current
IOL
VOUT = 11.6V, VDD = +12V
-
-
-15
mA
Input Capacitance
CIN
-
2
-
pF
P-Channel rDS(ON), Low Supply Voltage
rDS(ON)
VDD = +3V, ISOURCE = 250mA
-
1.6
2.1

N-Channel rDS(ON), Low Supply Voltage
rDS(ON)
VDD = +3V, ISINK = 250mA
-
1
1.5

P-Channel rDS(ON), High Supply Voltage
rDS(ON)
VDD = +12V, ISOURCE = 400mA
-
0.6
1.2

N-Channel rDS(ON), High Supply Voltage
rDS(ON)
VDD = +12V, ISINK = 400mA
-
0.5
1.1

OUTA, OUTB Source Current Limiting
IO(LIMIT)
VDD = +6V, VSS = 0V, VSSA = VSSB = -6V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-IO(LIMIT)
VDD = +6V, VSS = 0V, VSSA = VSSB = -6V
480
800
1500
mA
-
0.8
1.5
mA
4.2
4.5
-
V
-
0.4
0.6
V
2.415
2.6
-
V
-
0.25
0.375
V
Idle Supply Current; No Load
IDD
OUTA, OUTB Voltage High
VOH
ISOURCE = 450mA
OUTA, OUTB Voltage Low
VOL
ISINK = 450mA
OUTA, OUTB Voltage High
VOH
VDD = +3V, ISOURCE = 250mA
OUTA, OUTB Voltage Low
VOL
VDD = +3V, ISINK = 250mA
OUTA, OUTB Source Current Limiting
IO(LIMIT)
VDD = +12V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-IO(LIMIT)
VDD = +12V
480
800
1500
mA
OUTA, OUTB Source Current Limiting
IO(LIMIT)
VDD = +3V
480
625
1500
mA
OUTA, OUTB Sink Current Limiting
-IO(LIMIT)
VDD = +3V
480
800
1500
mA
3
FN3976.4
September 17, 2015
HIP4020
Electrical Specifications
TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
-
145
-
°C
-
2.5
-
s
tr
-
4
-
s
tPHL
-
0.1
-
s
tf
-
0.1
-
s
Thermal Shutdown
TSD
Response Time: VEN to VOUT
Turn-On: Prop Delay
tPLH
Rise Time
Turn-Off: Prop Delay
Fall Time
TEST CONDITIONS
IO = 0.5A (Note 3)
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
12, 19
VDD
Positive Power Supply pins; internally common and externally connect to the same Positive Supply (V+).
15
VSSA
Negative Power Supply pin; Negative or Ground return for Switch Driver A; externally connect to the Supply
(V-).
16
VSSB
Negative Power Supply pin; Negative or Ground return for Switch Driver B; externally connect to the Supply
(V-).
6
VSS
Common Ground pin for the Input Logic Control circuits. May be used as a common ground with VSSA and
VSSB.
8, 5
A1, B1
Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively. When
connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a
motor.
9, 3
A2, B2
Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be
controlled from the same logic signal to activate Dynamic Braking of a motor.
7, 4
ENA, ENB
Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respective
output is in a high impedance (Z) off-state. Since each Switch Driver is independently controlled, OUTA and
OUTB may be a separately PWM controlled as Half H-Switch Drivers.
14, 17
OUTA, OUTB
2
ILF
Respectively, Switch Driver A and Switch Driver B Output pins.
Current Limiting Fault Output Flag pin; when in a high logic state, signifies that Switch Driver A or B or both
are in a Current Limiting Fault Mode.
4
FN3976.4
September 17, 2015
HIP4020
V+
VDD
B2
ENB
OFF
A1
DIRECTION
CONTROL
LOGIC A
A2
OVER-TEMP LIMIT
ON
LEVEL SHIFTER
AND OC/OT LIMITER
CONTROL
LOGIC B
BRAKE
Q1
D1
D2
Q2
LEVEL SHIFTER
AND OC/OT LIMITER
B1
Q3
D3
D4
Q4
ENA
ENABLE
VSSA
VSS
OUTA
OUTB
(LOGIC
GROUND)
ILF
VSSB
LOAD
V-
FIGURE 1. TYPICAL MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL
TRUTH TABLE
SWITCH DRIVER A
VEN
SWITCH DRIVER B
INPUTS
OUTPUT
INPUTS
OUTPUT
A1 A2 ENA
OUTA
B1 B2 ENB
OUTB
H
L
H
OH
L
L
H
OH
L
L
H
OL
H
L
H
OL
H
H
H
OL
L
H
H
OL
L
H
H
OL
H
H
H
OL
X
X
L
Z
X
X
L
Z
VOUT
50%
tPLH
90%
10%
50%
tr
50%
VEN
tPHL
VOUT
L = Low logic level; H = High logic level
Z = High Impedance (off state)
OH = Output High (sourcing current to the output terminal)
OL = Output Low (sinking current from the output terminal)
X = Don’t Care
10%
90%
50%
tf
SWITCHING WAVEFORMS
FIGURE 2.
Application
The HIP4020 is designed to detect load current feedback
from sampling resistors of low value in the source
connections of the output drivers to VDD, VSSA and VSSB
(See Figure 1). When the sink or source current at OUTA or
OUTB exceeds the preset OC (Overcurrent) limiting value of
550mA typical, the current is held at the limiting value. If the
OT (Over-Temperature) Shutdown Protection limit is
exceeded, temperature sensing BiMOS circuits limit the
junction temperature to 150°C typical.
5
The circuit of Figure 1 shows the Full H-Switch in a small motordrive application. The left (A) and right (B) H-Switch’s are
controlled from the A and B inputs via the A and B CONTROL
LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The
circuit is intended to safely start, stop, and control rotational
direction for a motor requiring no more than 0.5A of supply
current. The stop function includes a Dynamic Braking feature.
With the ENABLE Inputs Low, the MOS transistors Q1 and Q3
are OFF; which cuts-off supply current to OUTA and OUTB.
With the BRAKE terminal Low and ENABLE Inputs High, either
Q1 and Q4 or Q3 and Q2 will be driven into conduction by the
FN3976.4
September 17, 2015
HIP4020
DIRECTION Input Control terminal. The MOS output transistor
pair chosen for conduction is determined by the logic level
applied to the DIRECTION control; resulting in either clockwise
(CW) or counter-clockwise (CCW) shaft rotation.
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both Q2 and Q4 are
driven high. Current flowing through Q2 (from the motor
terminal OUTA) at the moment of Dynamic Braking will
continue to flow through Q2 to the VSSA and VSSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through Q4 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
Q4 to the VSSB and VSSA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where VDD to VSS are the Power Supply reference
terminals for the Control Logic, the lowest practical supply
voltage for proper logic control should be no less than 2.0V.
The VSSA and VSSB terminals are separate and
independent from VSS and may be more negative than the
VSS ground reference terminal. However, the maximum
supply level from VDD to VSSA or VSSB must not be greater
than the Absolute Maximum Supply Voltage rating.
Terminals A1, B1, A2, B2, ENA and ENB are internally
connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level
Converters for TTL or CMOS Input Logic. These inputs are
designed to typically provide ESD protection up to 2kV.
However, these devices are sensitive to electrostatic
discharge. Proper I.C. handling procedures should be
followed.
VDD
INPUT
LEVEL
CONV.
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
VDD
A1
(DIR)
P-DR
LIMIT
A2
(BRAKE)
OT AND OC
PROTECT
Q1
D1
OUTA
Q2
D2
N-DR
LIMIT
ENA
(ENABLE)
VSSA
VDD
B1
(DIR)
P-DR
LIMIT
B2
(BRAKE)
OT AND OC
PROTECT
Q3
D3
OUTB
Q4
D4
N-DR
LIMIT
ENB
(ENABLE)
VSSB
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
6
FN3976.4
September 17, 2015
HIP4020
P-CHANNEL DRAIN CURRENT (mA)
Typical Performance Curves
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0.5
1
2
VDD = 12V
VDD = 5V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VDD = 3V
0.7 0.8 0.9 1.0 1.1 1.2 1.3
DRAIN-TO-SOURCE VOLTAGE (V)
1.4
TYPICAL CURRENT
LIMITING
1.5
1.6
1.7
1.8
1.9
2.0
N-CHANNEL DRAIN CURRENT (mA)
FIGURE 5. TYPICAL CHARACTERISTIC OF THE P-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE,
TAMBIENT = 25°C
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0.5
1
VDD = 5V
2
VDD = 3V
TYPICAL CURRENT
LIMITING
VDD = 12V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
DRAIN-TO-SOURCE VOLTAGE (V)
SHORT CIRCUIT CURRENT (mA)
FIGURE 6. TYPICAL CHARACTERISTIC OF THE N-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE,
TAMBIENT = 25°C
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
N-CHANNEL
P-CHANNEL
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0
VDD SUPPLY VOLTAGE (V)
FIGURE 7. TYPICAL CHARACTERISTIC OF THE P AND N OUTPUT DRIVER SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE,
TAMBIENT = 25°C
7
FN3976.4
September 17, 2015
HIP4020
Typical Performance Curves
(Continued)
SATURATION VOLTAGE, VDD - VOUT (V)
0.65
HIP4020 SPLIT 5V COMMON GROUND
VSAT vs LOAD CURRENT
VDD = +5V
VSS = VSSA = VSSB = GND
0.60
0.55
0.50
HIGH
0.45
LOW
0.40
0.35
0.30
0.25
VSAT(P)
VSAT(N)
0.20
0.15
0.10
0.05
0.00
0
100
200
300
OUTPUT CURRENT, IO (A)
400
500
FIGURE 8. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A +5V SUPPLY, TAMBIENT = 25°C
SATURATION VOLTAGE, VDD - VOUT (V)
0.70
HIP4020 SPLIT 3V
VSAT vs LOAD CURRENT
VDD = +3V
VSS = GND
VSSA = VSSB = -3V
0.65
0.60
0.55
0.50
HIGH
0.45
0.40
LOW
0.35
VSAT(P)
0.30
VSAT(N)
0.25
0.20
0.15
0.10
0.05
0.00
0
100
200
300
400
OUTPUT CURRENT, IO (A)
500
600
700
FIGURE 9. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A 3V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C
SATURATION VOLTAGE, VDD - VOUT (V)
0.70
0.65
HIP4020 SPLIT ±6V
VSAT vs LOAD CURRENT
VDD = +6V
VSS = GND
VSSA = VSSB = -6V
0.60
0.55
0.50
0.45
0.40
HIGH
0.35
LOW
0.30
0.25
0.20
VSAT(P)
0.15
VSAT(N)
0.10
0.05
0.00
0
100
200
300
400
OUTPUT CURRENT, IO (A)
500
600
FIGURE 10. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A 6V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C
8
FN3976.4
September 17, 2015
HIP4020
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 17, 2015
FN3976.4
CHANGE
- Updated Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD M20.3 to latest revision changes are as follow:
Top View:
Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion)
Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion)
Side View:
Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion)
Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion)
Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994"
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9
FN3976.4
September 17, 2015
HIP4020
Package Outline Drawing
M20.3
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 3, 2/11
20
INDEX
AREA
7.60
7.40
1
2
10.65
10.00
0.25 (0.10) M B M
3
3
TOP VIEW
13.00
12.60
SEATING PLANE
2
2.65
2.35
5
0.75
1.27
BSC
0.49
0.35
7
0.25 (0.10) M
0.25
0.30
MAX
C A M B S
1.27
0.40
x 45°
8°
MAX
0.10 (0.004)
SIDE VIEW
DETAIL "X"
0.32
0.23
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
(0.60)
1.27 BSC
2. Dimension does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
20
(2.00)
3. Dimension does not include interlead lash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
(9.40mm)
5. Dimension is the length of terminal for soldering to a substrate.
6. Terminal numbers are shown for reference only.
7. The lead width as measured 0.36mm (0.14 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
8. Controlling dimension: MILLIMETER.
1
2
3
9. Dimensions in ( ) for reference only.
TYPICAL RECOMMENDED LAND PATTERN
10
10. JEDEC reference drawing number: MS-013-AC.
FN3976.4
September 17, 2015