酸化物半導体を用いた全印刷薄膜トランジスタアレイの開発 All-Printed Oxide Thin Film Transistor Arrays for High Resolution Active Matrix 松本 真二* Shinji MATSUMOTO 安部 有希* 中村 美樹子* Mikiko ABE Yuki NAKAMURA 早乙女 遼一* Ryohichi SAOTOME 要 旨 新江 定憲* Sadanori ARAE 植田 尚之* Naoyuki UEDA 曽根 雄司* Yuji SONE 山田 平野 由希子* Yukiko HIRANO 勝幸* Katsuyuki YAMADA _________________________________________________ インクジェット法とスピンコート法を用いて，酸化物半導体を活性層に用いた100ppi RGBアクティブマトリックスの薄膜トランジスタアレイをマスクレスで製造するプロセス を開発した．熱酸化膜付シリコン基板上に製造したTFTは，平均電界効果移動度7.49cm2/Vs を示した．また，ドーピングによる活性層のキャリア制御を検討し，特性ばらつきの少ない 酸化物TFTアレイが製造できることを示した．さらに，新規の高誘電率酸化物絶縁体をゲー ト絶縁膜に用いた全印刷TFTは，平均電界効果移動度2.54cm2/Vsを示した．全印刷プロセス によって，ノーマリーオフの特性と立ち上がり電圧の揃った酸化物TFTアレイが実現できる ことを示した． ABSTRACT _________________________________________________ We have demonstrated oxide TFT arrays for 100 ppi RGB active matrix fabricated by inkjet printing and spin coating without photolithography and mask process. The average mobility of TFTs was 7.49 cm2/Vs on a thermally oxidized SiO2 /Si substrate. We have also shown the method of controlling the carrier generation by n-type doping technique and the printed oxide TFT arrays with small variation properties were obtained. Moreover, in the result of combination a novel oxide high-k gate insulator and the n-type doping to active layer, all-printed oxide TFTs on a glass substrate exhibited the average mobility of 2.54 cm2/Vs. Normally-off operation and excellent small variation of the turn-on voltage were obtained by the all printing processes. * 研究開発本部 未来技術総合研究センター Future Technology Research Center, Research and Development Group Ricoh Technical Report No.39 49 JANUARY, 2014 1. as the gate and source-drain electrodes, gate insulator, Background and semiconductor. Moreover, all-printed fabrication requires consistency against every process such as In recent years, researches of printing fabrication printing and heating of each layer from gate to technologies for electronics devices are activating. semiconductor. Therefore in the previous reports about Especially, direct patterning process like an inkjet solution processed oxide TFTs, photolithography and/or printing attracts big attention as the resource and energy mask processes have been used for patterning of the saving conventional source-drain electrodes and/or the semiconductor layers. photolithography and mask process which have been So there are no reports about all-printed process of oxide used as manufacturing of today’s display panels, it has TFTs. process. Compared to several advantages such as scalability to variable substrate size and small initial investment Recently we have reported the method of controlling for the carrier generation by substitutional doping technique manufacturing facilities, then it can realize on-demand, in MgIn2O4 TFT wide variety and variable quantities productions. high-k gate insulators for oxide TFTs 7). Building on the Therefore direct printing fabrication without mask technologies we have demonstrated all-printed oxide process is an expected manufacturing technology in TFT arrays for 100 ppi RGB active matrix fabricated by future. inkjet printing and spin coating in this paper. 6) and fabrication of the printed oxide After Nomura et al. disclosed a thin film transistor (TFT) using amorphous InGaZnO4 1) (a-IGZO) , 2. numerous studies on oxide semiconductor TFTs have been extensively carried out. Because of several advantages to amorphous silicon TFTs and 2-1 polycrystalline silicon TFTs such as high uniformity and Experimental Details and Results Fabrication of Gate Layer stability of device performance and small off-current For TFT fabrication we adopted bottom-gate and level, oxide TFTs have become the main candidate of bottom-contacts geometry. Because of endurance against backplane for large size and high resolution display high temperature and low resistivity, the gate layer was panels. In fact, the 32 inch active matrix LCD device manufactured from Au nano-particle ink by inkjet with printing on a glass substrate. The baking temperature 4K/2K resolution (140 ppi) has become was 250 C. commercially available made by traditional process with photolithography and vacuum film formation. Figure 1 shows a photograph of the gate layer for 100 In addition, there are many reports about solution ppi RGB active matrix with 2T1C circuits. processed oxide TFTs aimed at the resource, energy and 2) cost saving processes. So far, IGZO , IZO 3,4) The sub-pixel size and number are 85 x 255 μm and , and In2O3 18 x 9 arrays, respectively. The typical line width and based films , which were fabricated by solution process thickness were 10 μm and 90 nm, respectively. The such as spin coating, were used as active layers of oxide resistivity was evaluated by 2 wire method and typically TFTs and the high field effect mobility were obtained. 10 μΩcm, which value was enough low for the gate 5) electrodes. However, in fabrication of the oxide TFT and the active matrix device by using printing technique, there are many requirements for materials on each layer such Ricoh Technical Report No.39 50 JANUARY, 2014 500 m electrodes and OSC layers. The inset figure shows the Fig.1 expanded view of the channel region. Photograph of 100 ppi 2T1C gate layer manufactured from Au nano-particle ink. PAD OSC SD PAD 2-2 Fabrication of SD and OSC Layer Fig.2 Photographs of ITO SD and OSC layers printed on a Si/SiO2 substrate. 2-3 TFT Characteristics of N-typed Doped To evaluate electrical properties of printed oxide TFTs, whose source and drain (SD) electrodes and oxide semiconductor (OSC) layer were patterned by inkjet printing, we fabricated SD layer and OSC layer on a and Non-doped ISO TFT thermally oxidized SiO2/Si substrate. For the SD layer, we choose ITO electrode, which is expected to form excellent To evaluate TFT characteristics, the heavily doped Si electrical contact with oxide semiconductor. ITO nano- substrate and the thermally oxidized SiO2 layer (200 nm particle ink was used as the SD ink. The maximum baking thick) served as the gate and the gate insulator, temperature was 400 C. The typical line width and respectively. The TFT properties were measured by thickness were 10 μm and 100 nm, respectively. For Keithley fundamental evaluations of transistor characteristics, the system. 4200SCS semiconductor characterization small contact pads were patterned near the channel region. Figure 3 shows the IDS-VGS curves of the 76 non- The channel width and length (W/L) were defined by the doped ISO TFTs manufactured from ink A, as baked SD electrodes and measured by using optical microscope. (Fig.3 (a)) and after post-annealing (Fig.3 (b)). The field The typical W/L was 30/10 μm. effect mobility was calculated with conventional metal- Next, the OSC layer was formed on the channel oxide-semiconductor field effect transistor model at VGS regions by inkjet printing. An indium strontium oxide ~ 20 V. Figure 3 (c) shows the histogram of the mobility based oxide semiconductor was adopted for the TFTs. for the 76 non-doped ISO TFTs. The TFTs, as baked and We prepared two kinds of OSC inks; the ink A was a after post-annealing, exhibited the mean value in the solution for indium strontium oxide (ISO) and the ink B mobility of 7.94 and 7.49 cm2/Vs, the threshold voltage was that for n-type doped indium strontium oxide. To Vth of -4.9 and -3.2 V, the S-value of 0.47 and 0.47 remove residual solvent and other organic components, a V/dec, and the on/off current ratio over 108, respectively. baking process was performed at 400 °C for 1 hr. Post- The maximum mobility as baked and after post- annealing was carried out at 300 C for 1 hr to annealing reaches 10.57 and 10.49 cm2/Vs, respectively, investigate the effect of the heating process for the active which values are the top performance in oxide TFTs layer. Figure 2 shows the photographs of the printed SD patterned by inkjet printing. Ricoh Technical Report No.39 51 JANUARY, 2014 Figure 4 shows the IDS-VGS curves of the n-type doped mobility in the n-type doped TFTs tend to decrease under ISO TFTs manufactured from ink B, as baked (Fig.4 (a)) post-annealing process. On the contrary, the non-doped and after post-annealing (Fig.4 (b)), and the histogram of TFTs show an opposite tendency. the mobility for the 32 TFTs (Fig.4 (c)). The n-type One of the reasons that the non-doped ISO TFTs doped ISO TFTs, as baked and after post-annealing, exhibited the large amount of deviation in the mobility exhibited the mean value in the mobility of 2.46 and 2.66 both as baked and after post-annealing is presumed the 2 cm /Vs, the threshold voltage Vth of 2.55 and 1.34 V, the generation or extinction of oxygen vacancy in the active S-value of 0.80 and 0.70 V/dec, and the on/off current layer. The electron carriers generated by oxygen vacancy 8 ratio over 10 , respectively. Although the average mainly contribute to the property of the active layer. So mobility of the n-type doped ISO TFTs is lower than that in order to obtain the homogeneous device performance, of the non-doped ones, the standard deviation of the the amount of oxygen vacancy of the active layer in the mobility in the doped TFTs is better than that in the non- TFT array must strictly be controlled, but it seems doped ones both as baked and after post-annealing (Fig.3 difficult only by adjusting the heating conditions. (c), 4 (c)). In addition, the standard deviation of the 1e-3 76 TFTs 1e-9 1e-11 1e-7 Frequency 1e-7 1e-9 1e-11 1e-13 1e-13 VDS = 20 V 1e-15 -15 0 15 VGS (V) 30 20 after post-annealing average 7.49 1.67 10 VDS = 20 V 0 1e-15 -30 as baked average 7.94 1.34 1e-5 IDS (A) 1e-5 IDS (A) 30 1e-3 76 TFTs -30 -15 0 15 VGS (V) (a) 10111112 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 910 Mobility (cm2/Vs) 30 (c) (b) Fig.3 (a) Transfer curves as baked, (b) after post-annealing, (c) the histogram of the mobility for 76 non-doped ISO TFTs. 1e-3 1e-3 as baked 32 TFTs 1e-5 1e-7 1e-7 1e-9 1e-11 10 Frequency 1e-5 IDS (A) IDS (A) 32 TFTs 1e-9 1e-11 1e-13 VDS = 20 V 1e-15 -15 0 15 VGS (V) (a) 30 after post-annealing average 2.66 0.28 1e-13 VDS = 20 V 1e-15 -30 5 average 2.46 0.31 0 -30 -15 0 15 VGS (V) (b) 30 1.41.61.8 1.6 2 22.22.42.62.8 2.4 2.83 3.23.4 3.2 Mobility (cm2/Vs) (c) Fig.4 (a) Transfer curves as baked, (b) after post-annealing, (c) the histogram of the mobility for 32 n-type doped ISO TFTs. Ricoh Technical Report No.39 52 JANUARY, 2014 On the other hand, in the case of the n-type doped ISO spin-coated LRO. As a reference, the data of the RF TFTs, electron carriers generated by the doping dominate magnetron sputtered SiO2 film are also shown in the the property of the active layer, and the oxygen vacancy figures. The SiO2 film showed the k of 3.9 which value does not contribute to the device performance. Therefore, is equal to that of the thermally oxidized SiO2 film and the n-type doped ISO TFTs exhibit the better device the very low tan δ over all frequency range. For LMO1 uniformity as baked and after post-annealing process (La/Mg=1), LSO2 (La/Sr=2), LBO8 (La/Ba=8), and than the non-doped ones. This result means that the LSXO, which were added a little modification to LSO2, substitutional doping even in the solution process is the k at 1 kHz was 6.5, 9.9, 12.2, and 12.8 respectively. effective to enlarge the margin of the fabrication Tan δ of these samples was low enough for the actual processes in the same way of the doped IMO TFT application less than 0.02 under 100 kHz. 6) fabricated by the vacuum process as reported before . 14 2-4 Fabrication and Characteristics of Novel LSXO 12 Printed Oxide High-k Gate Insulators LBO8 10 kk As the gate insulator (GI) materials, we selected the novel printed oxide high-k gate insulators (POGI)7). The 6 POGI were manufactured from lanthanum alkaline earth 4 oxides (LRO). The inks of POGI were prepared by LSO2 8 LMO1 SiO2 (Sputtered) 2 dissolving 2-ethylhexanoate of lanthanum, magnesium, 100 strontium, and barium in toluene. The atomic ratio of 1k 10k Freq. Hz Freq. /(Hz) 100k 1M lanthanum by alkaline earth metal was changed from 1 to 11 (denoted by LRO1 to LRO11). Accordingly, colorless, Fig.5 transparent inks for forming LRO films were prepared. Frequency dependence of the dielectric constant k for POGI films. The POGI films were formed by spin coating on glass substrates. Then, a heating process was performed at 120 °C for 1 hr and 400 °C for 3 hrs in air. The thickness of the LRO films was controlled from 150 to 350 nm. For the dielectric property measurements, 0.06 SiO2 (Sputtered) 0.04 LMO1 LSO2 LBO8 LSXO we tan tan fabricated the capacitor devices, which have a structure of Al/LRO/Al. The aluminum electrodes were formed by vacuum evaporation via a metal mask and the thickness was 100 nm. As a reference, the capacitor device was 0.02 0.00 also fabricated with a SiO2 insulator film deposited by 100 RF magnetron sputtering method. The capacitor area was 1k 10k 100k 1M Freq. Hz Freq. /(Hz) 1.0 mm2. The dielectric properties were measured by 2 wire method using Agilent 4284 LCR meter. Figure 5 and Figure 6 show the frequency dependence of the Fig.6 dielectric constant k and the dielectric loss (tan ) of the Ricoh Technical Report No.39 53 Frequency dependence of the dielectric loss (tan) for POGI films. JANUARY, 2014 2-5 Fabrication and Characteristics of AllPrinted Oxide TFT In the next step, we fabricated all-printed oxide TFT arrays on a glass substrate. The gate lines for switching transistors of active matrix were solely fabricated by inkjet printing to evaluate TFT properties. The process in PAD detail was the same in the section 2-1. SD OSC As a GI layer we selected LSXO film and it was spin PAD coated by the same way described in the section 2-4. The Fig.7 thickness of the GI layer was 150 nm. Photographs of all-printed oxide TFTs on a glass substrate. Next, SD and OSC layers were fabricated by the same way described in the section 2-2. In this section, ink-B This is the first report of the all-printed oxide TFT was used for the OSC layer. Figure 7 shows photographs array which was patterned in the high resolution by of the all-printed oxide TFT arrays and the inset is the printing technique. Moreover, small standard deviation expanded view of the channel region. of the mobility was obtained. This result is consistent Figure 8 shows the IDS-VGS curves (Fig.8 (a)) and the with the case of the n-type doped TFTs fabricated on histogram of the mobility for the 22 all-printed n-type Si/SiO2 substrate in figure 4. On the other hand, the doped ISO TFTs (Fig.8 (b)). The device performance of average value of the turn-on voltage VON, at which the the all-printed oxide TFTs after 300 C post-annealing drain current starts to increase in the subthreshold region, exhibited the mean value in the mobility of 2.54 cm2/Vs, was -7.19 V. The TFTs operated normally ON and the the threshold voltage Vth of 7.2 V, the S-value of 0.92 variation of the VON value was still large, these were V/dec, and the on/off current ratio over 108, respectively. disadvantageous characteristics as switching transistors. Although the mobility of the TFTs is almost equal to that Finally, figure 9 shows the case that active layer was of the doped TFTs on Si/SiO2 substrate in figure 4, the baked at 350 C. The TFTs exhibited the mean value in on-current is about three times larger because of using of the mobility of 1.55 cm2/Vs (Fig.9 (b)), which was a 1e-3 10 22 TFTs Frequency IDS (A) 1e-5 1e-7 1e-9 1e-11 1e-13 8 after post-annealing average 2.54 0.32 6 4 10 Frequency the high-k gate insulator. 8 after post-annealing average -7.19 1.89 6 4 2 2 0 0 VDS = 10 V 1e-15 -30 -15 0 15 VGS (V) (a) 30 11 1.6 1.6 2.2 2.8 2.8 3.4 3.4 2.2 Mobility (cm2/Vs) (b) -13 -11 -11 -9 -9 -7 -7 -5 -5 -3 -3 -1 -1 11 33 -13 VON (V) (c) Fig.8 (a) Transfer curves after post-annealing, (b) the histogram of the mobility, (c) the histogram of the VON for 22 allprinted n-type doped ISO TFTs. Ricoh Technical Report No.39 54 JANUARY, 2014 30 60 as baked average 1.55 0.26 81 TFTs 25 Frequency IDS (A) 1e-5 1e-7 1e-9 1e-11 1e-13 20 15 10 5 50 Frequency 1e-3 40 as baked average 2.09 0.32 30 20 10 VDS = 10 V 1e-15 0 -30 -15 0 15 30 VGS (V) 0 11 1.6 2.2 2.2 2.8 2.8 3.4 3.4 1.6 Mobility (cm2/Vs) (a) -13 -11 -11 -9 -9 -7 -7 -5 -5 -3 -3 -1 -1 11 -13 VON (V) 33 (c) (b) Fig.9 (a) Transfer curves as baked, (b) the histogram of the mobility, (c) the histogram of the VON for 81 all- printed n-type doped ISO TFTs. little smaller than the 400 C baked TFTs. But the mean deviation in the mobility both as baked and after post- value and the standard deviation of the VON were 2.09 V annealing. This result indicates that the method of the n- and 0.32 V, respectively (Fig.9 (c)). Excellent small type doping to active layer has a great advantage even in variation of the VON value and normally-off operation the solution process; it is important for total fabrication were obtained. Although the detail mechanism about the of the active matrix backplane. difference of these results is not clear, the high In the result of combination the novel printed high-k performance and small variation will be satisfied all gate insulator and the technologies described above, the together even with the all-printed TFT. average mobility of 2.54 cm2/Vs was achieved in allprinted oxide TFTs. Moreover, excellent small variation 3. of TFT characteristics and normally-off operation were Conclusion obtained by the all printing processes. This is the great breakthrough in the technology for all-printed oxide For the first time we have developed all-printed oxide active matrix backplane fabrication. TFT arrays for 100 ppi RGB active matrix fabricated by inkjet printing and spin coating. Fine channel regions References ________________________________ were fabricated without photolithography and mask 1) process. K. Nomura et al.: Room-temperature fabrication of transparent flexible thin-film transistors using In the case of the non-doped ISO TFTs fabricated on amorphous oxide semiconductors, Nature, Vol.432, Si/SiO2 substrates, the average and maximum mobility pp.488-492 (2004). after post-annealing are 7.49 and 10.49 cm2/Vs, 2) Y. S. Rim et al.: High Performance Solution- respectively. This is the highest device performance Processed IGZO TFTs Formed by Using a High- among the TFTs whose source-drain electrodes and the Pressure Annealing Method, SID 11 Digest, active layer were patterned by inkjet printing. pp.1148-1150 (2011). We have also shown the method of controlling the carrier generation by n-type doping to the active layer. The n-type doped TFTs exhibited the small amount of Ricoh Technical Report No.39 55 JANUARY, 2014 3) K.K. Banger et al.: Low-temperature, highperformance, solution-processed metal oxide thinfilm transistors formed by a ‘sol-gel on chip’ process, Nature Materials, Vol.10, pp.45-50 (2011). 4) L. Lu et al.: High Performance Indium Zinc Oxide Thin-Film Transistors Fabricated by SolutionProcess at Low Temperature, IDW/AD ’12, pp.771772 (2012). 5) S. Botnaras et al.: Solution Processed Amorphous In2O3-Based TFT Performance Depending on the Semiconductor Film Morphology, IDW/AD ’12, pp.437-440 (2012). 6) Y. Hirano et al.: Novel Thin Film Transistors with Oxide Semiconductor MgIn2O4 with and without Substitutional Doping, Proc. EuroDisplay 2011, (2011). 7) N. Ueda et al.: Novel Printed Oxide High-k Gate Insulators, Proc. EuroDisplay 2011 (2011). Ricoh Technical Report No.39 56 JANUARY, 2014