ISL6609, ISL6609A ® Data Sheet April 27, 2009 FN9221.2 Synchronous Rectified MOSFET Driver Features The ISL6609, ISL6609A is a high frequency, MOSFET driver optimized to drive two N-Channel power MOSFETs in a synchronous-rectified buck converter topology. This driver combined with an Intersil ISL63xx or ISL65xx multiphase PWM controller forms a complete single-stage core-voltage regulator solution with high efficiency performance at high switching frequency for advanced microprocessors. • Drives Two N-Channel MOSFETs The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Each driver is capable of driving a 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. • ISL6605 Replacement with Enhanced Performance • Low Bias Supply Current The ISL6609, ISL6609A features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. • Pb-Free (RoHS Compliant) The ISL6609, ISL6609A also features an input that recognizes a high-impedance state, working together with Intersil multiphase PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from negative output voltage damage. In addition, the ISL6609A’s bootstrap function is designed to prevent the BOOT capacitor from overcharging, should excessively large negative swings occur at the transitions of the PHASE node. 1 • Adaptive Shoot-Through Protection • 0.4Ω On-Resistance and 4A Sink Current Capability • Supports High Switching Frequency - Fast Output Rise and Fall - Ultra Low Three-State Hold-Off Time (20ns) • BOOT Capacitor Overcharge Prevention (ISL6609A) • Low VF Internal Bootstrap Diode • Enable Input and Power-On Reset • QFN Package - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No Leads-Product Outline - Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile Applications • Core Voltage Supplies for Intel® and AMD® Microprocessors • High Frequency Low Profile High Efficiency DC/DC Converters • High Current Low Voltage DC/DC Converters • Synchronous Rectification for Isolated Power Supplies Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2009. All Rights Reserved. Intel® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners. ISL6609, ISL6609A Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL6609CBZ ISL66 09CBZ 0 to +70 8 Ld SOIC M8.15 ISL6609CBZ-T* ISL66 09CBZ 0 to +70 8 Ld SOIC M8.15 ISL6609CRZ 609Z 0 to +70 8 Ld 3x3 QFN L8.3x3 ISL6609CRZ-T* 609Z 0 to +70 8 Ld 3x3 QFN L8.3x3 ISL6609IBZ ISL66 09IBZ -40 to +85 8 Ld SOIC M8.15 ISL6609IBZ-T* ISL66 09IBZ -40 to +85 8 Ld SOIC M8.15 ISL6609IRZ 09IZ -40 to +85 8 Ld 3x3 QFN L8.3x3 ISL6609IRZ-T* 09IZ -40 to +85 8 Ld 3x3 QFN L8.3x3 ISL6609ACBZ 6609 ACBZ 0 to +70 8 Ld SOIC M8.15 ISL6609ACBZ-T* 6609 ACBZ 0 to +70 8 Ld SOIC M8.15 ISL6609ACRZ 09AZ 0 to +70 8 Ld 3x3 QFN L8.3x3 ISL6609ACRZ-T* 09AZ 0 to +70 8 Ld 3x3 QFN L8.3x3 ISL6609AIBZ 6609 AIBZ -40 to +85 8 Ld SOIC M8.15 ISL6609AIBZ-T* 6609 AIBZ -40 to +85 8 Ld SOIC M8.15 ISL6609AIRZ 9AIZ -40 to +85 8 Ld 3x3 QFN L8.3x3 ISL6609AIRZ-T* 9AIZ -40 to +85 8 Ld 3x3 QFN L8.3x3 ISL6609AIRZ-TK* 9AIZ -40 to +85 8 Ld 3x3 QFN L8.3x3 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts ISL6609, ISL6609A (8 LD QFN) TOP VIEW UGATE 1 8 PHASE UGATE PHASE ISL6609, ISL6609A (8 LD SOIC) TOP VIEW BOOT 2 7 EN 8 7 PWM 3 6 VCC GND 4 5 LGATE 66 EN BOOT 1 PWM 2 2 3 4 GND LGATE 5 VCC FN9221.2 April 27, 2009 ISL6609, ISL6609A Block Diagram ISL6609 and ISL6609A RBOOT VCC BOOT EN UGATE VCC PWM PHASE SHOOTTHROUGH PROTECTION 4.25k CONTROL LOGIC VCC 4k LGATE GND INTEGRATED 3Ω RESISTOR (RBOOT) AVAILABLE ONLY IN ISL6609A 3 FN9221.2 April 27, 2009 ISL6609, ISL6609A Typical Application - Multiphase Converter Using ISL6609 Gate Drivers VIN +5V +5V +5V BOOT VCC FB COMP EN VCC VSEN PWM1 PWM ISL6609 PHASE PWM2 PGOOD RUGPH UGATE LGATE PWM CONTROL (ISL63XX or ISL65XX) ISEN1 VID (OPTIONAL) +VCORE +5V ISEN2 VIN BOOT VCC FS/EN GND EN UGATE RUGPH PWM ISL6609 PHASE LGATE RUGPH IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS (SEE APPLICATION INFORMATION SECTION ON PAGE 8) 4 FN9221.2 April 27, 2009 ISL6609, ISL6609A Absolute Maximum Ratings Thermal Information Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . -0.3V to 27V (DC) or 36V (<200ns) BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 27V (DC) GND -8V (<20ns Pulse Width, 10μJ) to 30V (<100ns) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10μJ) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C Thermal Resistance (Notes 1, 2, 3) θJA(°C/W) θJC(°C/W) SOIC Package (Note 1) . . . . . . . . . . . . 110 N/A QFN Package (Notes 2, 3). . . . . . . . . . 95 36 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to 100°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 3. θJC, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details. Electrical Specifications These specifications apply for TA = -40°C to 100°C, unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 132 - μA POR Rising - 3.4 4.2 POR Falling 2.2 3.0 - - 400 - mV VCC SUPPLY CURRENT Bias Supply Current IVCC PWM pin floating, VVCC = 5V Hysteresis PWM INPUT Sinking Impedance RPWM_SNK 2.75 4 5.5 kΩ Source Impedance RPWM_SRC 3 4.25 5.75 kΩ Three-State Rising Threshold VVCC = 5V (100mV Hysteresis) - 1.70 2.00 V Three-State Falling Threshold VVCC = 5V (100mV Hysteresis) 3.10 3.41 - V - 20 - ns EN LOW Threshold 1.0 1.3 - V EN HIGH Threshold - 1.6 2.0 V Three-State Shutdown Holdoff Time tTSSHD tPDLU or tPDLL + Gate Falling Time EN INPUT SWITCHING TIME (See Figure 1 on Page 7) UGATE Rise Time (Note 4) tRU VVCC = 5V, 3nF Load - 8.0 - ns LGATE Rise Time (Note 4) tRL VVCC = 5V, 3nF Load - 8.0 - ns UGATE Fall Time (Note 4) tFU VVCC = 5V, 3nF Load - 8.0 - ns LGATE Fall Time (Note 4) tFL VVCC = 5V, 3nF Load - 4.0 - ns UGATE Turn-Off Propagation Delay tPDLU VVCC = 5V, Outputs Unloaded - 18 - ns LGATE Turn-Off Propagation Delay tPDLL VVCC = 5V, Outputs Unloaded - 25 - ns 5 FN9221.2 April 27, 2009 ISL6609, ISL6609A Electrical Specifications These specifications apply for TA = -40°C to 100°C, unless otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS UGATE Turn-On Propagation Delay tPDHU VVCC = 5V, Outputs Unloaded - 18 - ns LGATE Turn-On Propagation Delay tPDHL VVCC = 5V, Outputs Unloaded - 23 - ns tPTS VVCC = 5V, Outputs Unloaded - 20 - ns Three-state to UG/LG Rising Propagation Delay OUTPUT Upper Drive Source Resistance RUG_SRC 250mA Source Current - 1.0 2.5 Ω Upper Drive Sink Resistance RUG_SNK 250mA Sink Current - 1.0 2.5 Ω Lower Drive Source Resistance RLG_SRC 250mA Source Current - 1.0 2.5 Ω Lower Drive Sink Resistance RLG_SNK 250mA Sink Current - 0.4 1.0 Ω NOTE: 4. Limits established by characterization and are not production tested Functional Pin Description LGATE (Pin 5) Note: Pin numbers refer to the SOIC package. Check diagram for corresponding QFN pinout. Lower gate drive output. Connect to gate of the low side N-Channel power MOSFET. A gate resistor is never recommended on this pin, as it interferes with the operation shoot-through protection circuitry. UGATE (Pin 1) Upper gate drive output. Connect to gate of high-side N-Channel power MOSFET. A gate resistor is never recommended on this pin, as it interferes with the operation shoot-through protection circuitry. VCC (Pin 6) Connect this pin to a +5V bias supply. Locally bypass with a high quality ceramic capacitor to ground. BOOT (Pin 2) EN (Pin 7) Floating bootstrap supply pin for the upper gate drive. Connect a bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge used to turn on the upper MOSFET. See “Bootstrap Considerations” on page 7 for guidance in choosing the appropriate capacitor value. Enable input pin. Connect this pin high to enable and low to disable the driver. PHASE (Pin 8) Connect this pin to the source of the upper MOSFET. This pin provides the return path for the upper gate driver current. Thermal Pad (in QFN only) PWM (Pin 3) The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see “Three-State PWM Input” on page 7 for further details. Connect this pin to the PWM output of the controller. GND (Pin 4) Ground pin. All signals are referenced to this node. 6 The metal pad underneath the center of the IC is a thermal substrate. The PCB “thermal land” design for this exposed die pad should include vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the QFN to achieve its full thermal potential. This pad should be either grounded or floating, and it should not be connected to other nodes. Refer to TB389 for design guidelines. FN9221.2 April 27, 2009 ISL6609, ISL6609A Timing Diagram 2.5V PWM tPDHU tPDLU tTSSHD tRU tRU tFU tPTS 1V UGATE LGATE tPTS 1V tRL tTSSHD tPDHL tPDLL tFL FIGURE 1. TIMING DIAGRAM Operation and Adaptive Shoot-Through Protection Designed for high speed switching, the ISL6609, ISL6609A MOSFET driver controls both high-side and low-side NChannel FETs from one externally provided PWM signal. A rising transition on PWM initiates the turn-off of the lower MOSFET (see “Timing Diagram”). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the “Electrical Specifications” table on page 5. Adaptive shoot-through circuitry monitors the LGATE voltage and turns on the upper gate following a short delay time [tPDHU] after the LGATE voltage drops below ~1V. The upper gate drive then begins to rise [tRU] and the upper MOSFET turns on. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. The adaptive shoot-through circuitry monitors the UGATE-PHASE voltage and turns on the lower MOSFET a short delay time, tPDHL, after the upper MOSFET’s gate voltage drops below 1V. The lower gate then rises [tRL], turning on the lower MOSFET. These methods prevent both the lower and upper MOSFETs from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge characteristics of the MOSFETs being used. This driver is optimized for voltage regulators with large step down ratio. The lower MOSFET is usually sized larger compared to the upper MOSFET because the lower MOSFET conducts for a longer time during a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.4Ω ON-resistance and 4A sink 7 current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate capacitor of the lower MOSFET and help prevent shoot through caused by the self turn-on of the lower MOSFET due to high dV/dt of the switching node. Three-State PWM Input A unique feature of the ISL6609, ISL6609A is the adaptable three-state PWM input. Once the PWM signal enters the shutdown window, either MOSFET previously conducting is turned off. If the PWM signal remains within the shutdown window for longer than the gate turn-off propagation delay of the previously conducting MOSFET, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. The PWM rising and falling thresholds outlined in the “Electrical Specifications” table on page 5 determine when the lower and upper gates are enabled. During normal operation in a typical application, the PWM rise and fall times through the shutdown window should not exceed either output’s turn-off propagation delay plus the MOSFET gate discharge time to ~1V. Abnormally long PWM signal transition times through the shutdown window will simply introduce additional dead time between turn off and turn on of the synchronous bridge’s MOSFETs. For optimal performance, no more than 100pF parasitic capacitive load should be present on the PWM line of ISL6609, ISL6609A (assuming an Intersil PWM controller is used). Bootstrap Considerations This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The ISL6609A’s internal FN9221.2 April 27, 2009 ISL6609, ISL6609A bootstrap resistor is designed to reduce the overcharging of the bootstrap capacitor when exposed to excessively large negative voltage swing at the PHASE node. Typically, such large negative excursions occur in high current applications that use D2-PAK and D-PAK MOSFETs or excessive layout parasitic inductance. The following equation helps select a proper bootstrap capacitor size: Q GATE C BOOT_CAP ≥ -------------------------------------ΔV BOOT_CAP (EQ. 1) Q G1 • VCC Q GATE = ------------------------------- • N Q1 V GS1 where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The ΔVBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. As an example, suppose two IRLR7821 FETs are chosen as the upper MOSFETs. The gate charge, QG, from the data sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the QGATE is calculated to be 22nC at VCC level. We will assume a 200mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.110µF is required. The next larger standard value capacitance is 0.22µF. A good quality ceramic capacitor is recommended. 2.0 1.8 1.6 CBOOT_CAP (µF) 1.4 1.2 1.0 0.8 0.6 QGATE = 100nC 0.4 50nC 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ΔVBOOT (V) FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE Power Dissipation Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the external gate resistance, and the selected MOSFET’s internal gate resistance and total gate charge. Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum 8 allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the SO8 package is approximately 800mW at room temperature, while the power dissipation capacity in the QFN package, with an exposed heat escape pad, is slightly better. See “Layout Considerations” on page 9 for thermal transfer improvement suggestions. When designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses due to the gate charge of MOSFETs and the driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 2 and 3, respectively, P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q • VCC (EQ. 2) Q G1 • VCC 2 P Qg_Q1 = ---------------------------------- • F SW • N Q1 V GS1 Q G2 • VCC 2 P Qg_Q2 = ---------------------------------- • F SW • N Q2 V GS2 ⎛ Q G1 • UVCC • N Q1 Q G2 • LVCC • N Q2⎞ I DR = ⎜ ------------------------------------------------------ + -----------------------------------------------------⎟ • F SW + I Q V GS1 V GS2 ⎝ ⎠ (EQ. 3) where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ is the driver’s total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively. The IQ VCC product is the quiescent power of the driver without capacitive load and is typically negligible. The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2, should be a short to avoid interfering with the operation shoot-through protection circuitry) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. The power dissipation on the driver can be roughly estimated as: P DR = P DR_UP + P DR_LOW + I Q • VCC (EQ. 4) R LO1 R HI1 ⎛ ⎞ P Qg_Q1 P DR_UP = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------R + R R + R 2 ⎝ HI1 EXT1 LO1 EXT1⎠ R LO2 R HI2 ⎛ ⎞ P Qg_Q2 P DR_LOW = ⎜ -------------------------------------- + ----------------------------------------⎟ • --------------------2 ⎝ R HI2 + R EXT2 R LO2 + R EXT2⎠ R GI1 R EXT2 = R G1 + ------------N Q1 R GI2 R EXT2 = R G2 + ------------N Q2 FN9221.2 April 27, 2009 ISL6609, ISL6609A VCC Layout Considerations BOOT D CGD RHI1 RLO1 G UGATE CDS RGI1 RG1 CGS Q1 A good layout helps reduce the ringing on the switching node (PHASE) and significantly lower the stress applied to the output drives. The following advice is meant to lead to an optimized layout: • Keep decoupling loops (VCC-GND and BOOT-PHASE) as short as possible. • Minimize trace inductance, especially on low-impedance lines. All power traces (UGATE, PHASE, LGATE, GND, VCC) should be short and wide, as much as possible. S PHASE FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH • Minimize the inductance of the PHASE node. Ideally, the source of the upper and the drain of the lower MOSFET should be as close as thermally allowable. VCC D CGD RHI2 LGATE RLO2 G RG2 CDS RGI2 CGS Q2 S GND FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH Application Information MOSFET and Driver Selection The parasitic inductances of the PCB and of the power devices’ packaging (both upper and lower MOSFETs) can cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the PHASE node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper MOSFET driver. Careful layout, proper selection of MOSFETs and packaging, as well as the proper driver can go a long way toward minimizing such unwanted stress. The selection of D2-PAK, or D-PAK packaged MOSFETs, is a much better match (for the reasons discussed) for the ISL6609A. Low-profile MOSFETs, such as Direct FETs and multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK), have low parasitic lead inductances and can be driven by either ISL6609 or ISL6609A (assuming proper layout design). The ISL6609, missing the 3Ω integrated BOOT resistor, typically yields slightly higher efficiency than the ISL6609A. • Minimize the current loop of the output and input power trains. Short the source connection of the lower MOSFET to ground as close to the transistor pin as feasible. Input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible. In addition, connecting the thermal pad of the QFN package to the power ground through a via, or placing a low noise copper plane underneath the SOIC part is recommended for high switching frequency, high current applications. This is to improve heat dissipation and allow the part to achieve its full thermal potential. Upper MOSFET Self Turn-On Effects at Startup Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, because of self-coupling via the internal CGD of the MOSFET, the UGATE could momentarily rise up to a level greater than the threshold voltage of the MOSFET. This could potentially turn on the upper switch and result in damaging inrush energy. Therefore, if such a situation (when input bus powered up before the bias of the controller and driver is ready) could conceivably be encountered, it is a common practice to place a resistor (RUGPH) across the gate and source of the upper MOSFET to suppress the Miller coupling effect. The value of the resistor depends mainly on the input voltage’s rate of rise, the CGD/CGS ratio, as well as the gate-source threshold of the upper MOSFET. A higher dV/dt, a lower CDS/CGS ratio, and a lower gate-source threshold upper FET will require a smaller resistor to diminish the effect of the internal capacitive coupling. For most applications, a 5k to 10kΩ resistor is typically sufficient, not affecting normal performance and efficiency. The coupling effect can be roughly estimated with the following equations, which assume a fixed linear input ramp and neglect the clamping effect of the body diode of the upper drive and the bootstrap capacitor. Other parasitic components such as lead inductances and PCB capacitances are also not taken into account. These equations are provided for guidance purpose only. 9 FN9221.2 April 27, 2009 ISL6609, ISL6609A Therefore, the actual coupling effect should be examined using a very high impedance (10MΩ or greater) probe to ensure a safe design margin. –V DS ⎛ ----------------------------------⎞ dV ⎜ -----⋅ R ⋅C ⎟ dV iss⎟ V GS_MILLER = ------- ⋅ R ⋅ C rss ⎜ 1 – e dt ⎜ ⎟ dt ⎜ ⎟ ⎝ ⎠ R = R UGPH + R GI VCC (EQ. 5) C iss = C GD + C GS C rss = C GD VIN BOOT D CBOOT DU DL UGATE RUGPH ISL6609/A CGD G CDS RGI CGS QUPPER S PHASE FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE UPPER MOSFET MILLER COUPLING 10 FN9221.2 April 27, 2009 ISL6609, ISL6609A Package Outline Drawing L8.3x3 8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 3/07 3.00 4X 0.65 A B 6 PIN #1 INDEX AREA 8 7 6 PIN 1 INDEX AREA 1 5 2 3.00 6 (4X) 1 .10 ± 0 . 15 0.15 4 3 0.10 M C A B 4 8X 0.28 ± 0.05 TOP VIEW 8X 0.60 ± 0.15 BOTTOM VIEW SEE DETAIL "X" 0.10 C C 0 . 90 ± 0.1 ( 4X 0 . 65 ) ( 2. 60 TYP ) BASE PLANE SEATING PLANE 0.08 C ( 1. 10 ) SIDE VIEW ( 8X 0 . 28 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. ( 8X 0 . 80) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 11 FN9221.2 April 27, 2009 ISL6609, ISL6609A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN9221.2 April 27, 2009