IRFIZ34G, SiHFIZ34G Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Isolated Package • High Voltage Isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) • Sink to Lead Creepage Distance = 4.8 mm • 175 °C Operating Temperature • Dynamic dV/dt Rating • Low Thermal Resistance • Lead (Pb)-free Available 60 RDS(on) (Ω) VGS = 10 V 0.050 Qg (Max.) (nC) 46 Qgs (nC) 11 Qgd (nC) 22 Configuration Single D TO-220 FULLPAK COMPLIANT DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220 FULLPAK eliminates the need for additional insulating hardware in commercial-industrial applications. The molding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. The isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The FULLPAK is mounted to a heatsink using a single clip or by a single screw fixing. G S G D S Available RoHS* N-Channel MOSFET ORDERING INFORMATION Package TO-220 FULLPAK IRFIZ34GPbF SiHFIZ34G-E3 IRFIZ34G SiHFIZ34G Lead (Pb)-free SnPb ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 60 Gate-Source Voltage VGS ± 20 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM Linear Derating Factor Single Pulse Avalanche Energyb Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque for 10 s 6-32 or M3 screw UNIT V 20 14 A 80 0.28 W/°C EAS 300 mJ PD 42 W dV/dt 5.0 V/ns TJ, Tstg - 55 to + 175 300d °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 875 µH, RG = 25 Ω, IAS = 20 A (see fig. 12). c. ISD ≤ 30 A, dI/dt ≤ 200 A/µs, VDD ≤ VDS, TJ ≤ 175 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91188 S09-0010-Rev. A, 19-Jan-09 www.vishay.com 1 IRFIZ34G, SiHFIZ34G Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 3.6 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 µA 60 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.065 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage IGSS Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance IDSS RDS(on) gfs VGS = ± 20 V - - ± 100 VDS = 60 V, VGS = 0 V - - 25 VDS = 48 V, VGS = 0 V, TJ = 150 °C - - 250 - - 0.050 Ω 9.2 - - S ID = 12 Ab VGS = 10 V VDS = 25 V, ID = 12 Ab µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Drain to Sink Capacitance C Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 f = 1.0 MHz VGS = 10 V ID = 30 A, VDS = 48 V see fig. 6 and 13b - 1200 - - 600 - - 100 - - 12 - - - 46 - - 11 Gate-Drain Charge Qgd - - 22 Turn-On Delay Time td(on) - 13 - - 100 - - 29 - - 52 - - 4.5 - - 7.5 - - - 20 Rise Time tr Turn-Off Delay Time td(off) Fall Time VDD = 30 V, ID = 30 A RG = 12 Ω, RD= 1.0 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact D pF nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 20 A, VGS = 0 Vb TJ = 25 °C, IF = 30 A, dI/dt = 100 A/µsb - - 80 - - 1.6 V - 120 230 ns - 0.70 1.4 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 % www.vishay.com 2 Document Number: 91188 S09-0010-Rev. A, 19-Jan-09 IRFIZ34G, SiHFIZ34G Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 175 °C Document Number: 91188 S09-0010-Rev. A, 19-Jan-09 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRFIZ34G, SiHFIZ34G Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91188 S09-0010-Rev. A, 19-Jan-09 IRFIZ34G, SiHFIZ34G Vishay Siliconix RD VDS VGS D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91188 S09-0010-Rev. A, 19-Jan-09 www.vishay.com 5 IRFIZ34G, SiHFIZ34G Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T RG + - IAS V DD VDS 10 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91188 S09-0010-Rev. A, 19-Jan-09 IRFIZ34G, SiHFIZ34G Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91188. Document Number: 91188 S09-0010-Rev. A, 19-Jan-09 www.vishay.com 7 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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