DATASHEET

DATASHEET
Wide VIN Dual Integrated Buck Regulator With 4A/4A
Continuous Output Current and LDOs
ISL95901
Features
The ISL95901 is a dual, high-efficient buck regulator capable
of 4A per channel continuous output current. It integrates two
LDOs and one low-impedance switch. This power management
IC delivers power in portable and embedded systems. With an
input range of 4.5V to 16V, it provides a high frequency power
solution for a variety of point-of-load applications. Outputs are
adjustable to meet system needs.
• Wide input voltage range from 4.5V to 16V
A PWM controller drives two pairs of internal switching
N-channel power MOSFETs to generate output voltage. The
integrated power switch is optimized for excellent thermal
performance for up to 4A of output current per channel.
• Internally set SS and OCP
The ISL95901 modulator features Intersil R4™ Technology,
which combines the best features of fixed-frequency and
hysteretic PWMs while eliminating many of their drawbacks.
Like R3™ Technology, the R4™ Technology allows variable
frequency in response to load transients and maintains the
benefits of current-mode hysteretic controllers. In addition, it
reduces regulator output impedance and uses accurate
referencing to eliminate the need for a high-gain voltage
amplifier. The resulting topology can be tuned to voltage-mode
hysteretic transient speed while maintaining a linear control
model. This topology removes the need for compensation,
which greatly simplifies regulator design for customers and
reduces external component count and cost.
• Adjustable output voltages with continuous output current
up to 4A
• 1% accuracy over temperature and VCC range
• Built-in low-power LDO for external µC
• Built-in compensation
• Independent enable, power-good and standby control inputs
for each output
• Innovative R4™ Modulator
• Boot undervoltage detection
Applications
• General purpose, point-of-load DC/DC power conversion
• Notebook, netbook and tablet
• Embedded computing system
Related Literature
• See AN1743 “Wide VIN Dual Integrated Buck Regulator With
4A/4A Continuous Output Current and LDOs”
Protection features include overcorrect, negative overcorrect,
UVLO and thermal overload. The ISL95901 is available in a
46 Ld 5mmx6mm Quad Flat (QFN) Pb-free package.
00
EFFICIENCY (%)
90
80
IOUT
12VIN PFM
6VIN PFM
R4
8.4VIN PFM
R3
6VIN PWM
70
VCOMP
8.4VIN PWM
60
fSW = 300kHz, VOUT = 5V
12VIN PWM
VOUT
50
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
t
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD, VIN = 12V, TA = +25°C
January 22, 2015
FN7893.1
1
FIGURE 2. R3™ vs R4™ IDEALIZED TRANSIENT RESPONSE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013, 2015. All Rights Reserved
Intersil (and design) and R3 and R4 technologies are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL95901
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R4™ Modulator Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discontinuous Conduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
20
20
Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
20
20
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Regulator Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT Undervoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
21
21
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
22
22
22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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January 22, 2015
ISL95901
Pin Configuration
PG1
LDO3P3
MODE
BYP3P3
LDO5
VIN
VCC
BYP5
VSOUT2
PG2
ISL95901
(46 LD QFN)
TOP VIEW
46
45
44
43
42
41
40
39
38
37
36 STB2
FS 1
35 VSIN2
VSIN1 2
GND
FB1 3
GND 4
34 FB2
33 GND
PAD1
32 EN2
EN1 5
BOOT1 6
31 BOOT2
PHASE1 7
30 PHASE2
PHASE1
PHASE1 8
PHASE2
29 PHASE2
PGND1 9
28 PGND2
PGND1 10
27 PGND2
PGND1 11
26 PGND2
PGND1 12
14
15
16
17
18
19
20
21
22
23
VIN1
VIN1
PHASE1
PHASE2
VIN2
VIN2
VIN2
PHASE2
24 PGND2
VIN1
PAD2
PHASE1
PGND1 13
25 PGND2
PAD3
Pin Descriptions
PIN NUMBER
SYMBOL
1
FS
2
VSIN1
Sensing for output of Switching Mode Power Supply 1 -SMPS1. Must be connected to channel 1 output side
of inductor.
3
FB1
SMPS1 feedback input. Connect FB1 to a resistive voltage divider from SVIN1 to GND1 to adjust the output
from 0.8V to 5.5V.
4, 33, PAD1
GND
Analog ground for buck controllers and LDOs. Kelvin connect GND to the negative terminal of SMPS1/2. For
optimal thermal performance, place as many vias as possible under PAD1 and connecting to GND plane.
5
EN1
SMPS1 controller enable input. PWM controller is held off when pin is pulled to ground. When voltage on
this pin rises above 1.4V, PWM controller is enabled.
6
BOOT1
Floating bootstrap supply pin for power MOSFET gate driver. Bootstrap capacitor provides necessary charge
to turn on high-side internal N-channel MOSFET of channel 1. Connect an external capacitor from this pin to
PHASE1.
7, 8, 14, 18,
PAD2
PHASE1
Switch node output of channel 1. Connects source of internal power MOSFETs with external output inductor.
Connect exposed PAD2 as close to inductor of SMPS1 as possible.
9, 10, 11, 12, 13
PGND1
Power ground of SMPS1.
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PIN DESCRIPTION
Buck switching frequency selection. Tie to high for 1MHz, float for 500kHz, tie to GND for 300kHz.
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ISL95901
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
PIN DESCRIPTION
15, 16, 17
VIN1
19, 23, 29, 30,
PAD3
PHASE2
20, 21, 22
VIN2
24, 25, 26, 27,
28
PGND2
Power ground of SMPS2.
31
BOOT2
Floating bootstrap supply pin for power MOSFET gate driver. Bootstrap capacitor provides necessary charge
to turn on high-side internal N-channel MOSFET of channel 2. Connect an external capacitor from this pin to
PHASE2.
32
EN2
SMPS2 controller enable input. PWM controller is held off when pin is pulled to ground. When voltage on
this pin rises above 1.4V, PWM controller is enabled.
34
FB2
SMPS2 feedback Input. Connect FB2 to a resistive voltage divider from SVIN2 to GND2 to adjust the output
from 0.8V to 5.5V.
35
VSIN2
Sensing for output of SMPS2. Must be connected to channel 2 output side of inductor.
36
STB2
Standby output 2 enable input. Standby output 2 is held off when pin is pulled to ground. When voltage on
this pin rises above 1.4V, standby output 2 controller is enabled.
37
PG2
Open drain power-good of SMPS2. Pulled to ground when output voltage is below regulation limits or during
soft-start interval. Contains an internal 5MΩ pull-up resistor.
38
VSOUT2
39
BYP5
Connect BYP5 to 5V buck output or external 5V source, this will allow IC to disable VCC and LDO5, then the
power source will be drawn from BYP5 to minimize internal power dissipation. Tie to GND if not use.
40
VCC
Voltage bias for gate drivers as well as all other control circuitries. Power on or off by VIN. Decouple with at
least 1µF of an MLCC capacitor across VCC and PAD1.
41
VIN
Input LDO3P3, LDO5 and VCC. For decoupling, place a minimum of 1µF ceramic capacitance close to IC.
42
LDO5
43
BYP3P3
44
MODE
Mode selection pin. Connect to logic high or VCC for PWM mode. Connect to logic low or ground for DCM
mode. An internal 5MΩ pull-down resistor prevents undefined logic state in case of MODE pin float.
45
LDO3P3
3.3V linear regulator output. Power on or off by VIN. Can provide a total of 100mA external loads. Bypass
LDO3P3 output with a minimum of 4.7µF ceramic.
46
PG1
Open drain power-good of SMPS1. Pulled to ground when output voltage is below regulation limits or during
soft-start interval. Contains an internal 5MΩ pull-up resistor.
Input supply for power stage of SMPS1 regulator and source for internal linear regulator, LDO. For
decoupling, place a minimum of 10µF ceramic capacitance from VIN1 to PGND1 and close to IC.
Switch node output of channel 2. Connects source of internal power MOSFETs with external output inductor.
Connect exposed PAD3 as close to inductor of SMPS2 as possible.
Input supply for power stage of SMPS2 regulator. For decoupling, place a minimum of 10µF ceramic
capacitance from VIN2 to PGND2 and close to the IC.
Standby output 2. There is a switch between VSIN2 and VSOUT2.
5V linear regulator output. Power on or off by VIN. Can provide a total of 100mA external loads. Bypass
LDO5 output with a minimum of 4.7µF ceramic.
Connect BYP3P3 to 3.3V buck output or external 3.3V source, this will allow IC to disable LDO3P3, then the
power source will be drawn from BYP3P3 to minimize internal power dissipation. Tie to GND if not used.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL95901IRZ
95901 IRZ
ISL95901EVAL1Z
Evaluation Board
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(RoHS Compliant)
46 Ld QFN
PKG.
DWG. #
L46.5x6
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95901. For more information on MSL please see Tech Brief TB363.
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January 22, 2015
ISL95901
Typical Application Schematic
VIN: 4.5V TO 16V
2
C5
1µF
LDO3P3
3.3V
C7
4.7 µF
LDO3P3
VCC
1µF
VIN1
C1
10µF
L1: 1µH
C2
10µF
10
VIN
C4
0.1µF
BOOT2
PHASE1
(PAD2)
PHASE2
(PAD3)
PGND1
PGND2
C6
0.1µF
OUT2
L2: 1.5µH 5V/4A
C4
2x47µF
C3
2x47µF
(KELVIN SENSE)
C9 100pF
GND2
GND1
FB1
R1 31.6kΩ
R2
10kΩ
C6
4.7µF
VIN2
BOOT1
OUT1
3.3V/4A
LDO5
5V
LDO5
(KELVIN SENSE)
C10 100pF
FB2
R3 52.3kΩ
R4
10kΩ
ISL95901
GND
VSIN1
VSIN2
VSOUT2
5V
FS
VSOUT2
FS
C8
4.7µF
VIN
EN1
PG1
EN2
PG2
VIN
VCC
MODE
STB2
PAD1
FIGURE 3. DUAL 4A OUTPUT AT 1MHz (VIN RANGE FROM 4.5V TO 16V)
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January 22, 2015
ISL95901
MODE
FB2
FB1
VSIN1
Functional Block Diagram
MODE
VSIN1
PWM FREQUENCY
CONTROL
PWM FREQUENCY
CONTROL
+
gm
VIN1
+
gm
VIN1
-
-
R4™
MODULATOR
R4™
MODULATOR
VCC
-
-
-
+
+
gm
+
gm
VR1
CR
FS
VR2
CR
+
EN2
EN1
-
-
EA
+
VIN1
POR
-
DIGITAL
SOFTSTART
VREF
VR1
+
OCP
-
VREF
+
NOCP
VCC
DRIVER
+
NOCP
-
-
PGND1
PHASE2
PWM CONTROL
-
VR2
+
OCP
DRIVER
PGND2
+150°
OT
PHASE1
PG2
VCC
PHASE2
+
-
VCC
5M
+
+150°
OT
-
PG1
DRIVER
SD
+
UVP
0.85%*VREF
-
PWM CONTROL
+
UVP
-
VCC
BOOT2
1.15%*VREF
SD
PHASE1
POR
+
OVP
+
OVP
DIGITAL
SOFTSTART
DRIVER
VIN2
-
BOOT1
EA
+
VREF
5M
VIN
LDO3
LDO5
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6
LOGIC
SD
VSOUT2
STB2
BOTTOM
PACKAGE
LDO5
+
BYP5
VCC
LDO3P3
BYP3P3
GND
4.65V
GND
3.1V
VSIN2
100Ω
-
BOTTOM
PACKAGE
-
+
BIAS
FN7893.1
January 22, 2015
ISL95901
Absolute Maximum Ratings
Thermal Information
VIN1/2, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
PHASE1/2 to PGND1/2. . . . . . . . . . . . . . . . -0.3V to VIN1/2 + 0.3V(DC_) or
-2V to 19V (100ns)
BOOT1/2 to PHASE1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
VSIN1/2, VSOUT2, to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
BYP5, LDO5 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
BYP3P3, LDO3P3 to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
EN1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
STB2, MODE, PG1/2, FS to GND. . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
FB1, FB2 to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . .2.5kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .1.2kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V
Latch-up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
QFN Package (Notes 4, 5) . . . . . . . . . . . . . .
29.1
2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 16V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VIN = 4.5V to 16V, unless otherwise noted. Typical values are at TJ = +25°C. Boldface limits apply across the
junction temperature range, -40°C to +125°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
16
V
SUPPLY VOLTAGE
VIN Voltage Range
VIN
VIN Quiescent Supply Current
IQ
4.5
MODE = 0V, IVSIN1/2 = 0A, ISOUT2 = 0A
BYP5 = 5V
0.8
mA
FB1/2 = 0.9V
1.2
1.6
mA
120
200
µA
VIN Shutdown Supply Current
ISD
EN1/2 = 0V
VCC Voltage
VCC
VIN = 12V; IOUT = 0mA, BYP5 = 0V,
6V < VIN < 16V
4.9
5.25
5.6
V
LDO5
VIN = 12V, BYP5 = 0V,
0mA < ILDO5 < 100mA
4.90
5.0
5.12
V
LDO3P3
BYP3P3 = 0V, 0mA < ILDO3P3 < 100mA
3.23
3.32
3.4
V
150
425
mA
0.8
0.808
V
4.65
4.75
V
LDO
LDO5/LDO3P3 Output Short Current
Reference Voltage
IOUTLDO
0.792
VREF
BYP5 Threshold Voltage
Rising Edge
Falling Edge
BYP3P3 Threshold Voltage
4.40
Rising Edge
Falling Edge
4.50
3.1
2.9
V
3.2
3
V
V
BYP3P3 ON-resistance
2.2
4.2
Ω
BYP5 ON-resistance
1.2
2.2
Ω
3.9
4.25
V
POWER-ON RESET
VCC POR Threshold
Rising Edge
Soft-Start Ramp Time
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Falling Edge
3.25
3.7
EN1/2 = VIN
2
3
V
4
ms
FN7893.1
January 22, 2015
ISL95901
Electrical Specifications
VIN = 4.5V to 16V, unless otherwise noted. Typical values are at TJ = +25°C. Boldface limits apply across the
junction temperature range, -40°C to +125°C. (Continued)
PARAMETER
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
FS = High
0.8
1.0
1.2
MHz
FS = Float
400
500
600
kHz
FS = GND
240
300
360
kHz
-200
1
200
nA
115
118
108
112
SYMBOL
Switching Frequency
fSW
TEST CONDITIONS
OUTPUT REGULATION
FB1/2 Leakage Current
POWER-GOOD
OVP PG1/2 Trip Level
Rise
Fall
UVP PG1/2 Trip Level
Rise
Fall
90
83
PG1/2 Propagation Delay
93
87
ISINK = 3mA, PG1/2 = 0V
PG1/2 Leakage Current
PG1/2 Leakage Current
%
%
20
PG1/2 Low Voltage
%
%
µs
100
300
mV
PG1/2 = 0V
1
1.5
µA
PG1/2 = 5V
0.02
0.6
µA
ENABLE, MODE, STB2 and FS INPUT
EN1/2, STB2 Leakage Current
EN1/2 = 0V/5V, STB2 = 0V/5V
-0.2
0.01
0.2
µA
MODE Leakage Current
MODE = 0V
-0.2
0.01
0.2
µA
MODE = 5V
0.8
1
1.2
µA
0.40
V
EN1/2, MODE, STB2 Input Threshold
Voltage
Low Level
High Level
1.40
FS Voltage Threshold
Low Level
0.84
0.92
1
V
Float Level
1.14
1.2
1.26
V
High Level
1.76
1.81
1.86
V
V
FAULT PROTECTION
Thermal Shutdown Temperature
TSD
Rising Threshold
150
°C
THYS
Hysteresis
20
°C
Valley VIN1/2 to IPHASE1/2 (6 cycles delay)
Overcurrent Protection Threshold
4.8
Zero Cross Threshold
7.8
12
350
Negative Current Limit
INLIMIT
Standby Overcurrent Protection
Threshold
IPHASE1/2 to PGND1/2
-10.5
-6.2
IVSOUT2
2
IPHASE1/2 = 100mA
41
A
mA
-2.8
A
A
POWER MOSFET
Highside
RHDS
Lowside
RLDS
IPHASE1/2 = 100mA
EN1/2 = PHASE1/2 = 0V
PHASE Leakage Current (Note 7)
PHASE Rise Time (Note 7)
tRISE
VSOUT2 Standby Power MOSFET
55
mΩ
9
14
mΩ
0.01
2.5
µA
VIN = 16V
10
ns
IVSOUT2 = 100mA, VSIN1 = 5V
70
mΩ
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Care must be taken not to exceed the phase node max voltage rating.
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FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C.
100
90
12VIN DCM
80
70
6VIN PWM
8.4VIN PWM
60
40
0
0.5
1.0
1.5
2.0
8.4VIN DCM
12VIN DCM
80
70
6VIN PWM
8.4VIN PWM
60
12VIN PWM
50
6VIN DCM
90
8.4VIN DCM
EFFICIENCY (%)
EFFICIENCY (%)
100
6VIN DCM
12VIN PWM
50
2.5
3.0
3.5
40
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (300kHz, 3.3VOUT)
FIGURE 5. EFFICIENCY vs LOAD (500kHz, 3.3VOUT)
100
100
6VIN DCM
90
90
12VIN DCM
80
6VIN PWM
70
8.4VIN PWM
60
12VIN PWM
50
40
EFFICIENCY (%)
EFFICIENCY (%)
8.4VIN DCM
0
0.5
1.0
1.5
2.0
80
8.4VIN PFM
6VIN PWM
70
8.4VIN PWM
60
12VIN PWM
50
2.5
3.0
3.5
40
4.0
0
0.5
1.0
FIGURE 6. EFFICIENCY vs LOAD (1MHz, 3.3VOUT)
2.5
3.0
3.5
4.0
100
90
90
6VIN PFM
12VIN PFM
12VIN PFM
8.4VIN PFM
EFFICIENCY (%)
EFFICIENCY (%)
2.0
FIGURE 7. EFFICIENCY vs LOAD (300kHz, 5VOUT)
100
6VIN PWM
70
8.4VIN PWM
60
12VIN PWM
8.4VIN PFM
80
8.4VIN PWM
70
12VIN PWM
60
50
50
40
0.0
1.5
OUTPUT LOAD (A)
OUTPUT LOAD (A)
80
12VIN PFM
6VIN PFM
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
FIGURE 8. EFFICIENCY vs LOAD (500kHz, 5VOUT)
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40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
FIGURE 9. EFFICIENCY vs LOAD (1MHz, 5VOUT)
FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
3.320
4.974
3.315
4.966
3.310
4.958
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
12VIN DCM
3.305
12VIN PWM
3.300
3.295
3.290
3.285
3.280
12VIN PWM
4.950
4.942
12VIN DCM
4.934
4.926
4.918
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
FIGURE 10. VOUT REGULATION vs LOAD (300kHz 3.3VOUT)
4.910
0
0.5
1.0 1.5 2.0 2.5 3.0
OUTPUT LOAD (A)
3.5
4.0
FIGURE 11. VOUT REGULATION vs LOAD (300kHz 5VOUT)
PHASE2 10V/DIV
PHASE1 10V/DIV
VOUT2 2V/DIV
VOUT1 2V/DIV
VEN1 10V/DIV
VEN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 12. CH1 START-UP AT NO LOAD (PFM)
FIGURE 13. CH2 START-UP AT NO LOAD (PFM)
PHASE1 10V/DIV
PHASE2 10V/DIV
VOUT2 2V/DIV
VOUT1 2V/DIV
VEN1 10V/DIV
VEN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 14. CH1 START-UP AT NO LOAD (PWM)
FIGURE 15. CH2 START-UP AT NO LOAD (PWM)
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FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE2 10V/DIV
PHASE1 10V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
VEN1 10V/DIV
VEN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
5ms/DIV
5ms/DIV
FIGURE 16. CH1 SHUTDOWN AT NO LOAD (PFM)
FIGURE 17. CH2 SHUTDOWN AT NO LOAD (PFM)
PHASE2 10V/DIV
PHASE1 10V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
VEN1 10V/DIV
VEN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
5ms/DIV
5ms/DIV
FIGURE 18. CH1 SHUTDOWN AT NO LOAD (PWM)
FIGURE 19. CH2 SHUTDOWN AT NO LOAD (PWM)
PHASE1 10V/DIV
PHASE2 10V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
VEN1 10V/DIV
VEN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 20. CH1 START-UP AT 4A LOAD (PWM)
FIGURE 21. CH2 START-UP AT 4A LOAD (PWM)
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FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE1 10V/DIV
PHASE2 10V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
VEN1 10V/DIV
VEN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
5ms/DIV
5ms/DIV
FIGURE 22. CH1 SHUTDOWN AT 4A LOAD (PWM)
FIGURE 23. CH2 SHUTDOWN AT 4A LOAD (PWM)
PHASE2 10V/DIV
PHASE1 10V/DIV
VOUT1 2V/DIV
VOUT2 5V/DIV
VIN1 10V/DIV
VIN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 24. CH1 START-UP VIN AT NO LOAD (PFM)
FIGURE 25. CH2 START-UP VIN AT NO LOAD (PFM)
PHASE2 10V/DIV
PHASE1 10V/DIV
VOUT2 5V/DIV
VOUT1 2V/DIV
VIN1 10V/DIV
VIN2 10V/DIV
PG1 5V/DIV
PG2 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 26. CH1 START-UP VIN AT NO LOAD (PWM)
FIGURE 27. CH2 START-UP VIN AT NO LOAD (PWM)
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FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE1 5V/DIV
PHASE2 5V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
VIN1 5V/DIV
VIN2 5V/DIV
PG1 5V/DIV
PG2 5V/DIV
100ms/DIV
50ms/DIV
FIGURE 28. CH1 SHUTDOWN VIN AT NO LOAD (PFM)
FIGURE 29. CH2 SHUTDOWN VIN AT NO LOAD (PFM)
PHASE 5V/DIV
PHASE1 5V/DIV
VOUT 2V/DIV
VOUT1 2V/DIV
VIN 5V/DIV
VIN1 5V/DIV
PG 5V/DIV
PG1 5V/DIV
50ms/DIV
100ms/DIV
FIGURE 30. CH1 SHUTDOWN VIN AT NO LOAD (PWM)
FIGURE 31. CH2 SHUTDOWN VIN AT NO LOAD (PWM)
PHASE1 2V/DIV
5ns/DIV
FIGURE 32. CH1 JITTER AT NO LOAD PWM
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PHASE2 2V/DIV
5ns/DIV
FIGURE 33. CH1 JITTER AT FULL LOAD PWM
FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE2 5V/DIV
PHASE1 5V/DIV
VOUT2 RIPPLE 20mV/DIV
VOUT1 RIPPLE 20mV/DIV
IL1 2A/DIV
IL2 1A/DIV
2µs/DIV
2µs/DIV
FIGURE 34. CH1 STEADY STATE AT NO LOAD PWM
FIGURE 35. CH2 STEADY STATE AT NO LOAD PWM
PHASE1 5V/DIV
PHASE2 5V/DIV
VOUT1 RIPPLE 50mV/DIV
VOUT2 RIPPLE 50mV/DIV
IL1 2A/DIV
IL2 1A/DIV
5ms/DIV
10ms/DIV
FIGURE 36. CH1 STEADY STATE AT NO LOAD PFM
FIGURE 37. CH2 STEADY STATE AT NO LOAD PFM
PHASE1 5V/DIV
PHASE2 5V/DIV
VOUT1 RIPPLE 50mV/DIV
VOUT2 RIPPLE 50mV/DIV
IL2 2A/DIV
IL2 2A/DIV
2µs/DIV
FIGURE 38. CH1 STEADY STATE AT 4A LOAD PWM
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2µs/DIV
FIGURE 39. CH2 STEADY STATE AT 4A LOAD PWM
FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE1 10V/DIV
PHASE1 10V/DIV
VOUT1 RIPPLE 50mV/DIV
VOUT1 RIPPLE 50mV/DIV
PHASE2 10V/DIV
PHASE2 10V/DIV
VOUT2 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
2µs/DIV
2µs/DIV
FIGURE 40. STEADY STATE AT NO LOAD PWM ON BOTH CHANNELS
FIGURE 41. STEADY STATE AT 4A LOAD PWM ON BOTH CHANNELS
ILDO3P3 50mA/DIV
ILDO5 50mA/DIV
VIN 5V/DIV
VIN 5V/DIV
LDO5 2V/DIV
LDO3P3 2V/DIV
500µs/DIV
500µs/DIV
FIGURE 42. LDO3P3 START-UP VIN AT 100mA
FIGURE 43. LDO5 START-UP VIN AT 100mA
ILDO3P3 50mA/DIV
ILDO5 50mA/DIV
VIN 5V/DIV
VIN 5V/DIV
LDO3P3 2V/DIV
LDO5 2V/DIV
50ms/DIV
50ms/DIV
FIGURE 44. LDO3P3 SHUTDOWN VIN AT 100mA
FIGURE 45. LDO5 SHUTDOWN VIN AT 100mA
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FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
ILDO3P3 50mA/DIV
ILDO5 50mA/DIV
LDO5 RIPPLE 20mV/DIV
LDO3P3 RIPPLE 20mV/DIV
500µs/DIV
500µs/DIV
FIGURE 46. LDO3P3 LOAD TRANSIENT
FIGURE 47. LDO5 LOAD TRANSIENT
VOUT1 RIPPLE 100mV/DIV
VOUT2 RIPPLE 100mV/DIV
IL1 4A/DIV
IL2 4A/DIV
200µs/DIV
200µs/DIV
FIGURE 48. CH1 LOAD TRANSIENT (PWM)
FIGURE 49. CH2 LOAD TRANSIENT (PWM)
VOUT1 RIPPLE 100mV/DIV
IL1 4A/DIV
VOUT2 RIPPLE 100mV/DIV
IL2 4A/DIV
200µs/DIV
200µs/DIV
FIGURE 50. CH1 LOAD TRANSIENT (PFM)
FIGURE 51. CH2 LOAD TRANSIENT (PFM)
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FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE2 10V/DIV
PHASE1 10V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
IL1 10A/DIV
IL2 10A/DIV
PG1 5V/DIV
PG2 5V/DIV
10µs/DIV
20µs/DIV
FIGURE 52. CH1 OUTPUT SHORT CIRCUIT
FIGURE 53. CH2 OUTPUT SHORT CIRCUIT
PHASE2 5V/DIV
PHASE1 5V/DIV
VOUT1 2V/DIV
VOUT2 2V/DIV
IL1 5A/DIV
IL2 5A/DIV
PG1 5V/DIV
PG2 5V/DIV
50µs/DIV
50µs/DIV
FIGURE 54. CH1 OCP
FIGURE 55. CH2 OCP
PHASE1 5V/DIV
PHASE2 5V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 50mV/DIV
IL1 2A/DIV
IL2 2A/DIV
5µs/DIV
5µs/DIV
FIGURE 56. CH1 PFM TO PWM TRANSITION
FIGURE 57. CH2 PFM TO PWM TRANSITION
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FN7893.1
January 22, 2015
ISL95901
Typical Performance Curves
Circuit of Figure 3. VIN = 12V, VOUT1 = 3.3V, VOUT2 = 5, IOUT1 = 4A, IOUT2 = 4A, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PHASE1 5V/DIV
PHASE1 5V/DIV
VOUT1 RIPPLE 50mV/DIV
VOUT1 RIPPLE 20mV/DIV
IL1 2A/DIV
IL 1A/DIV
10µs/DIV
10µs/DIV
FIGURE 58. CH1 PWM TO PFM TRANSITION
FIGURE 59. CH2 PWM TO PFM TRANSITION
VOUT1 2V/DIV
VOUT1 2V/DIV
PG1 2V/DIV
PG 2V/DIV
50ms/DIV
50ms/DIV
FIGURE 60. CH1 OTP
FIGURE 61. CH2 OTP
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January 22, 2015
ISL95901
Detailed Description
The ISL95901 combines a dual PWM controller with two pairs of
integrated switching MOSFETs. The synchronous controller drives
the internal N-channel MOSFETs to deliver load current up to 4A
per channel. The buck regulator can operate from an unregulated
DC source such as a battery, with a voltage ranging from +4.5V to
+16V. The converter output can be regulated to as low as 0.8V.
These features make the ISL95901 ideally suited for FPGA,
set-top boxes, LCD panels, DVD drives, netbook, laptop and
wireless chipset power applications.
R4™ Modulator Technology
The ISL95901 modulator features Intersil R4™ Modulator
Technology. The R4™ modulator is an evolutionary step in
R3™ Technology. Like R3™, the R4™ Modulator allows variable
frequency in response to load transients and maintains the
benefits of current-mode hysteretic controllers. In addition, the
R4™ Modulator reduces regulator output impedance and uses
accurate referencing to eliminate the need for a high-gain
voltage amplifier. The result is a topology that can be tuned to
voltage-mode hysteretic transient speed while maintaining a
linear control model and removing the need for any
compensation. This greatly simplifies regulator design for
customers and reduces external component count and cost.
Removal of compensation derives from the R4™ Modulator’s
lack of need for high DC gain. In traditional architectures, high DC
gain is achieved with an integrator in the voltage loop. The
integrator introduces a pole in the open-loop transfer function at
low frequencies. This pole, combined with the double-pole from
the output L/C filter, creates a three-pole system that must be
compensated to maintain stability.
Classic control theory requires a single-pole transition through
unity gain to ensure a stable system. Current-mode architectures
(includes peak, peak-through, current-mode hysteretic, R3™ and
R4™) generate a zero at or near the L/C resonant point,
effectively canceling one of the system’s poles. The system still
contains two poles, one of which must be cancelled with a zero
before unity gain crossover to achieve stability. Compensation
components are added to introduce the necessary zero.
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VOUT
VCOMP
VREF
FIGURE 62. INTEGRATOR ERROR-AMPLIFIER CONFIGURATION
Figure 62 illustrates the classic integrator configuration for a
voltage loop error-amplifier. While the integrator provides the
high DC gain required for accurate regulation in traditional
technologies, it also introduces a low-frequency pole into the
control loop. Figure 63 shows the open-loop response that results
from the addition of an integrating capacitor in the voltage loop.
The compensation components found in Figure 62 are necessary
to achieve stability.
TRADITIONAL LOOP GAIN (dB)
INTEGRATOR POLE
p1
L/C DOUBLE-POLE
-20dB CROSSOVER
REQUIRED FOR
STABILITY
p2
p3
CURRENTz1
MODE
ZERO
COMPENSATOR TO
ADD z2 IS NEEDED
c
/de
dB
Stability
HIGH DC GAIN
ec
-60dB/d
To minimize solution size, the error amplifier internally integrates
all necessary poles and zeroes, thus eliminating the need for
compensation.
INTEGRATOR FOR
-40
R4™ Technology employs an innovative modulator that
synthesizes an AC ripple voltage signal, VR, analogous to the
output inductor ripple current. The AC signal enters a window
comparator where the lower threshold is the error amplifier
output, VCOMP and the upper threshold is a programmable voltage
reference, VW, resulting in generation of the PWM signal. The
voltage reference, VW, sets the steady-state PWM frequency. Both
edges of the PWM can be modulated in response to input voltage
transients and output load transients much faster than
conventional fixed-frequency PWM controllers. Unlike a
conventional hysteretic converter, each channel of the ISL95901
has an error amplifier that provides ±1% voltage regulation at the
FB pin.
COMPENSATION FOR/TO
COUNTER INTEGRATOR POLE
-2
0d
B
/d
ec
FIGURE 63. UNCOMPENSATED INTEGRATOR OPEN-LOOP RESPONSE
Because R4™ does not require a high-gain voltage loop, the
integrator can be removed, reducing the number of inherent
poles in the loop to two. The current-mode zero continues to
cancel one of the poles, ensuring a single-pole crossover for a
wide range of output filter choices. The result is a stable system
with no need for compensation components or complex
equations to properly tune the stability.
Figure 64 shows the R4™ error-amplifier that does not require an
integrator for high DC gain to achieve accurate regulation. The
result to the open loop response can be seen in Figure 65.
R2
R1
VOUT
VCOMP
VREF
FIGURE 64. NON-INTEGRATED R4™ ERROR-AMPLIFIER
CONFIGURATION
FN7893.1
January 22, 2015
ISL95901
decays solely as a function of load. The power FETs remain off
until the output voltage droops enough to trigger a PWM on
pulse. Because the rate of decay of VOUT scales proportionally
with load, so does the switching frequency. This increases
efficiency as the relatively fixed power loss associated with
switching the power FETs is averaged over the switching period.
R4 LOOP GAIN (dB)
L/C DOUBLE-POLE
p1
SYSTEM HAS 2
POLES AND 1 ZERO
p2
Operation Initialization
z1
c
de
B/
0d ec
-2 /d
B
0d
-2
c
/de
dB
-40
CURRENTMODE
ZERO
Like R3™, the R4™ architecture seamlessly enters and exits all
power saving modes to ensure accurate regulation.
NO COMPENSATOR
NEEDED
f (Hz)
FIGURE 65. UNCOMPENSATED R4™ OPEN-LOOP RESPONSE
The power-on reset circuitry and enable inputs prevent false
start-up of the PWM regulator output. When all input criteria are
met, the controller soft-starts the output voltage to the
programmed level.
Power-on Reset
Transient Response
In addition to requiring a compensation zero, the integrator in
traditional architectures slows system response to transient
conditions. The change in COMP voltage is slow in response to a
rapid change in output voltage. If the integrating capacitor is
removed, COMP moves as quickly as VOUT and the modulator
immediately increases or decreases switching frequency to
recover the output voltage.
The dotted red and blue lines in Figure 66 represent the time
delayed behavior of VOUT and VCOMP in response to a load
transient when an integrator is used. The solid red and blue lines
illustrate the increased response of R4™ in the absence of the
integrator capacitor.
The ISL95901 automatically initializes upon receipt of input
power supply. The power-on reset (POR) function continuously
monitors VCC voltage. While below the POR threshold, the
controller inhibits switching of the internal power MOSFET. When
exceeded, the controller initializes the internal soft-start circuitry.
If VCC supply drops below its falling POR threshold during
soft-start or operation, the buck regulator is disabled until the
input voltage returns.
Enable and Disable
When EN1/2 are pulled low, the device enters shutdown mode,
and the supply current drops to a typical value of 120µA. All
internal power devices are held in a high-impedance state while
in shutdown mode.
The EN pin enables the ISL95901 controller. When the voltage on
the EN pin exceeds its logic rising threshold, the controller
initiates the 2ms soft-start function for the regulator. If the
voltage on the EN pin drops below the falling threshold, the buck
regulator shuts down.
IOUT
R4
R3
VCOMP
Discharge Mode (Soft-stop)
When a transition to shutdown mode occurs or when the VCC POR
is set, the outputs discharge to GND through an internal 50Ω switch.
VOUT
t
FIGURE 66. R3™ vs R4™ IDEALIZED TRANSIENT RESPONSE
Discontinuous Conduction Modes
The ISL95901 supports two power-saving modes of operation
during light load conditions. If MODE is asserted HIGH, the
regulator remains in continuous conduction mode (CCM), which
offers the best transient response and the most stable operating
frequency.
If the MODE pin is pulled to ground potential, the regulator
operates in full discontinuous conduction mode (DCM). In this
mode, the inductor current is monitored and is prohibited from
going negative. When the inductor current reaches zero, both
internal power MOSFETs are turned off. The output voltage then
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Power-good
PG1/2 are the open-drain outputs of a window comparator that
continuously monitors the buck regulator output voltage via the
FB1/2 pin. PG1/2 is actively held low when EN1/2 is low and
during the buck regulator soft-start period. After the soft-start
period terminates, PG becomes high impedance as long as the
output voltage (monitored on the FB1/2 pin) is between 90% and
105% of the nominal regulation voltage set by FB1/2. When
VOUT drops 10% below the nominal regulation voltage, the
ISL95901 pulls PG1/2 low. Any fault condition forces PG1/2 low
until the fault condition is cleared by attempts to soft-start. There
is an internal 5MΩ internal pull-up resistor tied to PG1/2.
Output Voltage Selection
The regulator output voltage is easily programmed using an
external resistor divider to scale VSIN1/2 relative to the internal
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier (see Figure 67).
FN7893.1
January 22, 2015
ISL95901
The output voltage programming resistor, R2, depends on the
value chosen for the feedback resistor, R3, and the desired
output voltage, VSIN1/2, of the regulator. Equation 1 describes
the relationship between resistor values. R3 is often chosen to be
in the 10kΩ to 100kΩ range.
R 2 =  VSIN1/2-0.8   R 3  0.8
(EQ. 1)
If the desired output voltage is 0.8V, then R3 is left unpopulated,
and R2 is 0Ω.
VSIN1/2
R2
FB1/2
R3
0.8V
REFERENCE
FIGURE 67. EXTERNAL RESISTOR DIVIDER
Protection Features
The ISL95901 limits the current in all on-chip power devices.
Overcurrent protection limits the current on the LDO5, LDO3P3,
VCC, the two buck regulators and the standby outputs.
Buck Regulator Overcurrent Protection
If the current draw from the load becomes too high during
operation, the IC protects itself and the load by latching off. The
overcurrent mechanism is implemented as a two-fold protection
scheme.
The ISL95901 continuously monitors the lower N-channel
MOSFET current. It stores the valley of the inductor current each
cycle and compares it against the lower overcurrent protection
(OCP) threshold of 7.8A nominally. If the OCP threshold is
achieved for 6 consecutive PWM cycles, an overcurrent fault is
detected and buck is latched off. In this event, the power-good
monitor flags PG1/2 low and the high-side switching power
MOSFET is turned off. Inductor valley current is used to ensure
the minimum OCP threshold is above the ISL95901 normal
maximum load of 4A, regardless of chosen inductor value, the IC
remains latched off until POR or EN1/2 is toggled.
Buck Negative Current Protection
Similar to overcurrent protection, negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in Figure 3 on page 5. When the valley point of the inductor
current reaches -6.2A, both P-FET and N-FET are off. Boot
undervoltage engages when the condition exists for a long time
and the voltage difference between BOOT and PHASE drops below
2.5V. The buck controller begins to switch again when output is
back to regulation.
Standby Output Overcurrent Protection
The standby output (VSOUT2) current limit is 2A. Upon reaching
these threshold, the internal MOSFET is latched off to prevent
damage. Toggle EN2 or STB2 to reset faulty condition.
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Thermal overload protection limits maximum junction
temperature in the ISL95901. When the junction temperature
(TJ) exceeds +150°C, a thermal sensor sends a signal to the fault
monitor.
The fault monitor commands the buck regulator and LDOs to
shutdown. When the junction temperature has decreased by
+20°C, the regulators and LDOs attempt a normal soft-start
sequence and returns to normal operation. For continuous
operation, the +125°C junction temperature rating should not be
exceeded.
BOOT Undervoltage Protection
+
-
EA
Thermal Overload Protection
If the BOOT capacitor voltage falls below 2.5V, the BOOT
undervoltage protection circuit pulls the phase pin low for 400ns
to recharge the capacitor. This operation may arise during long
periods of no switching, as in no-load situations at PFM.
Application Guidelines
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 2:
V IN – V OUT V OUT
L = --------------------------------  ---------------f SW  I
V IN
(EQ. 2)
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
reduce the converter’s response time to a load transient. The
inductor current rating should be such that it does not saturate in
overcurrent conditions.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are two critical
factors when considering output capacitance choice. The current
mode control loop allows low ESR ceramic capacitors to be used
and results in smaller board layout. Electrolytic and polymer
capacitors may also be used.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturer data sheet to determine actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction generally suffices. The result of these
considerations can easily result in an effective capacitance that
is 50% lower than the rated value. Nonetheless, they are a very
good choice in many applications due to their reliability and
extremely low ESR.
FN7893.1
January 22, 2015
ISL95901
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
Equation 7:
For ceramic capacitors (low ESR) (Equation 3):
where TA is the ambient temperature. For the QFN package, θJA
is +29°C/W.
I
V OUTripple = ------------------------------------8 f SW C OUT
(EQ. 3)
where I is the inductor’s peak-to-peak ripple current, FSW is the
switching frequency, and COUT is the output capacitor.
If using electrolytic capacitors (Equation 4):
V OUTripple = I*ESR
(EQ. 4)
Input Capacitor Selection
To reduce the resulting input voltage ripple and to minimize EMI
by forcing the very high frequency switching current into a tight
local loop, an input capacitor is required. The input capacitor
must have an adequate ripple current rating, which can be
approximated by the Equation 5.
I RMS
------------ =
Io
D – D2
(EQ. 5)
where D = VO/VIN
If capacitors other than MLCC are used, attention must be paid to
ripple and surge current ratings.
The input ripple current is graphically represented in Figure 68
for each SMPS.
0.6
0.5
IRMS/IO
(EQ. 7)
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C.
The ISL95901 outputs current level depends on whether the
thermal impedance from the thermal pad maintains the junction
temperature below +125°C. This depends on the input
voltage/output voltage combination and the switching frequency.
The device power dissipation must be reduced otherwise,
thermal shutdown will occur.
Layout Considerations
Layout is very important in high frequency switching converter
design. With power devices switching efficiently between 100kHz
and 2MHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes
can degrade efficiency, radiate noise into the circuit and lead to
device overvoltage stress. Careful component layout and printed
circuit board design minimize these voltage spikes.
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the body diode of the low-side MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection; tight layout of the critical components; and
short, wide traces minimize the magnitude of voltage spikes.
There are two sets of critical components in the ISL95901
switching converter. The switching components are the most
critical because they switch large amounts of energy and
therefore tend to generate large amounts of noise. Next, are the
small signal components, which connect to sensitive nodes or
supply critical bypass current and signal coupling.
0.4
0.3
0.2
0.1
0
T J =  T A + T RISE 
0
0.2
0.4
0.6
DUTY CYCLE
0.8
FIGURE 68. IRMS/IO vs DUTY CYCLE
A minimum of 10µF ceramic capacitance is required on each VIN
pin. The capacitors must be as close to the IC as physically
possible. Additional capacitance may be used.
Power Derating Characteristics
To prevent the ISL95901 from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 6:
A multi-layer printed circuit board is recommended. Figure 64
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage levels.
Keep the metal runs from the PHASE terminals to the output
inductor short. The power plane should support the input power
and output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring.
(EQ. 6)
T RISE =  PD    JA 
Where PD is the power dissipated by the regulator and θJA is the
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by
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FN7893.1
January 22, 2015
ISL95901
To dissipate heat generated by the internal LDO and MOSFET, the
pads should be connected to the PCB planes through at least
eight vias. These allow heat to move away from the IC and also
tie PAD1 to the ground plane through a low impedance path.
The switching components should be placed close to the
ISL95901 first. Minimize the length of connections between the
input capacitors, CIN, and the power switches by placing them
nearby. Position both the ceramic and bulk input capacitors as
close to the upper MOSFET drain as possible. Position the output
inductor and output capacitors between PHASE1 (or PHASE2)
and the load.
The critical small-signal components include any bypass
capacitors, feedback components and compensation
components. Feedback resistors should be located as close as
possible to the FB pins with vias tied straight to the ground plane
as required.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
January 22, 2015
FN7893.1
Updated datasheet by changing the continuous output current from 6A to 4A throughout document.
Added Eval board to ordering information table on page 4.
Updated datasheet with all Intersil standards.
Dec. 17, 2014
FN7893.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN7893.1
January 22, 2015
ISL95901
Package Outline Drawing
L46.5x6
46 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 6/11
3.50
6
PIN 1
INDEX AREA
5.00
A
3.60
42x 0.40
B
4.50
2.85
6.00
0.60
1.275
6
PIN #1 INDEX AREA
(4X)
0.15
46x 0.40
TOP VIEW
b
2x 1.575
46X0.20
0.10 M C A B
3.50
BOTTOM VIEW
3.50
(4.80)
(3.60)
0.70
SEE DETAIL "X"
1.275
0.90±0.1
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
0.203 0.035
SIDE VIEW
2.85
(5.80)
(4.50)
0.60
(42X 0.40)
C 0.2 REF
(46X 0.20)
5
0.00 MIN
0.05 MAX
(46X 0.60)
2x 1.575
DETAIL "X"
3.50
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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24
FN7893.1
January 22, 2015