DATASHEET

ZL6100
S
DESIGN
R NEW
O
T
F
R
D
A
P
E
END
EMENT Data Sheet
C O MM
EPLAC
R
D
N OT R E
E
D
M EN
ZL6105
R E C OM
August 29, 2012
FN6876.3
Adaptive Digital DC/DC Controller with
Drivers and Current Sharing
Features
ZL6100 is a digital power controller with integrated MOSFET
drivers. Current sharing allows multiple devices to be
connected in parallel to source loads with very high current
demands. Adaptive performance optimization algorithms
improve power conversion efficiency across the entire load
range. Zilker Labs Digital-DC™ technology enables a blend
of power conversion performance and power management
features.
• Efficient Synchronous Buck Controller
The ZL6100 is designed to be a flexible building block for DC
power and can be easily adapted to designs ranging from a
single-phase power supply operating from a 3.3V input to a
multi-phase supply operating from a 12V input. The ZL6100
eliminates the need for complicated power supply managers
as well as numerous external discrete components.
All operating features can be configured by simple
pin-strap/resistor selection or through the SMBus™ serial
interface. The ZL6100 uses the PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for communication between other Zilker Labs devices.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
Power Conversion
• Adaptive Light Load Efficiency Optimization
• 3V to 14V Input Range
• 0.54V to 5.5V Output Range (with Margin)
• ±1% Output Voltage Accuracy
• Internal 3A MOSFET Drivers
• Fast Load Transient Response
• Current Sharing and Phase Interleaving
• Snapshot™ Parameter Capture
• 36 Ld 6mmx6mm QFN Package
• Pb-Free (RoHS Compliant)
Power Management
• Digital Soft-start/stop
• Precision Delay and Ramp-up
• Power-Good/Enable
• Voltage Tracking, Sequencing and Margining
• Voltage/Current/Temperature Monitoring
TEMP.
RANGE
(°C)
• I2C/SMBus Interface (PMBus Compatible)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ZL6100ALAF
(Note 4)
6100
-40 to +85
36 Ld QFN L36.6x6C
ZL6100ALBF
6100
-40 to +85
36 Ld QFN L36.6x6C
• Output Voltage and Current Protection
• Internal Non-volatile Memory (NVM)
Applications
• Servers/Storage Equipment
• Telecom/Datacom Equipment
NOTES:
1. Add “T*” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ZL6100. For more information on
MSL, please see Technical Brief TB363.
• Power Supplies (Memory, DSP, ASIC, FPGA)
EN PG DLY
V
SS
VTRK
MGN
SYNC
FC
ILIM CFG UVLO V25 VR VDD
LDO
POWER
MANAGEMENT
DDC
4. Only for customers that do not want to order new
firmware.
SCL
SDA
SALRT
DRIVER
NONVOLATILE
MEMORY
PWM
CONTROLLER
I2 C
MONITOR
ADC
SA
XTEMP
CURRENT
SENSE
BST
GH
SW
GL
VSEN+
VSENISENA
ISENB
TEMP
SENSOR
PGND SGND DGND
FIGURE 1. BLOCK DIAGRAM
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
Copyright Intersil Americas Inc. 2009, 2010, 2012. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
ZL6100
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ZL6100 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Conversion Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-side Driver Boost Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Limit Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-linear Response (NLR) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Efficiency Optimized Driver Dead-time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
13
14
15
15
16
19
22
22
23
23
23
23
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C/SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C/SMBus Device Address Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Adding/Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapshot™ Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
24
25
25
26
26
27
27
28
28
28
29
29
29
30
31
31
32
Related Tools and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2
FN6876.3
August 29, 2012
ZL6100
Absolute Maximum Ratings (Note 5)
Thermal Information
DC Supply Voltage for VDD Pin. . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic I/O Voltage for CFG, DLY(0,1), EN, FC(0,1), ILIM(0,1),
MGN, PG, SA(0,1), SALRT, SCL, SDA, SS,
SYNC, UVLO, V(0,1) Pins . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Analog Input Voltages for VSEN+, VSEN-, VTRK,
XTEMP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Analog Input Voltages for ISENA, ISENB Pins . . . . . . -1.5V to 6.5V
MOSFET Drive Reference for VR Pin . . . . . . . . . . . . . -0.3V to 6.5V
Logic Reference for V25 Pin . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Ground Voltage Differential (VDGND-VSGND) for
DGND - SGND, PGND - SGND Pins . . . . . . . . . . . -0.3V to +0.3V
High Side Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 30V
Boost to Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 8V
High Side Drive Voltage . . . . . . . . . . . . . . (VSW - 0.3) to (VBST + 0.3)
Low Side Drive Voltage . . . . . . . . . . . . . .(PGND - 0.3) to (VR + 0.3)
Switch Node Continuous . . . . . . . . . . . . . . . . . . . (PGND - 0.3) to 30
Switch Node Transient (<100ns) . . . . . . . . . . . . . . (PGND - 5) to 30
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Thermal Resistance (Typical, Notes 6, 7) θJA (°C/W)
θJC (°C/W)
36 Ld QFN . . . . . . . . . . . . . . . . . . . . . .
35
5
Operating Junction Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage Range (Typical)
VDD Tied to VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V
VR Floating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Output Voltage Range VOUT (Notes 5, 8) . . . . . . . . . . ..0.54 to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. Voltage measured with respect to SGND.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Includes margin limits.
Electrical Specifications
VDD = 12V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C. Boldface limits
apply over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITIONS
MIN
(Note 19)
TYP
MAX
(Note 19)
UNIT
INPUT AND SUPPLY CHARACTERISTICS
IDD Supply Current at fSW = 200kHz
IDD Supply Current at fSW = 1.4MHz
GH, GL no load;
MISC_CONFIG[7] = 1
–
–
16
25
30
50
mA
mA
IDDS Shutdown Current
EN = 0V
No I2C/SMBus activity
–
6.5
9
mA
VR Reference Output Voltage
VDD > 6V, IVR < 20mA
4.5
5.2
5.5
V
V25 Reference Output Voltage
VR > 3V, IV25 < 20mA
2.25
2.5
2.75
V
Output Voltage Adjustment range (Note 9)
VIN > VOUT
0.6
–
5.0
V
Output Voltage Set-point Resolution (Note 10)
Set using resistors
–
10
–
mV
–
±0.025
–
% FS
(Note 10)
OUTPUT CHARACTERISTICS
Set using
I2C/SMBus
Output Voltage Accuracy (Note 11)
Includes line, load, temp
-1
–
1
%
VSEN input Bias Current
VSEN = 5.5V
–
110
200
µA
Current Sense Differential Input
Voltage (Ground Referenced)
VISENA - VISENB
-100
–
100
mV
Current Sense Differential Input Voltage
VISENA - VISENB
(VOUT Referenced; VOUT must be less than 4.0V)
- 50
–
50
mV
Current Sense Input Bias Current
Ground referenced
-100
–
100
µA
Current Sense Input Bias Current
(VOUT Referenced, VOUT < 4.0 V)
ISENA
-1
–
1
µA
ISENB
-100
–
100
µA
3
FN6876.3
August 29, 2012
ZL6100
Electrical Specifications
VDD = 12V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C. Boldface limits
apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
Soft-start Delay Duration Range (Note 12)
Set using DLY pin or resistor
Set using
Soft-start Delay Duration Accuracy
Soft-start Ramp Duration Range
I2C/SMBus
Turn-on delay (precise mode) (Notes 12, 13)
MIN
(Note 19)
TYP
MAX
(Note 19)
UNIT
2
–
200
ms
0.002
–
500
s
–
±0.25
–
ms
Turn-on delay (normal mode) (Note 14)
–
-1/+5
–
ms
Turn-off delay (Note 14)
–
-1/+5
–
ms
Set using SS pin or resistor
0
–
200
ms
0
–
200
ms
–
100
–
µs
-250
–
250
nA
–
–
0.8
V
Set using
I 2C
pin
Soft-start Ramp Duration Accuracy
LOGIC INPUT/OUTPUT CHARACTERISTICS
Logic Input Leakage Current
Push-Pull Logic pins
Logic Input Low, VIL
Logic Input OPEN (N/C)
Multi-mode logic pins
Logic Input high, VIH
–
1.4
–
V
2.0
–
–
V
Logic Output Low, VOL
IOL ≤ 4mA (Note 18)
–
–
0.4
V
Logic Output High, VOH
IOH ≥ -2mA (Note 18)
2.25
–
–
V
200
–
1400
kHz
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
Switching Frequency Set-point Accuracy
Predefined settings (see Table 12)
-5
–
5
%
Maximum PWM Duty Cycle
Factory default
95
–
–
%
Minimum SYNC Pulse Width
Input Clock Frequency Drift Tolerance
External clock source
150
–
–
ns
-13
–
13
%
GATE DRIVERS
High-side Driver Voltage
(VBST - VSW)
–
4.5
–
V
High-side Driver Peak Gate Drive Current
(Pull-down)
(VBST - VSW) = 4.5V
2
3
–
A
High-side Driver Pull-up Resistance
(VBST - VSW) = 4.5V, (VBST - VGH) = 50mV
–
0.8
2
Ω
High-side Driver Pull-down Resistance
(VBST - VSW) = 4.5V, (VGH - VSW) = 50mV
–
0.5
2
Ω
Low-side Driver Peak Gate Drive Current
(Pull-up)
VR = 5V
–
2.5
–
A
Low-side Driver Peak Gate Drive
Current (pull-down)
VR = 5V
–
1.8
–
A
Low-side Driver Pull-up Resistance
VR = 5V, (VR - VGL) = 50mV
–
1.2
2
Ω
Low-side Driver Pull-down Resistance
VR = 5V, (VGL - PGND) = 50mV
–
0.5
2
Ω
GH Rise and Fall time
(VBST - VSW) = 4.5V, CLOAD = 2.2nF
–
5
20
ns
GL Rise and Fall time
VR = 5V, CLOAD = 2.2nF
–
5
20
ns
VTRK Input Bias Current
VTRK = 5.5V
–
110
200
µA
VTRK Tracking Ramp Accuracy
100% Tracking, VOUT - VTRK
-100
–
+100
mV
VTRK Regulation Accuracy
100% Tracking, VOUT - VTRK
-1
–
1
%
2.85
–
16
V
SWITCHING TIME
TRACKING
FAULT PROTECTION CHARACTERISTICS
Configurable via I2C/SMBus
UVLO Threshold Range
4
FN6876.3
August 29, 2012
ZL6100
Electrical Specifications
VDD = 12V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C. Boldface limits
apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
UVLO Set-point Accuracy
UVLO Hysteresis
Factory default
Configurable via
I2C/SMBus
UVLO Delay
MIN
(Note 19)
TYP
MAX
(Note 19)
UNIT
-150
–
150
mV
–
3
–
%
0
–
100
%
–
–
2.5
µs
Power-Good VOUT Threshold
Factory default
–
90
–
% VOUT
Power-Good VOUT Hysteresis
Factory default
–
5
–
%
Power-Good Delay
Using pin-strap or resistor (Note 15)
0
–
200
ms
0
–
500
s
Factory default
–
85
–
% VOUT
Configurable via I2C/SMBus
0
–
110
% VOUT
Factory default
–
115
–
% VOUT
Configurable via
VSEN Undervoltage Threshold
VSEN Overvoltage Threshold
I2C/SMBus
Configurable via
I2C/SMBus
0
–
115
% VOUT
–
5
–
% VOUT
–
16
–
µs
5
–
60
µs
Current Limit Set-point Accuracy
(VOUT Referenced)
–
±10
–
% FS
(Note 16)
Current Limit Set-point Accuracy
(Ground referenced)
–
±10
–
% FS
(Note 16)
Factory default
–
5
–
tSW
(Note 17)
Configurable via I2C/SMBus
1
–
32
tSW
(Note 17)
VSEN Undervoltage Hysteresis
VSEN Undervoltage/Overvoltage Fault
Response Time
Current Limit Protection Delay
Factory default
Configurable via
Temperature Compensation of
Current Limit Protection Threshold
Factory default
Thermal Protection Threshold
(Junction Temperature)
Factory default
I2C/SMBus
Configurable via I2C/SMBus
Configurable via
I2C/SMBus
Thermal Protection Hysteresis
–
4400
–
ppm/°C
100
–
12700
ppm/°C
–
125
–
°C
-40
–
125
°C
–
15
–
°C
NOTES:
9. Does not include margin limits.
10. Percentage of Full Scale (FS) with temperature compensation applied.
11. VOUT measured at the termination of the VSEN+ and VSEN- sense points.
12. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approx 2ms, where in normal mode it may vary up to 4ms.
13. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
14. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
15. Factory default Power-Good delay is set to the same value as the soft-start ramp time.
16. Percentage of Full Scale (FS) with temperature compensation applied.
17. tSW = 1/fSW, where fSW is the switching frequency.
18. Normal capacitance of logic pins is 5pF.
19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5
FN6876.3
August 29, 2012
ZL6100
Pinout
28 V25
29 XTEMP
30 DDC
31 MGN
32 CFG
33 EN
34 DLY0
35 DLY1
36 PG
ZL6100
36 LD QFN
TOP VIEW
DGND 1
27 VDD
SYNC 2
26 BST
SA0 3
25 GH
SA1 4
24 SW
THERMAL
PAD
ILIM0 5
23 PGND
VSEN- 18
VSEN+ 17
19 ISENB
VTRK 16
SALRT 9
SS 15
20 ISENA
UVLO 14
SDA 8
V1 13
21 VR
V0 12
SCL 7
FC1 11
22 GL
FC0 10
ILIM1 6
Pin Descriptions
PIN
NUMBER
LABEL
TYPE
(Note 20)
1
DGND
PWR
2
SYNC
I/O,M
(Note 21)
3
SA0
I, M
4
SA1
Serial address select pins. Used to assign unique SMBus address to each IC or to enable certain
management features.
5
ILIM0
I, M
Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
6
ILIM1
7
SCL
I/O
Serial clock. Connect to external host and/or to other Zilker Labs devices.
8
SDA
I/O
Serial data. Connect to external host and/or to other Zilker Labs devices.
9
SALRT
O
Serial alert. Connect to external host if desired.
10
FC0
I
Loop compensation selection pins.
11
FC1
12
V0
I
Output voltage selection pins. Used to set VOUT set-point and VOUT max.
13
V1
14
UVLO
I, M
Undervoltage lockout selection. Sets the minimum value for VDD voltage to enable VOUT.
15
SS
I, M
Soft start pin. Set the output voltage ramp time during turn-on and turnoff.
16
VTRK
I
Tracking sense input. Used to track an external voltage source.
17
VSEN+
I
Output voltage feedback. Connect to output regulation point.
18
VSEN-
I
Output voltage feedback. Connect to load return or ground regulation point.
19
ISENB
I
Differential voltage input for current limit.
6
DESCRIPTION
Digital ground. Common return for digital signals. Connect to low impedance ground plane.
Clock synchronization input. Used to set switching frequency of internal clock or for synchronization to
external frequency reference.
FN6876.3
August 29, 2012
ZL6100
Pin Descriptions (Continued)
PIN
NUMBER
LABEL
TYPE
(Note 20)
20
ISENA
I
21
VR
PWR
22
GL
O
23
PGND
PWR
Power ground. Connect to low impedance ground plane.
24
SW
PWR
Drive train switch node.
25
GH
O
26
BST
PWR
High-side drive boost voltage.
27
VDD
(Note 22)
PWR
Supply voltage.
28
V25
PWR
Internal 2.5V reference used to power internal circuitry.
29
XTEMP
I
30
DDC
I/O
31
MGN
I
32
CFG
I, M
33
EN
I
34
DLY0
I, M
35
DLY1
36
PG
O
ePad
SGND
PWR
DESCRIPTION
Differential voltage input for current limit. High voltage tolerant.
Internal 5V reference used to power internal drivers.
Low-side FET gate drive.
High-side FET gate drive.
External temperature sensor input. Connect to external 2N3904 diode connected transistor.
Digital-DC Bus. (Open Drain) Communication between Zilker Labs devices.
Signal that enables margining of output voltage.
Configuration pin. Used to control the switching phase offset, sequencing and other management
features.
Enable input. Active high signal enables PWM switching.
Soft-start delay select. Sets the delay from when EN is asserted until the output voltage starts to ramp.
Power-good output.
Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low
impedance ground plane.
NOTES:
20. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins.
21. The SYNC pin can be used as a logic pin, a clock input or a clock output.
22. VDD is measured internally and the value is used to modify the PWM loop gain.
7
FN6876.3
August 29, 2012
ZL6100
F.B
(Note 1).
VIN 12V
CIN
3 x 10µF
25V
4.7µF
25V
ENABLE
DDC Bus
(Note 3)
POWER GOOD OUTPUT
CV25
10µF
4V
V25 28
DDC 30
1 DGND
V25
XTEMP 29
MGN 31
EN 33
CFG 32
DLY0 34
PG 36
DLY1 35
QH
CB
BST 26
3 SA0
GH 25
4 SA1
SW 24
ZL6100
5 ILIM0
2.2µH
GL 22
18 VSEN-
EPAD
SGND
17 VSEN+
16 VRTK
15 SS
ISENB 19
14 UVLO
9 SALRT
13 V1
ISENA 20
12 V0
VR 21
8 SDA
11 FC1
7 SCL
VOUT
LOUT
PGND 23
6 ILIM1
10 FC0
1µF
16V
VDD 27
2 SYNC
I2C/SMBus
(Note 2)
DB
BAT54
COUT
2 x 47µF
6.3V
QL
CVR
4.7µF
470µF
2.5V
POS-CAP
2*220µF
6.3V
100m
RTN
6.3V
Ground unification
Notes:
N o te s :
is roptional
input
suppression
1 . F er rite be a d 1.
is Ferrite
o p tiobead
n a l fo
in pu t for
n ois
e snoise
up p re
s s io n
2. The I2C/SMBus requires pull-up resistors. Please refer to the I2C/SMBus
specifications for more details.
2 . T he I 2 C /S M B3.uThe
s reDDC
q u ire
s pu ll- up re s is to rs . P le as e re fe r to th e I 2C /S M B u s s p ec ific a tio n s fo r m o re d eta ils .
bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices
3 . T he D D C buconnected).
s re q u ire sThe
a p10
u ll-u
p r e sisvalue,
to r . assuming
T h e r e saismaximum
ta n c e wofill100
v a rpF
y bper
asdevice,
ed o nprovides
th e c athe
p a necessary
ci tiv e lo a1dµs
ingpull-up
o f thrise
e btime.
u s (aPlease
n d o nrefer
th etonthe
u m b e r o f d e vi ce s
k default
DDC1 Bus
c o n ne c te d) . T he
0k Ωsection
d e fa uforlt more
v a lu details.
e , a s s um in g a m a x im um o f 1 0 0 pF pe r d e v ic e , p r ov id e s th e n e c e s s a ry 1µ s p u ll-u p ris e tim e. P le as e r efe r to th e D D C
B u s s e ctio n fo r m o r e in fo rm atio n.
FIGURE 2. 12V TO 1.8V/20A APPLICATION CIRCUIT (4.5V UVLO, 10ms SS DELAY, 5ms SS RAMP)
Typical Application Circuit
The following application circuit represents a typical
implementation of the ZL6100. For PMBus operation, it is
recommended to tie the enable pin (EN) to SGND.
ZL6100 Overview
Digital-DC Architecture
The ZL6100 is an innovative mixed-signal power conversion
and power management IC based on Zilker Labs patented
Digital-DC technology that provides an integrated, high
performance step-down converter for a wide variety of power
supply applications.
Today’s embedded power systems are typically designed for
optimal efficiency at maximum load, reducing the peak
thermal stress by limiting the total thermal dissipation inside
the system. Unfortunately, many of these systems are often
operated at load levels far below the peak where the power
system has been optimized, resulting in reduced efficiency.
While this may not cause thermal stress to occur, it does
contribute to higher electricity usage and results in higher
overall system operating costs.
Zilker Labs’ efficiency-adaptive ZL6100 DC/DC controller
helps mitigate this scenario by enabling the power converter
to automatically change their operating state to increase
efficiency and overall performance with little or no user
interaction needed.
Its unique PWM loop utilizes an ideal mix of analog and
digital blocks to enable precise control of the entire power
conversion process with no software required, resulting in a
very flexible device that is also very easy to use. An
8
extensive set of power management functions are fully
integrated and can be configured using simple pin
connections. The user configuration can be saved in an
internal non-volatile memory (NVM). Additionally, all
functions can be configured and monitored via the SMBus
hardware interface using standard PMBus commands,
allowing ultimate flexibility.
Once enabled, the ZL6100 is immediately ready to regulate
power and perform power management tasks with no
programming required. Advanced configuration options and
real-time configuration changes are available via the
I2C/SMBus interface if desired and continuous monitoring of
multiple operating parameters is possible with minimal
interaction from a host controller. Integrated sub-regulation
circuitry enables single supply operation from any supply
between 3V and 14V with no secondary bias supplies needed.
The ZL6100 can be configured by simply connecting its pins
according to Tables 1 and 2 provided on page 10 and
page 11. Additionally, a comprehensive set of online tools
and application notes are available to help simplify the
design process. An evaluation board is also available to help
the user become familiar with the device. This board can be
evaluated as a standalone platform using pin configuration
settings. A Windows™-based GUI is also provided to enable
full configuration and monitoring capability via the
I2C/SMBus interface using an available computer and the
included USB cable.
Please refer to www.intersil.com for access to the most
up-to-date documentation or call your local Intersil sales
office to order an evaluation kit.
FN6876.3
August 29, 2012
ZL6100
Power Conversion Overview
Input Voltage Bus
>
PG
EN
MGN
ILIM(0,1)
SS
DLY(0,1)
V(0,1)
FC(0,1)
VDD
VR
VTRK
Power Management
SYNC
GEN
Digital
Compensator
NVM
BST
MOSFET
Drivers
D-PWM
SW
VOUT
NLR
PLL
SYNC
Σ
ADC
-
VSEN
+
ISEN B
ISENA
ADC
REFCN
DAC
VD D
D DC
2
IC
M UX
SALRT
SDA
SCL
SA(0,1)
Voltage
Sensor
ADC
Communication
VSEN+
VSENXTEMP
TEMP
Sensor
FIGURE 3. ZL6100 BLOCK DIAGRAM
The ZL6100 operates as a voltage-mode, synchronous buck
converter with a selectable constant frequency pulse width
modulator (PWM) control scheme that uses external
MOSFETs, capacitors, and an inductor to perform power
conversion.
VIN
DB
CIN
BST
QH
SW
CB
VOUT
QL
GL
VIN - VOUT
COUT
ILPK
FIGURE 4. SYNCHRONOUS BUCK CONVERTER
Figure 4 illustrates the basic synchronous buck converter
topology showing the primary power train components. This
converter is also called a step-down converter, as the output
voltage must always be lower than the input voltage. In its
most simple configuration, the ZL6100 requires two external
N-channel power MOSFETs, one for the top control
MOSFET (QH) and one for the bottom synchronous
MOSFET (QL). The amount of time that QH is on as a
fraction of the total switching period is known as the duty
cycle D, which is described by Equation 1:
V OUT
D ≈ ------------V IN
(EQ. 1)
9
IO
0
CURRENT
(A)
GH
ZL6100
When QH turns off (time 1-D), the current flowing in the
inductor must continue to flow from the ground up through QL,
during which the current ramps down. Since the output
capacitor COUT exhibits a low impedance at the switching
frequency, the AC component of the inductor current is filtered
from the output voltage so the load sees nearly a DC voltage.
VOLTAGE
(V)
VR
During time D, QH is on and VIN – VOUT is applied across
the inductor. The current ramps up as shown in Figure 5.
ILV
-VOUT
D
1-D
TIME
FIGURE 5. INDUCTOR WAVEFORM
Typically, buck converters specify a maximum duty cycle that
effectively limits the maximum output voltage that can be
realized for a given input voltage. This duty cycle limit
ensures that the lowside MOSFET is allowed to turn on for a
minimum amount of time during each switching cycle, which
enables the bootstrap capacitor (CB in Figure 4) to be
charged up and provide adequate gate drive voltage for the
FN6876.3
August 29, 2012
ZL6100
high-side MOSFET. for more details, see “High-side Driver
Boost Circuit” on page 11.
In general, the size of components L1 and COUT as well as
the overall efficiency of the circuit are inversely proportional
to the switching frequency, fSW. Therefore, the highest
efficiency circuit may be realized by switching the MOSFETs
at the lowest possible frequency; however, this will result in
the largest component size. Conversely, the smallest
possible footprint may be realized by switching at the fastest
possible frequency but this gives a somewhat lower
efficiency. Each user should determine the optimal
combination of size and efficiency when determining the
switching frequency for each application.
The block diagram for the ZL6100 is illustrated in “Typical
Application Circuit” on page 8 In this circuit, the target output
voltage is regulated by connecting the differential VSEN pins
directly to the output regulation point. The VSEN signal is
then compared to a reference voltage that has been set to
the desired output voltage level by the user. The error signal
derived from this comparison is converted to a digital value
with a low-resolution, analog-to-digital (A/D) converter. The
digital signal is applied to an adjustable digital compensation
filter, and the compensated signal is used to derive the
appropriate PWM duty cycle for driving the external
MOSFETs in a way that produces the desired output.
The ZL6100 has several features to improve the power
conversion efficiency. A non-linear response (NLR) loop
improves the response time and reduces the output
deviation as a result of a load transient. The ZL6100
monitors the power converter’s operating conditions and
continuously adjusts the turn-on and turn-off timing of the
high-side and low-side MOSFETs to optimize the overall
efficiency of the power supply. Adaptive performance
optimization algorithms such as dead-time control, diode
emulation, and frequency control are available to provide
greater efficiency improvement.
Power Management Overview
The ZL6100 incorporates a wide range of configurable power
management features that are simple to implement with no
external components. Additionally, the ZL6100 includes circuit
protection features that continuously safeguard the device
and load from damage due to unexpected system faults. The
ZL6100 can continuously monitor input voltage, output
voltage/current, internal temperature, and the temperature of
an external thermal diode. A Power-Good output signal is also
included to enable power-on reset functionality for an external
processor.
All power management functions can be configured using
either pin configuration techniques (see Figure 6) or via the
I2C/SMBus interface. Monitoring parameters can also be
pre-configured to provide alerts for specific conditions. See
Application Note AN2033 for more details on SMBus
monitoring.
10
Multi-mode Pins
In order to simplify circuit design, the ZL6100 incorporates
patented multi-mode pins that allow the user to easily
configure many aspects of the device with no programming.
Most power management features can be configured using
these pins. The multi-mode pins can respond to four different
connections as shown in Table 1. These pins are sampled
when power is applied or by issuing a PMBus Restore
command (see Application Note AN2033).
PIN-STRAP SETTINGS
This is the simplest implementation method, as no external
components are required. Using this method, each pin can
take on one of three possible states: LOW, OPEN, or HIGH.
These pins can be connected to the V25 pin for logic HIGH
settings as this pin provides a regulated voltage higher than
2V. Using a single pin, one of three settings can be selected.
Using two pins, one of nine settings can be selected.
MULTI-MODE PIN CONFIGURATION
TABLE 1. MULTI-MODE PIN CONFIGURATION
PIN TIED TO
VALUE
LOW (Logic LOW)
< 0.8VDC
OPEN (N/C)
No Connection
HIGH (Logic HIGH)
> 2.0VDC
Resistor to SGND
Set by resistor value
LOGIC
HIGH
OPEN
ZL6100
ZL6100
MULTI-MODE PIN
MULTI-MODE PIN
RSET
LOGIC
LOW
PIN-STRAP
SETTINGS
RESISTOR
SETTINGS
FIGURE 6. PIN-STRAP AND RESISTOR SETTING EXAMPLES
RESISTOR SETTINGS
This method allows a greater range of adjustability when
connecting a finite value resistor (in a specified range)
between the multi-mode pin and SGND. Standard 1%
resistor values are used, and only every fourth E96 resistor
value is used so the device can reliably recognize the value
of resistance connected to the pin while eliminating the error
associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
I2C/SMBUS METHOD
Almost any ZL6100 function can be configured via the
I2C/SMBus interface using standard PMBus commands.
Additionally, any value that has been configured using the
pin-strap or resistor setting methods can also be re-configured
and/or verified via the I2C/SMBus. See Application Note
AN2033 for more details.
FN6876.3
August 29, 2012
ZL6100
The SMBus device address and VOUT_MAX are the only
parameters that must be set by external pins. All other device
parameters can be set via the I2C/SMBus. The device address is
set using the SA0 and SA1 pins. VOUT_MAX is determined as
10% greater than the voltage set by the V0 and V1 pins.
Power Conversion Functional Description
Internal Bias Regulators and Input Supply
Connections
The ZL6100 employs two internal low dropout (LDO)
regulators to supply bias voltages for internal circuitry,
allowing it to operate from a single input supply. The internal
bias regulators are as follows:
• VR:The VR LDO provides a regulated 5V bias supply for
the MOSFET driver circuits. It is powered from the VDD
pin. A 4.7µF filter capacitor is required at the VR pin.
• V25:The V25 LDO provides a regulated 2.5V bias supply
for the main controller circuitry. It is powered from an
internal 5V node. A 10µF filter capacitor is required at the
V25 pin.
When the input supply (VDD) is higher than 5.5V, the VR pin
should not be connected to any other pins. It should only
have a filter capacitor attached as shown in Figure 7. Due to
the dropout voltage associated with the VR bias regulator,
the VDD pin must be connected to the VR pin for designs
operating from a supply below 5.5V. Figure 7 illustrates the
required connections for both cases.
VIN
VIN
VDD
VDD
ZL6100
VR
3V≤ VIN ≤ 5.5V
STANDARD MODE
The output voltage may be set to any voltage between 0.6V
and 5.0V provided that the input voltage is higher than the
desired output voltage by an amount sufficient to prevent the
device from exceeding its maximum duty cycle specification.
Using the pin-strap method, VOUT can be set to any of nine
standard voltages as shown in Table 2.
TABLE 2. PIN-STRAP OUTPUT VOLTAGE SETTINGS
V0
V1
LOW
OPEN
HIGH
LOW
0.6V
0.8V
1.0V
OPEN
1.2V
1.5V
1.8V
HIGH
2.5V
3.3V
5.0V
The resistor setting method can be used to set the output
voltage to levels not available in Table 2. Resistors R0 and
R1 are selected to produce a specific voltage between 0.6V
and 5.0V in 10mV steps. Resistor R1 provides a coarse
setting and resistor R0 provides a fine adjustment, thus
eliminating the additional errors associated with using two
1% resistors (this typically adds ~1.4% error).
To set VOUT using resistors, follow the steps below to calculate
an index value and then use Table 3 to select the resistor that
corresponds to the calculated index value as follows:
1. Calculate Index1:
Index1 = 4 x VOUT (VOUT in 10mV steps)
2. Round the result down to the nearest whole number.
ZL6100
VR
Output Voltage Selection
5.5V< VIN ≤ 14V
FIGURE 7. INPUT SUPPLY CONNECTIONS
3. Select the value of R1 from Table 3 using the Index1
rounded value from Step 2.
4. Calculate Index0: Index0 = 100 x VOUT – (25 x Index1)
5. Select the value of R0 from Table 3 using the Index0
value from Step 4.
Note: the internal bias regulators are not designed to be
outputs for powering other circuitry. Do not attach external
loads to any of these pins. The multi-mode pins may be
connected to the V25 pin for logic HIGH settings.
High-side Driver Boost Circuit
The gate drive voltage for the high-side MOSFET driver is
generated by a floating bootstrap capacitor, CB
(see Figure 4). When the lower MOSFET (QL) is turned on,
the SW node is pulled to ground and the capacitor is
charged from the internal VR bias regulator through diode
DB. When QL turns off and the upper MOSFET (QH) turns
on, the SW node is pulled up to VDD and the voltage on the
bootstrap capacitor is boosted approximately 5V above VDD
to provide the necessary voltage to power the high-side
driver. A Schottky diode should be used for DB to help
maximize the high-side drive supply voltage.
11
FN6876.3
August 29, 2012
ZL6100
POLA VOLTAGE TRIM MODE
TABLE 3. RESISTORS FOR SETTING OUTPUT
VOLTAGE
INDEX
R0 OR R1
(kΩ)
INDEX
R0 OR R1
(kΩ)
0
10
13
34.8
1
11
14
38.3
2
12.1
15
42.2
3
13.3
16
46.4
4
14.7
17
51.1
5
16.2
18
56.2
6
17.8
19
61.9
7
19.6
20
68.1
8
21.5
21
75
9
23.7
22
82.5
10
26.1
23
90.9
11
28.7
24
100
12
31.6
The output voltage mapping can be changed to match the
voltage setting equations for POLA and DOSA standard
modules.
The standard method for adjusting the output voltage for a
POLA module is defined by Equation 3:
0.69V
(EQ. 3)
R SET = 10kΩ × ---------------------------------- – 1.43kΩ
V OUT – 0.69V
The resistor, RSET, is external to the POLA module
(see Figure 9).
To stay compatible with this existing method for adjusting the
output voltage, the module manufacturer should add a 10kΩ
resistor on the module as shown in Figure 10. Now, the
same RSET used for an analog POLA module will provide the
same output voltage when using a digital POLA module
based on the ZL6100.
POLA MODULE
0.69V
+
Example from Figure 8: For VOUT = 1.33V,
VOUT
-
Index1 = 4 x 1.33V = 5.32;
From Table 3, R1 = 16.2k
Ω
1.43kO
Ω
10kO
Index0 = (100 x 1.33V) – (25 x 5) = 8;
RSET
From Table 3, R0 = 21.5k
The output voltage can be determined from the R0 (Index0)
and R1 (Index1) values using Equation 2:
Index0 + ( 25xIndex1 )
(EQ. 2)
V OUT = -------------------------------------------------------100
FIGURE 9. OUTPUT VOLTAGE SETTING ON POLA MODULE
SMBUS MODE
The output voltage may be set to any value between 0.6V
and 5.0V using a PMBus command over the I2C/SMBus
interface. See Application Note AN2033 for details.
POLA
MODULE
VIN
ZL6100
V0 V1
Ω
110kO
Ω
10kO
GH
VOUT
SW
ZL
1.33V
RSET
GL
V0
R0
Ω
21.5 kO
V1
R1
16.2 k Ω
O
FIGURE 10. RSET ON A POLA MODULE
FIGURE 8. OUTPUT VOLTAGE RESISTOR SETTING EXAMPLE
The POLA mode is activated through pin-strap by
connecting a 110k resistor on V0 to SGND. The V1 pin is
then used to adjust the output voltage as shown in Table 4
.
12
FN6876.3
August 29, 2012
ZL6100
TABLE 4. POLA MODE VOUT SETTINGS (R0 = 110k,
R1 = RSET + 10k)
VOUT
(V)
RSET
IN SERIES WITH
10kΩ
RESISTOR
(kΩ)
VOUT
(V)
RSET
IN SERIES
WITH 10kΩ
RESISTOR
(kΩ)
0.700
162
0.991
21.5
0.752
110
1.000
0.758
100
0.765
The DOSA mode VOUT settings are listed in Table 5.
TABLE 5. DOSA MODE VOUT SETTINGS (R0 = 110k,
R1 = RSET + 8.66k)
VOUT
(V)
RSET
IN SERIES
WITH 8.66kΩ
RESISTOR
(kΩ)
VOUT
(V)
RSET
IN SERIES
WITH 8.66kΩ
RESISTOR
(kΩ)
19.6
0.700
162
0.991
22.6
1.100
16.2
0.752
113
1.000
21.0
90.9
1.158
13.3
0.758
100
1.100
17.8
0.772
82.5
1.200
12.1
0.765
90.9
1.158
14.7
0.790
75.0
1.250
9.09
0.772
82.5
1.200
13.3
0.800
56.2
1.500
7.50
0.790
75.0
1.250
10.5
0.821
51.1
1.669
5.6
0.800
57.6
1.500
8.87
0.834
46.4
1.800
4.64
0.821
52.3
1.669
6.98
0.848
42.2
2.295
2.87
0.834
47.5
1.800
6.04
0.880
34.8
2.506
2.37
0.848
43.2
2.295
4.32
0.899
31.6
3.300
1.21
0.880
36.5
2.506
3.74
0.919
28.7
5.000
0.162
0.899
33.2
3.300
2.61
0.965
23.7
0.919
30.1
5.000
1.50
0.965
25.5
DOSA VOLTAGE TRIM MODE
On a DOSA module, the VOUT setting follows Equation 4:
6900
(EQ. 4)
R SET = ---------------------------------V OUT – 0.69V
To maintain DOSA compatibility, the same scheme is used
as with a POLA module except the 10kΩ resistor is replaced
with a 8.66k resistor as shown in Figure 11.
DOSA
MODULE
ZL6100
V0 V1
110 k Ω
8.66 k Ω
RSET
FIGURE 11. RSET ON A DOSA MODULE
Start-up Procedure
The ZL6100 follows a specific internal start-up procedure
after power is applied to the VDD pin. Table 6 describes the
start-up sequence.
If the device is to be synchronized to an external clock source,
the clock frequency must be stable prior to asserting the EN
pin. The device requires approximately 5ms to 10ms to check
for specific values stored in its internal memory. If the user has
stored values in memory, those values will be loaded. The
device will then check the status of all multi-mode pins and
load the values associated with the pin settings.
Once this process is completed, the device is ready to
accept commands via the I2C/SMBus interface and the
device is ready to be enabled. Once enabled, the device
requires approximately 2ms before its output voltage may be
allowed to start its ramp-up process. If a soft-start delay
period less than 2ms has been configured (using DLY pins
or PMBus commands), the device will default to a 2ms delay
period. If a delay period greater than 2ms is configured, the
device will wait for the configured delay period prior to
starting to ramp its output.
After the delay period has expired, the output will begin to
ramp towards its target voltage according to the
pre-configured soft-start ramp time that has been set using
the SS pin. It should be noted that if the EN pin is tied to
VDD, the device will still require approx 5ms to 10ms before
the output can begin its ramp-up as described in Table 6.
13
FN6876.3
August 29, 2012
ZL6100
TABLE 6. ZL6100 START-UP SEQUENCE
STEP
STEP NAME
DESCRIPTION
TIME DURATION
1
Power Applied
Input voltage is applied to the ZL6100’s VDD pin Depends on input supply ramp time
2
Internal Memory Check
3
Multi-mode Pin Check
The device will check for values stored in its
internal memory. This step is also performed after
Approx 5ms to 10ms (device will ignore an
a Restore command.
enable signal or PMBus traffic during this period)
The device loads values configured by the multimode pins.
4
Device Ready
The device is ready to accept an enable signal.
5
Pre-ramp Delay
The device requires approximately 2ms following Approximately 2ms
an enable signal and prior to ramping its output.
Additional pre-ramp delay may be configured
using the Delay pins.
-
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable
signal is received until the output voltage starts to ramp to its
target value. In addition, the designer may wish to precisely
set the time required for VOUT to ramp to its target value after
the delay period has expired. These features may be used
as part of an overall inrush current management strategy or
to precisely control how fast a load IC is turned on. The
ZL6100 gives the system designer several options for
precisely and independently controlling both the delay and
ramp time periods.
The soft-start delay period begins when the EN pin is
asserted and ends when the delay time expires. The
soft-start delay period is set using the DLY (0, 1) pins.
Precise ramp delay timing reduces the delay time variations
but is only available when the appropriate bit in the
MISC_CONFIG register has been set. Please refer to
Application Note AN2033 for details.
The soft-start ramp timer enables a precisely controlled ramp
to the nominal VOUT value that begins once the delay period
has expired. The ramp-up is guaranteed monotonic and its
slope may be precisely set using the SS pin.
The soft start delay and ramp times can be set to standard
values according to Tables 7 and 8 respectively.
TABLE 7. SOFT-START DELAY SETTINGS
DLY0
DLY1
LOW
(ms)
OPEN
(ms)
HIGH
(ms)
LOW
0
1
2
OPEN
5
10
20
HIGH
50
100
200
Note: When the device is set to 0ms or 1ms delay, it will begin
its ramp up after the internal circuitry has initialized (~2ms).
14
TABLE 8. SOFT-START RAMP SETTINGS
SS
RAMP TIME
(ms)
LOW
0
OPEN
5
HIGH
10
Note: When the device is set to 0ms ramp, it will attempt to
ramp as fast as the external load capacitance and loop
settings will allow. It is generally recommended to set the
soft-start ramp to a value greater than 500µs to prevent
inadvertent fault conditions due to excessive inrush current.
If the desired soft start delay and ramp times are not one of
the values listed in Tables 7 and 8, the times can be set to a
custom value by connecting a resistor from the DLY0 or SS
pin to SGND using the appropriate resistor value from
Table 9. The value of this resistor is measured upon start-up
or Restore and will not change if the resistor is varied after
power has been applied to the ZL6100. See Figure 12 for
typical connections using resistors.
TABLE 9. DLY AND SS RESISTOR SETTINGS
DLY OR SS
(ms)
RDLY OR RSS
(kΩ)
DLY OR SS
(ms)
RDLY OR RSS
(kΩ)
0
10
110
28.7
10
11
120
31.6
20
12.1
130
34.8
30
13.3
140
38.3
40
14.7
150
42.2
50
16.2
160
46.4
60
17.8
170
51.1
70
19.6
180
56.2
80
21.5
190
61.9
90
23.7
200
68.1
100
26.1
FN6876.3
August 29, 2012
ZL6100
RDLY
DLY1
DLY0
NC
SS
ZL6100
RSS
The SYNC pin is a unique pin that can perform multiple
functions depending on how it is configured. The CFG pin is
used to select the operating mode of the SYNC pin as
shown in Table 10. Figure 13 illustrates the typical
connections for each mode.
TABLE 10. SYNC PIN FUNCTION SELECTION
CFG PIN
SYNC PIN FUNCTION
LOW
SYNC is configured as an input
OPEN
Auto Detect mode
HIGH
SYNC is configured as an output
fSW = 400kHz
CONFIGURATION A: SYNC OUTPUT
FIGURE 12. DLY AND SS PIN RESISTOR CONNECTIONS
Note: Do not connect a resistor to the DLY1 pin. This pin is
not utilized for setting soft-start delay times. Connecting an
external resistor to this pin may cause conflicts with other
device settings.
The soft-start delay and ramp times can also be set to
custom values via the I2C/SMBus interface. When the SS
delay time is set to 0ms, the device will begin its ramp-up
after the internal circuitry has initialized (~2ms). When the
soft-start ramp period is set to 0ms, the output will ramp-up
as quickly as the output load capacitance and loop settings
will allow. It is generally recommended to set the soft-start
ramp to a value greater than 500µs to prevent inadvertent
fault conditions due to excessive inrush current.
Power-Good
The ZL6100 provides a Power-Good (PG) signal that
indicates the output voltage is within a specified tolerance of
its target level and no fault condition exists. By default, the PG
pin will assert if the output is within -10%/+15% of the target
voltage. These limits and the polarity of the pin may be
changed via the I2C/SMBus interface. See Application Note
AN2033 for details.
A PG delay period is defined as the time from when all
conditions within the ZL6100 for asserting PG are met to
when the PG pin is actually asserted. This feature is
commonly used instead of using an external reset controller
to control external digital logic. By default, the ZL6100 PG
delay is set equal to the soft-start ramp time setting.
Therefore, if the soft-start ramp time is set to 1ms, the PG
delay will be set to 10ms. The PG delay may be set
independently of the soft-start ramp using the I2C/SMBus as
described in Application Note AN2033.
Switching Frequency and PLL
The ZL6100 incorporates an internal phase-locked loop
(PLL) to clock the internal circuitry. The PLL can be driven by
an external clock source connected to the SYNC pin. When
using the internal oscillator, the SYNC pin can be configured
as a clock source for other Zilker Labs devices.
15
When the SYNC pin is configured as an output (CFG pin is
tied HIGH), the device will run from its internal oscillator and
will drive the resulting internal oscillator signal (preset to
400kHz) onto the SYNC pin so other devices can be
synchronized to it. The SYNC pin will not be checked for an
incoming clock signal while in this mode.
CONFIGURATION B: SYNC INPUT
When the SYNC pin is configured as an input (CFG pin is
tied LOW), the device will automatically check for a clock
signal on the SYNC pin each time EN is asserted. The
ZL6100’s oscillator will then synchronize with the rising edge
of the external clock.
The incoming clock signal must be in the range of 200kHz to
1.4MHz and must be stable when the enable pin is asserted.
The clock signal must also exhibit the necessary
performance requirements (see the “Electrical
Specifications” table beginning on page 3). In the event of a
loss of the external clock signal, the output voltage may
show transient over/undershoot.
If this happens, the ZL6100 will automatically switch to its
internal oscillator and switch at a frequency close to the
previous incoming frequency.
CONFIGURATION C: SYNC AUTO DETECT
When the SYNC pin is configured in auto detect mode (CFG
pin is left OPEN), the device will automatically check for a
clock signal on the SYNC pin after enable is asserted.
If a clock signal is present, The ZL6100’s oscillator will then
synchronize the rising edge of the external clock. Refer to
“Configuration B: SYNC INPUT”.
If no incoming clock signal is present, the ZL6100 will
configure the switching frequency according to the state of the
SYNC pin as listed in Table 15. In this mode, the ZL6100 will
only read the SYNC pin connection during the start-up
sequence. Changes to SYNC pin connections will not affect
fSW until the power (VDD) is cycled off and on If the user
wishes to run the ZL6100 at a frequency not listed in Table 11,
the switching frequency can be set using an external resistor,
RSYNC, connected between SYNC and SGND using Table 12.
FN6876.3
August 29, 2012
ZL6100
SYNC
200kHz – 1.33MHz
200kHz – 1.4MHz
ZL6100
ZL6100
A) SYNC = OUTPUT
Open
OR
ZL6100
LOGIC
LOW
SYNC
N/C
ZL6100
SYNC
OR
RSYNC
CFG
N/C
LOGIC
HIGH
CFG
SYNC
B) SYNC = INPUT
CFG
N/C
CFG
SYNC
CFG
LOGIC
HIGH
ZL6100
C) SYNC = AUTO DETECT
FIGURE 13. SYNC PIN CONFIGURATIONS
TABLE 11. SWITCHING FREQUENCY SELECTION
SYNC PIN
FREQUENCY
(Hz)
LOW
200k
OPEN
400k
HIGH
1M
Resistor
See Table 12
If a value other than fSW = 8MHz/N is entered using a
PMBus command, the internal circuitry will select the valid
switching frequency value that is closest to the entered
value. For example, if 810kHz is entered, the device will
select 800kHz (N = 10).
When multiple Zilker Labs devices are used together,
connecting the SYNC pins together will force all devices to
synchronize with each other. The CFG pin of one device
must set its SYNC pin as an output and the remaining
devices must have their SYNC pins set as Auto Detect.
TABLE 12. RSYNC RESISTOR VALUES
RSYNC
(kΩ)
fSW
(kHz)
RSYNC
(kΩ)
fSW
(kHz)
10
200
−
-
11
222
26.1
533
12.1
242
28.7
571
13.3
267
31.6
615
14.7
296
34.8
727
16.2
320
38.3
800
17.8
364
46.4
889
19.6
400
51.1
1000
21.5
421
56.2
1143
23.7
471
68.1
1333
Note: The switching frequency read back using the
appropriate PMBus command will differ slightly from the
selected values in Table 12. The difference is due to
hardware quantization.
Power Train Component Selection
The ZL6100 is a synchronous buck converter that uses
external MOSFETs, inductor and capacitors to perform the
power conversion process. The proper selection of the
external components is critical for optimized performance.
To select the appropriate external components for the
desired performance goals, the power supply requirements
listed in Table 13 must be known.
The switching frequency can also be set to any value
between 200kHz and 1.33MHz using the I2C/SMBus
interface. The available frequencies below 1.4MHz are
defined by fSW = 8MHz/N, where the whole number N is
6 ≤ N ≤ 40. See Application Note AN2033 for details.
16
FN6876.3
August 29, 2012
ZL6100
TABLE 13. POWER SUPPLY REQUIREMENTS
RANGE
EXAMPLE
VALUE
Input voltage (VIN)
3.0V to 14.0V
12V
Output voltage (VOUT)
0.6V to 5.0V
1.2V
Output current (IOUT)
0A to ~25A
20A
Output voltage ripple
(Vorip)
< 3% of VOUT
1% of VOUT
< Io
50% of Io
Output load step rate
-
10A/µs
Output deviation due to loadstep
-
±50mV
+120°C
+85°C
-
85%
Various
Optimize for
small size
PARAMETER
Output load step (Iostep)
Maximum PCB temp.
Desired efficiency
Other considerations
DESIGN GOAL TRADE-OFFS
The design of the buck power stage requires several
compromises among size, efficiency, and cost. The inductor
core loss increases with frequency, so there is a trade-off
between a small output filter made possible by a higher
switching frequency and getting better power supply
efficiency. Size can be decreased by increasing the
switching frequency at the expense of efficiency. Cost can
be minimized by using through-hole inductors and
capacitors; however these components are physically large.
To start the design, select a switching frequency based on
Table 14. This frequency is a starting point and may be
adjusted as the design progresses.
TABLE 14. CIRCUIT DESIGN CONSIDERATIONS
FREQUENCY RANGE
EFFICIENCY
CIRCUIT SIZE
200kHz to 400kHz
Highest
Larger
400kHz to 800kHz
Moderate
Smaller
800kHz to 1.4MHz
Lower
Smallest
Now the output inductance can be calculated using
Equation 6, where VINM is the maximum input voltage:
LOUT
⎛ V
VOUT × ⎜⎜1 − OUT
VINM
⎝
=
f sw × I opp
⎞
⎟⎟
⎠
(EQ. 6)
The average inductor current is equal to the maximum
output current. The peak inductor current (ILpk) is calculated
using Equation 7 where IOUT is the maximum output current.
I Lpk = I OUT +
I opp
(EQ. 7)
2
Select an inductor rated for the average DC current with a
peak current rating above the peak current computed .
In overcurrent or short-circuit conditions, the inductor may
have currents greater than 2x the normal maximum rated
output current. It is desirable to use an inductor that still
provides some inductance to protect the load and the
MOSFETs from damaging currents in this situation.
Once an inductor is selected, the DCR and core losses in
the inductor are calculated. Use the DCR specified in the
inductor manufacturer’s datasheet.
PLDCR = DCR × I Lrms
(EQ. 8)
2
ILrms is given by
(I )
2
I Lrms = I OUT +
2
opp
(EQ. 9)
12
where IOUT is the maximum output current. Next, calculate
the core loss of the selected inductor. Since this calculation
is specific to each inductor and manufacturer, refer to the
chosen inductor datasheet. Add the core loss and the ESR
loss and compare the total loss to the maximum power
dissipation recommendation in the inductor datasheet.
OUTPUT CAPACITOR SELECTION
INDUCTOR SELECTION
The output inductor selection process must include several
trade-offs. A high inductance value will result in a low ripple
current (Iopp), which will reduce output capacitance and
produce a low output ripple voltage, but may also
compromise output transient load performance. Therefore, a
balance must be struck between output ripple and optimal
load transient performance. A good starting point is to select
the output inductor ripple equal to the expected load
transient step magnitude (Iostep; see Equation 5):
I OPP = I OSTEP
(EQ. 5)
17
Several trade-offs must also be considered when selecting
an output capacitor. Low ESR values are needed to have a
small output deviation during transient load steps (Vosag) and
low output voltage ripple (Vorip). However, capacitors with
low ESR, such as semi-stable (X5R and X7R) dielectric
ceramic capacitors, also have relatively low capacitance
values. Many designs can use a combination of high
capacitance devices and low ESR devices in parallel.
For high ripple currents, a low capacitance value can cause
a significant amount of output voltage ripple. Likewise, in
high transient load steps, a relatively large amount of
capacitance is needed to minimize the output voltage
deviation while the inductor current ramps up or down to the
new steady state output current value.
FN6876.3
August 29, 2012
ZL6100
As a starting point, apportion one-half of the output ripple
voltage to the capacitor ESR and the other half to
capacitance, as shown in Equations 10 and 11:
I opp
C OUT =
8 × f sw ×
ESR =
PQL = 0.05 × VOUT × I OUT
(EQ. 14)
(EQ. 10)
Vorip
Calculate the RMS current in QL as shown in Equation 15:
2
I botrms = I Lrms × 1 − D
Vorip
(EQ. 11)
2 × I opp
Use these values to make an initial capacitor selection, using
a single capacitor or several capacitors in parallel.
After a capacitor has been selected, the resulting output
voltage ripple can be calculated using Equation 12:
Vorip = I opp × ESR +
rDS(ON) of QL (lower output voltages and higher step-down
ratios will be closer to 5%):
I opp
(EQ. 12)
8 × f sw × C OUT
Because each part of this equation was made to be less than
or equal to half of the allowed output ripple voltage, the Vorip
should be less than the desired maximum output ripple.
INPUT CAPACITOR
It is highly recommended that dedicated input capacitors be
used in any point-of-load design, even when the supply is
powered from a heavily filtered 5V or 12V “bulk” supply from
an off-line power supply. This is because of the high RMS
ripple current that is drawn by the buck converter topology.
This ripple (ICINrms) can be determined from Equation 13:
I CINrms = I OUT × D × (1 − D)
(EQ. 13)
Without capacitive filtering near the power supply circuit, this
current would flow through the supply bus and return planes,
coupling noise into other system circuitry. The input capacitors
should be rated at 1.2x the ripple current calculated above to
avoid overheating of the capacitors due to the high ripple
current, which can cause premature failure. Ceramic
capacitors with x7R or x5R dielectric with low ESR and 1.1x
the maximum expected input voltage are recommended.
BOOTSTRAP CAPACITOR SELECTION
The high-side driver boost circuit utilizes an external Schottky
diode (DB) and an external bootstrap capacitor (CB) to supply
sufficient gate drive for the high-side MOSFET driver. DB
should be a 20mA, 30V Schottky diode or equivalent device
and CB should be a 1µF ceramic type rated for at least 6.3V.
Calculate the desired maximum rDS(ON) as shown in
Equation 16:
RDS ( ON ) =
The bottom MOSFET should be selected primarily based on
the device’s rDS(ON) and secondarily based on its gate
charge. To choose QL, use Equations 14, 15 and 16, and
allow 2% to 5% of the output power to be dissipated in the
18
PQL
(I botrms )2
(EQ. 16)
Note that the rDS(ON) given in the manufacturer’s datasheet
is measured at +25°C. The actual rDS(ON) in the end-use
application will be much higher. For example, a Vishay
Si7114 MOSFET with a junction temperature of +125°C has
an rDS(ON) that is 1.4x higher than the value at +25°C. Select
a candidate MOSFET, and calculate the required gate drive
current as shown in Equation 17:
I g = f SW × Qg
(EQ. 17)
Keep in mind that the total allowed gate drive current for both
QH and QL is 80mA.
MOSFETs with lower rDS(ON) tend to have higher gate
charge requirements, which increases the current and
resulting power required to turn them on and off. Since the
MOSFET gate drive circuits are integrated in the ZL6100,
this power is dissipated in the ZL6100 according to
Equation 18:
PQL = f sw × Qg × VINM
(EQ. 18)
QH SELECTION
In addition to the rDS(ON) loss and gate charge loss, QH also
has switching loss. The procedure to select QH is similar to
the procedure for QL. First, assign 2% to 5% of the output
power to be dissipated in the rDS(ON) of QH using
Equation 18. As was done with QL, calculate the RMS
current as shown in Equation 19:
I toprms = I Lrms × D
(EQ. 19)
Calculate a starting rDS(ON) as follows, in this example using
5%
PQH = 0.05 × VOUT × I OUT
RDS ( ON ) =
QL SELECTION
(EQ. 15)
(I
PQH
)
2
toprms
(EQ. 20)
(EQ. 21)
Select a MOSFET and calculate the resulting gate drive
current. Verify that the combined gate drive current from QL
and QH does not exceed 80mA.
FN6876.3
August 29, 2012
ZL6100
Next, calculate the switching time using Equation 22:
t SW =
Qg
frequency on the inductance when determining the minimum
value of L. Use the typical value for DCR.
(EQ. 22)
I gdr
where Qg is the gate charge of the selected QH and Igdr is
the peak gate drive current available from the ZL6100.
Although the ZL6100 has a typical gate drive current of 3A,
use the minimum guaranteed current of 2A for a
conservative design. Using the calculated switching time,
calculate the switching power loss in QH using Equation 23:
Pswtop = VINM × t sw × I OUT × f sw
(EQ. 23)
The total power dissipated by QH is given by Equation 24:
PQHtot = PQH + Pswtop
The value of R1 should be as small as feasible and no
greater than 5kΩ for best signal-to-noise ratio. The designer
should make sure the resistor package size is appropriate
for the power dissipated and include this loss in efficiency
calculations. In calculating the minimum value of R1, the
average voltage across CL (which is the average IOUT . DCR
product) is small and can be neglected. Therefore, the
minimum value of R1 may be approximated by using
Equation 27:
D (VIN −max − VOUT ) + (1 − D ) ⋅ VOUT
=
PR1 pkg − max ⋅ δ P
2
R1−min
2
(EQ. 27)
(EQ. 24)
MOSFET THERMAL CHECK
Once the power dissipations for QH and QL have been
calculated, the MOSFETs junction temperature can be
estimated. Using the junction-to-case thermal resistance
(Rth) given in the MOSFET manufacturer’s datasheet and
the expected maximum printed circuit board temperature,
calculate the junction temperature as shown in Equation 25:
T j max = T pcb + (PQ × Rth )
where PR1pkg-max is the maximum power dissipation
specification for the resistor package and δP is the derating
factor for the same parameter (eg.: PR1pkg-max = 0.0625W
for 0603 package, δP = 50% @ +85°C). Once R1-min has
been calculated, solve for the maximum value of CL from
using Equation 28:
C L− max =
(EQ. 25)
CURRENT SENSING COMPONENTS
Once the current sense method has been selected (See
“Current Limit Threshold Selection” on page 19.”), the
components are selected as follows.
When using the inductor DCR sensing method, the user
must also select an R/C network comprised of R1 and CL
(see Figure 14).
(EQ. 28)
and choose the next-lowest readily available value (eg.: For
CL-max = 1.86µF, CL = 1.5µF is a good choice). Then
substitute the chosen value into the same equation and
recalculate the value of R1. Choose the 1% resistor standard
value closest to this re-calculated value of R1. The error due
to the mismatch of the two time constants is shown in
Equation 29:
⎛
ε τ = ⎜⎜1 −
⎝
VIN
L
R1− min ⋅ DCR
R1 ⋅ C L ⋅ DCR ⎞⎟
⋅ 100%
⎟
Lavg
⎠
(EQ. 29)
The value of R2 should be simply five times that of R1:
R2 = 5 ⋅ R1
GH
SW
R1
ZL6100
CL
VOUT
For the rDS(ON) current sensing method, the external low
side MOSFET will act as the sensing element as indicated in
Figure 16.
GL
R2
ISENA
ISENB
Current Limit Threshold Selection
FIGURE 14. DCR CURRENT SENSING
For the voltage across CL to reflect the voltage across the
DCR of the inductor, the time constant of the inductor must
match the time constant of the RC network (see
Equation 26).
τ RC = τ L / DCR
R1 ⋅ C L =
(EQ. 30)
(EQ. 26)
L
DCR
For L, use the average of the nominal value and the minimum
value. Include the effects of tolerance, DC Bias and switching
19
It is recommended that the user include a current limiting
mechanism in their design to protect the power supply from
damage and prevent excessive current from being drawn
from the input supply in the event that the output is shorted
to ground or an overload condition is imposed on the output.
Current limiting is accomplished by sensing the current
through the circuit during a portion of the duty cycle.
Output current sensing can be accomplished by measuring
the voltage across a series resistive sensing element
according to Equation 31:
V LIM = I LIM × RSENSE
(EQ. 31)
FN6876.3
August 29, 2012
ZL6100
Where:
VIN
ILIM is the desired maximum current that should flow in the
circuit
GH
RSENSE is the resistance of the sensing element
ZL6100
VLIM is the voltage across the sensing element at the point
the circuit should start limiting the output current.
VOUT
SW
ISENA
GL
ISENB
The ZL6100 supports “lossless” current sensing by
measuring the voltage across a resistive element that is
already present in the circuit. This eliminates additional
efficiency losses incurred by devices that must use an
additional series resistance in the circuit.
MOSFET RDS(ON) SENSING
VIN
To set the current limit threshold, the user must first select a
current sensing method. The ZL6100 incorporates two
methods for current sensing, synchronous MOSFET rDS(ON)
sensing and inductor DC resistance (DCR) sensing;
Figure 15 shows a simplified schematic for each method.
The current sensing method can be selected using the ILIM1
pin using Table 15. The ILIM0 pin must have a finite resistor
connected to ground in order for Table 15 to be valid. If no
resistor is connected between ILIM0 and ground, the default
method is MOSFET rDS(ON) sensing. The current sensing
method can be modified via the I2C/SMBus interface. Please
refer to Application Note AN2033 for details.
In addition to selecting the current sensing method, the
ZL6100 gives the power supply designer several choices for
GH
VOUT
SW
ZL6100
GL
ISENA
ISENB
INDUCTOR DCR SENSING
(VOUT MUST BE LESS THAN 4.0V)
FIGURE 15. CURRENT SENSING METHODS
the fault response during over or undercurrent condition. The
user can select the number of violations allowed before
declaring fault, a blanking time and the action taken when a
fault is detected.
TABLE 15. RESISTOR SETTINGS FOR CURRENT SENSING
NUMBER OF
VIOLATIONS
ALLOWED
(Note 24)
COMMENTS
ILIM0 PIN
(Note 23)
ILIM1 PIN
RILIM0
LOW
Ground-referenced, rDS(ON), sensing
Blanking time: 672ns
5
Best for low duty cycle and low fSW
RILIM0
OPEN
Output-referenced, down-slope sensing (Inductor
DCR sensing) Blanking time: 352ns
5
Best for low duty cycle and high
fSW
RILIM0
HIGH
Output-referenced, up-slope sensing (Inductor DCR
sensing) Blanking time: 352ns
5
Best for high duty cycle
CURRENT LIMITING CONFIGURATION
Resistor
Depends on resistor value used; see Table 16
NOTES:
23. 10kΩ < RILIM0 < 100kΩ
24. The number of violations allowed prior to issuing a fault response.
20
FN6876.3
August 29, 2012
ZL6100
TABLE 16. RESISTOR CONFIGURED CURRENT SENSING
METHOD SELECTION
RILIMI1
(kΩ)
CURRENT SENSING
METHOD
NUMBER OF
VIOLATIONS
ALLOWED
(Note 25)
10
1
11
3
12.1
13.3
14.7
7
9
11
17.8
13
19.6
15
21.5
1
23.7
3
26.1
31.6
ILIM0
ILIM1
5
Ground-referenced, rDS(ON), sensing
Best for low duty cycle and low fSW
Blanking time: 672ns
16.2
28.7
TABLE 17. CURRENT LIMIT THRESHOLD VOLTAGE
PIN-STRAP SETTINGS
5
Output-referenced, down-slope
sensing (Inductor DCR sensing) Best
for low duty cycle and high fSW
Blanking time: 352ns
7
9
LOW
(mV)
OPEN
(mV)
HIGH
(mV)
LOW
20
30
40
OPEN
50
60
70
HIGH
80
90
100
The threshold voltage can also be selected in 5mV
increments by connecting a resistor, RLIM0, between the
ILIM0 pin and ground according to Table 18. This method is
preferred if the user does not desire to use or does not have
access to the I2C/SMBus interface and the desired threshold
value is contained in Table 18.
The current limit threshold can also be set to a custom value
via the I2C/SMBus interface. Please refer to Application Note
AN2033 for further details.
TABLE 18. CURRENT LIMIT THRESHOLD VOLTAGE
RESISTOR SETTINGS
34.8
11
RILIM0
(kΩ)
VLIM for RDS
(mV)
VLIM for DCR
(mV)
38.3
13
10
0
0
42.2
15
11
5
2.5
46.4
1
12.1
10
5
51.1
3
13.3
15
7.5
5
14.7
20
10
7
16.2
25
12.5
9
17.8
30
15
75
11
19.6
35
17.5
82.5
13
21.5
40
20
90.9
15
23.7
45
22.5
NOTE:
26.1
50
25
25. The number of violations allowed prior to issuing a fault response
28.7
55
27.5
31.6
60
30
34.8
65
32.5
38.3
70
35
46.4
80
40
51.1
85
42.5
56.2
90
45
68.1
100
50
82.5
110
55
100
120
60
56.2
61.9
68.1
Output-referenced, up-slope sensing
(Inductor DCR sensing)
Best for high duty cycle Blanking
time: 352ns
The blanking time represents the time when no current
measurement is taken. This is to avoid taking a reading just
after a current load step (less accurate due to potential
ringing). It is a configurable parameter.
Table 15 includes default parameters for the number of
violations and the blanking time using pin-strap.
Once the sensing method has been selected, the user must
select the voltage threshold (VLIM), the desired current limit
threshold, and the resistance of the sensing element.
The current limit threshold can be selected by simply
connecting the ILIM0 and ILIM1 pins as shown in Table 17. The
ground-referenced sensing method is being used in this mode.
21
FN6876.3
August 29, 2012
ZL6100
Loop Compensation
The ZL6100 operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. Although the
ZL6100 uses a digital control loop, it operates much like a
traditional analog PWM controller. Figure 16 is a simplified
block diagram of the ZL6100 control loop, which differs from
an analog control loop only by the constants in the PWM and
compensation blocks. As in the analog controller case, the
compensation block compares the output voltage to the
desired voltage reference and compensation zeroes are
added to keep the loop stable. The resulting integrated error
signal is used to drive the PWM logic, converting the error
signal to a duty cycle to drive the external MOSFETs.
VIN
D
fn =
1
(EQ. 32)
2π L × C
Step 2: Based on Table 19 determine the FC0 settings.
Step 3: Calculate the ESR zero frequency (fZESR) using
Equation 33.
f zesr =
1
2πCRc
(EQ. 33)
Step 4: Based on Table 19 determine the FC1 setting.
Adaptive Compensation
L
VOUT
DPWM
1-D
Step 1: Using Equation 32, calculate the resonant frequency
of the LC filter, fn.
C
RO
RC
Compensation
FIGURE 16. CONTROL LOOP BLOCK DIAGRAM
In the ZL6100, the compensation zeros are set by configuring
the FC0 and FC1 pins or via the I2C/SMBus interface once
the user has calculated the required settings. This method
eliminates the inaccuracies due to the component tolerances
associated with using external resistors and capacitors
required with traditional analog controllers. Utilizing the loop
compensation settings shown in Table 19 will yield a
conservative crossover frequency at a fixed fraction of the
switching frequency (fSW/20) and 60° of phase margin.
Loop compensation can be a time-consuming process,
forcing the designer to accommodate design trade-offs
related to performance and stability across a wide range of
operating conditions. The ZL6100 offers an adaptive
compensation mode that enables the user to increase the
stability over a wider range of loading conditions by
automatically adapting the loop compensation coefficients
for changes in load current.
Setting the loop compensation coefficients through the
I2C/SMBus interface allows for a second set of coefficients
to be stored in the device in order to utilize adaptive loop
compensation. This algorithm uses the two sets of
compensation coefficients to determine optimal
compensation settings as the output load changes. Please
refer to Application Note AN2033 for further details on
PMBus commands.
TABLE 19. PIN-STRAP SETTINGS FOR LOOP COMPENSATION
FC0 RANGE
FC0 PIN
fsw/60 < fn < fsw/30
fsw/120 < fn < fsw/60
fsw/240 < fn < fsw/120
22
HIGH
OPEN
LOW
FC1 RANGE
FC1 PIN
fzesr > fsw/10
HIGH
fsw/10 > fzesr > fsw/30
OPEN
Reserved
LOW
fzesr > fsw/10
HIGH
fsw/10 > fzesr > fsw/30
OPEN
Reserved
LOW
fzesr > fsw/10
HIGH
fsw/10 > fzesr > fsw/30
OPEN
Reserved
LOW
FN6876.3
August 29, 2012
ZL6100
Non-linear Response (NLR) Settings
Adaptive Diode Emulation
The ZL6100 incorporates a non-linear response (NLR) loop
that decreases the response time and the output voltage
deviation in the event of a sudden output load current step. The
NLR loop incorporates a secondary error signal processing
path that bypasses the primary error loop when the output
begins to transition outside of the standard regulation limits.
This scheme results in a higher equivalent loop bandwidth than
what is possible using a traditional linear loop.
Most power converters use synchronous rectification to
optimize efficiency over a wide range of input and output
conditions. However, at light loads the synchronous
MOSFET will typically sink current and introduce additional
energy losses associated with higher peak inductor currents,
resulting in reduced efficiency. Adaptive diode emulation
mode turns off the low-side FET gate drive at low load
currents to prevent the inductor current from going negative,
reducing the energy losses and increasing overall efficiency.
Diode emulation is available to single-phase devices.
Efficiency Optimized Driver Dead-time Control
The ZL6100 utilizes a closed loop algorithm to optimize the
dead-time applied between the gate drive signals for the top
and bottom FETs. In a synchronous buck converter, the
MOSFET drive circuitry must be designed such that the top
and bottom MOSFETs are never in the conducting state at
the same time. Potentially damaging currents flow in the
circuit if both top and bottom MOSFETs are simultaneously
on for periods of time exceeding a few nanoseconds.
Conversely, long periods of time in which both MOSFETs are
off reduce overall circuit efficiency by allowing current to flow
in their parasitic body diodes.
Adaptive Frequency Control
Since switching losses contribute to the efficiency of the
power converter, reducing the switching frequency will
reduce the switching losses and increase efficiency. The
ZL6100 includes Adaptive Frequency Control mode, which
effectively reduces the observed switching frequency as the
load decreases.
Adaptive frequency mode is enabled by setting bit 0 of
MISC_CONFIG to 1 and is only available while the device is
operating within Adaptive Diode Emulation Mode. As the
load current is decreased, diode emulation mode decreases
the GL on-time to prevent negative inductor current from
flowing. As the load is decreased further, the GH pulse width
will begin to decrease while maintaining the programmed
frequency, fPROG (set by the FREQ_SWITCH command).
fSW(D)
SWITCHING
The ZL6100 has been pre-configured with appropriate NLR
settings that correspond to the loop compensation settings in
Table 19. Please refer to Application Note AN2032 for more
details regarding NLR settings.
Note: the overall bandwidth of the device may be reduced
when in diode emulation mode. It is recommended that diode
emulation is disabled prior to applying significant load steps.
It is therefore advantageous to minimize this dead-time to
provide optimum circuit efficiency. In the first order model of
a buck converter, the duty cycle is determined by
Equation 34:
D≈
VOUT
VIN
(EQ. 34)
However, non-idealities exist that cause the real duty cycle to
extend beyond the ideal. Dead-time is one of those
non-idealities that can be manipulated to improve efficiency.
The ZL6100 has an internal algorithm that constantly adjusts
dead-time non-overlap to minimize duty cycle, thus maximizing
efficiency. This circuit will null out dead-time differences due to
component variation, temperature, and loading effects.
This algorithm is independent of application circuit parameters
such as MOSFET type, gate driver delays, rise and fall times
and circuit layout. In addition, it does not require drive or
MOSFET voltage or current waveform measurements.
23
FREQUENCY
SWITCHING
FREQUENCY (fSW)
When a load current step function imposed on the output
causes the output voltage to drop below the lower regulation
limit, the NLR circuitry will force a positive correction signal
that will turn on the upper MOSFET and quickly force the
output to increase. Conversely, a negative load step (i.e.
removing a large load current) will cause the NLR circuitry to
force a negative correction signal that will turn on the lower
MOSFET and quickly force the output to decrease.
fPROG
fMIN
D
0
DUTY CYCLE
DNOM
2
DUTY CYCLE
FIGURE 17. ADAPTIVE FREQUENCY
Once the GH pulse width (D) reaches 50% of the nominal
duty cycle, DNOM (determined by VIN and VOUT), the
switching frequency will start to decrease according to
Equations 35, 36 and 37:
If:
D<
DNOM
2
(EQ. 35)
FN6876.3
August 29, 2012
ZL6100
The UVLO voltage can also be set to any value between
2.85V and 16V via the I2C/SMBus interface.
then:
fSW(D) =
⎛ 2( fSW − fMIN ) ⎞
⎜
⎟ D + fMIN
DNOM
⎝
⎠
(EQ. 36)
Otherwise:
f SW ( D ) = f PROG
(EQ. 37)
Once an input undervoltage fault condition occurs, the
device can respond in a number of ways as shown in Steps
1, 2 and 3.
1. Continue operating without interruption.
Refer to Figure 17. Due to quantizing effects inside the IC,
the ZL6100 will decrease its frequency in steps between fSW
and fMIN. The quantity and magnitude of the steps will
depend on the difference between fSW and fMIN as well as
the frequency range.
It should be noted that adaptive frequency mode is not
available for current sharing groups and is not allowed when
the device is placed in auto-detect mode and a clock source
is present on the SYNC pin, or if the device is outputting a
clock signal on its SYNC pin.
Power Management Functional Description
Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL6100
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The
UVLO threshold (VUVLO) can be set between 2.85V and 16V
using the UVLO pin. The simplest implementation is to
connect the UVLO pin as shown in Table 20. If the UVLO pin
is left unconnected, the UVLO threshold will default to 4.5V.
TABLE 20. UVLO THRESHOLD SETTINGS
PIN SETTING
UVLO THRESHOLD
(V)
LOW
3
OPEN
4.5
HIGH
10.8
3. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
The default response from a UVLO fault is an immediate
shutdown of the device. The device will continuously check
for the presence of the fault condition. If the fault condition is
no longer present, the ZL6100 will be re-enabled.
Please refer to Application Note AN2033 for details on how
to configure the UVLO threshold or to select specific UVLO
fault response options via the I2C/SMBus interface.
Output Overvoltage Protection
The ZL6100 offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry
from being subjected to a voltage higher than its prescribed
limits. A hardware comparator is used to compare the actual
output voltage (seen at the VSEN pin) to a threshold set to
15% higher than the target output voltage (the default
setting). If the VSEN voltage exceeds this threshold, the PG
pin will de-assert and the device can then respond in a
number of ways as shown in Steps 1 and 2.
1. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
If the desired UVLO threshold is not one of the listed
choices, the user can configure a threshold between 2.85V
and 16V by connecting a resistor between the UVLO pin and
SGND by selecting the appropriate resistor from Table 21.
TABLE 21. UVLO RESISTOR VALUES
RUVLO
(kΩ)
UVLO
(V)
RUVLO
(kΩ)
UVLO
(V)
17.8
2.85
46.4
7.42
19.6
3.14
51.1
8.18
21.5
3.44
56.2
8.99
23.7
3.79
61.9
9.9
26.1
4.18
68.1
10.9
28.7
4.59
75
12
31.6
5.06
82.5
13.2
34.8
5.57
90.9
14.54
38.3
6.13
100
16
42.2
6.75
24
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device will remain in
shutdown until instructed to restart.
2. Turn off the high-side MOSFET and turn on the low-side
MOSFET. The low-side MOSFET remains ON until the
device attempts a restart.
The default response from an overvoltage fault is to
immediately shut down. The device will continuously check
for the presence of the fault condition, and when the fault
condition no longer exists the device will be re-enabled.
For continuous overvoltage protection when operating from
an external clock, the only allowed response is an immediate
shutdown.
Please refer to Application Note AN2033 for details on how
to select specific overvoltage fault response options via
I2C/SMBus.
Output Pre-Bias Protection
An output pre-bias condition exists when an externally
applied voltage is present on a power supply’s output before
the power supply’s control IC is enabled. Certain
applications require that the converter not be allowed to sink
current during start up if a pre-bias condition exists at the
FN6876.3
August 29, 2012
ZL6100
output. The ZL6100 provides pre-bias protection by
sampling the output voltage prior to initiating an output ramp.
Overvoltage Protection” on page 24. for response options
due to an overvoltage condition.
If a pre-bias voltage lower than the target voltage exists after
the pre-configured delay period has expired, the target
voltage is set to match the existing pre-bias voltage and both
drivers are enabled. The output voltage is then ramped to
the final regulation value at the ramp rate set by the SS pin.
Pre-bias protection is not offered for current sharing groups
that also have tracking enabled.
The actual time the output will take to ramp from the pre-bias
voltage to the target voltage will vary depending on the prebias voltage but the total time elapsed from when the delay
period expires and when the output reaches its target value
will match the pre-configured ramp time. See Figure 18.
If a pre-bias voltage higher than the target voltage exists
after the pre-configured delay period has expired, the target
voltage is set to match the existing pre-bias voltage and both
drivers are enabled with a PWM duty cycle that would ideally
create the pre-bias voltage.
Output Overcurrent Protection
The ZL6100 can protect the power supply from damage if
the output is shorted to ground or if an overload condition is
imposed on the output. Once the current limit threshold has
been selected (see section “Current Limit Threshold
Selection” on page 19), the user may determine the desired
course of action in response to the fault condition. The
following Steps 1 through 5 overcurrent protection response
options are available:
1. Initiate a shutdown and attempt to restart an infinite
number of times with a preset delay period between
attempts.
2. Initiate a shutdown and attempt to restart a preset
number of times with a preset delay period between
attempts.
3. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
The default response from an overcurrent fault is an immediate
shutdown of the device. The device will continuously check for
the presence of the fault condition, and if the fault condition no
longer exists the device will be re-enabled.
Please refer to Application Note AN2033 for details on how
to select specific overcurrent fault response options via
I2C/SMBus.
Thermal Overload Protection
FIGURE 18. OUTPUT RESPONSES TO PRE-BIAS VOLTAGES
Once the pre-configured soft-start ramp period has expired, the
PG pin will be asserted (assuming the pre-bias voltage is not
higher than the overvoltage limit). The PWM will then adjust its
duty cycle to match the original target voltage and the output
will ramp down to the pre-configured output voltage.
If a pre-bias voltage higher than the overvoltage limit exists,
the device will not initiate a turn-on sequence and will
declare an overvoltage fault condition to exist. In this case,
the device will respond based on the output overvoltage fault
response method that has been selected. See “Output
25
The ZL6100 includes an on-chip thermal sensor that
continuously measures the internal temperature of the die
and shuts down the device when the temperature exceeds
the preset limit. The default temperature limit is set to
+125°C in the factory, but the user may set the limit to a
different value if desired. See Application Note AN2033 for
details. Note that setting a higher thermal limit via the
I2C/SMBus interface may result in permanent damage to the
device. Once the device has been disabled due to an
internal temperature fault, the user may select one of several
fault response options as shown in Steps 1 through 5:
1. Initiate a shutdown and attempt to restart an infinite
number of times with a preset delay period between
attempts.
2. Initiate a shutdown and attempt to restart a preset
number of times with a preset delay period between
attempts.
3. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
FN6876.3
August 29, 2012
ZL6100
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
If the user has configured the device to restart, the device
will wait the preset delay period (if configured to do so) and
will then check the device temperature. If the temperature
has dropped below a threshold that is approximately +15°C
lower than the selected temperature fault limit, the device
will attempt to re-start. If the temperature still exceeds the
fault limit the device will wait the preset delay period and
retry again.
device using the DLY(0,1) pins, and the user may also
configure a specific ramp rate using the SS pin. Any device
that is configured for tracking mode will ignore its soft-start
delay and ramp time settings (SS and DLY(0,1) pins) and its
output will take on the turn-on/turn-off characteristics of the
reference voltage present at the VTRK pin. All of the
ENABLE pins in the tracking group must be connected
together and driven by a single logic source. Tracking is
configured via the I2C/SMBus interface by using the
TRACK_CONFIG PMBus command. Please refer to
Application Note AN2033 for more information on
configuring tracking mode using PMBus.
The default response from a temperature fault is an
immediate shutdown of the device. The device will
continuously check for the fault condition, and once the fault
has cleared the ZL6100 will be re-enabled.
GH
ZL6100
VTRK
Please refer to Application Note AN2033 for details on how
to select specific temperature fault response options via
I2C/SMBus.
VIN
Q1
SW
GL
L1
Q2
VOUT
C1
VTRK
Voltage Tracking
Numerous high performance systems place stringent
demands on the order in which the power supply voltages are
turned on. This is particularly true when powering FPGAs,
ASICs, and other advanced processor devices that require
multiple supply voltages to power a single die. In most cases,
the I/O interface operates at a higher voltage than the core
and therefore the core supply voltage must not exceed the I/O
supply voltage according to the manufacturers' specifications.
Voltage tracking protects these sensitive ICs by limiting the
differential voltage between multiple power supplies during
the power-up and power down sequence. The ZL6100
integrates a lossless tracking scheme that allows its output
to track a voltage that is applied to the VTRK pin with no
external components required. The VTRK pin is an analog
input that, when tracking mode is enabled, configures the
voltage applied to the VTRK pin to act as a reference for the
device’s output regulation.
The ZL6100 offers two modes of tracking:
1. Coincident. This mode configures the ZL6100 to ramp
its output voltage at the same rate as the voltage applied
to the VTRK pin.
2. Ratiometric. This mode configures the ZL6100 to ramp
its output voltage at a rate that is a percentage of the
voltage applied to the VTRK pin. The default setting is
50%, but an external resistor string may be used to
configure a different tracking ratio.
Figure 19 illustrates the typical connection and the two
tracking modes.
The master ZL6100 device in a tracking group is defined as
the device that has the highest target output voltage within
the group. This master device will control the ramp rate of all
tracking devices and is not configured for tracking mode. A
delay of at least 10ms must be configured into the master
26
VOUT
VTRK
VOUT
Time
COINCIDENT
VOUT
VTRK
VOUT
Time
RATIOMETRIC
FIGURE 19. TRACKING MODES
Voltage Margining
The ZL6100 offers a simple means to vary its output higher
or lower than its nominal voltage setting in order to
determine whether the load device is capable of operating
over its specified supply voltage range. The MGN command
is set by driving the MGN pin or through the I2C/SMBus
interface. The MGN pin is a tri-level input that is continuously
monitored and can be driven directly by a processor I/O pin
or other logic-level output.
The ZL6100’s output will be forced higher than its nominal set
point when the MGN command is set HIGH, and the output
will be forced lower than its nominal set point when the MGN
command is set LOW. Default margin limits of VNOM ±5% are
pre-loaded in the factory, but the margin limits can be modified
through the I2C/SMBus interface to as high as VNOM + 10% or
FN6876.3
August 29, 2012
ZL6100
as low as 0V, where VNOM is the nominal output voltage set
point determined by the V0 and V1 pins. A safety feature
prevents the user from configuring the output voltage to
exceed VNOM + 10% under any conditions.
The margin limits and the MGN command can both be set
individually through the I2C/SMBus interface. Additionally, the
transition rate between the nominal output voltage and either
margin limit can be configured through the I2C interface.
Please refer to Application Note AN2033 for detailed
instructions on modifying the margining configurations.
I2C/SMBus Communications
The ZL6100 provides an I2C/SMBus digital interface that
enables the user to configure all aspects of the device
operation as well as monitor the input and output
parameters. The ZL6100 can be used with any standard 2wire I2C host device. In addition, the device is compatible
with SMBus version 2.0 and includes an SALRT line to help
mitigate bandwidth limitations related to continuous fault
monitoring. Pull-up resistors are required on the I2C/SMBus
as specified in the SMBus 2.0 specification. The ZL6100
accepts most standard PMBus commands. When controlling
the device with PMBus commands, it is recommended that
the enable pin is tied to SGND.
TABLE 23. SMBus ADDRESS VALUES
RSA
(kΩ)
SMBus
ADDRESS
RSA
(kΩ)
SMBus
ADDRESS
10
0x00
34.8
0x0D
11
0x01
38.3
0x0E
12.1
0x02
42.2
0x0F
13.3
0x03
46.4
0x10
14.7
0x04
51.1
0x11
16.2
0x05
56.2
0x12
17.8
0x06
61.9
0x13
19.6
0x07
68.1
0x14
21.5
0x08
75
0x15
23.7
0x09
82.5
0x16
26.1
0x0A
90.9
0x17
28.7
0x0B
100
0x18
31.6
0x0C
If more than 25 unique device addresses are required or if
other SMBus address values are desired, both the SA0 and
SA1 pins can be configured with a resistor to SGND
according to Equation 38 and Table 24.
SMBusaddress = 25 • ( SA1 index ) + ( SA0 index ) ( in decimal )
(EQ. 38)
I2C/SMBus Device Address Selection
When communicating with multiple SMBus devices using the
I2C/SMBus interface, each device must have its own unique
address so the host can distinguish between the devices.
The device address can be set according to the pin-strap
options listed in Table 22. Address values are right-justified.
TABLE 22. SMBus DEVICE ADDRESS SELECTION
SA0
SA1
LOW
OPEN
HIGH
LOW
0x20
0x21
0x22
OPEN
0x23
0x24
0x25
HIGH
0x26
0x27
Reserved
If additional device addresses are required, a resistor can be
connected to the SA0 pin according to Table 23 to provide
up to 25 unique device addresses. In this case, the SA1 pin
should be tied to SGND.
27
Using this method, the user can theoretically configure up to
625 unique SMBus addresses, however the SMBus is
inherently limited to 128 devices so attempting to configure
an address higher than 128 (0x80) will cause the device
address to repeat (i.e, attempting to configure a device
address of 129 (0x81) would result in a device address of 1).
Therefore, the user should use index values 0-4 on the SA1
pin and the full range of index values on the SA0 pin, which
will provide 125 device address combinations.
Note that the SMBus address 0x4B is reserved for device
test and cannot be used in the system.
TABLE 24. SMBus ADDRESS INDEX VALUES
RSA
(kΩ)
SA0 or SA1
INDEX
RSA
(kΩ)
SA0 or SA1
INDEX
10
0
34.8
13
11
1
38.3
14
12.1
2
42.2
15
13.3
3
46.4
16
14.7
4
51.1
17
16.2
5
56.2
18
17.8
6
61.9
19
19.6
7
68.1
20
21.5
8
75
21
23.7
9
82.5
22
26.1
10
90.9
23
28.7
11
100
24
31.6
12
FN6876.3
August 29, 2012
ZL6100
To determine the SA0 and SA1 resistor values given an
SMBus address (in decimal), follow the indicated steps to
calculate an index value and then use Table to select the
resistor that corresponds to the calculated index value as
shown in Steps 1 through 5:
Selecting the phase offset for the device is accomplished by
selecting a device address according to Equation 40:
1. Calculate SA1 Index:
SA1 Index = Address (in decimal) ÷ 25
2. Round the result down to the nearest whole number.
3. Select the value of R1 from Table using the SA1 Index
rounded value from Step 2.
4. Calculate SA0 Index:
5. Select the value of R0 from Table 24 using the SA0 Index
value from Step 4.
Digital-DC Bus
The Digital-DC (DDC) communications bus is used to
communicate between Zilker Labs Digital-DC devices. This
dedicated bus provides the communication channel between
devices for features such as sequencing, fault spreading,
and current sharing. The DDC pin on all Digital-DC devices
in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the
rise time as follows:
(EQ. 39)
where RPU is the DDC bus pull-up resistance and CLOAD is
the bus loading. The pull-up resistor may be tied to VR or to
an external 3.3V or 5V supply as long as this voltage is
present prior to or during device power-up. As rules of
thumb, each device connected to the DDC bus presents
approx 10pF of capacitive loading, and each inch of FR4
PCB trace introduces approx 2pF. The ideal design will use a
central pull-up resistor that is well-matched to the total load
capacitance. In power module applications, the user should
consider whether to place the pull-up resistor on the module
or on the PCB of the end application. The minimum pull-up
resistance should be limited to a value that enables any
device to assert the bus to a voltage that will ensure a logic 0
(typically 0.8V at the device monitoring point) given the
pull-up voltage (5V if tied to VR) and the pull-down current
capability of the ZL6100 (nominally 4mA).
Phase Spreading
When multiple point of load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching
cycle at a different point in time can dramatically reduce
input capacitance requirements and efficiency losses. Since
the peak current drawn from the input supply is effectively
spread out over a period of time, the peak current drawn at
any given moment is reduced and the power losses
proportional to the IRMS2 are reduced dramatically.
28
Phase offset = device address x 45°
(EQ. 40)
For example:
• A device address of 0x00 or 0x20 would configure no
phase offset
SA0 Index = Address – (25 x SA1 Index)
Rise time = R PU • C LOAD ≈ 1μs
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. The CFG pin is
used to set the configuration of the SYNC pin for each
device as described in section “Switching Frequency and
PLL” on page 15.
• A device address of 0x01 or 0x21 would configure 45° of
phase offset
• A device address of 0x02 or 0x22 would configure 90° of
phase offset
The phase offset of each device may also be set to any
value between 0° and 360° in 22.5° increments via the
I2C/SMBus interface. Refer to Application Note AN2033 for
further details.
Output Sequencing
A group of Digital-DC devices may be configured to power
up in a predetermined sequence. This feature is especially
useful when powering advanced processors, FPGAs, and
ASICs that require one supply to reach its operating voltage
prior to another supply reaching its operating voltage in order
to avoid latch-up from occurring. Multi-device sequencing
can be achieved by configuring each device through the
I2C/SMBus interface or by using Zilker Labs patented
autonomous sequencing mode.
Autonomous sequencing mode configures sequencing by
using events transmitted between devices over the DDC
bus. This mode is not available on current sharing rails.
The sequencing order is determined using each device’s
SMBus address. Using autonomous sequencing mode
(configured using the CFG pin), the devices must be
assigned sequential SMBus addresses with no missing
addresses in the chain. This mode will also constrain each
device to have a phase offset according to its SMBus
address as described in section “Phase Spreading” on
page 28”.
The sequencing group will turn on in order starting with the
device with the lowest SMBus address and will continue
through to turn on each device in the address chain until all
devices connected have been turned on. When turning off,
the device with the highest SMBus address will turn off first
followed in reverse order by the other devices in the group.
Sequencing is configured by connecting a resistor from the
CFG pin to ground as described in Table 25. The CFG pin is
also used to set the configuration of the SYNC pin as well as
to determine the sequencing method and order. Please refer
FN6876.3
August 29, 2012
ZL6100
to “Switching Frequency and PLL” on page 15” for more
details on the operating parameters of the SYNC pin.
Multiple device sequencing may also be achieved by issuing
PMBus commands to assign the preceding device in the
sequencing chain as well as the device that will follow in the
sequencing chain. This method places fewer restrictions on
SMBus address (no need of sequential address) and also
allows the user to assign any phase offset to any device
irrespective of its SMBus device address.
Active Current Sharing
Paralleling multiple ZL6100 devices can be used to increase
the output current capability of a single power rail. By
connecting the DDC pins of each device together and
configuring the devices as a current sharing rail, the units will
share the current equally within a few percent.
Figure 21 illustrates a typical connection for three devices.
VIN
3.3V - 5V
The Enable pins of all devices in a sequencing group must
be tied together and driven high to initiate a sequenced
turn-on of the group. Enable must be driven low to initiate a
sequenced turnoff of the group.
CIN
DDC
ZL6100
COUT
Refer to Application Note AN2033 for details on sequencing
via the I2C/SMBus interface.
CIN
Fault Spreading
Digital DC devices can be configured to broadcast a fault
event over the DDC bus to the other devices in the group.
When a non-destructive fault occurs and the device is
configured to shut down on a fault, the device will shut down
and broadcast the fault event over the DDC bus. The other
devices on the DDC bus will shut down together if configured
to do so, and will attempt to re-start in their prescribed order
if configured to do so.
DDC
ZL6100
VOUT
COUT
CIN
DDC
ZL6100
COUT
Temperature Monitoring Using the XTEMP Pin
The ZL6100 supports measurement of an external device
temperature using either a thermal diode integrated in a
processor, FPGA or ASIC, or using a discrete
diode-connected 2N3904 NPN transistor. Figure 20
illustrates the typical connections required.
FIGURE 21. CURRENT SHARING GROUP
The ZL6100 uses a low-bandwidth digital current sharing
technique to balance the unequal device output loading by
aligning the load lines of member devices to a reference device.
XTEMP
100pF
ZL6100
2N3904
SGND
DISCRETE NPN
XTEMP
ZL6100
100pF
SGND
µP
FPGA
DSP
ASIC
EMBEDDED THERMAL DIODE
FIGURE 20. EXTERNAL TEMPERATURE MONITORING
29
FN6876.3
August 29, 2012
ZL6100
TABLE 25. CFG PIN CONFIGURATIONS FOR SEQUENCING
RCFG
(kΩ)
SYNC PIN CONFIGURATION
10
Input
11
Auto Detect
12.1
Output
14.7
Input
16.2
Auto Detect
17.8
Output
21.5
Input
23.7
Auto Detect
26.1
Output
31.6
Input
34.8
Auto Detect
38.3
Output
SEQUENCING CONFIGURATION
Seguencing is disabled
The ZL6100 is configured as the first device in a nested
sequencing group. Turn on order is based on the device SMBus
address.
The ZL6100 is configured as a last device in a nested
sequencing group. Turn on order is based on the device SMBus
address.
The ZL6100 is configured as the middle device in a nested
sequencing group. Turn on order is based on the device SMBus
address.
Droop resistance is used to add artificial resistance in the
output voltage path to control the slope of the load line curve,
calibrating out the physical parasitic mismatches due to
power train components and PCB layout.
The relation between reference and member current and
voltage is given by using Equation 41:
Upon system start-up, the device with the lowest member
position as selected in ISHARE_CONFIG is defined as the
reference device. The remaining devices are members. The
reference device broadcasts its current over the DDC bus.
The members use the reference current information to trim
their voltages (VMEMBER) to balance the current loading of
each device in the system.
where R is the value of the droop resistance.
VREFERENCE
VOUT
-R
VMEMBER
-R
Vmember = VOUT + R × (I REFERENCE − I MEMBER )
(EQ. 41)
The ISHARE_CONFIG command is used to configure the
device for active current sharing. The default setting is a
stand-alone non-current sharing device. A current sharing
rail can be part of a system sequencing group.
For fault configuration, the current share rail is configured in
a quasi-redundant mode. In this mode, when a member
device fails, the remaining members will continue to operate
and attempt to maintain regulation. Of the remaining
devices, the device with the lowest member position will
become the reference. If fault spreading is enabled, the
current share rail failure is not broadcast until the entire
current share rail fails.
Up to eight (8) devices can be configured in a given current
sharing rail. The maximum current for a current sharing rail
is limited by the droop and number of phases. Refer to
Application Note AN2034 “Current Sharing with Digital-DC™
Devices” for complete details on current sharing.
Phase Adding/Dropping
IMEMBER
IOUT
I REFERENCE
FIGURE 22. ACTIVE CURRENT SHARING
Figure 22 shows that, for load lines with identical slopes, the
member voltage is increased towards the reference voltage
which closes the gap between the inductor currents.
30
The ZL6100 allows multiple power converters to be
connected in parallel to supply higher load currents than can
be addressed using a single-phase design. In doing so, the
power converter is optimized at a load current range that
requires all phases to be operational. During periods of light
loading, it may be beneficial to disable one or more phases
in order to eliminate the current drain and switching losses
associated with those phases, resulting in higher efficiency.
FN6876.3
August 29, 2012
ZL6100
The ZL6100 offers the ability to add and drop phases using a
simple command in response to an observed load current
change, enabling the system to continuously optimize
overall efficiency across a wide load range. All phases in a
current share rail are considered active prior to the current
sharing rail ramp to power-good.
Phases can be dropped after power-good is reached. Any
member of the current sharing rail can be dropped. If the
reference device is dropped, the remaining active device with
the lowest member position will become the new reference.
Additionally, any change to the number of members of a
current sharing rail will precipitate autonomous phase
distribution within the rail where all active phases realign
their phase position based on their order within the number
of active members.
If the members of a current sharing rail are forced to shut
down due to an observed fault, all members of the rail will
attempt to re-start simultaneously after the fault has cleared.
Monitoring via I2C/SMBus
A system controller can monitor a wide variety of different
ZL6100 system parameters through the I2C/SMBus
interface. The device can monitor for fault conditions by
monitoring the SALRT pin, which will be pulled low when any
number of pre-configured fault conditions occur.
The device can also be monitored continuously for any
number of power conversion parameters including but not
limited to the following:
Snapshot™ Parameter Capture
The ZL6100 offers a special mechanism that enables the
user to capture parametric data during normal operation or
following a fault. The Snapshot functionality is enabled by
setting bit 1 of MISC_CONFIG to 1.
See AN2033 for details on using the Snapshot feature in
addition to the parameters supported. The Snapshot feature
enables the user to read status and parameters via a block
read transfer through the SMBus.
The SNAPSHOT_CONTROL command enables the user to
store the snapshot parameters to Flash memory in response
to a pending fault as well as to read the stored data from
Flash memory after a fault has occurred. Table 26 describes
the usage of this command. Automatic writes to Flash
memory following a fault are triggered when any fault
threshold level is exceeded, provided that the specific fault’s
response is to shut down (writing to Flash memory is not
allowed if the device is configured to re-try following the
specific fault condition). It should also be noted that the
device’s VDD voltage must be maintained during the time
when the device is writing the data to Flash memory; a
process that requires between 700µs to 1400µs depending
on whether the data is set up for a block write. Undesirable
results may be observed if the device’s VDD supply drops
below 3.0V during this process.
TABLE 26. SNAPSHOT_CONTROL COMMAND
DATA VALUE
1
Copies current SNAPSHOT values from Flash
memory to RAM for immediate access using
SNAPSHOT command.
2
Writes current SNAPSHOT values to Flash
memory. Only available when device is disabled.
• Input voltage/Output voltage
• Output current
• Internal junction temperature
• Temperature of an external device
• Switching frequency
• Duty cycle
The PMBus Host should respond to SALRT as follows:
1. ZL device pulls SALRT Low
DESCRIPTION
In the event that the device experiences a fault and power is
lost, the user can extract the last SNAPSHOT parameters
stored during the fault by writing a 1 to
SNAPSHOT_CONTROL (transfers data from Flash memory
to RAM) and then issuing a SNAPSHOT command (reads
data from RAM via SMBus).
2. PMBus Host detects that SALRT is now low, performs
transmission with Alert Response Address to find which
ZL device is pulling SALRT low.
3. PMBus Host talks to the ZL device that has pulled SALRT
low. The actions that the host performs are up to the
System Designer.
If multiple devices are faulting, SALRT will still be low after
doing the above steps and will require transmission with the
Alert Response Address repeatedly until all faults are cleared.
Please refer to Application Note AN2033 for details on how
to monitor specific parameters via the I2C/SMBus interface.
31
FN6876.3
August 29, 2012
ZL6100
Non-Volatile Memory and Device Security Features
The ZL6100 has internal non-volatile memory where user
configurations are stored. Integrated security measures
ensure that the user can only restore the device to a level
that has been made available to them. Refer to “Start-up
Procedure” on page 13, for details on how the device loads
stored values from internal memory during start-up.
During the initialization process, the ZL6100 checks for
stored values contained in its internal non-volatile memory.
The ZL6100 offers two internal memory storage units that
are accessible by the user as follows:
1. Default Store: A power supply module manufacturer
may want to protect the module from damage by
preventing the user from being able to modify certain
values that are related to the physical construction of the
module. In this case, the module manufacturer would use
the Default Store and would allow the user to restore the
device to its default setting but would restrict the user
from restoring the device to the factory settings.
2. User Store: The manufacturer of a piece of equipment
may want to provide the ability to modify certain power
supply settings while still protecting the equipment from
modifying values that can lead to a system level fault. The
equipment manufacturer would use the User Store to
achieve this goal.
Please refer to Application Note AN2033 for details on how
to set specific security measures via the I2C/SMBus
interface.
Related Tools and Documentation
The following application support documents and tools are
available to help simplify your design.
Related Documentation
ITEM
DESCRIPTION
ZL6100EVAL1Z
Evaluation Board – 40A single phase
AN2033
Application Note: Digital-DC PMBus Command Set
AN2034
Application Note: Digital-DC Current Sharing
AN2035
Application Note: Digital-DC Control Loop Compensation
32
FN6876.3
August 29, 2012
ZL6100
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure
you have the latest Rev.
DATE
REVISION
CHANGE
8/6/12
FN6876.3
Added Note 4 for part ZL6100ALAF, Added part ZL6100ALBF and updated PKG DWG No. from L36.6X6A
TO L36.6X6C in ordering information
Stamped “Not Recommended for New Designs Recommended Replacement Part ZL6105”.
Changed POD from L36.6X6A TO L36.6X6C
11/30/10
FN6876.2
Added following statement to disclaimer on page 33: "This product is subject to a license from Power One,
Inc. related to digital power technology as set forth in U.S. Patent No. 7,000,125 and other related patents
owned by Power One, Inc. These license rights do not extend to stand-alone POL regulators unless a royalty
is paid to Power One, Inc."
Removed notes "Limits established by characterization and not production tested." and "Parameters with
MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested." from “Electrical Specifications” table and
replaced with new standard note in MIN/MAX columns, "Compliance to datasheet limits is assured by one
or more methods: production test, characterization and/or design."
10/28/10
Typo on page 30 in Table 25, second column heading CONFIGURATION was misspelled.
9/16/10
1. Page 1, 1st sentence, changed "The ZL6100 is a digital DC/DC controller with …" to "ZL6100 is a digital
power controller with…"
2. On page 1, Ordering Info table, added MSL note.
3. On page 3, Electrical Specifications table, added Boldface Limits…." Note to title area.
Added Note 19: "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested."
4. On page 6, Pin 9, IC diagram, changed "SALR" to "SALRT"
5. On page 13, Table 4, 4th column, 5th entry down, changed "12." To "12.1"
6. On page 13, Table 5 title, changed "DOSA MOSE" to "DOSA MODE"
7. On page 13, Table 5, 1st column, last entry, changed "0.965V" to "0.965"
8. On page 20, 2nd paragraph (starts with "To set the current limit…"), last sentence starts with "Figure 17
shows a simplified…", change to "Figure 15 shows a simplified…"
9. On page 21, Table 18, 1st column heading, changed "RLIM0" to "RILIM0"
10.On page 21, Table 18, 2nd column, 4th to last entry, changed "9" to "90"
11. On page 27, Table 23, add two entries
a. Between 19.6 and 21.5 changed to 23.7 with address 0x09
b. Between 68.1 and 75 changed to 82.5 with address 0x16
12. On page 27, 2nd column, added sentence "Note that the SMBus address 0x4B is reserved for device
test and cannot be used in the system." As a separate paragraph just before Table 24.
13.On page 31, 2nd column, 2nd paragraph, changed to read: "See AN2033 for details on using the
Snapshot feature in addition to the parameters supported. The Snapshot feature enables the user to read
status and parameters via a block read transfer through the SMBus."
14. On page 31, removed Table 26. Snapshot Parameters
15. Page 34. Updated POD to newest revision. Converted to new POD standard (Added Land Pattern and
moved dimensions from table onto drawing. Added JEDEC #)
9/08/09
FN6876.1
Initial Release to web.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
This product is subject to a license from Power One, Inc. related to digital power technology as set forth in U.S. Patent No. 7,000,125 and other related patents owned by
Power One, Inc. These license rights do not extend to stand-alone POL regulators unless a royalty is paid to Power One, Inc.
For information regarding Intersil Corporation and its products, see www.intersil.com
33
FN6876.3
August 29, 2012
ZL6100
Package Outline Drawing
L36.6x6C
36 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/10
4X 4.0
6.00
36X 0.50
A
B
28
6
PIN 1
INDEX AREA
36
6
PIN #1
INDEX AREA
27
6.00
1
4 .10 ± 0.10
9
19
(4X)
0.15
18
10
TOP VIEW
36X 0.60 ± 0.10
36X 0.25 4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
MAX 1.00
C
0.08 C
( 5. 60 TYP )
( 36 X 0 . 50 )
SIDE VIEW
(
4. 10 )
(36X 0.25 )
C
( 36X 0.80 )
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220VJJD.
either a mold or mark feature.
34
FN6876.3
August 29, 2012