EL7534 ® Data Sheet August 16, 2005 FN7431.5 Monolithic 600mA Step-Down Regulator Features The EL7534 is a synchronous, integrated FET 600mA stepdown regulator with internal compensation. It operates with an input voltage range from 2.5V to 5.5V, which accommodates supplies of 3.3V, 5V, or a Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider. • Less than 0.15 in2 (0.97 cm2) footprint for the complete 600mA converter • Components on one side of PCB • Max height 1.1 mm MSOP10 • 100ms Power-On-Reset output (POR) The EL7534 features PWM mode control. The operating frequency is typically 1.5MHz. Additional features include a 100ms Power-On-Reset output, <1µA shut-down current, short-circuit protection, and over-temperature protection. • Internally-compensated voltage mode controller The EL7534 is available in the 10-pin MSOP package, making the entire converter occupy less than 0.15 in2 of PCB area with components on one side only. Both packages are specified for operation over the full -40°C to +85°C temperature range. • Overcurrent and over-temperature protection Ordering Information PART NUMBER (BRAND) • Up to 94% efficiency • <1µA shut-down current • Pb-Free plus anneal available (RoHS compliant) Applications • PDA and pocket PC computers • Bar code readers PACKAGE TAPE & REEL PKG. DWG. # EL7534IY (BPAAA) 10-Pin MSOP - MDP0043 EL7534IY-T7 (BPAAA) 10-Pin MSOP 7” MDP0043 • Small form factor (SFP) modules EL7534IY-T13 (BPAAA) 10-Pin MSOP 13” MDP0043 Pinout and Typical Application Diagram EL7534IYZ (BGAAA) (Note) 10-Pin MSOP (Pb-free) - MDP0043 EL7534IYZ-T7 (BGAAA) (Note) 10-Pin MSOP (Pb-free) 7” MDP0043 EL7534IYZ-T13 (BGAAA) (Note) 10-Pin MSOP (Pb-free) 13” MDP0043 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Cellular phones • Portable test equipment • Li-Ion battery powered devices EL7534 TOP VIEW C1 10µF VO (1.8V@600mA) VIN (2.5V-6V) C2 10µF L1 1.8µH R3 100Ω C3 0.1µF 1 SGND FB 10 2 PGND VO 9 3 LX POR 8 R1* 100kΩ R2* 124kΩ POR 4 VIN EN 7 EN 5 VDD RSI 6 RSI R6 100kΩ R4 100kΩ R5 100kΩ * VO = 0.8V * (1 + R2 / R1) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7534 Absolute Maximum Ratings (TA = 25°C) VIN, VDD, POR to SGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) RSI, EN, VO, FB to SGND . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mA Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +145°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 790 800 810 mV 250 nA 2.5 5.5 V DC CHARACTERISTICS VFB Feedback Input Voltage IFB Feedback Input Current VIN, VDD Input Voltage VIN,OFF Minimum Voltage for Shutdown VIN falling 2 2.2 V VIN,ON Maximum Voltage for Startup VIN rising 2.2 2.4 V IDD Supply Current PWM, VIN = VDD = 5V 400 500 µA EN = 0, VIN = VDD = 5V 0.1 1 µA PMOS FET Resistance VDD = 5V, wafer test only 70 100 mΩ RDS(ON)-NMOS NMOS FET Resistance VDD = 5V, wafer test only 45 75 mΩ RDS(ON)-PMOS ILMAX Current Limit TOT,OFF Over-temperature Threshold TOT,ON 1.5 A T rising 145 °C Over-temperature Hysteresis T falling 130 °C IEN, IRSI EN, RSI Current VEN, VRSI = 0V and 3.3V VEN1, VRSI1 EN, RSI Rising Threshold VDD = 3.3V VEN2, VRSI2 EN, RSI Falling Threshold VDD = 3.3V VPOR Minimum VFB for POR, WRT Targeted VFB Value VFB rising POR Voltage Drop ISINK = 5mA VOLPOR VFB falling -1 1 µA 2.4 V 0.8 V 95 % 86 % 35 70 mV 1.5 1.75 MHz 25 50 ns AC CHARACTERISTICS FPWM PWM Switching Frequency tRSI Minimum RSI Pulse Width tSS Soft-start Time tPOR Power On Reset Delay Time 1.4 Guaranteed by design 650 2 80 100 µs 120 ms FN7431.5 August 16, 2005 EL7534 Pin Descriptions PIN NUMBER PIN NAME PIN FUNCTION 1 SGND Negative supply for the controller stage 2 PGND Negative supply for the power stage 3 LX Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage 4 VIN Positive supply for the power stage 5 VDD Power supply for the controller stage 6 RSI Resets POR timer 7 EN Enable 8 POR 9 VO Output voltage sense 10 FB Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output Power on reset open drain output Block Diagram 100Ω VDD 0.1µF VO + CURRENT LIMIT 10pF 124K FB 5M + PWM COMPENSATION 100K CLOCK 1.5MHz P-DRIVER LX CONTROL LOGIC RAMP GENERATOR 1.8µH 1.8V 600mA EN EN SOFT-START 10µF 2.5V3.5V + PWM COMPARATOR VIN 10µF N-DRIVER + – BANDGAP REFERENCE UNDERVOLTAGE LOCKOUT PGND 100K TEMPERATURE SENSE SGND POR PG POR RSI 3 FN7431.5 August 16, 2005 EL7534 Performance Curves and Waveforms All waveforms are taken at VIN=3.3V, VO=1.8V, IO=600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted. 100 VIN=5V 100 VO=3.3V 95 VO=2.5V 95 90 EFFICIENCY (%) 90 EFFICIENCY (%) VIN=3.3V 85 VO=1.8V 80 VO=1.2V 75 85 VO=1V 80 VO=1.8V 75 70 70 65 65 60 60 0 200 400 600 0 200 400 IO (mA) IO (mA) FIGURE 1. EFFICIENCY 0.1% VIN=3.3V, IO=600mA VIN=5V, IO=600mA VIN=5V, IO=0A 1.52 FS (MHz) FIGURE 2. EFFICIENCY 0.0% VO CHANGES 1.54 1.5 VIN=3.3V, IO=0A 1.48 1.46 -0.1% VIN=3.3V -0.2% VIN=5V -0.3% -0.4% 1.44 1.42 -50 -0.5% 0 50 100 0 150 0.2 0.4 0.1% 1 12 0.0% VIN=5V IO=0A 10 VIN=3.3V IO=0A 8 -0.2% IIN (mA) VO CHANGES 0.8 FIGURE 4. LOAD REGULATIONS FIGURE 3. FS vs JUNCTION TEMPERATURE -0.3% 0.6 IO (A) TA (°C) -0.1% 600 VIN=3.3V IO=600mA -0.4% 6 4 -0.5% -0.6% -0.7% -50 2 VIN=5V IO=600mA 0 50 100 150 TJ (°C) FIGURE 5. LOAD/LINE REGULATIONS vs JUNCTION TEMPERATURE 4 0 2.5 3 3.5 4 4.5 5 VIN (V) FIGURE 6. NO LOAD INPUT CURRENT FN7431.5 August 16, 2005 EL7534 Performance Curves and Waveforms (Continued) All waveforms are taken at VIN=3.3V, VO=1.8V, IO=600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted. VIN (2V/DIV) VIN (1V/DIV) VO (2V/DIV) IIN (0.5A/DIV) POR (2V/DIV) VO (1V/DIV) 50ms/DIV 0.5ms/DIV FIGURE 8. START-UP 2 FIGURE 7. START-UP 1 VIN (2V/DIV) VO (2V/DIV) IO (200mA/DIV) RSI (2V/DIV) ∆VO (50mV/DIV) POR (2V/DIV) 50µs/DIV 50ms/DIV FIGURE 10. TRANSIENT RESPONSE (100mA to 500mA) FIGURE 9. POR FUNCTION ∆VIN (100mV/DIV) iL (0.5A/DIV) VLX (2V/DIV) ∆VO (10mV/DIV) 1µs/DIV FIGURE 11. STEADY-STATE 5 FN7431.5 August 16, 2005 EL7534 Performance Curves and Waveforms (Continued) All waveforms are taken at VIN=3.3V, VO=1.8V, IO=600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted. 0.7 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 POWER DISSIPATION (W) POWER DISSIPATION (W) 607mW M SO JA P1 =2 0 06 °C /W θ 0.5 0.4 0.3 0.2 0.1 0 1 1.087W θ 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Applications Information Product Description 11 SO 5° 0.6 P1 C/ 0 W 0.4 0.2 0 0 M JA = 0.8 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to VO divided by VIN. The internally-compensated controller makes it possible to use only two ceramic capacitors and one inductor to form a complete, very small footprint 600mA DC:DC converter. The output LC filter has a second order effect. To maintain the stability of the converter, the overall controller must be compensated. This is done with the fixed internally compensated error amplifier and the PWM compensator. Because the compensations are fixed, the values of input and output capacitors are 10µF to 22µF ceramic. The inductor is nominally 1.8µH, though 1.5µA to 2.2µH can be used. Start-Up and Shut-Down 100% Duty Ratio Operation When the EN pin is tied to VIN, and VIN reaches approximately 2.4V, the regulator begins to switch. The output voltage is gradually increased to ensure proper softstart operation. EL7534 utilizes CMOS power FET's as the internal synchronous power switches. The upper switch is a PMOS and lower switch a NMOS. This not only saves a boot capacitor, it also allows 100% turn-on of the upper PFET switch, achieving VO close to VIN. The maximum achievable VO is, The EL7534 is a synchronous, integrated FET 600mA stepdown regulator which operates from an input of 2.5V to 6V. The output voltage is user-adjustable with a pair of external resistors. When the EN pin is connected to a logic low, the EL7534 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1µA. When the EN reaches logic HI, the regulator repeats the start-up procedure, including the soft-start function. PWM Operation In the PWM mode, the P channel MOSFET and N channel MOSFET always operate complementary. When the PMOSFET is on and the NMOSFET off, the inductor current increases linearly. The input energy is transferred to the output and also stored in the inductor. When the P channel MOSFET is off and the N channel MOSFET on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. Hence, the average current through the inductor is the output current. Since the inductor 6 V O = V IN – ( R L + R DSON1 ) × I O Where RL is the DC resistance on the inductor and RDSON1 the PFET on-resistance, nominal 70mΩ at room temperature with tempco of 0.2mΩ/°C. As the input voltage drops gradually close or even bellow the preset VO, the converter gets into 100% duty ratio. At this condition, the upper PFET needs some minimum turn-off time if it is turned off. This off-time is related to input/output conditions. This makes the duty ratio appears randomly and increases the output ripple somewhat until the 100% duty ratio is reached. Larger output capacitor could reduce the random-looking ripple. Users need to verify if this condition FN7431.5 August 16, 2005 EL7534 has adverse effect on overall circuit if close to 100% duty ratio is expected. RSI/POR Function ( V IN - V O ) × V O ∆I IL = ------------------------------------------L × V IN × f S • L is the inductance When powering up, the open-collector Power-On-Reset output holds low for about 100ms after VO reaches the preset voltage. When the active-HI reset signal RSI is issued, POR goes to low immediately and holds for the same period of time after RSI comes back to LOW. The output voltage is unaffected. (Please refer to the timing diagram). When the function is not used, connect RSI to ground and leave open the pull-up resister R4 at POR pin. The POR output also serves as a 100ms delayed Power Good signal when the pull-up resister R4 is installed. The RSI pin needs to be directly (or indirectly through a resister R6) connected to Ground for this to function properly. • fS the switching frequency (nominally 1.5MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 1.5A surge current that can occur during a current limit condition. Current Limit and Short-Circuit Protection The current limit is set at about 1.5A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point. Thermal Shut-Down VO MIN 25ns RSI 100ms 100ms POR FIGURE 14. RSI & POR TIMING DIAGRAM Output Voltage Selection Users can set the output voltage of the converter with a resister divider, which can be chosen based on the following formula: R V O = 0.8 × 1 + ------2- R 1 Once the junction reaches about 145°C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130°C, the regulator will restart again in the same manner as EN pin connects to logic HI. Thermal Performance The EL7534 is in a fused-lead MSOP10 package. Compared with regular MSOP10 package, the fused-lead package provides lower thermal resistance. The θJA is 100°C/W on a 4-layer board and 125°C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance. Layout Considerations Component Selection Because of the fixed internal compensation, the component choice is relatively narrow. We recommend 10µF to 22µF multi-layer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5µH to 2.2µH inductance for the inductor. The RMS current present at the input capacitor is decided by the following formula: The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: • Separate the Power Ground ( ) and Signal Ground ( connect them only at one point right at the pins ); • Place the input capacitor as close to VIN and PGND pins as possible This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. • Make the following PC traces as small as possible: - from LX pin to L - from CO to PGND • If used, connect the trace from the FB pin to R1 and R2 as close as possible The inductor peak-to-peak ripple current is given as: • Maximize the copper area around the PGND pin V O × ( V IN - V O ) I INRMS = ------------------------------------------------ × I O V IN • Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7534 Application Brief. 7 FN7431.5 August 16, 2005 EL7534 MSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN7431.5 August 16, 2005