ISL54065 ® Data Sheet April 3, 2009 +1.8V to +6.5V, Sub-ohm, Click and Pop Elimination, Dual SPDT w/ Enable, Analog Switch with Negative Signal Capability The Intersil ISL54065 device is a low ON-resistance, low voltage, bi-directional, dual single-pole/double-throw (SPDT) analog switch. It is designed to operate from a single +1.8V to +6.5V supply and pass signals that swing up to 6.5V below the positive supply rail. Targeted applications include battery powered equipment that benefit from low rON (0.56Ω), low power consumption (8nA) and fast switching speeds (tON = 55ns, tOFF = 18ns). The digital inputs are1.8V logic-compatible up to a +3V supply. The ISL54065 also features integrated circuitry to eliminate click and pop noise to an audio speaker. The ISL54065 is offered in a small form factor package, alleviating board space limitations. It is available in a tiny 12 Ld 2.2x1.4mm µTQFN. The ISL54065 is a committed dual single-pole/double-throw (SPDT) that consist of two normally open (NO) and two normally closed (NC) switches with independent logic control. This configuration can be used as a dual 2-to-1 multiplexer. TABLE 1. FEATURES AT A GLANCE ISL54065 Number of Switches 2 SW SPDT or 2-1 MUX 4.3V rON 0.65Ω 4.3V tON/tOFF 43ns/23ns 2.7V rON 0.9Ω 2.7V tON/tOFF 55ns/18ns 1.8V rON 1.8Ω 1.8V tON/tOFF 145ns/28ns Packages 12 Ld µTQFN FN6583.1 Features • Pb-Free (RoHS Compliant) • Single Supply Operation . . . . . . . . . . . . . . . . .+1.8V to +6.5V • Negative Signal Capability (up to V+ - 6.5V) • Enable Pin to Disable All Switches • Integrated Click and Pop Elimination Circuitry • Click and Pop Circuitry Disable Pin • ON-Resistance (rON) - V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.52Ω - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω - V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9Ω - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8Ω • rON Matching Between Channels . . . . . . . . . . . . . . . . . 10mΩ • rON Flatness Across Signal Range . . . . . . . . . . . . . . . . 0.33Ω • Low THD+N @ 32Ω Load . . . . . . . . . . . . . . . . . . . . . . .0.02% • Low Power Consumption (PD). . . . . . . . . . . . . . . . . . . 8nA • Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ns • ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV • Guaranteed Break-Before-Make • 1.8V Logic Compatible (+3V supply) • Low I+ Current when VINH is not at the V+ Rail • Available in 12 Ld 2.2mm x 1.4mm µTQFN Package Applications • Audio and Video Switching • Battery powered, Handheld, and Portable Equipment - MP3 and Multimedia Players - Cellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Portable Test and Measurement • Medical Equipment Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54065 Pinout Pin Descriptions (Note 1) ISL54065 (12 LD µTQFN) TOP VIEW GND 1 CP 2 NC1 COM1 NO1 12 11 10 PIN FUNCTION V+ Supply Voltage(+1.8V to +6.5V). Decouple V+ to ground by placing a 0.1µF capacitor at the V+ and GND supply lines as near as the IC as possible. GND 9 IN1 8 EN 7 IN2 INx Input Select Pin EN Switch Enable Pin COMx V+ CLICK AND POP CIRCUITRY 3 4 5 6 NC2 COM2 NO2 Ground Connection Analog Switch Common Pin NOx Analog Switch Normally Open Pin NCx Analog Switch Normally Closed Pin CP Click and Pop Circuitry Enable Pin NOTE: 1. Switches Shown for EN = Logic “1” and INx = Logic “0”. Truth Table EN IN1 IN2 NC1 NC2 NO1 NO2 0 X X OFF OFF OFF OFF 1 0 0 ON ON OFF OFF 1 0 1 ON OFF OFF ON 1 1 0 OFF ON ON OFF 1 1 1 OFF OFF ON ON NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply. Ordering Information PART NUMBER (Note) ISL54065IRUZ-T* PART MARKING GG TEMP. RANGE (°C) -40 to +85 PACKAGE (Pb-Free) 12 Ld Thin µTQFN (Tape and Reel) PKG. DWG. # L12.2.2x1.4A *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6583.1 April 3, 2009 ISL54065 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V Input Voltages NOx, NCx (Note 2) . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) INx, EN (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COMx (Note 2) . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) Continuous Current NOx, NCx, or COMx . . . . . . . . . . . . . . ±300mA Peak Current NOx, NCx, or COMx (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV Thermal Resistance (Typical) θJA (°C/W) 12 Ld µTQFN Package (Note 3) . . . . . . . . . . . . . . . 155 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . (V+ - 6.5)V to V+ CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2. Signals on NCx, NOx, INx, EN, CP, or COMx exceeding V+ or GND by the specified amount are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, VEN VCP = VINL (Note 4), unless otherwise specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP = VINH, MAX (Notes 5, 6) UNITS ANALOG SWITCH CHARACTERISTICS V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ -6.5) to V+ (see Figure 5) 25 - 0.52 - Ω Full - 0.68 - Ω rON Matching Between Channels, ΔrON V+ = 4.5V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 8) 25 - 10 - mΩ Full - 13.1 - mΩ rON Flatness, RFLAT(ON) V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ -6.5) to V+ (Note 7) 25 - 0.11 - Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = 5V, -1.5V Full - COM ON Leakage Current, ICOM(ON) V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = Float 25 - Full - 25 - ON-Resistance, rON Full - 0.14 - Ω 25 - -8.13 - nA -0.4 - µA -4.42 - nA -0.33 - µA 35 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) Break-Before-Make Time Delay, tD V+ = 5.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 3) Charge Injection, Q VG = 0V, RG = 0Ω, CL = 1.0nF (see Figure 2) OFF Isolation Full - 50 - ns 25 - 16 - ns Full - 22 - ns Full - 18 - ns 25 - 170 - pC RL = 50Ω, CL = 5pF, f = 100kHz, VNO or VNC = 1VRMS (see Figure 4) 25 - 60 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, VNO or VNC = 1VRMS (See Figure 6) 25 - -75 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω 25 - 0.02 - % -3dB Bandwidth VCOM = 1VRMS, RL = 50Ω, CL = 5pF 25 - 60 - MHz NOx or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 25 - 88 - pF 3 FN6583.1 April 3, 2009 ISL54065 Electrical Specifications - 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, VEN VCP = VINL (Note 4), unless otherwise specified. (Continued) TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP = VINH, MAX (Notes 5, 6) UNITS POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 5.5V, VINx = 0V or V+ 25 - 0.008 0.1 µA Full - 1.41 - µA Full - - 0.8 V Full 2.4 - - V 25 -0.1 - 0.1 µA Full - 0.3 - µA DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 5.5V, VINx = 0V or V+ Electrical Specifications - 4.3V Supply PARAMETER Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VEN = V+, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS 25 - 0.65 - Ω Full - 0.72 - Ω 25 - 10 - mΩ Full - 15 - mΩ 25 - 0.1 - Ω Full - 0.14 - Ω 25 -0.1 - 0.1 µA Full -1 -0.33 1 µA 25 -0.1 - 0.1 µA Full -1 -0.33 1 µA 25 - 43 - ns Full - 50 - ns 25 - 23.1 - ns Full - 23.2 - ns ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+ (see Figure 5 ) rON Matching Between Channels, ΔrON V+ = 4.3V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 8) rON Flatness, RFLAT(ON) V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+ (Note 7) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = 4.3V, -1.2V COM ON Leakage Current, ICOM(ON) V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = Float DYNAMIC CHARACTERISTICS V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) Turn-ON Time, tON V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 1) Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF (see Figure 3) Full - 22 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 200 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VNO or VNC = 1VRMS (see Figure 4) 25 - 60 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, VNO or VNC = 1VRMS (see Figure 6) 25 - -75 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω 25 - 0.025 - % NOx or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 25 - 88 - pF 25 - 0.003 0.1 µA Full - 0.9 - µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 4.5V, VIN = 0V or V+ 4 FN6583.1 April 3, 2009 ISL54065 Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VEN = V+, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified. (Continued) TEMP (°C) MIN (Notes 5, 6) TYP 25 - 0.78 12 µA Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.6 - - V 25 -0.5 - 0.5 µA Full - 0.2 - µA PARAMETER TEST CONDITIONS Positive Supply Current, I+ V+ = 4.2V, VIN = 2.85V MAX (Notes 5, 6) UNITS DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ Electrical Specifications - 3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VEN = V+, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS 25 - 0.9 - Ω Full - 0.96 - Ω ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+, (See Figure 5) rON Matching Between Channels, ΔrON V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 8) 25 - 10 - mΩ Full - 17 - mΩ rON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+, (Notes 7, 9) 25 - 0.33 0.5 Ω Full - 0.35 0.55 Ω 25 - 55 - ns Full - 82 - ns 25 - 18 - ns Full - 24 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 1) Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF (see Figure 3) Full - 30 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 150 - pC OFF-Isolation RL = 50Ω, CL = 35pF, f = 100kHz, VNO or VNC = 1VRMS (see Figure 4) 25 - 60 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 35pF, f = 1MHz, VNO or VNC = 1VRMS (see Figure 6) 25 - -75 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32Ω 25 - 0.04 - % NOx or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 25 - 88 - pF 25 - - 0.5 V DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ 5 25 1.4 - - V 25 -0.5 - 0.5 µA Full - 0.2 - µA FN6583.1 April 3, 2009 ISL54065 Electrical Specifications - 1.8V Supply PARAMETER Test Conditions: V+ = +1.8V, GND = 0V, VEN = V+, VINH = 1.0V, VINL = 0.4V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS 25 - 1.87 - Ω Full - 1.97 - Ω 25 - 16 - mΩ Full ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+ (see Figure 5) rON Matching Between Channels, ΔrON V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 8) - 30 - mΩ rON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ -6.5V) to V+, (Note 7) 25 - 1.34 - Ω Full - 1.43 - Ω V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 1) 25 - 145 - ns Full - 150 - ns 25 - 20 - ns Full - 22 - ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 1) Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF (see Figure 3) Full - 130 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 40 - pC NOx or NCx OFF Capacitance, COFF f = 1MHz (see Figure 7) 25 - 36 - pF COMx ON Capacitance, CCOM(ON) f = 1MHz (see Figure 7) 25 - 88 - pF Input Voltage Low, VINL 25 - - 0.4 V Input Voltage High, VINH 25 1.0 - - V 25 -0.5 - 0.5 µA Full - 0.19 - µA DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NC1 and NC2 or between NO1 and NO2. 9. Limits established by characterization and are not production tested. 6 FN6583.1 April 3, 2009 ISL54065 Test Circuits and Waveforms V+ V+ LOGIC INPUT tr < 5ns tf < 5ns 50% C 0V tOFF SWITCH INPUT VNO SWITCH INPUT COM IN VOUT 90% SWITCH OUTPUT VOUT NO OR NC 90% LOGIC INPUT CL 35pF RL 50Ω GND 0V tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------R L + r ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ RG SWITCH OUTPUT VOUT ΔVOUT V+ LOGIC INPUT ON ON C VG VOUT COM NO OR NC GND IN CL OFF 0V LOGIC INPUT Q = ΔVOUT x CL Repeat test for all switches. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ V+ NO LOGIC INPUT VNX VOUT COM NC 0V RL 50Ω IN SWITCH OUTPUT VOUT C 90% LOGIC INPUT CL 35pF GND 0V tBBM FIGURE 3A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 7 FN6583.1 April 3, 2009 ISL54065 Test Circuits and Waveforms (Continued) V+ *50Ω SOURCE C V+ C SIGNAL GENERATOR rON = V1/100mA NO OR NC NO OR NC IN VNX 0V OR V+ 100mA 0V OR V+ IN V1 COM ANALYZER GND COM RL GND Signal direction through switch is reversed, worst case values are recorded. FIGURE 4. OFF-ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT V+ *50Ω SOURCE V+ C C SIGNAL GENERATOR NO1 OR NC1 RL COM1 NO OR NC INX IN COM NC2 OR NO2 COM2 ANALYZER 0V OR V+ IMPEDANCE ANALYZER 0V OR V+ NC GND GND 50Ω Signal direction through switch is reversed, worst case values are recorded. COM is connected to NO or NC during ON capacitance measurement. FIGURE 7. CAPACITANCE TEST CIRCUIT FIGURE 6. CROSSTALK TEST CIRCUIT INx VDC 0V 220µF NCx VINx* 0V VDC tD tD CLICK AND POP CIRCUITRY COMx RL 220µF *VINx waveform for Click and Pop Elimination on NOx terminal. For Click and Pop Elimination on NCx terminal invert INx. NOx VDC tD = 200ms measured at 50% points. FIGURE 8A. CLICK AND POP WAVEFORM FIGURE 8B. CLICK AND POP TEST CIRCUIT FIGURE 8. CLICK AND POP ELIMINATION 8 FN6583.1 April 3, 2009 ISL54065 Detailed Description V+ The ISL54065 is a bidirectional, dual single pole-double throw (SPDT) analog switch that offers precise switching from a single 1.8V to 6.5V supply with low ON-resistance (0.83Ω) and high speed operation (tON = 55ns, tOFF = 18ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (8nA), and a tiny 2.2x1.4mm µTQFN package. The low ON-resistance and RON flatness provide very low insertion loss and signal distortion for applications that require signal switching with minimal interference by the switch. +RING VNCx VCOMx VNOx CLAMP 1kΩ LOGIC INPUTS GND -RING Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. The ISL54065 contains ESD protection diodes on each pin of the IC (see Figure 9). These diodes connect to either a +Ring or -Ring for ESD protection. To prevent forward biasing the ESD diodes to the +Ring, V+ must be applied before any input signals, and the input signal voltages must remain between recommended operating range. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a logic pin or switch terminal goes above the V+ rail. Logic inputs can be protected by adding a 1kΩ resistor in series with the logic input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting external Schottky diodes to the signal pins will shunt the fault current to the V+ supply instead of through the internal ESD diodes thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current. FIGURE 9. OVERVOLTAGE PROTECTION Power-Supply and By-Pass Considerations The ISL54065 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 5.5V maximum supply voltage, the ISL54065’s 6.5V maximum supply voltage provides plenty of head room for the 10% tolerance of 5.5V supplies due to overshoot and noise spikes. The minimum recommended supply voltage is 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to “Electrical Specifications” tables, beginning on page 3, and “Typical Performance Curves”, beginning on page 11, for details. V+ and GND also power the internal logic and level shiftiers. The level shiftiers convert the input logic levels to V+ and GND signals levels to drive the analog switch gate terminals. A high frequency decoupling capacitor placed as close to the V+ and GND pin as possible is recommended for proper operation of the switch. A value of 0.1µF is highly recommended. Negative Signal Capability The ISL54065 contains circuitry that allows the analog input signal to swing below ground. The device has an analog signal range of 6.5V below V+ up to the V+ rail (see Figure 16) while maintaining low rON performance. For example, if V+ = 5V, then the analog input signal range is from -1.5V to +5V. If V+ = 2.7V then the range is from -3.8V to +2.7V. Click and Pop Operation The ISL54065 contains circuitry that prevents audible click and pop noises that may occur when audio sources are powered on or off. Single supply audio sources are biased at a DC offset that can generate transients during power on/off. A DC blocking capacitor is needed to remove the DC bias at the speaker load. For 32Ω headphones, a 220µF capacitor is 9 FN6583.1 April 3, 2009 ISL54065 typically used to preserve the audio bandwidth. The power on/off transients are AC coupled by the 220µF capacitor to the speaker load causing a click and pop noise. The ISL54065 has shunt switches on the NO and NC pins to eliminate click and pop transients (see Figure 10). These switches are driven complimentary to the main switch. When NC is connected to COM, the shunt switch is active on the NO pin (and vice versa). The shunt switches connect an impedance (140Ω typical, see Figure 25) from the NO/NC pin to ground to discharge any transients that may appear on the NO or NC pins. When the DC bias becomes active at the source, the NO and NC terminals will also have a DC offset due to capacitor dv/dt principle. The DC offset will be discharged through the shunt impedance on the NO and NC terminals instead of the speaker, eliminating click and pop noise. On the ISL54065, the Click and Pop Circuitry is enabled when the CP pin is logic high (>1.4V). The Click and Pop Circuitry may be disabled by tying the CP pin low (<0.4V). *Under high impedance loads (20kΩ) such as the input impedance of pre-amplifiers, the COM terminal voltage may rise due to small leakage currents charging the COM capacitance. This is not seen when low impedance (32Ω) loads such as headphones are used because the small leakage currents does not result in significant potential drop across the load. If the user desires to reduce the voltage build up on the COM pin, a 1kΩ to ground may be placed on the COM pin. This impedance is small enough to reduce the voltage build up significantly while not increasing the power dissipation dramatically. Current consumption considerations will need to be taken for driving a smaller load impedance under this scenario. V+ C AUDIO SOURCE A 220µF NO RSH COM RL 32Ω 220µF AUDIO SOURCE B NC RSH EN µP CP IN GND ISL54065 FIGURE 10. CLICK AND POP OPERATION 10 Click and Pop with Enable Pin Click and pop elimination can be driven with the Enable pin by setting it low. Having the Enable pin low turns OFF the main switches (NO and NC) while the Click and Pop Circuitry will be active. Transient voltages due to power on/off from both sources will be shunted to ground. For proper Click and Pop Elimination the Enable pin should be driven high at least 200ms after any source transients occurs to avoid audible transients at the speaker load. Click and Pop with Input Select Pin Click and pop elimination can also be driven with the Input Select pin. When INx = 0, the NOx terminals are connected to the shunt impedance. When INx = 1, the NCx terminals are connected to the shunt impedance. In this situation, only one of the source transient voltages will be shunted to ground, depending on the Input Select state. The Input Select pin should be driven 200ms after any source transients occurs to prevent audible transients at the speaker load. Logic-Level Thresholds This switch family is 1.8V CMOS compatible (0.45V VOLMAX and 1.35V VOHMIN) over a supply range of 1.8V to 3.3V (see Figure 16). At 3.3V the VIL level is 0.5V maximum. This is still below the 1.8V CMOS guaranteed low output maximum level of 0.45V, but noise margin is reduced. At 3.3V the VIH level is 1.4V minimum. While this is above the 1.8V CMOS guaranteed high output minimum of 1.35V under most operating conditions the switch will recognize this as a valid logic high. The digital input stages draws a larger supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54065 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 2.85V logic high while operating with a 4.2V supply the device draws only 1µA of current. High-Frequency Performance In 50Ω systems, the ISL54065 has an ON switch -3dB bandwidth of 60MHz (see Figure 21). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor across the open terminals and AC couples higher frequencies, resulting in signal feed-through from a switch’s input to its output. Off-Isolation is the resistance to this feed-through. Crosstalk indicates the amount of feed-through from one switch channel to another switch channel. Figure 22 details the high Off-Isolation and Crosstalk rejection provided by this part. At 100kHz, Off-Isolation is about 60dB in 50Ω systems, decreasing approximately 20dB per decade as frequency FN6583.1 April 3, 2009 ISL54065 Virtually all the analog switch leakage current comes from the ESD diodes and reversed biased junctions in the switch cell. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased to either the +Ring or -Ring and the analog input signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the +Ring or -Ring and the reverse biased junctions at the internal switch cell constitutes the analog-signal-path leakage current. increases. At 1MHz, Crosstalk is about -75dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin, V+ and GND. One of these diodes conducts if any analog signal exceeds the recommended analog signal range. Typical Performance Curves TA = +25°C, Unless Otherwise Specified 1.00 2.0 1.8 ICOM = 100mA V+ = 4.5V ICOM = 100mA 0.95 V+ = 1.8V 0.90 0.85 1.6 0.80 0.75 rON (Ω) rON (Ω) 1.4 1.2 1.0 0.65 0.60 T = +25°C 0.55 V+ = 2.7V 0.8 T = +85°C 0.70 0.50 0.6 V+ = 4.5V T = -40°C 0.45 0.40 0.4 0.35 0.2 -6 -5 -4 -3 -2 0 -1 1 2 3 4 5 0.30 -3 -2 0 -1 VCOM (V) FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 1 VCOM (V) 2 3 4 5 FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE 1.00 1.25 0.95 V+ = 4.3V ICOM = 100mA 0.90 V+ = 2.7V ICOM = 100mA 1.15 0.85 1.05 0.80 0.95 0.70 rON (Ω) rON (Ω) 0.75 T = +85°C 0.65 0.60 T = +25°C 0.55 0.85 0.75 0.65 T = +85°C 0.55 T = +25°C 0.50 T = -40°C 0.45 0.40 0.45 0.35 0.30 -3 -2 -1 0 1 2 3 4 VCOM (V) FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE 11 5 0.35 -5 T = -40°C -4 -3 -2 0 -1 VCOM (V) 1 2 3 4 FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE FN6583.1 April 3, 2009 ISL54065 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 2.2 6 V+ = 1.8V 2.0 5 ICOM = 100mA ANALOG SIGNAL RANGE (V) 1.6 rON (Ω) 1.4 1.2 1.0 0.8 T = +85°C 0.6 T = +25°C -5 2 1 0 -1 -2 -3 -4 -3 -2 -1 VCOM (V) 0 1 2 -6 3 1.5 700 V+ = 5.5V 650 ABSOLUTE VALUES 550 500 VINH AND VINL (V) V+ = 4.5V Q (pC) 450 400 350 V+ = 3.3V 300 250 200 150 100 V+ = 2.0V 50 0 -5 -4 -3 -2 -1 0 1 VCOM (V) 2 3 4 5 FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 6 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 6.0 VINH VINL 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5 40 T = -40°C 140 T = -40°C 35 T = +25°C T = +25°C T = +85°C 30 100 25 tOFF (ns) 120 tON (ns) 5.5 FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE 160 80 15 40 10 20 5 1.8 3.3 4.5 5.5 V+ (V) FIGURE 19. TURN - ON TIME vs SUPPLY VOLTAGE 12 T = +85°C 20 60 0 5.0 FIGURE 16. ANALOG SIGNAL RANGE vs SUPPLY VOLTAGE FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE 600 SIGNAL MIN -5 T = -40°C 6 3 -4 0.4 0.2 SIGNAL MAX 4 1.8 0 1.8 3.3 4.5 5.5 V+ (V) FIGURE 20. TURN - OFF TIME vs SUPPLY VOLTAGE FN6583.1 April 3, 2009 ISL54065 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 0 V+ = 1.8V TO 5.5V -10 V+ = 1.8V TO 5.5V -20 RL = 50Ω VIN = 1VRMS @ 0VDC OFFSET -30 -2 CROSSTALK (dB) NORMALIZED GAIN (dB) -1 -3 -4 -5 -40 -50 OFF-ISOLATION -60 CROSSTALK -70 -80 -90 RL = 50Ω VIN = 1VRMS @ 0VDC OFFSET 1k 10k 100k 1M 10M FREQUENCY (Hz) -100 100M -110 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 21. FREQUENCY RESPONSE INx (1V/DIV) 1G V+ = 3V VDC = 1.5VDC RL = 20kΩ VDC (1V/DIV) VNO (500mV/DIV) FIGURE 22. CROSSTALK AND OFF ISOLATION V+ = 3V VDC = 1.5VDC INx (1V/DIV) RL = 32Ω VDC (1V/DIV) VNO (500mV/DIV) *VCOM (10mV/DIV) VCOM (10mV/DIV) *See Page 10: CLICK AND POP OPERATION TIME ( 200ms/DIV) FIGURE 23. CLICK AND POP ELIMINATION 20kΩ LOAD 200ms DELAY 13 TIME (200ms/DIV) FIGURE 24. CLICK AND POP ELIMINATION 32Ω LOAD 200ms DELAY FN6583.1 April 3, 2009 ISL54065 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 0.05 350 V+ = 1.8V 325 300 707mVRMS 0.04 360mVRMS 250 225 200 V+ = 3V 175 V+ = 4.3V THD+N (%) SHUNT RESISTANCE (Ω) 275 0.03 177mVRMS 0.02 150 125 0.01 V+ = 5V 100 RL =32Ω 75 50 -5 V+ = 3.3V VBIAS = 0VDC -4 -3 -2 -1 0 1 2 SWITCH VOLTAGE (V) 3 4 5 FIGURE 25. SHUNT RESISTANCE vs SWITCH VOLTAGE 6 0 20 100 200 1k 2k FREQUENCY (Hz) 10k 20k FIGURE 26. TOTAL HARMONIC DISTORTION vs FREQUENCY Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND (DFN Paddle Connection: Tie to GND or Float) TRANSISTOR COUNT: 432 PROCESS: Submicron CMOS 14 FN6583.1 April 3, 2009 ISL54065 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D L12.2.2x1.4A B 12 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE 6 INDEX AREA 2X A N MILLIMETERS E 0.10 C 1 2X 2 0.10 C TOP VIEW C NOMINAL A 0.45 A1 - 0.05 C SIDE VIEW (DATUM A) PIN #1 ID 1 NX L 2 MAX NOTES 0.50 0.55 - - 0.05 - 0.127 REF - b 0.15 0.20 0.25 5 D 2.15 2.20 2.25 - E 1.35 1.40 1.45 - e A1 LEADS COPLANARITY 0.40 BSC - k 0.20 - - - L 0.35 0.40 0.45 - N 12 2 Nd 3 3 Ne 3 3 θ 0 - 12 4 Rev. 0 12/06 e Ne NOTES: (DATUM B) 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. NX b 2. N is the number of terminals. 5 0.10 M C A B 0.05 M C Nd 3 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. BOTTOM VIEW CL NX (b) MIN A3 0.10 C A SYMBOL (A1) L 5 7. Maximum package warpage is 0.05mm. e SECTION "C-C" 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 8. Maximum allowable burrs is 0.076mm in all directions. TERMINAL TIP C C 1.50 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 2.30 1 2 0.40 3 0.45 (12x) 0.25 (12x) 0.40 TYPICAL RECOMMENDED LAND PATTERN 10 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN6583.1 April 3, 2009