HCS195MS Radiation Hardened Inverting 8-Bit Parallel-Input/Serial Output Shift Register September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Fanout (Over Temperature Range) - Standard Outputs - 10 LSTTL Loads MR 1 16 VCC J 2 15 Q0 K 3 14 Q1 D0 4 13 Q2 D1 5 12 Q3 D2 6 11 Q3 D3 7 10 CP GND 8 9 PE • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW • Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min • Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCS195MS is a Radiation Hardened 8-Bit Parallel-In/Serial-Out Shift Register with complementary serial outputs and an asynchronous parallel load input. The HCS195MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. MR 1 16 VCC J 2 15 Q0 K 3 14 Q1 D0 4 13 Q2 D1 5 12 Q3 D2 6 11 Q3 D3 7 10 CP GND 8 9 PE The HCS195MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS195DMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP HCS195KMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack HCS195D/Sample +25oC Sample 16 Lead SBDIP HCS195K/Sample +25oC Sample 16 Lead Ceramic Flatpack HCS195HMSR +25oC Die Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 280 Spec Number File Number 518760 3385.1 HCS195MS Functional Diagram D0 D1 D2 D3 PE CP P J CL CL CL CL DP PL DP PL DP PL DP PL DS Q MR DS Q MR DS Q MR DS Q MR TG N P TG K N MR Q0 Q1 Q2 Q3 Q3 TRUTH TABLE INPUTS OUTPUTS MR CP PE J K Dn Q0 Q1 Q2 Q3 Q3 L X X X X X L L L L H H h h h X H q0 ql q2 q3 H h l l X L q0 ql q2 q3 H h h l X q0 q0 ql q2 q3 H h l h X q0 q0 ql q2 q3 H l X X dn d0 dl d2 d3 d3 Dn or Qn = referenced input (or output) one set-up time prior to clock l or h = level one set-up time prior to clock = positive clock Spec Number 281 518760 Specifications HCS195MS Absolute Maximum Ratings Reliability Information Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (All voltage reference to VSS) Thermal Resistance θJA θJC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.. Operating Conditions Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . . .10ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . .0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . VCC to 70% of VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Quiescent Current Output Current (Sink) Output Current (Source) Output Voltage Low Output Voltage High Input Leakage Current Noise Immunity Functional Test GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 40 µA 2, 3 +125oC, -55oC - 750 µA 1 +25oC 4.8 - mA 2, 3 +125oC, -55oC 4.0 - mA 1 +25oC -4.8 - mA 2, 3 +125oC, -55oC -4.0 - mA VCC = 4.5V, VIH = 3.15V, IOL = 50µA, VIL = 1.35V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 5.5V, VIH = 3.85V, IOL = 50µA, VIL = 1.65V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 4.5V, VIH = 3.15V, IOH = -50µA, VIL = 1.35V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIH = 3.85V, IOH = -50µA, VIL = 1.65V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIN = VCC or GND 1 +25oC - ±0.5 µA 2, 3 +125oC, -55oC - ±5.0 µA 7, 8A, 8B +25oC, +125oC, -55oC - - - (NOTE 1) CONDITIONS SYMBOL ICC IOL IOH VOL VOH IIN FN VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3) LIMITS NOTES: 1. All voltages reference to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. Spec Number 282 518760 Specifications HCS195MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL Propagation Delay (CP - Qn) TPHL1 Propagation Delay (CP - Qn) TPLH1 Propagation Delay (MR - Q0-3) TPHL2 Propagation Delay (MR - Q3) TPLH2 VCC = 4.5V, VIH = 4.5V VIL = 0 VCC = 4.5V, VIH = 4.5V VIL = 0 VCC = 4.5V, VIH = 4.5V VIL = 0 VCC = 4.5V, VIH = 4.5V VIL = 0 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN MAX UNITS 9 +25oC 2 31 ns 10, 11 +125oC, -55oC 2 37 ns 9 +25oC 2 34 ns 10, 11 +125oC, -55oC 2 42 ns 9 +25oC 2 32 ns 10, 11 +125oC, -55oC 2 39 ns 9 +25oC 2 32 ns 10, 11 +125oC, -55oC 2 39 ns NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Capacitance Power Dissipation CPD Input Capacitance CIN Output Capacitance COUT Pulse Width Time (CP or MR) TW Setup Time TSU Hold Time TH MR to CP Removal Time TREM Recovery Time PL to CP TREC Maximum Clock Frequency FMAX Output Transition Time TTHL TTLH (NOTE 1) CONDITIONS VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V LIMITS TEMPERATURE MIN MAX UNITS +25oC - 90 pF +125oC, -55oC - 120 pF +25oC - 10 pF +125oC, -55oC - 10 pF +25oC - 20 pF +125oC, -55oC - 20 pF +25oC 16 - ns +125oC, -55oC 24 - ns +25oC 20 - ns +125oC, -55oC 20 - ns +25oC 3 - ns +125oC, -55oC 3 - ns +25oC 16 - ns +125oC, -55oC 24 - ns +25oC 20 - ns +125oC, -55oC 30 - ns +25oC 30 - MHz +125oC, -55oC 20 - MHz +25oC 1 15 ns +125oC, -55oC 1 22 ns NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Spec Number 283 518760 Specifications HCS195MS TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL TEMPERATURE MIN MAX UNITS Supply Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.75 mA Output Current (Sink) IOL VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0 +25oC 4.0 - mA Output Current (Source) IOH VCC = VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0 +25oC -4.0 - mA Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOL = 50µA +25oC - 0.1 V Output Voltage High VOH VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOH = -50µA +25oC VCC -0.1 - V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC - ±5 µA Noise Immunity Functional Test FN VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3) +25oC - - - Propagation Delay (CP - Qn) TPHL1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 37 ns Propagation Delay (CP - Qn) TPLH1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 42 ns Propagation Delay (MR - Q0-3) TPHL2 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 39 ns Propagation Delay (MR - Q3) TPLH2 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 39 ns NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP DELTA LIMIT ICC 5 12µA IOL/IOH 5 -15% of 0 Hour PARAMETER Spec Number 284 518760 Specifications HCS195MS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test III (Postburn-In) 100%/5004 1, 7, 9 PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample/5005 1, 7, 9 Sample/5005 1, 7, 9 Group A (Note 1) Group B Group D READ AND RECORD ICC, IOL/H Subgroups 1, 2, 3, 9, 10, 11, (Note 2) NOTES: 1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. 2. Table 5 parameters only. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS TEST READ AND RECORD METHOD PRE RAD POST RAD PRE RAD POST RAD 5005 1, 7, 9 Table 4 1,9 Table 4 (Note 1) Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V 50kHz 25kHz - 16 - - - 1 - 7, 9 - 10, 16 - - 1 - 3, 16 11 - 15 10 4-7 STATIC BURN-IN I TEST CONNECTIONS (Note 1) 11 - 15 1 - 10 STATIC BURN-IN II TEST CONNECTIONS (Note 1) 11 - 15 8 DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) - 8, 9 NOTES: 1. Each pin except VCC and GND will have a resistor of 10kΩ ± 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 1kΩ ± 5% for dynamic burn-in TABLE 9. IRRADIATION TEST CONNECTIONS OPEN GROUND VCC = 5V ± 0.5V 11 - 15 8 1 - 7, 9 - 10, 16 NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Spec Number 285 518760 HCS195MS Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2 (T2) Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 1, Method 5004 (Notes 1and 2) 100% Internal Visual Inspection, Method 2010, Condition A 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Delta Calculation (T0-T1) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Interim Electrical Test 3 (T3) 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% PIND, Method 2020, Condition A 100% Final Electrical Test 100% External Visual 100% Fine/Gross Leak, Method 1014 100% Serialization 100% Radiographic, Method 2012 (Note 3) 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 286 518760 HCS195MS AC Timing Diagram AC Load Circuit VIH DUT TEST POINT INPUT VS VIL CL TPLH RL TPHL VOH VS OUTPUT CL = 50pF VOL VOH RL = 500Ω TTLH TTHL 80% 20% VOL 80% 20% OUTPUT AC VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V Pulse Width, Setup, Hold Timing Diagram Load Circuit Positive Edge Trigger DUT TEST POINT TW INPUT VIH CL RL VIL TH TSU CL = 50pF TW RL = 500Ω CP INPUT VIH VS VIL TH = Hold Time TSU = Setup Time TW = Pulse Width AC VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V Spec Number 287 518760 HCS195MS Die Characteristics DIE DIMENSIONS: 95 x 94 mils 2.380 x 2.410mm METALLIZATION: Type: AlSi Metal Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ ± 2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100µm x 100µm 4 x 4 mils Metallization Mask Layout HCS195MS J (2) MR (1) VCC (16) Q0 (15) Q1 (14) K (3) (13) Q2 D0 (4) (12) Q3 D1 (5) (11)Q3 (6) D2 (7) D3 (8) GND (9) PE (10) CP NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS195 is TA14387A. Spec Number 288 518760