cd00004040

AN1059
APPLICATION NOTE
®
DESIGN EQUATIONS OF HIGH-POWER-FACTOR
FLYBACK CONVERTERS BASED ON THE L6561
by Claudio Adragna
Despite specific for Power Factor Correction circuits using boost topology, the L6561 can be successfully used to control flyback converters. Among the various configurations that an L6561-based
flyback converter can assume, the high-PF one is particularly interesting because of both its peculiarity and the advantages it is able to offer. AC-DC adapters for mobile or office equipment, off-line battery chargers and low-power SMPS are the most noticeable examples of application that this configuration can fit.
This paper describes the equations governing such a kind of flyback converter with the aim of providing a number of relationships useful to the system designer.
Figure 1a. TM Flyback Configuration
INTRODUCTION
Three different configurations that an L6561-based
Vout
flyback converter can assume have been identified.
Vac
They are illustrated in fig. 1.
C
Configurations a) and b) are basically conventional
flyback converters. The former works in TM (Transition Mode, i.e. on the boundary between continuous
DISABLE
and discontinuous inductor current mode), therefore
at a frequency depending on both input voltage and
ZCD
VCC
output current. The latter works at a fixed frequency,
L6561
imposed by the synchronisation signal, and is thereGD
fore completely equivalent to a flyback converter
OPTO
+
based on a standard PWM controller.
TL431
Configuration c), which most exploits the aptitude of
the L6561 for performing power factor correction,
works in TM too but quite differently: the input capacitance is so small that the input voltage is very close to a rectified sinusoid. Besides, the control loop
has a narrow bandwidth so as to be little sensitive to the twice mains frequency ripple appearing at the
output.
BULK
Figure 1b. Synchronised Flyback Configuration
Figure 1c. High-PF Flyback Configuration
Vout
Vout
Vac
Vac
CBULK
CIN
SYNCH
DISABLE
DISABLE
ZCD
VCC
ZCD MULT VCC
L6561
L6561
GD
COMP
OPTO
+
TL431
INV
GD
OPTO
+
TL431
(BW<100 Hz)
September 2003
1/20
AN1059 APPLICATION NOTE
Actually, the high power factor (PF) exhibited by this topology can be considered just as an additional
benefit but not the main reason that makes this solution attractive. In fact, despite a PF greater than 0.9
can be easily achieved, it is a real challenge to comply with EMC norms regarding the THD of line current, especially in universal mains applications.
There are, however, several applications in the low-power range (to which EMC norms do not apply) that
can benefit from the advantages offered by a high-PF flyback converter. These advantages can be summarised as follows:
● for a given power rating, the input capacitance can be 200 times less, thus the bulky and costly high
voltage electrolytic capacitor after the rectifier bridge will be replaced by a small-size, cheaper film capacitor.
● efficiency is high at heavy load, more than 90% is achievable: TM operation ensures low turn-on
losses in the MOSFET and the high PF reduces dissipation in the rectifier bridge. This, in turn, minimises requirements on heatsinks;
● low parts count, which helps reduce encumbrance and assembly cost.
In addition, the unique features of the L6561 offer remarkable advantages in numerous applications:
● efficiency is high even at very light load: the low current consumption of the L6561 minimises the
power dissipated by both the start-up resistor and the self-supply circuit. An L6561-based high-PF flyback converter can easily meet Blue Angel regulations;
● additional functions available: the L6561 provides overvoltage protection as well as the possibility to
enable/disable the converter by means of its ZCD pin.
There are, on the other hand, some drawbacks, inherent in high-PF topologies, limiting the applications
that such a converter can fit (AC-DC adaptors, battery chargers, low-power SMPS, etc.) and which one
has to be aware of:
● twice-mains-frequency ripple on the output: unavoidable if a high PF is desired. A large output capacitance will reduce its amount. Speeding up the control loop may lead to a compromise between a
reasonably low output ripple and a PF still reasonably high;
● poor transient response: as to this point too, speeding up the control loop may lead to a compromise
between an acceptable transient response and a reasonably high PF;
Figure 2. Internal Block Diagram of the L6561.
INV
1
2.5V
VOLTAGE
REGULATOR
VCC
COMP
MULT
2
3
-
CS
4
MULTIPLIER
+
OVER-VOLTAGE
DETECTION
+
40K
5pF
-
VCC
8
INTERNAL
SUPPLY 7V
20V
R
R1
Q
S
+
7
UVLO
DRIVER
-
R2
VREF2
2.1V
1.6V
+
ZERO CURRENT
DETECTOR
STARTER
-
DISABLE
6
GND
2/20
5
ZCD
D97IN547D
GD
AN1059 APPLICATION NOTE
large output capacitance (in the thousand µF, depending on the output power) is required: however,
cheap standard capacitors and not costly high-quality parts are needed. In fact, a low ESR and an
adequate AC current capability are automatically achieved. Besides, in conventional flyback converters there is usually plenty of output capacitance too, thus this is not so dramatic as it may seem at
first sight;
● secondary post-regulation will be required where tight specifications on the output ripple and/or on
the transient behaviour are given. However, this is true also for a standard flyback;
● the system is unable to cope with line missing cycles at heavy load unless an exceedingly high output
capacitance is used.
In the following, the operation of a high-PF flyback converter will be discussed in details and numerous
relationships, useful for its design, will be established.
●
Preliminary statements
In order to generate the equations governing the operation of a high-PF flyback converter working in TM,
refer also to the internal block diagram of the L6561(see fig. 2). For details concerning the operation of
the L6561, please refer to Ref. [1].
The following assumptions will be made:
1. the line voltage is perfectly sinusoidal and the rectifier bridge is ideal, thus the voltage downstream
the bridge, sensed by the input of the L6561’s multiplier (MULT, pin 3) is a rectified sinusoid:
Vin (t) = VPK ⋅ |sin (2 ⋅ π ⋅ fL ⋅ t)|
where VPK is equal to the RMS line voltage, VRMS, times the square root of 2, and fL is the line frequency (usually 50 or 60 Hz).
2. the output of L6561’s Error Amplifier (VCOMP) is constant for a given line half-cycle;
3. transformer’s efficiency is 1 and its windings are perfectly coupled.
4. ZCD circuit’s delay is negligible thus the converter works exactly on the boundary between continuous
and discontinuous current conduction mode (TM operation).
As a result of the first two assumptions, the peak primary current is enveloped by a rectified sinusoid:
Ipkp(t) = IPKp ⋅ |sin (2 ⋅ π ⋅ fL ⋅ t)| (1)
One consequence of assumption 3 is that the peak secondary current is proportional to the primary one,
depending on transformer’s primary-to-secondary turns ratio n:
Ipks(t) = n ⋅ Ipkp(t)
To simplify the notation, in the following the phase angle θ = 2 ⋅ π ⋅ fL ⋅ t of the sinusoidal quantities will
be indicated and all the quantities depending on the instantaneous line voltage will be considered as a
function of θ, instead of time.
Timing relationships
The ON-time of the power switch is expressed by:
TON =
Lp ⋅ Ipkp (θ) Lp ⋅ IPKp
(2),
=
VPK
Vin(θ)
where Lp is the inductance of transformer’s primary winding. Eqn. (2) shows that TON is constant over a
line half-cycle, exactly like in boost topology. The OFF-time is instead variable:
Lp
TOFF =
⋅ n ⋅ Ipkp(θ)
Ls ⋅ Ipks(θ) n2
Lp ⋅ IPKp ⋅ |sin (θ)|
=
=
n ⋅ (Vout +Vf)
(Vout + Vf)
(Vout + Vf)
(3),
3/20
AN1059 APPLICATION NOTE
where Ls is the inductance of the secondary winding, Ipks(θ) the peak secondary current, Vout the output
voltage of the converter (supposed to be a regulated DC value) and Vf the forward drop on the output
catch diode.
Since the system works in TM, the sum of the ON and the OFF times equals the switching period:
T = TON + TOFF =
Lp ⋅ IPKp
VPK
VPK


⋅ 1 +
⋅ |sin(θ)|
V
R


(4)
where VR = n ⋅ (Vout + Vf ) is the so-called reflected voltage.
The switching frequency fsw = T -1, therefore, varies with the instantaneous line voltage:
fsw =
VPK
⋅
Lp ⋅ IPKp
1
VPK
1+
⋅ |sin(θ)|
VR
and reaches its minimum value on the peak of the sinusoid (sin (θ)=1):
fsw min =
VPK
⋅
Lp ⋅ IPKp
1
VPK
1+
VR
(5)
This value, calculated at the minimum line voltage, must be greater than the maximum one of the internal starter of the L6561 (≈14 kHz ), in order to ensure a correct TM operation. To accomplish with this
requirement, the primary inductance Lp will be properly selected (not exceeding an upper limit). Actually,
to minimise the size of the transformer, the minimum frequency will usually be selected quite higher than
15 kHz, say 25-30 kHz or more, so the value of Lp needs not have a tight tolerance.
The duty cycle, that is the ratio between the ON-time and the switching period, will vary with the instantaneous line voltage as well (because of the variation of TOFF), as it is possible to find by dividing eqn.(2)
by (4):
D=
TON
=
T
1
VPK
1+
⋅ |sin(θ)|
VR
(5’)
Equations (2) and (4) show that TON and T, respectively, can be short at will if IPKp (i.e. the load) tends to
zero, especially at high input voltage. In the real-world operation, it must be considered that TON cannot
go below a minimum amount and so will do the switching period as well. This minimum (typically, 0.40.5µs) is imposed by the internal delay of the L6561 and by the turn-off delay of the MOSFET.
When this minimum is reached, the energy drawn each cycle exceeds the short-term demand from the
load, thus the control loop causes some cycles to be skipped so as to maintain the long-term energy balance. When the load is so low that many cycles need to be skipped, the amplitude of the drain voltage
ringing becomes so small that it can no longer trigger the ZCD Block of the L6561. In that case the internal starter of the IC will start a new switching cycles sequence.
Something similar applies to the duty cycle as well, which eqn. (5’) predicts to be unity when θ = 0, that
is at the zero-crossings of the mains voltage. In reality, a number of parasitic effects cause TON and TOFF
not to follow the ideal relationships (2) and (3). The effect of that on the overall operation is however
negligible because the energy processed near a zero-crossing is very little.
In the following, the ratio between the line peak voltage VPK and the reflected voltage VR will be indicated with Kv:
Kv =
VPK
VR
Energetic relationships
Apart from the duty cycle, all the quantities expressed in the timing relationships depend on the throughput power, which is represented in the above equations by IPKp, the peak primary current occurring at
4/20
AN1059 APPLICATION NOTE
the peak of the sinusoid of the primary voltage.
The following relationships relate IPKp to the input power Pin and allow both to explicate the timing relationships and to calculate all the currents circulating in the circuit.
Figure 3. High-PF Flyback current waveforms
Secondary current
peak envelope
Primary current
peak envelope
Average
primary current
ON
OFF
SWITCH
The primary current Ip(t) is triangular-shaped and flows only during the switch ON-time, as illustrated by
the shaded triangles shown in fig. 3. As earlier stated by equation (1), during each half-cycle the height
of these triangles varies with the instantaneous line voltage:
Ipkp(θ) = IPKp ⋅ |sin (θ)|,
their width is constant but they are spaced out by a variable amount given by (3).
Looking at the primary on a "fL" time scale, the current Iin(θ) downstream the bridge rectifier is the average value of each triangle over a switching cycle (the thick black curve of fig. 3):
Iin(θ) =
|sin (θ)|
1
1
⋅ Ipkp(θ) ⋅ D = ⋅ IPKp ⋅
2
2
1 + Kv ⋅ |sin (θ)|
Figure 4a. Primary Current (@ fL time scale)
Figure 4b. Line Current (@ fL time scale)
1
1
Kv=0.5
Kv=0.5
Kv=4
Kv=2
after the 0.5
bridge
Kv=2
Iin(θ)
Kv=1
Iin(θ)
before
the
bridge
Kv=4
0
0.5
0.25
0
Kv=1
0.5
0.75
0
1.57
3.14
θ
4.71
6.28
1
0
1.57
3.14
4.71
6.28
θ
5/20
AN1059 APPLICATION NOTE
This function, shown in fig. 4a for different values of Kv, is a periodic even function, at twice line frequency, not negative because of the bridge rectifier. Conversely, the current drawn from the mains will
be the "odd counterpart" of (6), at line frequency, as shown in fig. 4b).
Actually, it is realistic to think that a filtering action eliminates the switching frequency component of the
current upstream the rectifier bridge, so that the mains "can see" only the average value. This current
would be sinusoidal for Kv = 0 but will be distorted from an ideal sinusoid so much as Kv increases.
Since Kv cannot be zero (which would require the reflected voltage to tend to infinity), flyback topology
does not permit unity power factor even in the ideal case, unlike boost topology.
In order to simplify the following calculations, it is possible to eliminate the absolute value from | sin (θ)|
by considering θ ∈ [0 , π] and assuming the various functions to be either even or odd by definition, depending on their physical role.
The input power Pin will be calculated by averaging the product Vin(θ) • Iin(θ) over a line half-cycle:
____________ 1
sin2 (θ)
Pin = Vin (θ) ⋅ Iin (θ) = ⋅ VPK ⋅ IPKp ⋅
2
1 + Kv ⋅ sin (θ)
(7).
It is now advantageous to introduce the following function:
F2(x) =
sin2 (θ)
sin2 (θ)
1 π
dθ
= ⋅∫
1 + x ⋅ sin (θ) π o 1 + x ⋅ sin (θ)
(8),
whose diagram as a function of the variable x is shown in fig. 5.
Although a closed form exists for the integral in (8),
it is not so handy, thus for practical use it is more
convenient to provide a "best fit" approximation:
Figure 5. High-PF Flyback characteristic
functions: F2(x) diagram
0.5
F2(x) ≈
0.4
F2( x )
0.3
0.5 + 1.4 ⋅ 10−3 ⋅ x
.
1 + 0.815 ⋅ x
From (7), taking (8) into account, it is possible to
calculate IPKp:
0.2
0.1
IPKp =
0
0
1
2
3
4
5
x
6
7
8
9
10
2 ⋅ Pin
,
VPK ⋅ F2(Kv)
which will assume its maximum value at minimum
mains voltage.
The total RMS value of the primary current, useful for power loss estimate on the primary side, is calculated considering the RMS value of each triangle of Ip(t) and averaging over a line half-cycle:
1 2

 = IPKp ⋅
IRMSp = √
⋅ Ipkp (θ) ⋅ D
3
sin (θ)
1
√

⋅
3
2
1 + Kv ⋅ sin(θ)
= IPKp ⋅
F2 (Kv)
√
3
(9).
The DC component of the primary current, useful to discriminate DC and AC losses in the transformer, is
the average value of Iin(θ) over a line half-cycle:
_____ 1
sin (θ)
IDCp = Iin(θ) = ⋅ IPKp ⋅
2
1 + Kv ⋅ sin(θ)
(10).
Considering the following function:
F1(x) =
6/20
sin (θ)
sin (θ)
1 π
dθ,
= ⋅∫
1 + x ⋅ sin (θ) π o 1 + x ⋅ sin (θ)
AN1059 APPLICATION NOTE
equation (10) can be rewritten as follows:
IDCp =
Figure 6. High-PF Flyback characteristic
functions: F1(x) diagram
Also for F1(x) it is more practical to furnish a best fit
approximation rather than the exact expression:
0.7
0.6
0.5
F1( x )
1
⋅ IPKp ⋅ F1(Kv).
2
F1(x) ≈
0.4
0.637 + 4.6 ⋅ 10−3 ⋅ x
.
1 + 0.729 ⋅ x
0.3
0.2
0.1
0
0
1
2
3
4
5
x
Io(θ) =
6
7
8
9
10
As to the current on the secondary side, Is(t), it is
the series of triangles complementary to the primary’s (the white ones in fig. 3). Its twice line frequency representation will be again the average
over a switching cycle:
sin2 (θ)
1
1
⋅ Ipks(θ) ⋅ (1 − D) = ⋅ IPKs ⋅ Kv ⋅
2
2
1 + Kv ⋅ sin(θ)
(11).
Like the primary current (6), also (11) is a not negative periodic even function.
According to assumption 3), IPKs would equal n•IPKp. To consider a more realistic case (the secondary
peak current is slightly less than n•IPKp because of transformer’s losses and other non-idealities) it is
possible to derive IPKs from the DC value of the output current, Iout, of the converter, which is one of the
design data.
By equalling the average value of (11) over one line half-cycle to Iout, it is possible to find:
IPKs =
2 ⋅ Iout
.
Kv ⋅ F2(Kv)
The total RMS secondary current is calculated as follows:
______________
1 2

IRMSs = √
⋅ Ipks(θ) ⋅ (1 − D) = IPKs ⋅
3
sin (θ)
K
√

⋅
3
3
v
(12)
1 + Kv ⋅ sin(θ)
It will be now introduced the third characteristic function of the high-PF flyback:
F3(x) =
sin3(θ)
sin3(θ)
0.424 + 5.7 ⋅ 10−4 ⋅ x
1 π
dθ ≈
.
= ⋅∫
1 + x ⋅ sin(θ) π 0 1 + x ⋅ sin(θ)
1 + 0.862 ⋅ x
With this definition, it is possible to express (12) as follows:
IRMSs = IPKs ⋅
F3(Kv)

√
Kv ⋅ 3 .
Figure 7. High-PF Flyback characteristic
functions: F3(x) diagram
For both primary and secondary side, the AC component of current can be calculated with the general
relationship:
0.5
0.4
0.3
I2RMSi − I2DCi
IACi = √

(i = p,s).
F3( x )
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
x
7/20
AN1059 APPLICATION NOTE
Power Factor and Total Harmonic Distortion
Under the assumption of a sinusoidal line voltage, the Power Factor PF can be expressed as:
PF =
VRMS ⋅ IRMS1 IRMS1
Real Input Power
=
=
Apparent Input Power VRMS ⋅ IRMSin IRMSin
(13)
where VRMS is the (effective) line voltage, IRMS1 is the effective value of the first harmonic (it will be in
phase with the line voltage) and IRMSin the total effective value of the input current waveform (6).
IRMS1 can be simply calculated from the numerator of (13):
IRMS1 =
Pin
Pin
=√
2 ⋅
VRMS
VPK
(14).
It is worth noticing that IRMSin ≠ IRMSp. In fact (9) contains also the energy contribution due to the switching frequency, while equation (13) - and therefore IRMSin too - refers only to line frequency quantities.
IRMSin is the RMS value of (6), which is by definition:
_____ 1
IRMSin = √

I2in(θ) = 2 ⋅ IPKp ⋅
sin(θ)


1
√

dθ
⋅∫ 
1 + K ⋅ sin(θ) 
π
2
π
0

(15).

v
Inserting (14) and (15) in (13) yields the theoretical expression of PF (note that it depends only on Kv).
Its diagram, depicted in fig. 8, shows how it keeps quite close to 1. For practical use, PF can be approximated by:
PF(Kv) ≈ 1 - 8.1 ⋅ 10-3 ⋅ Kv + 3.4 ⋅ 10-4 ⋅ K2v
(16)
Obviously numerous non-idealities, basically the
ones mentioned in the section "Timing Relationships", contribute to achieve a real-world PF lower
than the theoretical value given by (16), especially
at light load and high mains voltage.
The Total Harmonic Distortion (THD) of the line current is defined in percentage as:
Figure 8. Theoretical Power Factor of
high-PF Flyback converters
1
0.99
0.98
PF(Kv)
0.97
0.96
0.95
∞
THD % = 100 ⋅

√
∑2 I2RMSn
IRMS1
0
1
2
3
4
5
6
7
8
9
10
Kv
,
where IRMSn is the RMS amplitude of the n-th harmonic. Still under the assumption of an ideally sinusoidal input voltage, the THD is related to the Power Factor by the following relationship:
1

THD% = 100 ⋅ √
− 1.
PF2
Fig. 9 illustrates the dependence of THD% on Kv.
For a given reflected voltage, it shows how the Total
Harmonic Distortion degrades when the line voltage
builds up.
Figure 9. THD% as a function of Kv
40
THD%
(Kv)
32
24
16
Transformer
The design of the transformer is a complex procedure that involves several steps: selecting the core
material and geometry, determining the maximum
peak magnetic flux density (and whether this is lim8/20
8
0
0
1
2
3
4
5
Kv
6
7
8
9
10
AN1059 APPLICATION NOTE
ited by core saturation or losses), determining the core size, defining the primary and secondary windings (turns number and wire gauge) as well as calculating the air-gap necessary to achieve the desired
inductance. Moreover, additional considerations concerning the assembly are needed for meeting safety
requirements, maximising magnetic coupling and minimising parasitic high frequency effects, not to
mention the constraints imposed by the specific application, if any.
Some parameters are needed to start the design of the transformer. The (maximum) primary inductance
will be calculated by solving (5) for Lp:
Lp ≤
V2PKmin
1 F2(Kvmin)
,
⋅
⋅
2 1 + Kvmin fswmin ⋅ Pinmax
or by simply looking up the diagram of fig. 10, where the primary inductance required for 1W input power
is plotted against fswmin, for different values of Kvmin and for the two typical mains voltage ranges. The
value taken from fig. 10 (in mH), will be divided by the maximum input power to get the actual primary inductance required by the specific application.
The primary-to-secondary turns ratio will be given by:
n=
VR
Vout + Vf
.
Figure 10. Maximum specific primary inductance required
85
400
110Vac or
Wide-range Mains
L( 0.5 , fmin ) 65
L( 1 , fmin )
220Vac Mains
L( 0.5 , fmin ) 300
Kvmin = 0.5
L( 1 , fmin )
1
1
Lmax
L( 1.5 , fmin ) 45
[mH·W]
L( 1.5 , fmin ) 200
L( 2 , fmin )
L( 2 , fmin )
L( 2.5 , fmin ) 25
Lmax
[mH·W]
2
Kvmin = 0.5
1.5
L( 2.5 , fmin ) 100
2
2.5
2.5
5
4
2 10
1.5
4
3 10
4
4 10
4
4
6 10
5 10
0
4
2 10
4
3 10
fmin
fswmin
[Hz]
4
4 10
5 10
4
4
6 10
fmin[Hz]
fswmin
With the peak and RMS current values calculated in the "Energetic relationships" section, the design can
be carried out just like for any conventional flyback transformer, thus no particular procedure will be considered.
Anyway, as a design aid to core selection, two expressions for determining the minimum required core
Area-Product (winding window area times effective magnetic cross section) will be provided:
1.316
460 ⋅ Pin


APmin = 

F2(K
f
K
)
⋅

√


)
⋅
(1
+
v
v 
 swmin
(17);
1.585
480 ⋅ Pin


APmin = 
F2(Kv) 

 fswmin ⋅ (1 + Kv) ⋅ √
⋅ [ JH(Kv) ⋅ fswmin + JE(Kv) ⋅ f2swmin ] 0.66
(18);
.
9/20
AN1059 APPLICATION NOTE
where JH (Kv) and JE (Kv) are functions related to hysteresis and eddy current losses, whose best fit approximation are respectively:
JH(Kv) ≈
1.87 + 1.26 ⋅ Kv
⋅ 10−5
1 + 0.55 ⋅ Kv
JE(Kv) ≈
1.88 + 1.06 ⋅ Kv
⋅ 10−10.
1 + 0.34 ⋅ Kv
Formula (17) assumes that the maximum peak flux density inside the core is limited by core saturation
and that all transformer losses are located in the windings; (18) assumes that core losses limit the flux
swing and the total dissipation are half due to core losses and half to windings losses.
Common to both formulae are the following
Figure 11. Minimum Transformer AP required for a
assumptions:
30W application.
1. the material is a typical power ferrite
1
(3C85 from Philips, N67 from Siemens or
similar grades) with a saturation flux density
0.9
above 0.3 Tesla;
Kv = 0.5
0.8
2. the windings occupy 40% of the total
0.7
window area to leave space for isolation layKv = 1
V( fmin , 0.5)
ers, creepage and clearance distances;
V( fmin , 1 ) 0.6
Kv = 1.5
4
AP [cm ]
3. primary and secondary winding wires
V( fmin , 1.5) 0.5
Kv = 2
are proportioned for equal RMS current denV( fmin , 2 )
0.4
sity;
V( fmin , 2.5)
0.3
4. core and/or copper losses result in 30 °C
Kv = 2.5
hot spot temperature rise (no forced cooling);
0.2
5. skin and proximity effects are neglected,
0.1
considering the frequency range involved.
0
4
4
4
4
4
4
4
4
4
For a given fswmin, one should try both formu2 10
2.5 10
3 10
3.5 10
4 10
4.5 10
5 10
5.5 10
6 10
fmin [Hz]
fswmin
lae (considering Kv at minimum line voltage)
and use the higher resulting value. Core
losses become dominant for core selection above 45 kHz at this power level.
In fig. 11, the higher value resulting from (17) and (18) is plotted against fswmin for different values of Kv,
considering 30W output power with an estimate of 85% efficiency.
Figure 12a. RCD Clamp.
Clamp network
The overvoltage spikes due to the leakage inductance of the transformer are usually limited by an RCD clamp network, as illustrated in
fig. 12a. It can be advantageous the use of a zener (or transil) clamp
(see fig. 12b) when minimisation of power losses at light load is desired.
Considering the RCD clamp, the capacitor is selected so as to have an
assigned overvoltage ∆V (as a rule of thumb, half the reflected voltage)
at turn-off such that the voltage rating of the MOSFET is never exceeded. From energetic balance, it is possible to write:
Llk ⋅ I2PKpmax
,
Cmin =
∆V ⋅ (∆V + 2 ⋅ VR)
where Llk is the leakage inductance, which can be estimated in the
range of 1 to 3% of the primary inductance if the transformer is properly
manufactured, and:
2 ⋅ Pinmax
IPKpmax =
VPKmin ⋅ F2(Kvmin)
The capacitor undergoes large current spikes and therefore it should
be a very low ESR type with polypropylene or polystyrene film dielectric.
10/20
C
R
D
Figure 12b. Zener (Transil)
Clamp.
T
D
AN1059 APPLICATION NOTE
The minimum resistor value can be found by imposing that the voltage on the capacitor at the beginning
of each switching cycle never falls below the reflected voltage :
Rmin =
1

∆V 
fswmin ⋅ C ⋅ ln 1 +
VR 

The power rating of this resistor can be estimated by considering the DC dissipation due to the reflected
voltage and the leakage inductance energy:
PR =
V2R 1
+ ⋅ (1 + Kvmin) ⋅ F2(Kvmin) ⋅ Llk ⋅ I2PKpmax ⋅ fswmin.
R 2
The blocking diode will be not only a very fast recovery type but will also feature a very fast turn-on time.
In fact, the instantaneous forward drop at turn-on generates a spike, exceeding the overvoltage ∆V, that
must be small. The diode will be rated for repetitive peak currents equal to IPKp, and with a breakdown
voltage greater than VPKmax + VR.
Considering a zener or a transil, its clamping voltage can be approximated with its breakdown voltage. In
fact, the peak current is quite small and it is possible to neglect the contribution due to the dynamic resistance. The breakdown voltage, which should account for the drift due to the temperature rise, will then be:
V(BR) ≈ VCL = VR + ∆V.
The steady-state power dissipation capability must be at least:
Ptransil =
V(BR)
⋅ (1 + Kvmin) ⋅ F2(Kvmin) ⋅ Llk ⋅ I2PKpmax ⋅ fswmin,
2 ⋅ ( V(BR) − VR )
while there is no concern about its peak power dissipation, since this is defined for power pulses of 1 ms
(leakage inductance is typically demagnetized in less than 1 µs).
As to the blocking diode, what said earlier about the one of the RCD clamp still applies.
Output Capacitor
The output capacitor undergoes the AC component of the secondary current Is(t), (see fig 3).
Besides, to achieve a reasonably high PF, the voltage control loop is slow (typically, its bandwidth is below 100 Hz). As a result, there is a quite large voltage ripple appearing across the output capacitor. This
ripple has two components.
One is related to the high frequency triangles and depends almost entirely on the ESR of the output capacitor, being the capacitive contribution practically negligible. Its maximum amplitude, occurring on the
peak of the sinusoid, will be:
= IPKs ⋅ ESR.
∆V(HF)
o
The second component of the ripple is related to the twice line frequency envelope and, unlike the high
frequency component, depends on the capacitance value, while the ESR contribution can be neglected.
To calculate the amplitude of this component, only the fundamental harmonic of (11), at twice line frequency, will be taken into account. In fact, the amplitude of the higher order (even) harmonics is much
smaller and the impedance of the capacitor decreases with frequency as well.
According to Fourier’s analysis, the (peak) amplitude of the fundamental harmonic of (11) is:
Io2 =
IPKs ⋅ Kv π sin2(θ) ⋅ cos(2 ⋅ θ)
dθ,
⋅∫
1 + Kv ⋅ sin(θ)
π
0
that, defining the following function:
11/20
AN1059 APPLICATION NOTE
H2(x) =
2
0.25 − 1.5 ⋅ 10−3 ⋅ x
1  π sin (θ) ⋅ cos(2 ⋅ θ) 
⋅∫
 dθ ≈
1 + 1.074 ⋅ x
π  0 1 + x ⋅ sin(θ) 
(19),
can be expressed as:
Io2 = IPKs ⋅ Kv ⋅ H2(Kv) = 2 ⋅ Iout ⋅
H2(Kv)
.
F2(Kv)
The absolute value in (19) is needed since the integral results negative, because the harmonic is 180°
out of phase. Finally, the peak-to-peak amplitude of the low frequency output ripple is:
∆Vo = 2 ⋅ Io2 ⋅ Z(2fL) (Co) =
Iout
1 H2(Kv)
.
⋅
⋅
π F2(Kv) fL ⋅ Co
In most cases, once a capacitor is selected so as to meet the requirement on the low frequency ripple,
the ESR will be low enough to make the high frequency ripple negligible.
Multiplier Bias and Sense Resistor Selection
A resistor divider feeds a portion of the input voltage into pin 3 (MULT) to build the sinusoidal reference
for the peak primary current. To set properly the operating point of the multiplier the following procedure
is recommended.
First, the maximum peak value for VMULT, VMULTpkmax, is selected. This value, which will occur at maximum mains voltage, should be 2.5 to 3V in wide range mains applications and 1 to 1.5V in case of single
mains. The minimum peak value, occurring at minimum mains voltage will be:
VMULTpkmin = VMULTpkmax ⋅
VPKmin
VPKmax
This value, multiplied by the minimum guaranteed ∆VCS/∆VCOMP will give the maximum peak output voltage of the multiplier:
Vcxpk = 1.65 ⋅ VMULTpkmin
If the resulting Vcxpk exceeds the linearity limit of the current sense (1.6 V), the calculation should be repeated beginning with a lower Vmultpkmax value.
In this way, the divider ratio will be:
KP =
VMULTpkmax
VPKmax
and the individual resistor values can be chosen by setting the current through them, in the hundreds µA
or less, to minimise power dissipation.
The value of the sense resistor, connected between the source of the MOSFET and ground, across
which the L6561 reads the primary current, is calculated as follows:
Rs ≤
Vcxpk
.
IPKpmax
The resistor will be rated for a power dissipation equal to:
Ps = Rs ⋅ I2PKpmax ⋅
12/20
F2(Kvmin)
3
AN1059 APPLICATION NOTE
Closing the Control Loop
The control loop of a high-PF flyback converter based on the L6561, can be synthesised as in the block
diagram of fig. 13.
Unlike conventional converters, in such regulators the control loop will have quite a narrow bandwidth so
as to maintain VCOMP fairly constant over a given line cycle, as assumed at the beginning. This will ensure a high PF. On the other hand, it is not possible to achieve a very high PF (>0.99), thus it makes no
sense to have a very narrow bandwidth (<20 Hz) like in boost PFC preregulators. This would degrade
the transient response to line and load changes without any benefit. A compromise will then be found
between these two contrasting terms.
Figure 13. Block Diagram of the Control Loop of an L6561 - based high-PF flyback.
Vin
ZCD
Vref
+
Ve ERROR AMPLIFIER Vcomp
-
G1(s)
MULTIPLIER
Vcx
+
PWM MODULATOR IPKp
-
G2(s)
POWER STAGE
Vout
G4(s)
G3(s)
FEEDBACK
H(s)
To the aim of deriving the transfer functions of the blocks in fig. 13, the narrow bandwidth of the control
loop allows to assume that the control action takes place on the peak amplitude of the various quantities.
The error amplifier (E/A) of the L6561 is compensated as illustrated in fig. 14. The transfer function
G1(s) will be then:
G1(s) =
1 + s ⋅ (C2 ⋅ R8)
R7
∆VCOMP
.
=−
⋅
R
∆VE
6 1 + s ⋅ [C2 ⋅ (R7 + R8)]
Figure 14. Compensation of the Error Amplifier.
R7
R8
C2
R6
COMP
INV
_
E/A
+
2.5V
TO MULTIPLIER
L6561
13/20
AN1059 APPLICATION NOTE
The pole is placed at a very low frequency so that the gain at twice line frequency is quite less than
unity, while the zero boosts the phase in the neighbourhood of the open-loop crossover frequency so as
to provide phase margin.
A variation ∆VCOMP, due to a line and/or load change, modifies the amplitude Vcx of the rectified sinusoid
at the output of the multiplier. This considering, the transfer function of the multiplier block will be:
G2 =
∆Vcx
= KM ⋅ KP ⋅ VPK
∆VCOMP
where KM is the gain of the multiplier (= 0.75 max.).
The gain of the PWM modulator, which includes the current loop, is simply:
G3 =
∆IPKp 1
=
∆Vcx Rs
where Rs is the sense resistor.
Small-Signal analysis shows that the gain G4(s) of the power stage is:
G4(s) =
∆Vout n ⋅ Kv ⋅ F2(Kv) Ro
=
⋅
⋅
2
∆IPKp
Γ(Kv) + 1
1 + s ⋅ (Co ⋅ ESR)
,
Ro
1 + s ⋅ (Co ⋅
)
Γ(Kv) + 1
where the function Γ(x) is defined as follows:
Γ(x) = 1 +
dF2(x) 1 + 0.01 ⋅ x
x
.
⋅
≈
dx
F2(x)
1 + 0.8 ⋅ x
The feedback network can have different configurations, depending on the requirements on the tolerance and on the regulation of the output voltage.
In this context a popular configuration (see fig. 15) will be taken into consideration. It uses an optocoupler for galvanic isolation between primary and secondary and a TL431, a cheap voltage reference/opamp housed in a three pin package.
The gain, H(s), at twice line frequency must be low. In fact, being the output voltage ripple quite high, a
high gain could saturate the dynamics of the TL431 and/or of the optocoupler, besides complicating
things in getting a narrow overall bandwidth.
Referring to fig. 15, it is possible to write:
H(s) =
1 + s ⋅ C1 ⋅ (R1 + R3)
∆VE
1 R5 ⋅ R6
,
=
⋅
⋅ CTR ⋅
s ⋅ (C1 ⋅ R1)
∆Vout R4 R5 + R6
where CTR is the Current Transfer Ratio of the optocoupler.
When designing the control loop, first select the operating current of optocoupler’s transistor (IC). It is advantageous to selects a low IC value (e.g. 1 mA): this will not only extend the lifetime of the device but, in
the present case, will also help keep low the gain of the feedback network at twice line frequency.
Since in closed-loop operation the quiescent value of VE will be in the neighbourhood of 2.5V (internal
reference of the L6561 E/A), R5 will be:
R5 =
2.5
.
IC
R4 will be selected so as to maintain VK voltage above 2.5V for a correct functionality of the TL431 even
in the worst case, that is when the optocoupler exhibits its minimum CTR, because of the statistical
spread of this parameter.
14/20
AN1059 APPLICATION NOTE
Figure 15. Feedback network and connection to the error amplifier.
Vout
R7
R8
COMP
C2
L6561
INV
IF
R4
VCC
R1
≈1 µF
R6
C1
VE
IC
R5
R3
VK
TL431
R2
Therefore:
R4 <
Vout − 1 − 2.5
⋅ CTRmin ⋅ R5,
2.5
where 1V is the typical drop across optocoupler’s photodiode. Keep R4 close to the maximum for a low
gain. R1 and R2 are selected to get the desired output voltage:
R2 =
Vout − 2.5
2.5
; R1 =
⋅ R2
IR2
2.5
where 2.5 is the internal reference of the TL431 and IR2 the current flowing through R2.
To have a low gain at twice line frequency, the zero of H(s) will be placed below 100Hz and R3 will be 45 times less than R1. This yields the value of C1.
The value of R6 will be such that the twice mains frequency ripple superimposed on the static VE cannot
trip the dynamic overvoltage protection of the L6561 (40 µA entering pin COMP). Approximately:
R6 > R5 +
R5 CTRmax ⋅ ∆Vo
⋅
R4
40 ⋅ 10−6
R7 will be selected so as to allow the output of the error amplifier to swing all the dynamics. Finally, R8
and C2 will be adjusted so that the crossover frequency of the open-loop gain is a good compromise between a high enough PF and an acceptable transient response, ensuring also sufficient phase margin.
The optional capacitor (in the µF range) connected in parallel to R1 acts as a soft-start circuit that prevents overvoltages of the output at start-up, especially at light load. The two diodes decouple the capacitor during steady-state operation so that it does not interfere with the loop gain and provide a discharge
path when the converter is turned off.
15/20
AN1059 APPLICATION NOTE
CALCULATION EXAMPLE
An example of step-by-step design procedure of an L6561-based, high-PF flyback converter will be here
described for reference. It concerns a 30W AC adapter for portable equipment. The application was actually realised and some experimental results are here presented.
1. Design Specifications:
- Mains voltage range: VACmin = 88 Vac, VACmax = 264 Vac
- Minimum mains frequency: f L = 50 Hz
- DC Output Voltage: Vout = 15 V
- Maximum output current: Iout = 2A
- Maximum 2fL output ripple: ∆Vo = 1V peak-to-peak
2. Pre-design Choices:
- Minimum switching frequency: fswmin = 25 kHz
- Reflected voltage: VR = 100V
- Leakage inductance overvoltage: ∆V =70V
- Expected efficiency: η = 85%
3. Preliminary Calculations:
- Minimum Input Peak Voltage: VPKmin = VACmin ⋅ √
2 = 88 ⋅ √
2 −4 = 120V
(4V total drop on RDS(on), Rs, ...)
- Maximum Input Peak Voltage: VPKmin = VACmin ⋅ √
2 = 264 ⋅ √
2 = 373V
- Maximum Output Power: Pout = Vout ⋅ Iout = 15 ⋅ 2 = 30W
Pout
30
⋅ 100 =
⋅ 100 = 35.3W
85
η
VPKmin 120
- Peak-to-reflected Voltage Ratio: Kv =
=
= 1.2
VR
100
- Maximum Input Power: Pin =
- Characteristic functions value: F1(1.2)=0.343; F2(1.2)=0.254; F3(1.2)=0.209; F5(1.2)=0.108
4. Operating Conditions:
- Peak Primary Current: IPKp =
2 ⋅ Pin
2 ⋅ 35.3
=
= 2.32A
VPKmin ⋅ F2(Kv) 120 ⋅ 0.254
- RMS Primary Current: IRMSp = IPKp ⋅
- Peak Secondary current: IPKs =
F2(Kv)
0.254 0.675A
√

= 2.32 ⋅ √
=
3
3
2 ⋅ Iout
2⋅2
=
= 13.1A
Kv ⋅ F2(Kv) 1.2 ⋅ 0.254
- RMS Secondary Current: IRMSs = IPKs ⋅
5. Transformer:
- Primary inductance: Lp =
F3(Kv)
0.209 = 3.79A

√

Kv ⋅
= 13.1 ⋅ √
1.2 ⋅
3
3
VPKmin
120
=
= 940µH
(1 + Kv) ⋅ fswmin ⋅ IPKp (1 + 1.2) ⋅ 25 ⋅ 103 ⋅ 2.32
- Primary-to-secondary turns ratio: n =
VR
100
=
= 6.41
(Vout + Vf) 15 + 0.6
From diagram of fig. 11, by interpolation, the minimum AP required is about 0.5 cm4. An
ETD29 core (AP = 0.684 cm4), 3C85 grade is selected. From the relevant datasheet, with 1
16/20
AN1059 APPLICATION NOTE
mm air gap 90 primary turns will result in about 970µH primary inductance. 14 secondary
turns give a 6.43 turns ratio, very close to the target. Estimating the thermal resistance of the
ETD29 equal to 26°C/W, the maximum power dissipation (supposed to be on copper only) for
30°C hot-spot temperature rise will be 1.15W (half will be allocated to the primary and half to
the secondary). This requires the resistance of the primary to be no more than 1.26 Ω and the
secondary’s no more than 40 mΩ. An AWG27 (∅ ≈ 0.4 mm) wire for the primary and a strand
of 5xAWG27 for the secondary will meet the requirement.The primary winding will be split in
two halves of 45 turns each, series connected, and the secondary will be sandwiched in between to reduce leakage inductance.
6. MOSFET selection
- Maximum Drain Voltage:VDSmax = VPKmax + VR + ∆V = 373 + 100 + 70 = 543V
There is margin to select a 600 V device. This will minimise gate drive and capacitive losses.
Assuming that the MOSFET will dissipate 5% of the input power, that losses are due to conduction only, and that RDS(on) doubles at working temperature, the RDS(on) at 25°C should be
about 2Ω. An STP4NA60 (RDS(on) = 2.2 Ω max.) is selected.
7. Catch diode selection
VPKmax
373
- Maximum reverse voltage: VREVmax =
+ Vout =
+ 15 = 73.2V
n
6.41
A 100V Schottky diode will minimise conduction losses. As to its current rating, a tentative
value can be 40% of the peak current: IF = 0.4 ⋅ IPKs = 0.4 ⋅ 13.1 = 5.2A. A suitable device
could be the STPS8H100D. From the relevant datasheet, the power dissipation is estimated
as: Pdiode = 0.48 ⋅ Iout + 0.013 ⋅ I2RMSs = 0.55 ⋅ 2 + 0.013 ⋅ 3.792 = 1.15W, which is acceptable.
8. Output Capacitor Selection
The minimum capacitance value that meets the specification on the 100/120 Hz ripple is:
H2(Kv) Iout
0.108 ⋅ 2
1
Coutmin =
⋅
⋅
=
= 5417µF
π ⋅ fL F2(kv) ∆Vo 3.14 ⋅ 50 ⋅ 0.254 ⋅ 1
Three 2200µF electrolytic capacitors will have an ESR low enough to consider the high frequency ripple negligible as well as sufficient AC current capability.
9. Clamp network
With a proper construction technique, the leakage inductance can be reduced to as much as
2% of the primary inductance, that is 20µH in the present case. A transil clamp is selected.
The clamp voltage will be VCL = VR + ∆V = 100 + 70 = 170V. The steady-state power dissipation is estimated to be about 2W. A P6KE170A transil is selected. The blocking diode is an
STTA106.
10. Multiplier bias and sense resistor selection
Assuming a peak value of 2.4V (@VAC = 264V) on the multiplier input (MULT, pin 3), the peak
value at minimum line voltage will be VMULTpkmin = 2.4 ⋅ 88/264 = 0.8V which, multiplied by the
maximum slope of the multiplier, 1.65, gives 1.32V peak voltage on current sense (CS, pin 4).
Since the linearity limit (1.6V) is not exceeded, this is acceptable. The divider ratio will then be
2.4/(√
2 ⋅ 264) = 6.43 ⋅ 10-3. Considering 120µA current for the divider, the lower resistor will
be 20kΩ, and the upper one 3MΩ.The sense resistor will not exceed 1.32/2.32 = 0.57Ω (0.5Ω
is selected), while its power rating will be 0.5 ⋅ I2RMSp = 0.5 ⋅ 0.6752 = 228mW
11. Feedback and Control Loop
The selected optocoupler is a 4N35 from Toshiba. 1 mA quiescent collector current is selected. From opto’s datasheet, with 1mA collector current, the diode current can be between 1
and 2 mA approximately (0.5 < CTR < 1).
17/20
AN1059 APPLICATION NOTE
An emitter resistor of 2.4kΩ, will give the desired collector current, thus the bias resistor
15 − 1.2 − 2.5
should satisfy the inequality R4 <
⋅ 0.5 ⋅ 2.4 = 5.4kΩ.
2.5
Select R4 = 5.1kΩ. As to the output divider, with R2 = 2.4kΩ, the upper resistor will be R1 =
12kΩ. Select R3 = 2.2 kΩ. With C1 = 1µF the zero will be at about 70 Hz, which is acceptable.
1⋅1
2.4
R6 should be so that R6 > 2.4 ⋅ 103 +
⋅
= 14kΩ. Select R6 = 20 kΩ. By selecting
5.1 40 ⋅ 10−6
R7 = 39 kΩ, R7 = 9.1 kΩ and C2 = 220 nF, the open-loop crossover frequency and phase margin will be 50 Hz and 42° respectively.
The complete electrical schematic of this application is illustrated in fig.16, fig. 17 presents some results
of its bench evaluation and fig. 18 shows some significant waveforms.
Figure 16. 30W High-PF Flyback with the L6561: electrical schematic
2A fuse
DF06M
STPS8H100D
88 to 264
Vac
15 Vdc / 2A
3x2200 µF
P6KE170A
N1
N2
470 nF
3 MΩ
470 kΩ
STTA106
1N4148
47 µF
5.1 kΩ 12 kΩ
4.7 nF
N3
2
9.1 kΩ
47 kΩ
8
3
L6561
7
2.2 nF
2.2 µF
1 µF
2.2 kΩ
5
39 kΩ
220 nF
20 kΩ
4N35
1
1N4148
10 Ω
TL431
DISABLE
6
4
2.4 kΩ
STP4NA60
1N4148
20 kΩ
4N35
TRANSFORMER SPECS:
Core: ETD29, 3C85 grade or equivalent
≈1 mm airgap for 1 mH primary inductance.
N1: 2 series windings, 45 T each, AWG27 (∅ 0.41 mm)
N2: 14 T,5xAWG27
N3: 14T, AWG32 (∅ 0.24 mm).
0.5 Ω
2.4 kΩ
Figure 17. 30W High-PF Flyback with the L6561: evaluation results
Input Power [W]
Power Factor
Efficiency [%]
100
1.4
1
Iout = 2A
Iout = 1A
Iout = 1A
90
0.9
Pout = 500 mW
1.3
Iout = 2A
Iout = 0.5A
80
Iout = 0.5A
1.2
0.8
Iout = 0.1A
70
Iout = 0.1A
60
50
0.6
120
180
Mains Voltage [Vac]
18/20
0.7
240
1.1
1
0.9
120
180
Mains Voltage [Vac]
240
120
180
Mains Voltage [Vac]
240
AN1059 APPLICATION NOTE
Figure 18. 30W High-PF Flyback with the L6561: principal waveforms
Vin = 90 VAC, Pout = 30W
Left : Peak primary current envelope
Right, upper trace: Mains current
Right, lower trace: Low-frequency primary current
References
[1] "L6561, Enhanced Transition Mode Power Factor Corrector", (AN966)
[2] "Flyback Converters with the L6561 PFC Controller", (AN1060)
19/20
AN1059 APPLICATION NOTE
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia – Belgium - Brazil - Canada - China – Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
20/20