DS5028B 00

®
RT5028B
PMIC for Industrial Application
General Description
Features
The RT5028B is a highly-integrated low-power highperformance analog SOC with PMIC in one single chip
designed for Industrial applications.

Input Voltage Operating Range is 3.3V to 5.5V

Step-Down Regulator : VIN Range is 3.3V to 5.5V
 Max Current 2.5A/2.5A/1.6A/2A
 Programmable Frequency from 500kHz to 2MHz
2
 I C Programmable Output Level
2
 I C Programmable Operation Mode (Force PWM
or Auto PSM/PWM)
2
 I C Programmable Output Discharge Mode
(Discharge or Flatting)
Linear Regulators : VIN Range is 2.5V to 5.5V
 Max Current 0.3A
2
 I C Programmable Output Level
Embedded 32Bytes MTP for Factory Tuning
 External MTP Pin for Write Protection
Sequence can be Controlled by I2C or Each EN Pins
Defined by MASK_GPIO Pin
OT/UVP/VIN LV/POWRON Press Time Interrupt
(IRQ).
2
 I C Control Interface : Support Fast Mode up to
400kb/s
The RT5028B includes four synchronous step-down DC/
DC converters and eight LDOs for system power.
The RT5028B also embeds one EEPROM (MTP) for
setting sequence and timing etc.
Additionally, the RT5028B PMIC also includes one IRQ
report.

Applications


Industrial

Ordering Information
RT5028B

Package Type
QW : WQFN-56L 7x7 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :

RoHS compliant and compatible with the current require-

Suitable for use in SnPb or Pb-free soldering processes.
ments of IPC/JEDEC J-STD-020.
Simplified Application Circuit
VIN
RT5028B
VOUTLx
VDDP
SCL
SDA
IRQ
VINL456
RESET
VINL78
PWRHOLD
PWRON
LXBx
REBOOT
VOUTBxS
MTP
VINBx
MASK_GPIO
ENBx
ENLx
SADDR
AGND
VINL123
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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1
RT5028B
Marking Information
Pin Configurations
RT5028BGQW : Product Number
(TOP VIEW)
AGND
ENL3
ENL2
ENL1
VIN
VDDP
VOUTB1S
ENB1
LXB1
LXB1
VINB1
VINB1
VINB2
VINB2
RT5028B
GQW
YMDNN
YMDNN : Date Code
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VOUTL1
VINL123
VOUTL2
VOUTL3
VOUTL6
VOUTL5
VINL456
VOUTL4
VOUTL7
VINL78
VOUTL8
ENL4
ENL5
ENL6
1
42
2
41
3
40
4
39
5
38
37
6
7
36
AGND
8
35
34
9
33
10
57
11
32
31
12
13
30
14
29
LXB2
LXB2
ENB2
VOUTB2S
VINB3
VINB3
LXB3
LXB3
AGND
VOUTB3S
VINB4
LXB4
ENB3
VOUTB4S
SCL
SDA
ENL7
ENL8
IRQ
RESET
AGND
PWRON
REBOOT
MTP
MASK_GPIO
PWRHOLD
SADDR
ENB4
15 16 17 18 19 20 21 22 23 24 25 26 27 28
WQFN-56L 7x7
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VOUTL1
Output Voltage Regulation Node for LDO1.
2
VINL123
Input Power for LDO1, LDO2 and LDO3.
3
VOUTL2
Output Voltage Regulation Node for LDO2.
4
VOUTL3
Output Voltage Regulation Node for LDO3.
5
VOUTL6
Output Voltage Regulation Node for LDO6.
6
VOUTL5
Output Voltage Regulation Node for LDO5.
7
VINL456
Input Power for LDO4, LDO5 and LDO6.
8
VOUTL4
Output Voltage Regulation Node for LDO4.
9
VOUTL7
Output Voltage Regulation Node for LDO7.
10
VINL78
Input Power for LDO7 and LDO8.
11
VOUTL8
Output Voltage Regulation Node for LDO8.
12
ENL4
Enable Control Input for LDO4. Connect a 100k pull-low resistor.
13
ENL5
Enable Control Input for LDO5. Connect a 100k pull-low resistor.
14
ENL6
Enable Control Input for LDO6. Connect a 100k pull-low resistor.
15
SCL
Clock Input for I2C. Open-drain output, connect a 10k pull-up resistor.
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RT5028B
Pin No.
Pin Name
Pin Function
2
16
SDA
Data Input for I C. Open-drain output, connect a 10k pull-up resistor.
17
ENL7
Enable Control Input for LDO7. Connect a 100k pull-low resistor.
18
ENL8
Enable Control Input for LDO8. Connect a 100k pull-low resistor.
19
IRQ
Open-Drain IRQ Output Node.
20
RESET
Reset Output.
21, 34, 56, 57
AGND
(Exposed Pad)
Analog Ground. The exposed pad must be soldered to a large PCB and
connected to AGND for maximum power dissipation.
22
PWRON
Manual Power On. Connect a 100k pull-up resistor.
23
REBOOT
System Power Reboot. Connect a 100k pull-low resistor.
24
MTP
MTP Write Protection Pin. Connect a 100k pull-low resistor, logic low is
inhibited and logic high is permit to write.
25
MASK_GPIO
Select I2C or use EN pin for Bucks and LDOs. Connect a 100k pull-low resistor.
As MASK_GPIO is high, ignore all EN pins.
As MASK_GPIO is low, EN pins and I2C both can control. EN pins priority is
higher than I2C.
26
PWRHOLD
Power Hold Input. Connect a 100k pull-low resistor.
27
SADDR
I2C Slave Address. Connect a 100k pull-low resistor.
28
ENB4
Enable Control Input for Buck4. Connect a 100k pull-low resistor.
29
VOUTB4S
Output Voltage Regulation Node for Buck4.
30
ENB3
Enable Control Input for Buck3. Connect a 100k pull-low resistor.
31
LXB4
Internal Switch Node to Output Inductor Connection for Buck4.
32
VINB4
Input Power for Buck4.
33
VOUTB3S
Output Voltage Regulation Node for Buck3.
35, 36
LXB3
Internal Switch Node to Output Inductor Connection for Buck3.
37, 38
VINB3
Input Power for Buck3.
39
VOUTB2S
Output Voltage Regulation Node for Buck2.
40
ENB2
Enable Control Input for Buck2. Connect a 100k pull-low resistor.
41, 42
LXB2
Internal Switch Node to Output Inductor Connection for Buck2.
43, 44
VINB2
Input Power for Buck2.
45, 46
VINB1
Input Power for Buck1.
47, 48
LXB1
Internal Switch Node to Output Inductor Connection for Buck1.
49
ENB1
Enable Control Input for Buck1. Connect a 100k pull-low resistor.
50
VOUTB1S
Output Voltage Regulation Node for Buck1
51
VDDP
Internal Bias Regulator Voltage. External load on this pin is not allowed.
52
VIN
Input Power for Analog Base.
53
ENL1
Enable Control Input for LDO1. Connect a 100k pull-low resistor.
54
ENL2
Enable Control Input for LDO2. Connect a 100k pull-low resistor.
55
ENL3
Enable Control Input for LDO3. Connect a 100k pull-low resistor.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5028B-00 April 2016
is a registered trademark of Richtek Technology Corporation.
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RT5028B
Functional Block Diagram
VOUTL1
VINL123
LDO1
300mA
VOUTL2
LDO2
300mA
VOUTL3
LDO3
300mA
VOUTL4
VINL456
LDO4
300mA
VOUTL5
LDO5
300mA
VIN
VDDP
Analog
Base
VINB1
Buck1
2.4A
LXB1
GND
VOUTB1S
VINB2
VOUTL6
LDO6
300mA
VOUTL7
VINL78
LDO7
300mA
VOUTL8
LDO8
300mA
Central
Controller
2
I C
Programmable
Buck2
2A
LXB2
GND
VOUTB2S
SDA
VINB3
SCL
IRQ
Buck3
1.6A
RESET
LXB3
PWRHOLD
REBOOT
MTP
GND
State
Machine
MASK_GPIO
VOUTB3S
VINB4
SADDR
PWRON
ENB1 to ENB4
Buck4
2A
LXB4
ENL1 to ENL8
AGND
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GND
VOUTB4S
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DS5028B-00 April 2016
RT5028B
Operation
The RT5028B is a highly-integrated solution for industrial
system including 4-CH step-down DC/DC converters and
8-CH LDOs. The RT5028B application mechanism will be
introduced in later sections.
The power-on and power-off sequences can be controlled
by I2C or each EN pin and detected in MASK_GPIO pin.
When the MASK_GPIO pin is at Hi level, the PMIC follows
the power-on sequence to turn on channels. When the
MASK_GPIO pin is at Lo level, the channels of PMIC will
be controlled by the EN pin.
Synchronous Step-Down DC/DC Converter
Four current mode synchronous step-down DC/DC
converters operate with internal power MOSFETs, FB
resistors and compensation network. These channels are
suitable for core power in industrial system. They can be
operated at 100% maximum duty cycle to extend battery
operating voltage range. When the input voltage is close
to the output voltage, the converter enters low dropout
mode with low output ripple. The operating frequency of
step-down converter is adjustable from 500kHz to 2MHz
and is controlled by I2C. Besides, the I2C interface also
can be used to select different operation modes, On/Off
Sequence, programmable the output voltage, RAMP
control and discharge function. To enable AUTO Mode, it
is used to improve the efficiency at light load. If the AUTO
Mode is disabled, the converter operates in force PWM
mode with fixed switching frequency.
Over-Temperature Protection
An Over-Temperature Protection (OTP) is contained in the
device. The protection is triggered to force the device
shutdown for protecting itself when the junction
temperature exceeds 165°C typically. Once the junction
temperature drops below the hysteresis 10°C typically,
the device must be re-send PWRON to start system.
Output Under-Voltage Protection
The output under-voltage protection is implemented in order
to prevent operation at low output voltage conditions.
When the step-down DC/DC converters output voltage is
lower than 1/2 x (VOUT), the UVP event triggers and PMIC
turns off immediately.
Linear Regulator
Eight generic low voltage LDOs for multiple purpose power.
The LDOs are stable over the entire operating load range
with the use of external ceramic capacitors. The LDOs
also have I2C programmable power on/off sequence and
discharge function. The output voltage is adjustable by
the I2C interface in the range of 1.6V to 3.6V.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5028B-00 April 2016
is a registered trademark of Richtek Technology Corporation.
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5
RT5028B
Absolute Maximum Ratings










(Note 1)
Analog Base Input Voltage, VIN ---------------------------------------------------------------------------------------PMIC Input Voltage, VINL123/456/78, VINB1/2/3/4 ---------------------------------------------------------------PMIC Output Voltage, VOUTLx, VOUTBxS, LXBx ----------------------------------------------------------------PMIC related Other Pins -------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WQFN-56L 7x7 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN-56L 7x7, θJA -------------------------------------------------------------------------------------------------------WQFN-56L 7x7, θJC ------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions


−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
3.7W
27°C/W
7°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(Note 5)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
3.3
--
5.5
V
VIN = 5V, LDOs, Bucks are ON with No Load. 300
450
600
A
VIN = 5V, LDOs, Bucks are OFF.
SCL = SDA = 0V
5
20
40
A
Temperature 1
--
100
--
Temperature 2
--
125
--
--
165
--
C
--
10
--
C
70
115
160
k
As f SW > 1MHz, 3.3V  VIN  5.5V.
If f SW  1MHz, VIN  4V.
Operation Voltage of VIN
PMIC
Quiescent Current
IIN
Warning for Die
Temperature
OTW
Over-Temperature
Protection
OTP
OTP and Warning
Hysteresis
Input Pull-low 100k Resistor RLow
VIN = 5V
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C
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RT5028B
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
3.3
--
5.5
V
Buck1 I C Programmable per step 25mV
0.7
--
1.8
Buck2 I2C Programmable per step 25mV
0.7
--
1.8
Buck3 I C Programmable per step 50mV
0.7
--
3.6
Buck4 I2C Programmable per step 50mV
0.7
--
3.6
Buck1 to Buck4
Input Voltage
VINB
2
Output Voltage
VOUTB
2
V
Consumption Current
IVINB
AUTO Mode IOUT = 0mA, Each Buck
10
20
40
A
Output Voltage Accuracy
VOUTAcc
3.1V < VIN < 5.5V, 1mA < IOUT < IMAX
3
--
3
%
Switching Frequency
f SW
I2C Programmable
0.43
--
2
MHz
1MHz  f SW
10
--
10
f SW  1MHz
20
--
20
Buck1
3.1
4.4
5.8
Buck2
3.1
4.4
5.8
Buck3
2.6
3.7
4.8
Buck4
2.8
4.1
5.3
VOUTB1S to VOUTB4S < 0.66 x (VOUT
Target)
56
66
76
Buck1
2.5
--
--
Buck2
2.5
--
--
Buck3
1.6
--
--
Buck4
2.0
--
--
Switching Frequency
Accuracy
Peak Current Limit
Under-Voltage Protection
Maximum Output Current
OCP
UVP
IMAX
%
A
%
A
High-Side On-Resistance
Rpon
VIN = 3.7V
50
150
250
m
Low-Side On-Resistance
Rnon
VIN = 3.7V
40
110
160
m
2.5
--
5.5
V
LDO1 to LDO8
Input Voltage for
VINL123/456/78
VINL
Output Voltage LDO123/78
VOUTL
3.1V  VIN  5.5V, 50A  IOUT  IMAX
3
--
3
%
Output Voltage LDO456
VOUTL
3.1V  VIN  5.5V, 50A  IOUT  IMAX
3
--
3
%
Output Current
IOUT
300
--
--
mA
Output Short Current
Isht
330
450
600
mA
Voltage Difference
VIN 
VOUT
0.05
0.1
0.3
VIN > 2.5V
0.05
0.11
0.5
Supply Current
ISS
IOUT = 0mA
10
35
60
A
Shutdown Current
IOFF
0
1
2
A
VIN > 3.1V
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5028B-00 April 2016
VIN = VSET, IOUT = IOUTMAX
V
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7
RT5028B
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VOL
--
--
0.4
V
High-Level
VIH
1.5
--
--
Low-Level
VIL
--
--
0.4
Control Input Pin Electrical Characteristics
Voltage Output Low
Input Voltage
V
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Limits apply to the recommended operating temperature range of −40°C to 85°C, unless otherwise noted. Minimum
and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TA = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply : VIN = 3.3V to 5.5V
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RT5028B
Typical Application Circuit
1µF
1µF
1µF
1µF
1µF
52 VIN
RT5028B
51 VDDP
2 VINL123
7 VINL456
10 VINL78
VOUTL1
VOUTL2
VOUTL3
1
3
4
1µF
1µF
1µF
1µF
VOUTL4
8
1µF
VOUTL5 6
1µF
45, 46
VINB1
VOUTL6 5
10µF
2.2µH
47, 48
22µF
50
43, 44
VOUTL7 9
LXB1
VOUTB1S
VOUTL8 11
VINB2
SCL
10µF
SDA
2.2µH
22µF
41, 42
39
37, 38
LXB2
VOUTB2S
VINB3
MTP
MASK_GPIO
35, 36
22µF
33
32
SADDR
LXB3
VOUTB3S
PWRON
VIN
1µF
SADDR
MASK_GPIOMTP
15
16
IRQ 19
20
RESET
26
PWRHOLD
23
REBOOT
10µF
2.2µH
1µF
As SADDR connect to AGND
slave address
=0111111
As SADDR connect to VIN
slave address
=0110111
24
25
27
As MASK_GPIO connect to AGND
EN pins can control.
As MASK_GPIO connect to VIN
Ignore all EN pins.
22
VINB4
10µF
2.2µH
31
22µF
29
AGND
AP
ENL1 to ENL8
ENB1 to ENB4
LXB4
VOUTB4S
AGND 21, 34, 56,
57 (Exposed Pad)
As MTP connect to AGND
Inhibit to write MTP.
As MTP connect to VIN
Permit to write MTP.
Suggested Components for Typical Application Circuit
Description
P/N
Manufacture
Inductor for Buck-2.2H
LQH43PB2R2M26L
Murata
CIN for Buck-10F
C1206X7R1E516DT
Murata
COUT for Buck-22F
C1206X7R22E416DT
Murata
CIN/COUT for LDO-1F
C0603X7R1E216DT
Murata
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RT5028B
Typical Operating Characteristics
CH1 Buck Efficiency vs. Output Current
CH2 Buck Efficiency vs. Output Current
100
100
90
90
80
VIN
VIN
VIN
VIN
VIN
VIN
70
60
50
40
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
Efficiency (%)
Efficiency (%)
80
30
20
VIN
VIN
VIN
VIN
VIN
VIN
70
60
50
40
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
30
20
10
10
VOUT = 1.35V, L = 2.2μH, COUT = 10μF
0
VOUT = 1.5V, L = 2.2μH, COUT = 10μF
0
10
100
1000
10000
10
100
Output Current (mA)
CH3 Buck Efficiency vs. Output Current
100
90
90
VIN
VIN
VIN
VIN
VIN
VIN
80
70
60
50
40
3.3V
3.6V
3.9V
4.2V
5V
5.5V
Efficiency (%)
Efficiency (%)
80
=
=
=
=
=
=
30
20
70
60
50
=
=
=
=
=
=
3.6V
3.9V
4.2V
4.5V
5V
5.5V
40
30
20
10
10
VOUT = 1.2V, L = 2.2μH, COUT = 10μF
0
VOUT = 3.3V, L = 2.2μH, COUT = 10μF
0
10
100
1000
10000
10
Output Current (mA)
100
1000
10000
Output Current (mA)
CH2 Buck Output Voltage vs. Output Current
CH1 Buck Output Voltage vs. Output Current
1.39
1.53
1.37
1.36
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
1.52
Output Voltage (V)
VIN
VIN
VIN
VIN
VIN
VIN
1.38
Output Voltage (V)
10000
CH4 Buck Efficiency vs. Output Current
100
VIN
VIN
VIN
VIN
VIN
VIN
1000
Output Current (mA)
1.35
1.34
VIN
VIN
VIN
VIN
VIN
VIN
1.51
1.50
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
1.49
1.48
1.33
L = 2.2μH, COUT = 10μF
1.32
L = 2.2μH, COUT = 10μF
1.47
0
300
600
900
1200 1500 1800 2100 2400
Output Current (mA)
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0
500
1000
1500
2000
Output Current (A)
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DS5028B-00 April 2016
RT5028B
CH4 Buck Output Voltage vs. Output Current
CH3 Buck Output Voltage vs. Output Current
3.38
1.25
VIN
VIN
VIN
VIN
VIN
VIN
3.33
1.23
VIN
VIN
VIN
VIN
VIN
VIN
1.22
1.21
1.20
=
=
=
=
=
=
Output Voltage (V)
Output Voltage (V)
1.24
3.3V
3.6V
3.9V
4.2V
5V
5.5V
1.19
3.28
=
=
=
=
=
=
3.6V
3.9V
4.2V
4.5V
5V
5.5V
3.23
3.18
3.13
1.18
L = 2.2μH, COUT = 10μF
L = 2.2μH, COUT = 10μF
3.08
1.17
0
200
400
600
800
0
1000 1200 1400 1600
500
Output Current (mA)
1000
1500
2000
Output Current (mA)
CH1 Buck Output Voltage vs. Input Voltage
CH2 Buck Output Voltage vs. Input Voltage
1.40
1.55
1.39
1.53
Output Voltage (V)
Output Voltage (V)
1.38
1.37
1.36
1.35
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
IOUT = 2400mA
1.34
1.33
1.32
1.31
1.51
1.49
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
1.47
L = 2.2μH, COUT = 10μF
L = 2.2μH, COUT = 10μF
1.30
1.45
3.3
3.8
4.3
4.8
5.3
3.3
5.8
3.8
Input Voltage (V)
4.3
4.8
5.3
5.8
Input Voltage (V)
CH4 Buck Output Voltage vs. Input Voltage
CH3 Buck Output Voltage vs. Input Voltage
3.80
1.24
1.23
3.60
Output Voltage (V)
Output Voltage (V)
1.22
1.21
1.20
1.19
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1600mA
1.18
1.17
3.40
3.20
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
3.00
2.80
1.16
2.60
1.15
L = 2.2μH, COUT = 10μF
L = 2.2μH, COUT = 10μF
2.40
1.14
3.3
3.8
4.3
4.8
5.3
Input Voltage (V)
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5028B-00 April 2016
5.8
3.3
3.8
4.3
4.8
5.3
5.8
Input Voltage (V)
is a registered trademark of Richtek Technology Corporation.
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11
RT5028B
LDO2 Output Voltage vs. Output Current
LDO5 Output Voltage vs. Output Current
3.32
1.790
3.30
VIN
VIN
VIN
VIN
VIN
VIN
1.780
1.775
1.770
=
=
=
=
=
=
2.5V
3V
3.6V
4.2V
5V
5.5V
Output Voltage (V)
Output Voltage (V)
1.785
1.765
1.760
3.28
VIN
VIN
VIN
VIN
VIN
VIN
3.26
3.24
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
3.22
1.755
COUT = 1μF
COUT = 1μF
3.20
1.750
0
50
100
150
200
250
0
300
50
2.50
1.78
Output Voltage (V)
Output Voltage (V)
1.78
2.48
2.44
2.42
=
=
=
=
=
=
200
250
300
LDO2 Output Voltage vs. Input Voltage
LDO7 Output Voltage vs. Output Current
2.52
VIN
VIN
VIN
VIN
VIN
VIN
150
Output Current (mA)
Output Current (mA)
2.46
100
2.5V
3V
3.6V
4.2V
5V
5.5V
IOUT = 0mA
1.77
IOUT = 100mA
1.77
IOUT = 200mA
1.76
IOUT = 300mA
1.76
COUT = 1μF
COUT = 1μF
1.75
2.40
0
50
100
150
200
250
2.5
300
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Output Current (mA)
LDO5 Output Voltage vs. Input Voltage
LDO7 Output Voltage vs. Input Voltage
2.50
3.50
3.45
2.48
Output Voltage (V)
Output Voltage (V)
3.40
3.35
3.30
3.25
IOUT = 0mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
3.20
3.15
2.46
IOUT = 0mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
2.44
2.42
3.10
3.05
COUT = 1μF
3.00
COUT = 1μF
2.40
3.3
3.8
4.3
4.8
5.3
Input Voltage (V)
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12
5.8
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
Application Information
The RT5028B is a highly-integrated solution for industrial
system including PMIC and memory system. The
RT5028B application mechanism and I2C compatible
interface are introduced in later sections. The system's
slave address is 0110111 (As SADDR = high) or
0111111(As SADDR = low).
PMIC - Power management system provides 8 low dropout
linear regulator and 4 high efficiency synchronous stepdown DC/DC converters. Power-On and Power-Off
sequences are control by PWRON and RESET input pins.
Parameter
Symbol
Detail time sequence control is described in Power ON/
OFF diagram. The I2C interface can program individual
regulator output voltage as well as on/off control and
voltage setting.
I2C Interface Timing Diagram
The RT5028B acts as an I2C -bus slave. The I2C-bus master
configures the settings for all function blocks by sending
command bytes to the RT5028B via the 2-wire I2C-bus.
The I2C timing diagrams are list in the following.
Test Conditions
Min
Typ
Max
Unit
SDA, SCLK Input High Level
Threshold
0.7 x
VDDA
--
--
V
SDA, SCLK Input Low Level
Threshold
--
--
0.3 x
VDDA
V
--
--
400
kHz
2
I C Interface Electrical Characteristics
SCLK Clock Rate
f SCL
Hold Time (Repeated) START
Condition.
After this period, the first clock
pulse is generated
tHD;STA
0.6
--
--
s
LOW Period of the SCL Clock
tLOW
1.3
--
--
s
HIGH Period of the SCL Clock
tHIGH
0.6
--
--
s
Set-Up Time for a Repeated
START Condition
tSU;STA
0.6
--
--
s
Data Hold Time
tHD;DAT
0
--
0.9
s
Data Set-Up Time
tSU;DAT
100
--
--
ns
Set-Up Time for STOP
Condition
tSU;STO
0.6
--
Bus Free Time Between a
STOP and START Condition
tBUF
1.3
--
--
s
Rise Time of Both SDA and
SCL Signals
tR
20
--
300
ns
Fall Time of Both SDA and
SCL Signals
tF
20
--
300
ns
2
--
--
mA
SDA and SCL Output Low Sink
IOL
Current
SDA or SCL voltage = 0.4V
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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s
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13
RT5028B
Read Function
Reading One Indexed Byte of Data from RT (With 1-Byte)
Acknowledge from RT
S
Slave Address
Acknowledge from RT
0
A
Acknowledge from RT
Register Address
R/W
A Sr
Acknowledge from Master
Slave Address
Repeated Start
1
A
Data Byte
A
P
A
P
R/W
1Byte
Reading n Indexed Words of Data from RT (With N-Byte)
Acknowledge from RT
S
Slave Address
Acknowledge from RT
0
A
Register Address
R/W
A Sr
Slave Address
Repeated Start
Acknowledge from Master
Data Byte
Acknowledge from RT
Data Byte
1st Byte
A
R/W
Acknowledge from Master
A
1
Acknowledge from Master
A
……
2nd Byte
Data Byte
Acknowledge from Master
A
(n-1)th Byte
Data Byte
nth Byte
Write Function
Writing One Byte of Data to RT (With 1-Byte)
Acknowledge from RT
S
Slave Address
Acknowledge from RT
0
A
Register Address
Acknowledge from RT
A
Data Byte
A
P
R/W
1Byte
Writing n Bytes of Data to RT (With N-Byte)
Acknowledge from RT
S
Slave Address
Acknowledge from RT
0
A
Register Address
Acknowledge from RT
A
Data Byte
Acknowledge from RT
A
Data Byte
A
…
A
P
R/W
1st Byte
2nd Byte
Acknowledge from RT
Acknowledge from RT
Data Byte
(n-1)th Byte
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A
Data Byte
nth Byte
is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
PMIC
Power Channels Control Methodology
When VIN power Good or PWRON event occurs, the PMIC
will follow the power on sequence to turn on channels.
During normal operation, users can use the REBOOT pin
to restart PMIC again. Another PWROFF event, OTP or
UVP occurs, PMIC will execute the power off. In the
RT5028B PMIC, the UVP event will be set out when the
Buck1 to Buck4s' output voltage is lower than 1/2 x (VOUT).
Power Off
Edge
trigger
Edge
trigger
No
No
VIN Power
Good
PWRON
Check
Yes
1
2
(Internal I C)
Yes
Mask_GPIO
0
(External Enable Control)
No
External EN
Check
Power On
Sequence
Yes
Yes
Yes
REBOOT
Check
REBOOT
Check
Normal Operation
No
No
No
OTP Check
Yes
UVP Check
Yes
PWROFF
Check
No
Yes
Power Off
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15
RT5028B
PMIC - POWER ON/OFF Setting
The circuit setting for communication between RT5028B
and AP is showed as below.
VIN
SADDR
MASK_GPIOMTP
SCL
SDA
AGND
IRQ
RESET
PWRHOLD
State
Machine
REBOOT
MTP
MASK_GPIO
SADDR
PWRON
ENL1 to ENL8
ENB1 to ENB4
AP
As SADDR connect ot AGND
slave address
=0111111
As SADDR connect ot VIN
slave address
=0110111
As MASK_GPIO connect ot
AGND
EN pins can control.
As MASK_GPIO connect ot VIN
Ignore all EN pins.
As MTP connect ot AGND
Inhibit to write MTP.
As MTP connect ot VIN
Permit to write MTP.
Power Hold Function
When the “PWRHOLD” signal does not come during
THOLD time, the RT5028B will do shutdown sequence.
If users want to disable power hold function, set
“DisTHOLD” bit in I2C register 10 bit[0] to disable this
function. In the timing diagram below, the “THOLD” and
“RESET_DLY” can be set by MTP program.
START_TIME
PWRON
BUCK1
……
BUCK4
LDO1
……
LDO8
RESET_DLY
RESET
PWRHOLD
THOLD
Always Low
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Turn off sequence :
First-on-last-Off
is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
When AP sends the “PWRHOLD” signal during THOLD time, the RT5028B will keep power-on.
START_TIME
PWRON
BUCK1
……
BUCK4
LDO1
……
LDO8
RESET_DLY
THOLD
RESET
Low to High signal from AP.
PWRHOLD
Timing Based ON/OFF Sequence
START_TIME
Normal power on
Normal power off
SHDN_PRESS
PWRON
TSS
BUCK1
TSS
BUCK2
……
BUCK4
TSS
TSS
LDO1
...
……
LDO8
RESET_DLY
RESET
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17
RT5028B
Level Based ON/OFF Sequence
Normal power on
START_TIME
SHDN_PRESS
Normal power off
PWRON
8ms
>80 %
BUCK1
>80 %
BUCK2
……
>80 %
BUCK4
8ms
>80 %
LDO1
……
LDO8
RESET_DLY
RESET
Abnormal OFF
START_TIME
Normal power on
IRQ Even Occur
Abnormal power off
PWRON
IRQ
SHDN_DLYTIME
BUCK1
TSS
BUCK2
……
BUCK4
TSS
LDO1
……
LDO8
RESET_DLY
RESET
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is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
PMU On/Off Sequence Setting
In the RT5028B, users can set the power on/off sequence and output voltage by I2C register 0x01 to 0x04 for Buck
output voltage, 0x07 to 0x0E for LDO output voltage and 0x2C to 0X32 for startup sequence setting.
In the table below, users must set one by one (continues number) and missing code is not allowed.
If users miss sequence code, the RT5028B will wait for next channel and the IC will be hold in waiting status.
Buck1
Buck2
Buck3
Buck4
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
LDO8
Output Voltage Setting
Startup Sequence Setting
Buck1Output[5:0]
Buck1_Seq[3:0]
[000000]
[0001]
Buck2Output[5:0]
Buck2_Seq[3:0]
[101100]
[0010]
Buck3Output[5:0]
Buck3_Seq[3:0]
[000000]
[0011]
Buck4Output[5:0]
Buck4_Seq[3:0]
[101100]
[0100]
LDO1OUT[6:0]
LDO1_Seq[3:0]
[0000000]
[0101]
LDO2OUT[6:0]
LDO2_Seq[3:0]
[0101000]
[0110]
LDO3OUT[6:0]
LDO3_Seq[3:0]
[0000000]
[0111]
LDO4OUT[6:0]
LDO4_Seq[3:0]
[0101000]
[1000]
LDO5OUT[6:0]
LDO5_Seq[3:0]
[0000000]
[1001]
LDO6OUT[6:0]
LDO6_Seq[3:0]
[0101000]
[1010]
LDO7OUT[6:0]
LDO7_Seq[3:0]
[0000000]
[1011]
LDO8OUT[6:0]
LDO8_Seq[3:0]
[0101000]
[1100]
Startup Enable Method
(Soft-Start Control)
[10]
Note :
* Output Voltage Setting: fill relative binary code to set the output voltage.
* Startup Sequence Setting :
“0000” denotes no operation (disable).
“0001” denotes first-startup.
“1100 to 1111” denotes last-startup.
If same number, it means startup at the same time.
*Startup Enable Method :
[01] to [11] : each startup enable interval time (1ms, 4ms, 8ms).
[00] : start end voltage (the output voltage's 80%)
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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19
RT5028B
Synchronous Step-Down DC/DC Converter
REBOOT Function
Four current mode synchronous step-down DC/DC
converters operate with internal power MOSFETs and
compensation network. These channels supply the power
core chip of portable system. They can be operated at
100% maximum duty cycle to extend battery operating
voltage range. When the input voltage is close to the output
voltage, the converter enters low dropout mode with low
output ripple. The operating frequency range of step-down
converter is 0.5MHz to 2MHz.
As the REBOOT pin is set from low to high, the REBOOT
function will be active. The REBOOT's FSM is shown as
below. It concludes 100ms de-bouncing time and delay1/
delay2 power off delay time.
Four step-down converters have RAMP control function
as the following diagram.
Table 1. REBOOT Input Control Setting
Description
delayed2
delayed1
Action
00 : 100ms
01 : 500ms
10 : 1s
11 : 2s
Default
10
10
delayed1 power-off then
delayed2 power-on PMIC
From “LOW“ to “HIGH” rising
input into REBOOT pin with
100ms debouncing time
DC/DC 1/2/3/4
Output Voltage4
DC/DC 1/2/3/4
Output Voltage2
Wait for delayed1 time
DC/DC 1/2/3/4
Output Voltage1
Power off the PMIC
DC/DC 1/2/3/4
Output Voltage3
Wait for delayed2 time
Power on the PMIC
IRQ Table
We summarize all IRQ items in the register table. All IRQ_status registers are implemented as reset after read. If
IRQ_enable bit is Low, the IRQ_status bit will not update status. IRQ_enable will mask IRQ_status to trigger IRQ_PMIC
Low, so the system can decide which interrupt is necessary.
Waveform - (when the other IRQ_status are low)
Mask
IRQ_Status
IRQ_Enable_OVP
OVP
Reset after
Read
Reset after
Read
IRQ_Status_OVP
IRQ_PMIC
Waveform - (when the other IRQ_status are low)
* OTW125/OTW100 means the 125°C/100°C pre-warming over temperature. It only change IRQ status bits and don't
trigger IRQ pin.
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is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
EEPROM (MTP) Control Flow
Thermal Considerations
The RT5028B embeds 32 bytes MTP memory, and it allows
users to save some I2C register bank data to MTP. When
the I2C register 0x3A Bit[0]/Bit[1] is wrote to “1”, the
MTP Page1/Page2 will execute erase process firstly.
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Because the erase process will be done in every writing
time, the MTP data will be missed. So it would be best
for users to read data from MTP to I2C first before
executing writing process.
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
Page 1 writing follow :
Set I2C Register 0x3A Bit[4] =1
Reading MTP process
PMU will read MTP data to
relative I2C register bank.
Writing MTP process
P D(MAX) = (125°C − 25°C) / (27°C/W) = 3.7W for
WQFN-56L 7x7 package
Page 2 writing follow :
Set I2C Register 0x3A Bit[5] =1
Reading MTP process
PMU will read MTP data to
relative I2C register bank.
Set I2C Register 0x3A Bit[1]
Writing MTP process
Maximum Power Dissipation (W)1
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
PMU will move relative I2C
register bank data to MTP
PMU will erase the MTP page2
data
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-56L 7x7 package, the thermal resistance, θJA, is
27°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
Set I2C Register 0x3A Bit[0]
PMU will erase the MTP page1
data
PD(MAX) = (TJ(MAX) − TA) / θJA
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
PMU will move relative I2C
register bank data to MTP
25
50
75
100
125
Ambient Temperature (°C)
Figure 1. Derating Curve of Maximum Power Dissipation
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21
RT5028B
Layout Consideration

For the best performance of the RT5028B, the following
PCB layout guidelines must be strictly followed.
The switching node area connected to LX and inductor
should be minimized for lower EMI.

Connect the GND and Exposed Pad to a strong ground
plane for maximum thermal dissipation and noise


Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
protection.

Keep the main power traces as wide and short as
possible.
Directly connect the output capacitors to the feedback
network of each channel to avoid bouncing caused by
parasitic resistance and inductance from the PCB trace.
VOUTB1
GND
GND
LX should be connected to Inductor by wide and short
trace, keep sensitive compontents away from this trace.
48
47
VINB2
49
VIN
50
VINB2
VIN
51
VINB1
LXB1
52
VINB1
LXB1
53
ENB1
54
VOUTB1S
ENL1
55
VIN VIN
ENL2
56
VDDP
AGND
ENL3
Input/Output capacitors must be
placed as close as possible to the
Input/Output pins.
46
45
44
43
VOUTL1 1
42 LXB2
VIN VINL123 2
41 LXB2
VOUTB2
GND
40 ENB2
GND
VOUTL2
3
VOUTL3
4
39 VOUTB2S
VOUTL6
5
38 VINB3
VOUTL5
6
37 VINB3
VIN
GND
36 LXB3
VIN VINL456 7
VOUTB3
VOUTL4
8
VOUTL7
9
35 LXB3
GND
34 AGND
GND
33 VOUTB3S
VIN VINL78 10
10
VOUTL8 11
32 VINB4 VIN
GND
31 LXB4
ENL4 12
ENL5 13
GND
VOUTB4
30 ENB3
GND
29 VOUTB4S
SCL
ENL7
ENL8
IRQ
/RESET
AGND
22
23
24
25
26
27
28
ENB4
21
SADDR
20
PWRHOLD
19
MTP
18
MASK_GPIO
17
PWRON
16
REBOOT
15
SDA
ENL6 14
GND
Connect the Exposed
Pad to a ground plane.
GND
Figure 2. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
Table 2. I2C Register Table
Detail Description
Address 00
Bit
Device ID
Name
Description
Read/Write
Reset Value
[7:4]
VENDOR_ID
Vendor Identification : Richtek : 1000b
R
1000
[3:0]
CHIP_REV
Chip Revision
R
0001
Address 01
Bit
BUCKcontrol1
Name
Description
R/W
Reset Value
[7:2]
Buck1Output[5:0]
Buck1 output voltage regulation
000000 : 0.7V, 25mV per step
000001 : 0.725V
…
101100 : 1.8V
…
111111 : 1.8V
R/W
Option
[1:0]
Buck1VRC
VRC setting
00 : 25mV/10s, 01 : 50mV/10s,
10 : 100mV/10s, 11 : 200mV/10s
R/W
Option
Address 02
Bit
BUCKcontrol2
Name
Description
[7:2]
Buck2Output[5:0]
Buck2 output voltage regulation
000000 : 0.7V, 25mV per step
000001 : 0.725V
…
101100 : 1.8V
…
111111 : 1.8V
[1:0]
Buck2VRC
VRC setting
00 : 25mV/10s, 01 : 50mV/10s,
10 : 100mV/10s, 11 : 200mV/10s
Address 03
Bit
R/W
Reset Value
R/W
Option
R/W
Option
BUCKcontrol3
Name
Description
R/W
Reset Value
[7:2]
Buck3Output[5:0]
Buck3 output voltage regulation
000000 : 0.7V, 50mV per step
000001 : 0.75V
…
111010 : 3.6V
…
111111 : 3.6V
R/W
Option
[1:0]
Buck3VRC
VRC setting
00 : 50mV/10s, 01 : 100mV/10s,
10 : 200mV/10s, 11 : 400mV/10s
R/W
Option
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23
RT5028B
Address 04
Bit
BUCKcontrol4
Name
Description
R/W
Reset Value
R/W
Option
R/W
Option
Description
R/W
Reset Value
Buck1VRC_EN
Buck1 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
R/W
Option
Buck2VRC_EN
Buck2 VRC
0 - disable - voltage ramps up to target voltage
with one time
1 - enable - voltage ramps up to target voltage
with slope control
R/W
Option
Buck3VRC_EN
Buck3 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
R/W
Option
Buck4VRC_EN
Buck4 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
R/W
Option
R/W
0000
R/W
Reset Value
[7:2]
Buck4Output[5:0]
Buck4 output voltage regulation
000000 : 0.7V, 50mV per step
000001 : 0.75V
…
111010 : 3.6V
…
111111 : 3.6V
[1:0]
Buck4VRC
VRC setting
00 : 50mV/10s, 01 : 100mV/10s,
10 : 200mV/10s, 11 : 400mV/10s
Address 05
Bit
7
6
5
4
[3:0]
VRC Control
Name
Reserved
Address 06
Bit
BUCK Mode
Name
Description
7
Buck1mode
Buck1 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
1
6
Buck2mode
Buck2 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
1
5
Buck3mode
Buck3 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
1
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4
Buck4mode
Buck4 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
1
3
Buck1oms
Buck1 output off mode state
0 : floating
1 : Ground-discharged
R/W
1
2
Buck2oms
Buck2 output off mode state
0 : floating
1 : Ground-discharged
R/W
1
1
Buck3oms
Buck3 output off mode state
0 : floating
1 : Ground-discharged
R/W
1
0
Buck4oms
Buck4 output off mode state
0 : floating
1 : Ground-discharged
R/W
1
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
Address 07
Bit
7
[6:0]
Name
7
[6:0]
LDO1OUT[6:0]
Name
7
[6:0]
LDO1 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
LDOcontrol2
Description
Reserved
LDO2OUT[6:0]
Address 09
Bit
Description
Reserved
Address 08
Bit
LDOcontrol1
Name
LDO2 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
LDOcontrol3
Description
Reserved
LDO3OUT[6:0]
LDO3 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
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25
RT5028B
Address 0A
Bit
7
[6:0]
Name
7
[6:0]
LDO4OUT[6:0]
Name
7
[6:0]
LDO5OUT[6:0]
Name
LDO6OUT[6:0]
7
[6:0]
Name
Description
LDO5 output voltage regulation
0000000 : 3V, 25mV per step
0000001 : 3.025V
...
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Description
LDO6 output voltage regulation
0000000 : 3.0V, 25mV per step
0000001 : 3.025V
...
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
LDOcontrol7
Description
LDO7output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
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26
Reset Value
LDOcontrol6
Reserved
LDO7UT[6:0]
R/W
LDOcontrol5
Reserved
Address 0D
Bit
LDO4 output voltage regulation
0000000 : 3 V, 25mV per step
0000001 : 3.025V
...
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Reserved
Address 0C
Bit
Description
Reserved
Address 0B
Bit
LDOcontrol4
is a registered trademark of Richtek Technology Corporation.
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RT5028B
Address 0E
Bit
7
[6:0]
Name
LDO8T[6:0]
Name
7
LDO8oms
6
LDO7oms
5
LDO6oms
4
LDO5oms
3
LDO4oms
2
LDO3oms
1
LDO2oms
0
LDO1ms
Address 10
Bit
Description
Reserved
Address 0F
Bit
LDOcontrol8
LDO8utput voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
0101000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
LDOs off mode state
Description
LDO8 output off mode state
0 : floating
1 : Ground-discharged
LDO7 output off mode state
0 : floating
1 : Ground-discharged
LDO6 output off mode state
0 : floating
1 : Ground-discharged
LDO5 output off mode state
0 : floating
1 : Ground-discharged
LDO4 output off mode state
0 : floating
1 : Ground-discharged
LDO3 output off mode state
0 : floating
1 : Ground-discharged
LDO2 output off mode state
0 : floating
1 : Ground-discharged
LDO1output off mode state
0 : floating
1 : Ground-discharged
REBOOT/PWRHOLD delay time control
Name
Description
R/W
Reset Value
[7:6]
Delayed2[1:0]
Delayed2 setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
R/W
Option
[5:4]
Delayed1[1:0]
Delayed1 setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
R/W
Option
[3:2]
THOLD[1:0]
THOLD setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
R/W
Option
R/W
0
R/W
Option
1
Reserved
0
DisTHOLD
Ignore THOLD Time.
0 : Keep PWRHOLD function.
1 : Ignore PWRHOLD function.
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RT5028B
Address 11
Bit
ON Event Setting
Name
Description
[7:5]
On_Event
Powered on because of
000 : PWRON key-pressed
001 : VIN plugged in
010 : from REBOOT pin event
111 : No event happen
[4:0]
Reserved
Address 12
Bit
[7:5]
Name
VOFF setting
R/W
Reset Value
R
111
R/W
0
R/W
Reset Value
R/W
Option
R/W
0
VIN UVLO/Buck On/Off
Description
VIN UVLO 2.8V to 3.5V per 0.1V to power off
PMIC
000 : 2.8V
001 : 2.9V
010 : 3V
011 : 3.1V (Default)
100 : 3.2V
101 : 3.3V
110 : 3.4V
111 : 3.5V
4
Reserved
3
Buck4
Buck4 control
(0 : Disable Buck4/1 : Enable Buck4)
R/W
Option
2
Buck3
Buck3 control
(0 : Disable Buck3/1 : Enable Buck3)
R/W
Option
1
Buck2
Buck2 control
(0 : Disable Buck2/1 : Enable Buck2)
R/W
Option
0
Buck1
Buck1 control
(0 : Disable Buck1/1 : Enable Buck1)
R/W
Option
Address 13
LDOs On/Off
Bit
Name
Description
R/W
Reset Value
7
LDO8
LDO8 control
(0 : Disable LDO8 / 1 : Enable LDO8)
R/W
Option
6
LDO7
LDO7 control
(0 : Disable LDO7 / 1 : Enable LDO7)
R/W
Option
5
LDO6
LDO6 control
(0 : Disable LDO6 / 1 : Enable LDO6)
R/W
Option
4
LDO5
LDO5 control
(0 : Disable LDO5 / 1 : Enable LDO5)
R/W
Option
3
LDO4
LDO4 control (0 : Disable LDO4 / 1 : Enable
LDO4)
R/W
Option
2
LDO3
LDO3 control
(0 : Disable LDO3 / 1 : Enable LDO3)
R/W
Option
1
LDO2
LDO2 control
(0 : Disable LDO2 / 1 : Enable LDO2)
R/W
Option
0
LDO1
LDO1 control
(0 : Disable LDO1 / 1 : Enable LDO1)
R/W
Option
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RT5028B
Address 14
Bit
Name
[7:6]
START_TIME
[5:4]
L_PRESS_TIME
[3:2]
SHDN_PRESS
[1:0]
RESET_DLY
Address 15
Bit
PWRON(Power On Key) time Parameters
Setting / RESET delay
Description
Startup time setting
00 : 100s (pressing time - low level)
01 : 100ms
10 : 1s
11 : 2s
Long-press time setting (after Power-On,
00 : 1s (falling edge to rising edge)
01 : 1.5s
10 : 2s
11 : 2.5s
Sending short/long-press IRQ to CPU
ex :1.5s
=> low time < 1.5s (short IRQ)
=> low time > 1.5s but < 6s(shutdown time)
(long IRQ)
=> low time > 6s(shutdown time) (shutdown)
Key-press forced shutdown time setting
00 : 4s (pressing time : low level)
01 : 6s
10 : 8s
11 : 10s
RESET signal delay after the last power startup
is done
00 : 10ms
01 : 50ms
10 : 100ms
11 : 200ms
R/W
Reset Value
R/W
Option
R/W
Option
R/W
Option
R/W
Option
Read/Write
Reset Value
SHDN Control
Name
Description
SHDN_CTRL
Power Off setting by CPU, after set, 100ms
delayed power off
0 : Normal operation
1 : Disable the PMIC output
R/W
Option
SHDN_TIMING
Disable Buck/LDO only for normal power off
(SHDN_CTRL = 1)
0 : disable at the same time
1 : contrary to the startup timing
(first_on-last_off)
R/W
Option
[5:4]
SHDN_DLYTIME
Delayed shutdown time after send the
(PWRON)key-press-forced-shutdown IRQ
(when IRQ is disable, there is no delay)
00 : 100ms
01 : 500ms
10 : 1s
11 : 2s
R/W
Option
[3:0]
Reserved
R/W
0000
7
6
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RT5028B
Address 16
Bit
Powered off conditions enable setting
Name
Description
Read/Write
Reset Value
7
BCK1LV_ENSHDN
Buck1 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
6
BCK2LV_ENSHDN
Buck2 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
5
BCK3LV_ENSHDN
Buck3 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
4
BCK4LV_ENSHDN
Buck4 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
3
PWRON_ENSHDN
PWRON key-pressed forced SHDN
0 : disable this event. 1 : enable this event
R/W
1
2
OT_ENSHDN
Over temperature SHDN
0 : disable this event. 1 : enable this event
R/W
1
1
VINLV_ENSHDN
VIN voltage low (VOFF) (Set by reg) SHDN
0 : disable this event. 1 : enable this event
R/W
0
0
Reserved
R/W
0
Read/Write
Reset Value
R
1111
R
0000
R/W
0
Address 17
Bit
OFF Event (Only reset by POR)
Name
Description
[7:4]
OFF_Event
Powered off because of (Only shows last
power-off event)
0000 : VIN voltage low (VOFF) (Set by reg)
0001 : Buck1 output voltage low
0010 : Buck2 output voltage low
0011 : Buck3 output voltage low
0100 : PWRON key-pressed forced shutdown
0101 : Power Off register setting
0110 : Over temperature event
0111 : Reboot restart.
1000 : Buck4 output voltage low
1001 : PWR_HOLD fail.
1010 : No event happen.
….
1111 : No event happen
[3:0]
Reserved
Address 18 to 27
16 bytes registers Data Cache (Only reset by
POR)
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IRQ_PMIC (Power Channels)
Address 28
Bit
IRQ Enable1
Name
Description
Read/Write
Reset Value
7
OT_IRQ
Internal over-temperature was triggered, IRQ
enable
R/W
1
6
Bck1LV_IRQ
Buck1 output voltage equal 66% x VTarget , IRQ
enable
R/W
1
5
Bck2LV_IRQ
Buck2 output voltage equal 66% x VTarget, IRQ
enable
R/W
1
4
Bck3LV_IRQ
Buck3 output voltage equal 66% x VTarget, IRQ
enable
R/W
1
3
Bck4LV_IRQ
Buck4 output voltage equal 66% x VTarget, IRQ
enable
R/W
1
2
PWRONSP_IRQ
PWRON short press, IRQ enable
(32s deglitch time)
R/W
0
1
PWRONLP_IRQ
PWRON long press, IRQ enable
(32s deglitch time)
R/W
0
0
SYSLV_IRQ
VIN voltage is lower than VOFF, IRQ enable
R/W
0
Read/Write
Reset Value
Address 29
Bit
IRQ Status1
Name
Description
7
OT
Internal over-temperature
R
0
6
Bck1LV
Buck1 output voltage equal 66% x VTarget
R
0
5
Bck2LV
Buck2 output voltage equal 66% x VTarget
R
0
4
Bck3LV
Buck3 output voltage equal 66% x VTarget
R
0
3
Bck4LV
Buck4 output voltage equal 66% x VTarget
R
0
2
PWRONSP
PWRON short press (32s deglitch time)
R
0
1
PWRONLP
PWRON long press (32s deglitch time)
R
0
0
VINLV
VIN voltage is lower than VOFF
R
0
Read/Write
Reset Value
Address 2A
Bit
IRQ Enable2
Name
Description
7
KPSHDN_IRQ
Key-press forced shutdown, IRQ enable
R/W
1
6
PWRONR_IRQ
PWRON press rising edge, IRQ enable
R/W
0
5
PWRONF_IRQ
PWRON press falling edge, IRQ enable
R/W
0
R
0000
Read/Write
Reset Value
[4:0]
Reserved
Address 2B
Bit
IRQ Status2
Name
Description
7
KPSHDN
Key-press forced shutdown
R
0
6
PWRONR
PWRON press rising edge
R
0
5
PWRONF
PWRON press falling edge
R
0
[4:2]
Reserved
R
000
1
OTW125
Internal 125C pre-warning over-temperature.
R
0
0
OTW100
Internal 100C pre-warning over-temperature.
R
0
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RT5028B
Address 2C
PMU On/Off Sequence1
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
Buck2_Seq[3:0]
[3:0]
Buck1_Seq[3:0]
Bit
Address 2D
Read/Write
Reset Value
Setting Buck2 on/off sequence priority
R/W
Option
Setting Buck1 on/off sequence priority
R/W
Option
Read/Write
Reset Value
PMU On/Off Sequence2
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
Buck4_Seq[3:0]
Setting Buck4 on/off sequence priority
R/W
Option
[3:0]
Buck3_Seq[3:0]
Setting Buck3 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Bit
Address 2E
PMU On/Off Sequence3
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO2_Seq[3:0]
Setting LDO2 on/off sequence priority
R/W
Option
[3:0]
LDO1_Seq[3:0]
Setting LDO1 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Bit
Address 2F
PMU On/Off Sequence4
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO4_Seq[3:0]
Setting LDO4 on/off sequence priority
R/W
Option
[3:0]
LDO3_Seq[3:0]
Setting LDO3 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Bit
Address 30
PMU On/Off Sequence5
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO6_Seq[3:0]
Setting LDO6 on/off sequence priority
R/W
Option
[3:0]
LDO5_Seq[3:0]
Setting LDO5 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Bit
Address 31
PMU On/Off Sequence5
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO8_Seq[3:0]
Setting LDO8 on/off sequence priority
R/W
Option
[3:0]
LDO7_Seq[3:0]
Setting LDO7 on/off sequence priority
R/W
Option
Read/Write
Reset Value
R
Option
Bit
Address 32
Bit
[7:6]
Name
Soft-Start Control
Description
Reserved
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RT5028B
[5:2]
[1:0]
Soft-Start End Control
@ MASK_GPIO = 0
(External Enable pin
define)
0000 : First turn on channel decide the
RESET_DLY time.
0001 : Buck1 decide the RESET_DLY time.
….
0100 : Buck1 decide the RESET_DLY time.
0101 : LDO1 decide the RESET_DLY time.
….
1100 : LDO8 decide the RESET_DLY time.
….
1111 : LDO8 decide the RESET_DLY time.
R/W
Option
Soft-Start Voltage level
/ time soft-start control.
Voltage Level
00 : When output voltage arrives to 80%
VTarget, next channel will turn on.
Soft-start time interval (TSS) :
01 : 1ms
10 : 4ms
11 : 8ms
R/W
Option
Read/Write
Reset Value
Address 33
Bit
[7:6]
[5:0]
Name
Description
VCO_VRC
VCO input voltage slop.
00: 25mV/10s, 01: 25mV/20s
10: 25mV/40s, 11: 25mV/80s
Note :
The VCO’s voltage input range is 0.375V to
1.8V and the output frequency is 500kHz to
2.18MHz.
R/W
Option
VCO_DVS
VCO input voltage DVS control
000000 : 0.375V (500kHz)
………
111001 : 1.8V (2MHz)
………
111111 : 1.8V (2MHz)
R/W
Option
Read/Write
Reset Value
R/W
0000000
R/W
Option
Read/Write
Reset Value
R/W
00
Address 34
Bit
[7:1]
0
Name
[7:6]
Buck Syn-Clock Spread Spectrum Control
Description
Reserved
SSOSC
Address 3A
Bit
Buck Syn-Clock Control
Name
Buck Clock Spread Spectrum Control
0 : Disable spread spectrum function.
1 : Turn on spread spectrum function.
EEPROM (MTP) Control
Description
Reserved
5
MTP Page 2 Read
Read MTP Page 2
R
0
4
MTP Page 1 Read
Read MTP Page 1
R
0
R/W
00
[3:2]
Reserved
1
MTP Page 2 write
Write MTP Page 2, and MTP also needs to be
logic high.
W
0
0
MTP Page 1 write
Write MTP Page 1, and MTP also needs to be
logic high.
W
0
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33
RT5028B
Table 3. I2C to MTP Mapping Table
MTP Page-1
MTP
I2C Register Address
Address
Bit7
Bit6
Bit5
Bit4
Function
0x01
1
1
0
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
BUCKcontrol2
Buck2Output[5:0]
1
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
BUCKcontrol3
Buck3Output[5:0]
0
0
1
0
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
BUCKcontrol4
Meaning
0x04
Buck4Output[5:0]
0x05
1
1
0
0
1
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
VRC Control
Meaning
Buck1V
RC_EN
Buck2V
RC_EN
Buck3V
RC_EN
Buck4V
RC_EN
Reserved
Reserved
Reserved
Reserved
Default
1
1
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Condition
A
A
A
A
A
A
A
A
Function
0x04
0x07
LDOcontrol1
Meaning
Reserved
LDO1OUT[6:0]
Default
0
0
1
1
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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34
Buck4VRC
Default
Function
0x0D
Buck3VRC
Default
Function
0x03
Buck2VRC
Default
Meaning
0x03
Buck1VRC
0
Function
0x02
Bit0
Default
Meaning
0x02
Bit1
Buck1Output[5:0]
Function
0x01
Bit2
BUCKcontrol1
Meaning
0x00
Bit3
is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
MTP
Address
I2C Register Address
Bit7
Bit6
Bit5
Function
0x05
Default
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x08
LDOcontrol3
Meaning
Reserved
Default
0
0
1
1
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x09
LDO3OUT[6:0]
LDOcontrol4
Meaning
Reserved
Default
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0A
LDO4OUT[6:0]
LDOcontrol5
Meaning
Reserved
Default
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0B
LDO5OUT[6:0]
LDOcontrol6
Meaning
Reserved
Default
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0C
LDO6OUT[6:0]
Function
0x0A
LDOcontrol7
Meaning
Reserved
Default
0
0
1
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0D
LDO7OUT[6:0]
Function
0x0B
Bit0
LDO2OUT[6:0]
Function
0x09
Bit1
Reserved
Function
0x08
Bit2
Meaning
Function
0x07
Bit3
LDOcontrol2
Function
0x06
Bit4
LDOcontrol8
Meaning
Reserved
Default
0
1
0
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0E
LDO8OUT[6:0]
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5028B-00 April 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
35
RT5028B
MTP
Address
I2C Register Address
Bit7
Bit6
Function
0x0F
0x12
No
mapping
VOFF setting
Bit3
Bit2
Bit1
Bit0
Reserved Reserved Reserved Reserved Reserved
Default
0
1
1
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
B
B
B
B
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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36
Bit4
VIN UVLO (update default value after power on)
Meaning
0x0C
Bit5
is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
MTP Page-2
MTP
2
I C Register Address
Address
Bit7
Bit6
Function
Meaning
0x00
0x10
0x15
0
1
0
1
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
START_TIME
L_PRESS_TIME
RESET_DLY
1
1
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
SHDN Control
Meaning
SHDN_
CTRL
SHDN_
TIMING
Default
0
1
1
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
B
A
A
A
A
A
A
A
SHDN_DLYTIME
Reserved Reserved Reserved Reserved
PMU On/Off Sequence1
Buck2_Seq[3:0]
Buck1_Seq[3:0]
Default
0
0
1
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
PMU On/Off Sequence2
Buck4_Seq[3:0]
Buck3_Seq[3:0]
Default
0
1
0
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
PMU On/Off Sequence3
Meaning
0x2E
SHDN_PRESS
1
Function
0x05
Reserved DisTHOLD
Default
Meaning
0x2D
THOLD
PWRON time Parameters Setting / RESET delay
Function
0x04
Bit0
1
Meaning
0x2C
Bit1
Default
Function
0x03
Bit2
Delayed1[1:0]
Function
0x02
Bit3
Delayed2[1:0]
Meaning
0x14
Bit4
REBOOT/PWRHOLD delay time control
Function
0x01
Bit5
LDO2_Seq[3:0]
LDO1_Seq[3:0]
Default
0
1
1
0
0
1
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5028B-00 April 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
37
RT5028B
MTP
I2C Register Address
Address
Bit7
Bit6
Bit5
Function
0x2F
LDO4_Seq[3:0]
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
PMU On/Off Sequence5
LDO6_Seq[3:0]
1
0
0
1
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
PMU On/Off Sequence6
LDO8_Seq[3:0]
1
0
0
1
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Soft-Start Control
Reversed Reversed
Soft-Start End Select @MASK_GPIO=1
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Meaning
0x33
Buck Syn-Clock Control
VCO_VRC
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Meaning
0x0C
0x34
No
mapping
Buck Syn-Clock Spread Spectrum Control
Reversed Reversed Reversed Reversed Reversed Reversed Reversed
SSOSC
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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38
VCO_DVS
Default
Function
0x0B
Soft-Start Control
Default
Function
0x0A
LDO7_Seq[3:0]
Default
Meaning
0x32
LDO5_Seq[3:0]
Default
Function
0x09
LDO3_Seq[3:0]
0
Meaning
0x31
Bit0
0
Function
0x08
Bit1
1
Meaning
0x30
Bit2
Default
Function
0x07
Bit3
PMU On/Off Sequence4
Meaning
0x06
Bit4
is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
MTP
2
I C Register Address
Address
0x0D
0x0E
0x0F
No
mapping
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
No
mapping
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
No
mapping
Function
x
Meaning
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Reset Condition
A
Reset by MTP (Register 0x12 VOFF Setting).
B
Reset when VIN < 1.7V.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5028B-00 April 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
39
RT5028B
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
6.900
7.100
0.272
0.280
D2
5.150
5.250
0.203
0.207
E
6.900
7.100
0.272
0.280
E2
5.150
5.250
0.203
0.207
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 56L QFN 7x7 Package
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
40
is a registered trademark of Richtek Technology Corporation.
DS5028B-00 April 2016
RT5028B
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS5028B-00 April 2016
www.richtek.com
41