CBTL06141 Gen1 display 2 : 1 multiplexer Rev. 2 — 15 July 2010 Product data sheet 1. General description The CBTL06141 is a six-channel (‘hex’) multiplexer for DisplayPort and PCI Express applications at Generation 1 (‘Gen1’) speeds. It provides four differential channels capable of 1 : 2 switching or 2 : 1 multiplexing (bidirectional and AC-coupled) PCI Express or DisplayPort signals, using high-bandwidth pass-gate technology. Additionally, it provides for switching/multiplexing of the Hot Plug Detect signal as well as the AUX or DDC (Direct Display Control) signals, for a total of six channels on the display side. The AUX and DDC channels provide a four-position multiplexer such that an additional level of multiplexing can be accomplished when AUX and DDC I/Os are on separate pins of the display source device. The CBTL06141 is designed for Gen1 speeds, at 2.5 Gbit/s for PCI Express or 2.7 Gbit/s for DisplayPort, and for inputs voltages of up to 3.3 V typical. It consumes very low current in operational mode (less than 1 mA typical) and provides for a shutdown function (less than 10 μA) to support battery-powered applications. A typical application of CBTL06141 is on motherboards where one of two GPU display sources needs to be selected to connect to a display sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the non-directional nature of the signal paths (which use high-bandwidth passgate technology), the CBTL06141 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors. Optionally, the hex MUX device can be used in conjunction with an HDMI/DVI level shifter device (PTN3300A, PTN3300B or PTN3301) to allow for DisplayPort as well as HDMI/DVI connectivity. 2. Features and benefits 1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.1 - 2.7 Gbit/s) or PCI Express (v1.1 - 2.5 Gbit/s) signals 4 high-speed differential channels with 2 : 1 muxing/switching for DisplayPort or PCI Express signals 1 channel with 4 : 1 muxing/switching for AUX differential signals or DDC single-ended clock and data signals 1 channel with 2 : 1 muxing/switching for single-ended HPD signals High-bandwidth analog pass-gate technology Very low intra-pair differential skew (< 5 ps) Very low inter-pair skew (< 180 ps) Switch/multiplexer position select CMOS input Shutdown mode CMOS input CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer Shutdown mode minimizes power consumption while switching all channels off DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor Supports HDMI/DVI incorrect dongle connection Single 3.3 V power supply Very low operation current of 0.2 mA typical Very low shutdown current of < 10 μA ESD 8 kV HBM, 1 kV CDM ESD 2 kV HBM, 500 V CDM for control pins Available in 5 mm × 5 mm, 0.5 mm ball pitch TFBGA48 package 3. Applications Motherboard applications requiring DisplayPort and PCI Express switching/multiplexing Docking stations Notebook computers Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board connectors 4. Ordering information Table 1. Ordering information Type number CBTL06141EE/G [1] Solder process Pb-free (SnAgCu solder compound) Package Name Description Version TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; SOT918-1 body 5 × 5 × 0.8 mm[1] Total height including solder balls after printed circuit board mounting = 1.15 mm. CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 2 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 5. Functional diagram VDD CBTL06141 4 DIN1_n+ DIN1_n− 0 4 DOUT_n+ DOUT_n− 4 DIN2_n+ DIN2_n− 1 DAUX1+ DAUX1− 00 DAUX2+ DAUX2− 10 DDC_CLK1 DDC_DAT1 01 DDC_CLK2 DDC_DAT2 11 AUX+ or SCL HPD_1 0 HPD_2 1 AUX− or SDA AUX+ AUX− HPDIN GPU_SEL DDC_AUX_SEL TST0 XSD Fig 1. CBTL06141 Product data sheet GND 002aad554 Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 3 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 6. Pinning information 6.1 Pinning ball A1 index area CBTL06141EE/G 1 2 3 4 5 6 7 8 9 A B C D E F G H J 002aad360 Transparent top view Fig 2. Pin configuration for TFBGA48 1 2 A GPU_SEL VDD B DOUT_0− DOUT_0+ C 3 GND 4 5 6 DIN1_0− DIN1_1− DIN1_2− DIN1_0+ DIN1_1+ DIN1_2+ 7 XSD 8 9 DIN1_3+ DIN1_3− DIN2_0+ DIN2_0− DDC_AUX _SEL GND D DOUT_1− DOUT_1+ DIN2_1+ DIN2_1− E DOUT_2− DOUT_2+ DIN2_2+ DIN2_2− F DOUT_3− DOUT_3+ DIN2_3+ DIN2_3− TST0 GND G H AUX− AUX+ J HPDIN HPD_1 HPD_2 GND DDC_CLK2 DAUX2+ VDD DDC_DAT2 DAUX2− GND DDC_CLK1 DAUX1+ DDC_DAT1 DAUX1− 002aad361 Transparent top view Fig 3. CBTL06141 Product data sheet Ball mapping All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 4 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 6.2 Pin description Table 2. Pin description Symbol Ball Type Description GPU_SEL A1 3.3 V low-voltage CMOS single-ended input Selects between two multiplexer/switch paths. When HIGH, path 2 left-side is connected to its corresponding right-side I/O. When LOW, path 1 left-side is connected to its corresponding right-side I/O. DDC_AUX_SEL C2 3.3 V low-voltage CMOS single-ended input Selects between DDC and AUX paths. When HIGH, the CLK and DAT I/Os are connected to their respective DDCOUT terminals. When LOW, the AUX+ and AUX− I/Os are connected to their respective DDCOUT terminals. XSD B7 3.3 V low-voltage CMOS single-ended input Shutdown pin. Should be driven HIGH or connected to VDD for normal operation. When LOW, all paths are switched off (non-conducting) and supply current consumption is minimized. TST0 G2 3.3 V low-voltage CMOS single-ended input Test pin for NXP use only. Should be tied to ground in normal operation. DIN1_0+ B4 differential I/O DIN1_0− A4 differential I/O Four high-speed differential pairs for DisplayPort or PCI Express signals, path 1, left-side. DIN1_1+ B5 differential I/O DIN1_1− A5 differential I/O DIN1_2+ B6 differential I/O DIN1_2− A6 differential I/O DIN1_3+ A8 differential I/O DIN1_3− A9 differential I/O DIN2_0+ B8 differential I/O DIN2_0− B9 differential I/O DIN2_1+ D8 differential I/O DIN2_1− D9 differential I/O DIN2_2+ E8 differential I/O DIN2_2− E9 differential I/O DIN2_3+ F8 differential I/O DIN2_3− F9 differential I/O DOUT_0+ B2 differential I/O DOUT_0− B1 differential I/O DOUT_1+ D2 differential I/O DOUT_1− D1 differential I/O DOUT_2+ E2 differential I/O DOUT_2− E1 differential I/O DOUT_3+ F2 differential I/O DOUT_3− F1 differential I/O DAUX1+ H9 differential I/O DAUX1− J9 differential I/O DAUX2+ H6 differential I/O DAUX2− J6 differential I/O CBTL06141 Product data sheet Four high-speed differential pairs for DisplayPort or PCI Express signals, path 2, left-side. Four high-speed differential pairs for DisplayPort or PCI Express signals, right-side. High-speed differential pair for AUX signals, path 1, left-side. High-speed differential pair for AUX signals, path 2, left-side. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 5 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer Table 2. Pin description …continued Symbol Ball Type Description DDC_CLK1 H8 differential I/O DDC_DAT1 J8 differential I/O Pair of single-ended terminals for DDC clock and data signals, path 1, left-side. DDC_CLK2 H5 differential I/O DDC_DAT2 J5 differential I/O AUX+ H2 differential I/O AUX− H1 differential I/O High-speed differential pair for AUX or single-ended DDC signals, right-side. HPD_1 J2 single-ended I/O Single ended channel for the HPD signal, path 1, left-side. HPD_2 H3 single-ended I/O Single ended channel for the HPD signal, path 2, left-side. HPDIN J1 single-ended I/O Single ended channel for the HPD signal, right-side. VDD A2, J4 power supply 3.3 V power supply. GND B3, C8, G8, H4, H7 ground Ground. Pair of single-ended terminals for DDC clock and data signals, path 2, left-side. 7. Functional description Refer to Figure 1 “Functional diagram”. The CBTL06141 uses a 3.3 V power supply. All main signal paths are implemented using high-bandwidth pass-gate technology and are non-directional. No clock or reset signal is needed for the multiplexer to function. The switch position for the main channels is selected using the select signal GPU_SEL. Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the DDC / AUX channel. The detailed operation is described in Section 7.1. 7.1 Multiplexer/switch select functions The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and DDC_AUX_SEL as described below. Table 3. DIN1_n DIN2_n 0 active; connected to DOUT_n high-impedance 1 high-impedance active; connected to DOUT_n Table 4. CBTL06141 Product data sheet Multiplexer/switch select control for DIN and DOUT channels GPU_SEL Multiplexer/switch select control for HPD channel GPU_SEL HPD1 HPD2 0 active; connected to HPDIN high-impedance 1 high-impedance active; connected to HPDIN All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 6 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer Table 5. Multiplexer/switch select control for DDC and AUX channels DDC_AUX_SEL GPU_SEL DAUX1 DAUX2 DDC_CLK1, DDC_DAT1 DDC_CLK2, DDC_DAT2 0 0 active; connected to AUX high-impedance high-impedance high-impedance 0 1 high-impedance active; connected to AUX high-impedance high-impedance 1 0 high-impedance high-impedance active; connected to AUX high-impedance 1 1 high-impedance high-impedance high-impedance active; connected to AUX 7.2 Shutdown function The CBTL06141 provides a shutdown function to minimize power consumption when the application is not active but power to the CBTL06141 is provided. Pin XSD (active LOW) puts all channels in off mode (non-conducting) while reducing current consumption to near-zero. Table 6. CBTL06141 Product data sheet Shutdown function XSD State 0 shutdown 1 active All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 7 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage Tcase case temperature VESD electrostatic discharge HBM voltage HBM; CMOS inputs Min Max Unit −0.3 +5 V −40 +85 °C [1] - 8000 V [1] - 2000 V CDM [2] - 1000 V CDM; CMOS inputs [2] 500 V [1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. [2] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 9. Recommended operating conditions Table 8. Recommended operating conditions Symbol Parameter VDD supply voltage VI input voltage Conditions CMOS inputs other inputs HPD, DDC inputs Tamb [1] CBTL06141 Product data sheet ambient temperature operating in free air [1] Min Typ Max Unit 3.0 3.3 3.6 V −0.3 - VDD + 0.3 V −0.3 - +2.6 V −0.3 - VDD + 0.3 V −10 - +85 °C HPD input is tolerant to 5 V input, provided a 1 kΩ series resistor between the voltage source and the pin is placed in series. See Section 11.1 “Special considerations”. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 8 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 10. Characteristics 10.1 General characteristics Table 9. General characteristics Symbol Parameter Conditions Min Typ Max Unit IDD supply current operating mode (XSD = HIGH); VDD = 3.3 V - 0.2 1 mA shutdown mode (XSD = LOW); VDD = 3.3 V - - 10 μA Pcons power consumption operating mode (XSD = HIGH); VDD = 3.3 V - - 5 mW tstartup start-up time supply voltage valid or XSD going HIGH to channel specified operating characteristics - - 1 ms trcfg reconfiguration time GPU_SEL or DDC_AUX_SEL state change to channel specified operating characteristics - - 1 ms 10.2 DisplayPort channel characteristics Table 10. DisplayPort channel characteristics Symbol Parameter VI Conditions Min Typ Max Unit input voltage −0.3 - +2.6 V VIC common-mode input voltage 0 - 2.0 V VID differential input voltage DDIL differential insertion loss −1.2 - +1.2 V channel is on; 0 Hz ≤ f ≤ 1.0 GHz −2.5 −1.6 - dB channel is on; f = 2.5 GHz −4.5 - - dB channel is off; 0 Hz ≤ f ≤ 3.0 GHz - - −20 dB channel is on; 0 Hz ≤ f ≤ 1.0 GHz - - −10 dB DDNEXT differential near-end crosstalk adjacent channels are on; 0 Hz ≤ f ≤ 1.0 GHz - - −30 dB B bandwidth −3.0 dB intercept - 2.5 - GHz −5.0 dB intercept - 4.0 - GHz tPD propagation delay from left-side port to right-side port or vice versa - 180 - ps tsk(dif) differential skew time intra-pair - - 5 ps tsk skew time inter-pair - - 180 ps DDRL differential return loss CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 9 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 10.3 AUX and DDC ports Table 11. AUX and DDC port characteristics Symbol Parameter Conditions Min Typ Max Unit VI input voltage no series resistor −0.3 - VDD + 0.3 V 2.2 kΩ series resistor −0.3 - +5.0 V output voltage VO VIC common-mode input voltage VID differential input voltage propagation delay tPD [1] no series resistor; VI = 3.6 V 3.0 - 3.6 V 2.2 kΩ series resistor; VI = 5.0 V 3.0 - 4.3 V DDC or AUX 0 - 2.0 V −1.2 - +1.2 V - 180 - ps from left-side port to right-side port or vice versa [1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time. 10.4 HPDIN input, HPD_x outputs Table 12. HPD input and output characteristics Symbol Parameter Conditions VI input voltage no series resistor 1 kΩ series resistor output voltage VO propagation delay tPD [1] Min Typ Max Unit −0.3 - VDD + 0.3 V −0.3 - +5.0 V no series resistor; VI = 3.6 V 3.0 - 3.6 V 1 kΩ series resistor; VI = 5.0 V 3.0 - 4.3 V - 180 - ps from HPDIN to HPD_x or vice versa [2] [1] Voltage measured at HPD_1 or HPD_2 with input voltage applied to HPDIN, or vice versa. [2] Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time. 10.5 GPU_SEL, DDC_AUX_SEL and XSD inputs Table 13. GPU_SEL, DDC_AUX_SEL, XSD input characteristics Symbol Parameter Min Typ Max Unit VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V ILI input leakage current - - 10 μA CBTL06141 Product data sheet Conditions VDD = 3.6 V; 0.3 V ≤ VI ≤ 3.9 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 10 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 11. Application information 11.1 Special considerations Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to occur on pins AUX+ and AUX−, as well as HPDIN. When AUX+ and AUX− are connected through a minimum of 2.2 kΩ each, the CBTL06141 will sink current but will not be damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 kΩ resistor. (Correct functional operation to specification is not expected in these scenarios.) The latter also prevents the HPDIN input from loading down the system HPD signal when power to the CBTL06141 is off. CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 11 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 12. Package outline TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm B D SOT918-1 A ball A1 index area E A2 A A1 detail X e1 ∅v ∅w b e M M C C A B C y1 C y J H G F E e2 e D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.15 0.25 0.15 0.90 0.75 0.35 0.25 5.1 4.9 5.1 4.9 0.5 4 4 0.15 0.05 0.08 0.1 Fig 4. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT918-1 --- MO-195 --- EUROPEAN PROJECTION ISSUE DATE 05-09-21 05-10-13 Package outline TFBGA48 (SOT918-1) CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 12 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 13 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 5) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 15. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 5. CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 14 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 5. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 16. Abbreviations Acronym Description DDC Direct Display Control DUT Device Under Test DVI Digital Video Interface HDMI High-Definition Multimedia Interface PCB Printed-Circuit Board SMA SubMiniature, version A (connector) TDR Time-Domain Reflectometry AUX Auxiliary channel (in DisplayPort definition) HPD Hot Plug Detect GPU Graphics Processor Unit PCIe PCI Express 15. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTL06141 v.2 20100715 Product data sheet - CBTL06141 v.1 Modifications: CBTL06141 v.1 CBTL06141 Product data sheet • Removed “COMPANY CONFIDENTIAL” watermark 20080624 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 15 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 16 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 © NXP B.V. 2010. All rights reserved. 17 of 18 CBTL06141 NXP Semiconductors Gen1 display 2 : 1 multiplexer 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 9 10 10.1 10.2 10.3 10.4 10.5 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Multiplexer/switch select functions . . . . . . . . . . 6 Shutdown function . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General characteristics . . . . . . . . . . . . . . . . . . . 9 DisplayPort channel characteristics . . . . . . . . . 9 AUX and DDC ports . . . . . . . . . . . . . . . . . . . . 10 HPDIN input, HPD_x outputs . . . . . . . . . . . . . 10 GPU_SEL, DDC_AUX_SEL and XSD inputs . 10 Application information. . . . . . . . . . . . . . . . . . 11 Special considerations . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering of SMD packages . . . . . . . . . . . . . . 13 Introduction to soldering . . . . . . . . . . . . . . . . . 13 Wave and reflow soldering . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 July 2010 Document identifier: CBTL06141