NXP 5-bit multiplexed / 1-bit latched 6-bit I2C-bus EEPROM PCA9559 I2C-bus EEPROM DIP switch for easy system management A simple way to implement open-drain buffer, jumperless configurations. The device provides four sets of potential outputs — logic high, logic lows, outputs that reflect the part’s parallel inputs, or outputs configured by the I2C-bus. Key features 4 Supports 5-bit, 2-to-1 multiplexing 4 One channel with flow-through inputs 4 One channel with inputs configurable via the I2C-bus 4 Supports one-bit, non-multiplexed latch for select pin control 4 Open-drain outputs support voltages up to 3.6 V 4 Two address pins enable up to four devices per bus 4 Active-low override drives multiplexer outputs low 4 Active-high write-protect disables EEPROM tampering 4 Glitch-free operation on power-up and power-down 4 28-pin TSSOP (PW) package Applications 4 Configuration of processor frequency 4 Configuration of voltage identification (VID) 4 Dual-bios selection The NXP PCA9559 is used to multiplex a default parallel input with an alternative set of inputs provided by the I2C-bus or SMBus. It is a derivative of the popular NXP PCA8550 device, with the addition of open-drain outputs for driving different voltage loads. It also adds two address pins to allow for up to four PCA9559 devices per bus. Typical applications for the PCA9559 include processor frequency configuration, system clock generator frequency selection (FS), voltage identification (VID) configuration, and dual-BIOS selection. The PCA9559 makes it possible to perform Intel processor frequency configuration using non-Intel chipsets such as those provided by ServerWorks and Via Technologies. The PCA9559 also enables processor VID configuration and system clock generator FS by all chipsets. Processor VID indicates to the voltage regulator module (VRM) which voltage is required by the processor. Its five-bit value is usually provided by the processor, but, in special applications like Mobile SpeedStep and Desktop Overclocking, can also be provided by the chipset. V CC 3.3 = 20 GND = 10 11 18 6-Bit E 2PROM LATCH 1 2 19 A1 Q4 1.1k7 A0 I2C 1.6k7 OR SMBus 10k7 SCL I2C CLOCK 1.6k7 OR SMBus 10k7 FSBM[0-3] 1030k7 17 OE# Open Drain Voltage Buffers 1.6V 1.1k7 FSBM[0-3] 16,15,14,13,12 MUX_OUT A,B,C,D CPU Q0 FSBM = > Front-side System Bus Multiple 1 5 MUX_IN A,B,C,D The PCA9559 used for processor frequency configuration 11 18 10-30k7 MUX SELECT OVERRIDE# 6-Bit E 2PROM LATCH QNMO Application Note AN250 provides more uses of the PCA9559 and PCA8550 devices. 2 19 CPU 5,6,7,8,9 A1 Q4 1.1k7 A0 I2C 1.6k7 OR SMBus 10k7 SCL 100150k7 I2C CLOCK I2C 1.6k7 OR SMBus 10k7 SDA NMO Q2 Q1 1030k7 VID [0-4] 1030k7 NON_MUXED_OUT 17 Q3 I2C DATA WRITE PROTECT SELECT 0 5-Bit 2-to-1 Multiplexer 4 1.1k7 I2C Interface Logic Chip Set 3 1 For more information please visit www.nxp.com/i2c. Q2 I C DATA 1030k7 NON_MUXED_OUT Q3 Q1 WRITE PROTECT SELECT 0 2 V CC 3.3 = 20 GND = 10 The parallel inputs of the PCA9559 can be left unconnected so that the outputs either pass the default values of chipsetwritten values. If logic-low levels are required, an override pin is available to default the outputs to zeroes. This is especially useful in dual-BIOS selection for systems with multiple configurations. 100150k7 I 2C SDA NMO 5-Bit 2-to-1 Multiplexer 4 1.1k7 I2C Interface Logic 3 5,6,7,8,9 Mobile SpeedStep does not require a change in system clock frequency, since it uses a proprietary ASIC to handle clocking differences. OVERRIDE# QNMO Non Intel Chip Set System clock generation FS indicates to the clock generator which frequency is required to accommodate a change in VID. For example, in Desktop Overclocking, the chipset provides a VID value greater than that provided by the processor. This increases processor voltage to increase the speed of the processor and maximize performance. However, a consistent radio of processor to system bus frequency must be maintained, so the system clock frequency must also be increased. 10-30k7 MUX SELECT OE# Open Drain Voltage Buffers 3.3V VID[0-4] 1.1k7 MUX_OUT A,B,C,D,E 16,15,14,13,12 Voltage Regulator Module Q0 1 5 MUX_IN A,B,C,D,E The PCA9559 used for voltage identification (VID) configuration I2C SCL 1 20 V CC I2C SDA 2 19 WP V CC 3.3 = 20 GND = 10 13 A1 3 18 OVERRIDE # A0 4 17 NON_MUXED_OUT 10-30k7 74HC4066 CHIPSET WR MUX SELECT 7 MUX_IN D 8 MUX_IN E GND MUX_OUT A 15 MUX_OUT B 14 MUX_OUT C 13 MUX_OUT D WATCHDOG TIMER SCL 9 12 MUX_OUT E 10 11 MUX_SELECT PCA9559 pin configuration SDA 1 2 5,6,7,8,9 I2C 1.6k7 OR SMBus 10k7 100150k7 I2C CLOCK I2C 1.6k7 OR SMBus 10k7 NMO 1 Q4 5-Bit 2-to-1 Multiplexer 6 MUX_IN C 16 I2C Interface Logic MUX_IN B 5 PCA9559 QNMO MUX_IN A ROM0 WE0 WE LATCH • • • Q2 I2C DATA NO CONNECTS MUX_IN A,B,C,D,E 1030k7 NON_MUXED_OUT 17 WRITE PROTECT ROM0 CHIPSET CS Open Drain Voltage Buffers MUX_OUT A 16 A0-A16 DQ0-DQ7 CE0 CE SELECT ROM0 ROM1 • • • CHIPSET CS MUX_OUT E 12 SELECT ROM1 CHIPSET WR 0 CE1 CE A0-A16 DQ0-DQ7 WE1 WE 5 WRITE PROTECT ROM1 The PCA9559 used for dual-BIOS selection with multiple system configurations www.nxp.com © 2007 NXP B.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The Date of release: August 2007 information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and Document order number: 9397 750 16090 may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof Printed in the USA does not convey nor imply any license under patent or other industrial or intellectual property rights.