PCU9955A
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current
LED driver
Rev. 3.1 — 29 June 2015
Product data sheet
1. General description
The PCU9955A is an Ultra Fast-mode (UFm) I2C-bus controlled 16-channel constant
current LED driver optimized for dimming and blinking 57 mA Red/Green/Blue/Amber
(RGBA) LEDs in amusement products. Each LED output has its own 8-bit resolution (256
steps) fixed frequency individual PWM controller that operates at 31.25 kHz with a duty
cycle that is adjustable from 0 % to 100 % to allow the LED to be set to a specific
brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both
a fixed frequency of 122 Hz and an adjustable frequency between 15 Hz to once every
16.8 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either
dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCU9955A operates
with a supply voltage range of 3 V to 5.5 V and the constant current sink LED outputs
allow up to 20 V for the LED supply. The output peak current is adjustable with an 8-bit
linear DAC from 225 A to 57 mA.
Gradation control for all current sources is achieved via the I2C-bus serial interface and
allows user to ramp current automatically without MCU intervention. 8-bit DACs are
available to adjust brightness levels for each LED current source. There are four
selectable gradation control groups and each group has independently four registers to
control ramp-up and ramp-down rate, step time, hold ON/OFF time and final hold ON
output current. Two gradation operation modes are available for each group, one is single
shot mode (output pattern once) and the other is continuous mode (output pattern repeat).
Each channel can be set to either gradation mode or normal mode and assigned to any
one of these four gradation control groups.
This device has built-in overtemperature detection circuitry. A thermal shutdown feature
protects the device when internal junction temperature exceeds the limit allowed for the
process.
The PCU9955A device is the first LED controller device in a new Ultra Fast-mode (UFm)
I2C-bus family. UFm I2C-bus devices offer higher frequency (up to 5 MHz). The UFm
I2C-bus slave devices operate in receive-only mode. That is, only I2C writes to the
PCU9955A are supported. As such, there are no status registers in PCU9955A. The
PCU9955A allows significantly higher data transfer rate compared to the Fast-mode Plus
version (PCA9955A).
The active LOW output enable input pin (OE) blinks all the LED outputs and can be used
to externally PWM the outputs, which is useful when multiple devices must be dimmed or
blinked together without using software control.
PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCU9955A devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2C-bus commands. On power-up, PCU9955A has a unique
Sub Call address to identify it as a 16-channel LED driver. This allows mixing of devices
with different channel widths. Three hardware address pins on PCU9955A allow up to
125 devices on the same bus.
The Software Reset (SWRST) function allows the master to perform a reset of the
PCU9955A through the I2C-bus, identical to the Power-On Reset (POR) that initializes the
registers to their default state causing the output current switches to be OFF (LED off).
This allows an easy and quick way to reconfigure all device registers to the same
condition.
2. Features and benefits
16 LED drivers. Each output programmable at:
Off
On
Programmable LED brightness
Programmable group dimming/blinking mixed with individual LED brightness
Programmable LED output delay to reduce EMI and surge currents
Gradation control for all channels
Each channel can assign to one of four gradation control groups
Programmable gradation time and rate for ramp-up and/or ramp-down operations
Programmable step time (6-bit) from 0.5 ms (minimum) to 512 ms (maximum)
Programmable hold-on time after ramp-up and hold-off time after ramp-down (3-bit)
from 0 s to 6 s
Programmable final ramp-up and hold-on current
Programmable brightness current output adjustment, either linear or exponential
curve
16 constant current output channels can sink up to 57 mA, tolerate up to 20 V when
OFF
Output current adjusted through an external resistor (REXT input)
Output current accuracy
4 % between output channels
6 % between PCU9955A devices
Thermal shutdown for overtemperature
5 MHz Ultra Fast-mode I2C-bus interface
256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness fully ON using a 31.25 kHz PWM signal
256-step group brightness control allows general dimming (using a 122 Hz PWM
signal) from fully off to maximum brightness (default)
256-step group blinking with frequency programmable from 15 Hz to 16.8 s and duty
cycle from 0 % to 99.6 %
PCU9955A
Product data sheet
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Rev. 3.1 — 29 June 2015
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Output state change programmable on the Acknowledge (bit 9, this bit is always set
to 1 by I2C-bus master) or the STOP condition to update outputs byte-by-byte or all at
the same time (default to ‘Change on STOP’).
Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of
the LEDs
Three quinary hardware address pins allow 125 PCU9955A devices to be connected
to the same I2C-bus and to be individually programmed
4 software programmable I2C-bus addresses (one LED Group Call address and three
LED Sub Call addresses) allow groups of devices to be addressed at the same time in
any combination (for example, one register used for ‘All Call’ so that all the
PCU9955As on the I2C-bus can be addressed at the same time and the second
register used for three different addresses so that 1⁄3 of all devices on the bus can be
addressed at the same time in a group). Software enable and disable for each
programmable I2C-bus address.
Unique power-up default Sub Call address allows mixing of devices with different
channel widths
Software Reset feature (SWRST Call) allows the device to be reset through the
I2C-bus
8 MHz internal oscillator requires no external components
Internal power-on reset
Noise filter on USDA/USCL inputs
No glitch on LEDn outputs on power-up
Low standby current
Operating power supply voltage (VDD) range of 3 V to 5.5 V
5.5 V tolerant inputs on non-LED pins
40 C to +85 C operation
ESD protection exceeds 4000 V HBM per JESD22-A114
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: HTSSOP28
3. Applications
PCU9955A
Product data sheet
Amusement products
RGB or RGBA LED drivers
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
Fade-in and fade-out for breathlight control
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Rev. 3.1 — 29 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 58
PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
4. Ordering information
Table 1.
Ordering information
Type number
PCU9955ATW
Topside mark
PCU9955ATW
Package
Name
Description
Version
HTSSOP28
plastic thermal enhanced thin shrink small outline package; SOT1172-3
28 leads; body width 4.4 mm; lead pitch 0.65 mm;
exposed die pad
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature
PCU9955ATW
PCU9955ATWJ
HTSSOP28
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
PCU9955A
Product data sheet
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
5. Block diagram
REXT
AD0 AD1 AD2
LED0
LED1
LED14
LED15
I/O
REGULATOR
PCU9955A
DAC0
USCL
INPUT FILTER
DAC1
USDA
individual LED
current setting
8-bit DACs
I2C-BUS
CONTROL
DAC
14
DAC
15
POWER-ON
RESET
VDD
OUTPUT DRIVER, DELAY CONTROL,
AND THERMAL SHUTDOWN
200 kΩ
VSS
LED STATE
SELECT
REGISTER
INPUT
FILTER
RESET
PWM
REGISTER X
BRIGHTNESS
CONTROL
÷ 256
31.25 kHz
8 MHz
OSCILLATOR
GRADATION
CONTROL
MUX/
CONTROL
GRPFREQ
REGISTER
MUX/
CNTL
GRPPWM
REGISTER
DIM CLOCK
'0' – permanently OFF
'1' – permanently ON
OE
002aah726
Dim repetition rate = 122 Hz.
Blink repetition rate = 15 Hz to every 16.8 seconds.
Fig 1.
Block diagram of PCU9955A
PCU9955A
Product data sheet
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
6. Pinning information
6.1 Pinning
REXT
1
28 VDD
AD0
2
27 USDA
AD1
3
AD2
4
OE
5
24 VSS
LED0
6
23 LED15
LED1
7
22 LED14
LED2
8
21 LED13
LED3
9
VSS 10
PCU9955ATW
26 USCL
25 RESET
20 LED12
(1)
19 VSS
LED4 11
18 LED11
LED5 12
17 LED10
LED6 13
16 LED9
LED7 14
15 LED8
002aah727
(1) Thermal pad; connected to VSS.
Fig 2.
Pin configuration for HTSSOP28
6.2 Pin description
Table 3.
PCU9955A
Product data sheet
Pin description
Symbol
Pin
Type
Description
REXT
1
I
current set resistor input; resistor to ground
AD0
2
I
address input 0
AD1
3
I
address input 1
AD2
4
I
address input 2
OE
5
I
active LOW output enable for LEDs
LED0
6
O
LED driver 0
LED1
7
O
LED driver 1
LED2
8
O
LED driver 2
LED3
9
O
LED driver 3
LED4
11
O
LED driver 4
LED5
12
O
LED driver 5
LED6
13
O
LED driver 6
LED7
14
O
LED driver 7
LED8
15
O
LED driver 8
LED9
16
O
LED driver 9
LED10
17
O
LED driver 10
LED11
18
O
LED driver 11
LED12
20
O
LED driver 12
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
LED13
21
O
LED driver 13
LED14
22
O
LED driver 14
LED15
23
O
LED driver 15
RESET
25
I
active LOW reset input
USCL
26
I
UFm serial clock line
USDA
27
I/O
UFm serial data line
ground
supply ground
power supply
supply voltage
VSS
10, 19, 24
VDD
28
[1]
[1]
HTSSOP28 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on
the board and for proper heat conduction through the board, thermal vias must be incorporated in the
printed-circuit board in the thermal pad region.
7. Functional description
Refer to Figure 1 “Block diagram of PCU9955A”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
For PCU9955A there are a maximum of 125 possible programmable addresses using the
three quinary hardware address pins.
7.1.1 Regular I2C-bus slave address
The I2C-bus slave address of the PCU9955A is shown in Figure 3. The 7-bit slave
address is determined by the quinary input pads AD0, AD1 and AD2. Each pad can have
one of five states (GND, pull-up, floating, pull-down, and VDD) based on how the input pad
is connected on the board. At power-up or hardware/software reset, the quinary input
pads are sampled and set the slave address of the device internally. To conserve power,
once the slave address is determined, the quinary input pads are turned off and will not be
sampled until the next time the device is power cycled. Table 4 lists the five possible
connections for the quinary input pads along with the external resistor values that must be
used.
Table 4.
Pad connection
(pins AD2, AD1, AD0)[1]
Mnemonic
tie to ground
resistor pull-down to ground
Product data sheet
External resistor (k)
Min.
Max.
GND
0
17.9
PD
34.8
270
open (floating)
FLT
503
resistor pull-up to VDD
PU
31.7
340
tie to VDD
VDD
0
22.1
[1]
PCU9955A
Quinary input pad connection
These AD[2:0] inputs must be stable before the supply VDD to the chip.
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 5 lists all 125 possible slave addresses of the device based on all combinations of
the five states connected to three address input pins AD0, AD1 and AD2.
Table 5.
I2C-bus slave address
Hardware selectable input pins I2C-bus slave address for PCU9955A
AD2
AD1
AD0
Decimal Hexadecimal Binary (A[6:0]) Address (R/W = 0)
GND
GND
GND
1
01
0000001[1]
02h
GND
GND
PD
2
02
0000010[1]
04h
03
0000011[1]
06h
04
0000100[1]
08h
0Ah
GND
GND
PCU9955A
Product data sheet
GND
GND
FLT
PU
3
4
GND
GND
VDD
5
05
0000101[1]
GND
PD
GND
6
06
0000110[1]
0Ch
0Eh
GND
PD
PD
7
07
0000111[1]
GND
PD
FLT
8
08
0001000
10h
GND
PD
PU
9
09
0001001
12h
GND
PD
VDD
10
0A
0001010
14h
GND
FLT
GND
11
0B
0001011
16h
GND
FLT
PD
12
0C
0001100
18h
GND
FLT
FLT
13
0D
0001101
1Ah
GND
FLT
PU
14
0E
0001110
1Ch
GND
FLT
VDD
15
0F
0001111
1Eh
GND
PU
GND
16
10
0010000
20h
GND
PU
PD
17
11
0010001
22h
GND
PU
FLT
18
12
0010010
24h
GND
PU
PU
19
13
0010011
26h
GND
PU
VDD
20
14
0010100
28h
GND
VDD
GND
21
15
0010101
2Ah
GND
VDD
PD
22
16
0010110
2Ch
GND
VDD
FLT
23
17
0010111
2Eh
GND
VDD
PU
24
18
0011000
30h
GND
VDD
VDD
25
19
0011001
32h
PD
GND
GND
26
1A
0011010
34h
PD
GND
PD
27
1B
0011011
36h
PD
GND
FLT
28
1C
0011100
38h
PD
GND
PU
29
1D
0011101
3Ah
PD
GND
VDD
30
1E
0011110
3Ch
PD
PD
GND
31
1F
0011111
3Eh
PD
PD
PD
32
20
0100000
40h
PD
PD
FLT
33
21
0100001
42h
PD
PD
PU
34
22
0100010
44h
PD
PD
VDD
35
23
0100011
46h
PD
FLT
GND
36
24
0100100
48h
PD
FLT
PD
37
25
0100101
4Ah
PD
FLT
FLT
38
26
0100110
4Ch
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 5.
I2C-bus slave address …continued
Hardware selectable input pins I2C-bus slave address for PCU9955A
PCU9955A
Product data sheet
AD2
AD1
AD0
Decimal Hexadecimal Binary (A[6:0]) Address (R/W = 0)
PD
FLT
PU
39
27
0100111
4Eh
PD
FLT
VDD
40
28
0101000
50h
PD
PU
GND
41
29
0101001
52h
PD
PU
PD
42
2A
0101010
54h
PD
PU
FLT
43
2B
0101011
56h
PD
PU
PU
44
2C
0101100
58h
PD
PU
VDD
45
2D
0101101
5Ah
PD
VDD
GND
46
2E
0101110
5Ch
PD
VDD
PD
47
2F
0101111
5Eh
PD
VDD
FLT
48
30
0110000
60h
PD
VDD
PU
49
31
0110001
62h
PD
VDD
VDD
50
32
0110010
64h
FLT
GND
GND
51
33
0110011
66h
FLT
GND
PD
52
34
0110100
68h
FLT
GND
FLT
53
35
0110101
6Ah
FLT
GND
PU
54
36
0110110
6Ch
FLT
GND
VDD
55
37
0110111
6Eh
FLT
PD
GND
56
38
0111000
70h
FLT
PD
PD
57
39
0111001
72h
FLT
PD
FLT
58
3A
0111010
74h
FLT
PD
PU
59
3B
0111011
76h
FLT
PD
VDD
60
3C
0111100
78h
FLT
FLT
GND
61
3D
0111101
7Ah
FLT
FLT
PD
62
3E
0111110
7Ch
FLT
FLT
FLT
63
3F
0111111
7Eh
FLT
FLT
PU
64
40
1000000
80h
FLT
FLT
VDD
65
41
1000001
82h
FLT
PU
GND
66
42
1000010
84h
FLT
PU
PD
67
43
1000011
86h
FLT
PU
FLT
68
44
1000100
88h
FLT
PU
PU
69
45
1000101
8Ah
FLT
PU
VDD
70
46
1000110
8Ch
FLT
VDD
GND
71
47
1000111
8Eh
FLT
VDD
PD
72
48
1001000
90h
FLT
VDD
FLT
73
49
1001001
92h
FLT
VDD
PU
74
4A
1001010
94h
FLT
VDD
VDD
75
4B
1001011
96h
PU
GND
GND
76
4C
1001100
98h
PU
GND
PD
77
4D
1001101
9Ah
PU
GND
FLT
78
4E
1001110
9Ch
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 5.
I2C-bus slave address …continued
Hardware selectable input pins I2C-bus slave address for PCU9955A
PCU9955A
Product data sheet
AD2
AD1
AD0
Decimal Hexadecimal Binary (A[6:0]) Address (R/W = 0)
PU
GND
PU
79
4F
1001111
9Eh
PU
GND
VDD
80
50
1010000
A0h
PU
PD
GND
81
51
1010001
A2h
PU
PD
PD
82
52
1010010
A4h
PU
PD
FLT
83
53
1010011
A6h
PU
PD
PU
84
54
1010100
A8h
PU
PD
VDD
85
55
1010101
AAh
PU
FLT
GND
86
56
1010110
ACh
PU
FLT
PD
87
57
1010111
AEh
PU
FLT
FLT
88
58
1011000
B0h
PU
FLT
PU
89
59
1011001
B2h
PU
FLT
VDD
90
5A
1011010
B4h
PU
PU
GND
91
5B
1011011
B6h
PU
PU
PD
92
5C
1011100
B8h
PU
PU
FLT
93
5D
1011101
BAh
PU
PU
PU
94
5E
1011110
BCh
PU
PU
VDD
95
5F
1011111
BEh
PU
VDD
GND
96
60
1100000
C0h
PU
VDD
PD
97
61
1100001
C2h
PU
VDD
FLT
98
62
1100010
C4h
PU
VDD
PU
99
63
1100011
C6h
PU
VDD
VDD
100
64
1100100
C8h
VDD
GND
GND
101
65
1100101
CAh
VDD
GND
PD
102
66
1100110
CCh
VDD
GND
FLT
103
67
1100111
CEh
VDD
GND
PU
104
68
1101000
D0h
VDD
GND
VDD
105
69
1101001
D2h
VDD
PD
GND
106
6A
1101010
D4h
VDD
PD
PD
107
6B
1101011
D6h
VDD
PD
FLT
108
6C
1101100
D8h
VDD
PD
PU
109
6D
1101101
DAh
VDD
PD
VDD
110
6E
1101110
DCh
VDD
FLT
GND
111
6F
1101111
DEh
VDD
FLT
PD
112
70
1110000
E0h
VDD
FLT
FLT
113
71
1110001
E2h
VDD
FLT
PU
114
72
1110010
E4h
VDD
FLT
VDD
115
73
1110011
E6h
VDD
PU
GND
116
74
1110100
E8h
VDD
PU
PD
117
75
1110101
EAh
VDD
PU
FLT
118
76
1110110
ECh
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 5.
I2C-bus slave address …continued
Hardware selectable input pins I2C-bus slave address for PCU9955A
AD2
AD1
AD0
Decimal Hexadecimal Binary (A[6:0]) Address (R/W = 0)
VDD
PU
PU
119
PU
VDD
VDD
120
77
1110111
EEh
78
1111000[1]
F0h
F2h
VDD
VDD
GND
121
79
1111001[1]
VDD
VDD
PD
122
7A
1111010[1]
F4h
7B
1111011[1]
F6h
7C
1111100[1]
F8h
7D
1111101[1]
FAh
VDD
VDD
VDD
VDD
123
PU
VDD
VDD
[1]
FLT
124
VDD
125
See ‘Remark’ below.
Remark: Reserved I2C-bus addresses must be used with caution since they can interfere
with:
•
•
•
•
‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX)
write only
slave address(1)
A6
A5
A4
A3
A2
A1
A0
0
002aah728
(1) This slave address must match one of the 125 internal addresses as shown in Table 5.
Fig 3.
PCU9955A slave address
The last bit of the address byte defines the operation to be performed. Only writes to
PCU9955A are supported, therefore the last bit is set to 0. No read available with UFm
I2C-bus.
7.1.2 LED All Call I2C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000X
• Programmable through I2C-bus (volatile programming)
• At power-up, LED All Call I2C-bus address is enabled
See Section 7.3.11 “ALLCALLADR, LED All Call I2C-bus address” for more detail.
Remark: The default LED All Call I2C-bus address (E0h or 1110 000X) must not be used
as a regular I2C-bus slave address since this address is enabled at power-up. All of the
PCU9955As on the I2C-bus recognize the address if sent by the I2C-bus master.
PCU9955A
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.1.3 LED Sub Call I2C-bus addresses
• 3 different I2C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: ECh or 1110 110X
– SUBADR2 register: ECh or 1110 110X
– SUBADR3 register: ECh or 1110 110X
• Programmable through I2C-bus (volatile programming)
• At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 I2C-bus
addresses are disabled.
Remark: At power-up SUBADR1 identifies this device as a 16-channel driver.
See Section 7.3.10 “LED Sub Call I2C-bus addresses for PCU9955A” for more detail.
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus
slave addresses as long as they are disabled.
7.2 Control register
Following the slave address, LED All Call address or LED Sub Call address, the bus
master sends a byte to the PCU9955A, which is stored in the Control register.
The lowest 7 bits are used as a pointer to determine which register is accessed (D[6:0]).
The highest bit is used as Auto-Increment Flag (AIF).
This bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature.
register address
AIF
D6
D5
D4
D3
D2
Auto-Increment Flag
D1
D0
002aad850
reset state = 80h
Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 4.
Control register
When the Auto-Increment Flag is set (AIF = logic 1), the seven low-order bits of the
Control register are automatically incremented after a write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values of MODE1 register.
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 6.
Auto-Increment options
AIF
AI1[1]
AI0[1] Function
0
0
0
no Auto-Increment
1
0
0
Auto-Increment for registers (00h to 43h). D[6:0] roll over to 00h after the last
register 43h is accessed.
1
0
1
Auto-Increment for individual brightness registers only (08h to 17h).
D[6:0] roll over to 08h after the last register (17h) is accessed.
1
1
0
Auto-Increment for MODE1 to IREF15 control registers (00h to 27h).
D[6:0] roll over to 00h after the last register (27h) is accessed.
1
1
1
Auto-Increment for global control registers and individual brightness registers
(06h to 17h). D[6:0] roll over to 06h after the last register (17h) is accessed.
[1]
AI1 and AI0 come from MODE1 register.
Remark: Other combinations not shown in Table 6 (AIF + AI[1:0] = 001b, 010b and 011b)
are reserved and must not be used for proper device operation.
AIF + AI[1:0] = 000b is used when the same register must be accessed several times
during a single I2C-bus communication, for example, changes the brightness of a single
LED. Data is overwritten each time the register is accessed during a write operation.
AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for
example, power-up programming.
AIF + AI[1:0] = 101b is used when the 16 LED drivers must be individually programmed
with different values during the same I2C-bus communication, for example, changing color
setting to another color setting.
AIF + AI[1:0] = 110b is used when MODE1 to IREF15 registers must be programmed with
different settings during the same I2C-bus communication.
AIF + AI[1:0] = 111b is used when the 16 LED drivers must be individually programmed
with different values in addition to global programming.
Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits.
When the Control register is written, the register entry point determined by D[6:0] is the
first register that is addressed (write operation), and can be anywhere between 00h and
49h (as defined in Table 7). When AIF = 1, the Auto-Increment Flag is set and the rollover
value at which the register increment stops and goes to the next one is determined by AIF,
AI1 and AI0. See Table 6 for rollover values. For example, if MODE1 register bit AI1 = 0
and AI0 = 1 and if the Control register = 1001 0000, then the register addressing
sequence is (in hexadecimal):
10 11 … 17 08 09 … 17 08 09 … as long as the master
keeps sending data.
If MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1010 0010, then the
register addressing sequence is (in hexadecimal):
22 23 … 43 00 01 … 17 08 09 … as long as the master
keeps sending data.
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
If MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1000 0101, then the
register addressing sequence is (in hexadecimal):
05 06 … 17 08 09 … 17 08 09 … as long as the master
keeps sending data.
Remark: Writing to registers marked ‘not used’ are ignored.
7.3 Register definitions
Table 7.
Register summary
Register
number
(hexadecimal)
D6
D5
D4
D3
D2
D1
D0
Name
Type
Function
00h
0
0
0
0
0
0
0
MODE1
write only
Mode register 1
01h
0
0
0
0
0
0
1
MODE2
write only
Mode register 2
02h
0
0
0
0
0
1
0
LEDOUT0
write only
LED output state 0
03h
0
0
0
0
0
1
1
LEDOUT1
write only
LED output state 1
04h
0
0
0
0
1
0
0
LEDOUT2
write only
LED output state 2
05h
0
0
0
0
1
0
1
LEDOUT3
write only
LED output state 3
06h
0
0
0
0
1
1
0
GRPPWM
write only
group duty cycle control
07h
0
0
0
0
1
1
1
GRPFREQ
write only
group frequency
08h
0
0
0
1
0
0
0
PWM0
write only
brightness control LED0
09h
0
0
0
1
0
0
1
PWM1
write only
brightness control LED1
0Ah
0
0
0
1
0
1
0
PWM2
write only
brightness control LED2
0Bh
0
0
0
1
0
1
1
PWM3
write only
brightness control LED3
0Ch
0
0
0
1
1
0
0
PWM4
write only
brightness control LED4
0Dh
0
0
0
1
1
0
1
PWM5
write only
brightness control LED5
0Eh
0
0
0
1
1
1
0
PWM6
write only
brightness control LED6
0Fh
0
0
0
1
1
1
1
PWM7
write only
brightness control LED7
10h
0
0
1
0
0
0
0
PWM8
write only
brightness control LED8
11h
0
0
1
0
0
0
1
PWM9
write only
brightness control LED9
12h
0
0
1
0
0
1
0
PWM10
write only
brightness control LED10
13h
0
0
1
0
0
1
1
PWM11
write only
brightness control LED11
14h
0
0
1
0
1
0
0
PWM12
write only
brightness control LED12
15h
0
0
1
0
1
0
1
PWM13
write only
brightness control LED13
16h
0
0
1
0
1
1
0
PWM14
write only
brightness control LED14
17h
0
0
1
0
1
1
1
PWM15
write only
brightness control LED15
18h
0
0
1
1
0
0
0
IREF0
write only
output gain control register 0
19h
0
0
1
1
0
0
1
IREF1
write only
output gain control register 1
1Ah
0
0
1
1
0
1
0
IREF2
write only
output gain control register 2
1Bh
0
0
1
1
0
1
1
IREF3
write only
output gain control register 3
1Ch
0
0
1
1
1
0
0
IREF4
write only
output gain control register 4
1Dh
0
0
1
1
1
0
1
IREF5
write only
output gain control register 5
1Eh
0
0
1
1
1
1
0
IREF6
write only
output gain control register 6
1Fh
0
0
1
1
1
1
1
IREF7
write only
output gain control register 7
PCU9955A
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 7.
Register summary …continued
Register
number
(hexadecimal)
D6
D5
D4
D3
D2
D1
D0
Name
Type
Function
20h
0
1
0
0
0
0
0
IREF8
write only
output gain control register 8
21h
0
1
0
0
0
0
1
IREF9
write only
output gain control register 9
22h
0
1
0
0
0
1
0
IREF10
write only
output gain control register 10
23h
0
1
0
0
0
1
1
IREF11
write only
output gain control register 11
24h
0
1
0
0
1
0
0
IREF12
write only
output gain control register 12
25h
0
1
0
0
1
0
1
IREF13
write only
output gain control register 13
26h
0
1
0
0
1
1
0
IREF14
write only
output gain control register 14
27h
0
1
0
0
1
1
1
IREF15
write only
output gain control register 15
28h
0
1
0
1
0
0
0
RAMP_RATE_GRP0
write only
ramp enable and rate control
for group 0
29h
0
1
0
1
0
0
1
STEP_TIME_GRP0
write only
step time control for group 0
2Ah
0
1
0
1
0
1
0
HOLD_CNTL_GRP0
write only
hold ON/OFF time control for
group 0
2Bh
0
1
0
1
0
1
1
IREF_GRP0
write only
output gain control for group 0
2Ch
0
1
0
1
1
0
0
RAMP_RATE_GRP1
write only
ramp enable and rate control
for group 1
2Dh
0
1
0
1
1
0
1
STEP_TIME_GRP1
write only
step time control for group 1
2Eh
0
1
0
1
1
1
0
HOLD_CNTL_GRP1
write only
hold ON/OFF time control for
group 1
2Fh
0
1
0
1
1
1
1
IREF_GRP1
write only
output gain control for group 1
30h
0
1
1
0
0
0
0
RAMP_RATE_GRP2
write only
ramp enable and rate control
for group 2
31h
0
1
1
0
0
0
1
STEP_TIME_GRP2
write only
step time control for group 2
32h
0
1
1
0
0
1
0
HOLD_CNTL_GRP2
write only
hold ON/OFF time control for
group 2
33h
0
1
1
0
0
1
1
IREF_GRP2
write only
output gain control for group 2
34h
0
1
1
0
1
0
0
RAMP_RATE_GRP3
write only
ramp enable and rate control
for group 3
35h
0
1
1
0
1
0
1
STEP_TIME_GRP3
write only
step time control for group 3
36h
0
1
1
0
1
1
0
HOLD_CNTL_GRP3
write only
hold ON/OFF time control for
group 3
37h
0
1
1
0
1
1
1
IREF_GRP3
write only
output gain control for group 3
38h
0
1
1
1
0
0
0
GRAD_MODE_SEL0 write only
gradation mode select register
for channel 7 to channel 0
39h
0
1
1
1
0
0
1
GRAD_MODE_SEL1 write only
gradation mode select register
for channel 15 to channel 8
3Ah
0
1
1
1
0
1
0
GRAD_GRP_SEL0
write only
gradation group select for
channel 3 to channel 0
3Bh
0
1
1
1
0
1
1
GRAD_GRP_SEL1
write only
gradation group select for
channel 7 to channel 4
3Ch
0
1
1
1
1
0
0
GRAD_GRP_SEL2
write only
gradation group select for
channel 11 to channel 8
PCU9955A
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 7.
Register summary …continued
Register
number
(hexadecimal)
D6
D5
D4
D3
D2
D1
D0
Name
Type
Function
3Dh
0
1
1
1
1
0
1
GRAD_GRP_SEL3
write only
gradation group select for
channel 15 to channel 12
3Eh
0
1
1
1
1
1
0
GRAD_CNTL
write only
gradation control register for all
four groups
3Fh
0
1
1
1
1
1
1
OFFSET
write only
Offset/delay on LEDn outputs
40h
1
0
0
0
0
0
0
SUBADR1
write only
I2C-bus subaddress 1
41h
1
0
0
0
0
0
1
SUBADR2
write only
I2C-bus subaddress 2
42h
1
0
0
0
0
1
0
SUBADR3
write only
I2C-bus subaddress 3
43h
1
0
0
0
0
1
1
ALLCALLADR
write only
All Call I2C-bus address
44h
1
0
0
0
1
0
0
PWMALL
write only
brightness control for all LEDn
45h
1
0
0
0
1
0
1
IREFALL
write only
output gain control for all
registers IREF0 to IREF15
46h to 7Fh
-
-
-
-
-
-
-
reserved
write only
not used[1]
[1]
Writing to reserved registers are ignored.
7.3.1 MODE1 — Mode register 1
Table 8.
MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
AIF
W only
-
Not used.
6
AI1
W only
0*
Auto-Increment bit 1 = 0. Auto-increment range as defined in Table 6.
1
Auto-Increment bit 1 = 1. Auto-increment range as defined in Table 6.
5
AI0
W only
0*
Auto-Increment bit 0 = 0. Auto-increment range as defined in Table 6.
1
Auto-Increment bit 0 = 1. Auto-increment range as defined in Table 6.
0*
Normal mode[1].
1
Low-power mode. Oscillator off[2][3].
0
PCU9955A does not respond to I2C-bus subaddress 1.
1*
PCU9955A responds to I2C-bus subaddress 1.
0*
PCU9955A does not respond to I2C-bus subaddress 2.
1
PCU9955A responds to I2C-bus subaddress 2.
0*
PCU9955A does not respond to I2C-bus subaddress 3.
1
PCU9955A responds to I2C-bus subaddress 3.
0
PCU9955A does not respond to LED All Call I2C-bus address.
1*
PCU9955A responds to LED All Call I2C-bus address.
4
SLEEP
3
SUB1
2
SUB2
1
SUB3
0
[1]
ALLCALL
W only
W only
W only
W only
W only
It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.
[2]
No blinking, dimming or gradation control is possible when the oscillator is off.
[3]
The device must be reset if the LED driver output state is set to LDRx=11 after the device is set back to Normal mode.
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.2 MODE2 — Mode register 2
Table 9.
MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
-
-
-
not used (must write a logic 0)
6
-
-
-
not used (must write a logic 0)
5
DMBLNK
W only
0*
group control = dimming
1
group control = blinking
4
-
-
-
not used (must write a logic 0)
3
OCH
W only
0*
outputs change on STOP condition
1
outputs change on ACK, this ninth bit is always set to
1 by UFm I2C-bus master.
0*
linear adjustment for gradation control
1
exponential adjustment for gradation control
2
EXP_EN
W only
1
-
-
0*
reserved (must write a logic 0)
0
-
-
1*
reserved (must write a logic 1)
Brightness adjustment for gradation control is either linear or exponential by setting the
EXP_EN bit as shown in Figure 5. When EXP_EN = 0, linear adjustment scale is used.
When EXP_EN = 1, exponential scale is used.
002aah635
255
IREF_OUT
200
EXP_EN = 0
150
100
EXP_EN = 1
50
0
0
50
100
150
200
255
IREF_IN
Fig 5.
PCU9955A
Product data sheet
Linear and exponential adjustment curves
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.3 LEDOUT0 to LEDOUT3, LED driver output state
Table 10.
LEDOUT0 to LEDOUT3 - LED driver output state registers (address 02h to 05h)
bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
02h
LEDOUT0
7:6
LDR3
W only
10*
LED3 output state control
5:4
LDR2
W only
10*
LED2 output state control
3:2
LDR1
W only
10*
LED1 output state control
1:0
LDR0
W only
10*
LED0 output state control
7:6
LDR7
W only
10*
LED7 output state control
5:4
LDR6
W only
10*
LED6 output state control
3:2
LDR5
W only
10*
LED5 output state control
1:0
LDR4
W only
10*
LED4 output state control
7:6
LDR11
W only
10*
LED11 output state control
5:4
LDR10
W only
10*
LED10 output state control
3:2
LDR9
W only
10*
LED9 output state control
1:0
LDR8
W only
10*
LED8 output state control
7:6
LDR15
W only
10*
LED15 output state control
5:4
LDR14
W only
10*
LED14 output state control
3:2
LDR13
W only
10*
LED13 output state control
1:0
LDR12
W only
10*
LED12 output state control
03h
04h
05h
LEDOUT1
LEDOUT2
LEDOUT3
LDRx = 00 — LED driver x is off (x = 0 to 15).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled). The OE pin can be used as external dimming/blinking control in this state.
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register (default power-up state) or PWMALL register for all LEDn outputs.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
Remark: Setting the device in low power mode while being on group dimming/blinking
mode may cause the LED output state to be in an unknown state after the device is set
back to normal mode. The device must be reset and all register values reprogrammed.
7.3.4 GRPPWM, group duty cycle control
Table 11. GRPPWM - Group brightness control register (address 06h) bit description
Legend: * default value
Address
Register
Bit
Symbol
Access
Value
Description
06h
GRPPWM
7:0
GDC[7:0]
W only
1111 1111*
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed
frequency signal is superimposed with the 31.25 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
PCU9955A
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
General brightness for the 16 outputs is controlled through 255 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
67 ms to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
GDC 7:0
duty cycle = -------------------------256
(1)
7.3.5 GRPFREQ, group frequency
Table 12. GRPFREQ - Group frequency register (address 07h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
07h
GRPFREQ
7:0
GFRQ[7:0]
W only
0000 0000*
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz)
to FFh (16.8 s).
GFRQ 7:0 + 1
global blinking period = ---------------------------------------- s
15.26
(2)
7.3.6 PWM0 to PWM15, individual brightness control
Table 13. PWM0 to PWM15 - PWM registers 0 to 15 (address 08h to 17h) bit description
Legend: * default value.
PCU9955A
Product data sheet
Address
Register
Bit
Symbol
Access Value
Description
08h
PWM0
7:0
IDC0[7:0]
W only
0000 0000* PWM0 Individual Duty Cycle
09h
PWM1
7:0
IDC1[7:0]
W only
0000 0000* PWM1 Individual Duty Cycle
0Ah
PWM2
7:0
IDC2[7:0]
W only
0000 0000* PWM2 Individual Duty Cycle
0Bh
PWM3
7:0
IDC3[7:0]
W only
0000 0000* PWM3 Individual Duty Cycle
0Ch
PWM4
7:0
IDC4[7:0]
W only
0000 0000* PWM4 Individual Duty Cycle
0Dh
PWM5
7:0
IDC5[7:0]
W only
0000 0000* PWM5 Individual Duty Cycle
0Eh
PWM6
7:0
IDC6[7:0]
W only
0000 0000* PWM6 Individual Duty Cycle
0Fh
PWM7
7:0
IDC7[7:0]
W only
0000 0000* PWM7 Individual Duty Cycle
10h
PWM8
7:0
IDC8[7:0]
W only
0000 0000* PWM8 Individual Duty Cycle
11h
PWM9
7:0
IDC9[7:0]
W only
0000 0000* PWM9 Individual Duty Cycle
12h
PWM10
7:0
IDC10[7:0]
W only
0000 0000* PWM10 Individual Duty Cycle
13h
PWM11
7:0
IDC11[7:0]
W only
0000 0000* PWM11 Individual Duty Cycle
14h
PWM12
7:0
IDC12[7:0]
W only
0000 0000* PWM12 Individual Duty Cycle
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Table 13.
PWM0 to PWM15 - PWM registers 0 to 15 (address 08h to 17h) bit description
…continued
Address
Register
Bit
Symbol
Access Value
Description
15h
PWM13
7:0
IDC13[7:0]
W only
0000 0000* PWM13 Individual Duty Cycle
16h
PWM14
7:0
IDC14[7:0]
W only
0000 0000* PWM14 Individual Duty Cycle
17h
PWM15
7:0
IDC15[7:0]
W only
0000 0000* PWM15 Individual Duty Cycle
A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled
through 255 linear steps from 00h (0 % duty cycle = LED output off) to FEh
(99.2 % duty cycle = LED output at maximum brightness) and FFh (100 % duty cycle =
LED output completed ON). Applicable to LED outputs programmed with LDRx = 10 or 11
(LEDOUT0 to LEDOUT3 registers).
IDCx 7:0
duty cycle = --------------------------256
(3)
Remark: The first lower end 8 steps of PWM and the last (higher end) steps of PWM do
not have effective brightness control of LEDs due to edge rate control of LED output pins.
7.3.7 IREF0 to IREF15, LED output current value registers
These registers reflect the gain settings for output current for LED0 to LED15.
Table 14.
IREF0 to IREF15 - LED output gain control registers (address 18h to 27h)
bit description
Legend: * default value.
PCU9955A
Product data sheet
Address
Register
Bit
Access
Value
Description
18h
IREF0
7:0
W only
00h*
LED0 output current setting
19h
IREF1
7:0
W only
00h*
LED1 output current setting
1Ah
IREF2
7:0
W only
00h*
LED2 output current setting
1Bh
IREF3
7:0
W only
00h*
LED3 output current setting
1Ch
IREF4
7:0
W only
00h*
LED4 output current setting
1Dh
IREF5
7:0
W only
00h*
LED5 output current setting
1Eh
IREF6
7:0
W only
00h*
LED6 output current setting
1Fh
IREF7
7:0
W only
00h*
LED7 output current setting
20h
IREF8
7:0
W only
00h*
LED8 output current setting
21h
IREF9
7:0
W only
00h*
LED9 output current setting
22h
IREF10
7:0
W only
00h*
LED10 output current setting
23h
IREF11
7:0
W only
00h*
LED11 output current setting
24h
IREF12
7:0
W only
00h*
LED12 output current setting
25h
IREF13
7:0
W only
00h*
LED13 output current setting
26h
IREF14
7:0
W only
00h*
LED14 output current setting
27h
IREF15
7:0
W only
00h*
LED15 output current setting
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.8 Gradation control
Gradation control is designed to use four independent groups of registers to program the
full cycle of the gradation timing to implement on each selected channel. Each group has
four registers to define the ramp rate, step time, hold ON/OFF time, and final hold ON
current, as shown in Figure 6.
output current
(mA)
final current
set in
IREF_GRPx
hold ON
ramp-down
ramp-up
hold OFF
T1
T2
T3
T4
T1
time (second)
full cycle
002aah636
Fig 6.
Gradation timing
• The ‘final’ and ‘hold ON’ current is defined in IREF_GRPx register value (225 A if
REXT = 1 k, or 112.5 A if REXT = 2 k).
• Ramp rate value and enable/disable ramp operation is defined in
RAMP_RATE_GRPx register.
• Total number of ramp steps (or level changes) is calculated as
‘IREF_GRPx value’ ‘ramp rate value in RAMP_RATE_GRPx’. If the total number is
not an integer, the number is rounded up to the next integer.
• Time for each step is calculated as ‘cycle time’ ‘multiple factor’ bits in
STEP_TIME_GRPx register. Minimum time for one step is 0.5 ms (0.5 ms 1) and
maximum time is 512 ms (8 ms 64).
• The ramp-up or ramp-down time (T1 or T3) is calculated as
‘(total steps + 1)’ ‘step time’.
• Hold ON or OFF time (T2 or T4) is defined in HOLD_CNTL_GRPx register in the
range of 0/0.25/0.5/0.75/1/2/4/6 seconds.
• Gradation start or stop with single shot mode (one full cycle only) or continuous mode
(repeat full cycle) is defined in the GRAD_CNTL register for all groups.
• Each channel can be assigned to one of these four groups in the GRAD_GRP_SELx
register.
• Each channel can set either normal mode or gradation mode operation in the
GRAD_MODE_SELx register.
To enable the gradation operation, the following steps are required:
1. Program all gradation control registers except the gradation start bit in GRAD_CNTL
register.
2. Program either LDRx = 01 (LED fully ON mode) only, or LDRx = 10 or 11 (PWM
control mode) with individual brightness control PWMx register for duty cycle.
3. Program output current value IREFx register to non-zero, which enables LED output.
PCU9955A
Product data sheet
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
4. Set the gradation start bit in GRAD_CNTL register for enabling gradation operation.
7.3.8.1
RAMP_RATE_GRP0 to RAMP_RATE_GRP3, ramp rate control registers
Table 15.
RAMP_RATE_GRP[0:3] - Ramp enable and rate control registers (address 28h,
2Ch, 30h, 34h) for each group bit description
Legend: * default value.
Address
Register
Bit
Access
28h
RAMP_RATE_GRP0
7
W only
2Ch
RAMP_RATE_GRP1
30h
RAMP_RATE_GRP2
34h
RAMP_RATE_GRP3
6
5:0
7.3.8.2
W only
W only
Value
Description
0*
Ramp-up disable
1
Ramp-up enable
0*
Ramp-down disable
1
Ramp-down enable
0x00*
Ramp rate value per step is defined
from 1 (00h) to 64 (3Fh)[1][2]
[1]
Total number of ramp steps is defined as ‘IREF_GRP[7:0]’ ‘ramp_rate[5:0]’. (Round up to next integer if it
is not an integer number.)
[2]
Per step current increment or decrement is calculated by the (ramp_rate Iref), where the Iref reference
current is 112.5 A (REXT = 2 k) or 225 A (REXT = 1 k).
STEP_TIME_GRP0 to STEP_TIME_GRP3, step time control registers
Table 16.
STEP_TIME_GRP[0:3] - Step time control registers (address 29h, 2Dh, 31h, 35h)
for each group bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
29h
STEP_TIME_GRP0
7
W only
0*
reserved (must write a logic 0)
2Dh
STEP_TIME_GRP1
6
W only
0*
Cycle time is set to 0.5 ms
31h
STEP_TIME_GRP2
1
Cycle time is set to 8 ms
35h
STEP_TIME_GRP3
0x00*
Multiple factor per step, the
multiple factor is defined from
1 (00h) to 64 (3Fh)[1]
[1]
PCU9955A
Product data sheet
5:0
W only
Step time = cycle time (0.5 ms or 8 ms) multiple factor (1 ~ 64); minimum step time is 0.5 ms and
maximum step time is 512 ms.
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NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.8.3
HOLD_CNTL_GRP0 to HOLD_CNTL_GRP3, hold ON and OFF control registers
Table 17.
HOLD_CNTL_GRP[0:3] - Hold ON and OFF enable and time control registers
(address 2Ah, 2Eh, 32h, 36h) for each group bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
2Ah
HOLD_CNTL_GRP0
7
W only
0*
Hold ON disable
2Eh
HOLD_CNTL_GRP1
1
Hold ON enable
32h
HOLD_CNTL_GRP2
36h
HOLD_CNTL_GRP3
6
5:3
W only
W only
0*
Hold OFF disable
1
Hold OFF enable
000*
Hold ON time select:[1]
000: 0 s
001: 0.25 s
010: 0.5 s
011: 0.75 s
100: 1 s
101: 2 s
110: 4 s
111: 6 s
2:0
W only
000*
Hold OFF time select:[1]
000: 0 s
001: 0.25 s
010: 0.5 s
011: 0.75 s
100: 1 s
101: 2 s
110: 4 s
111: 6 s
[1]
7.3.8.4
Hold ON or OFF minimum time is 0 s and maximum time is 6 s.
IREF_GRP0 to IREF_GRP3, output gain control
Table 18.
IREF_GRP[0:3] - Final and hold ON output gain setting registers
(address 2Bh, 2Fh, 33h, 37h) for each group bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
2Bh
IREF_GRP0
7:0
W only
00h*
2Fh
IREF_GRP1
Final ramp-up and hold ON output
current gain setting[1]
33h
IREF_GRP2
37h
IREF_GRP3
[1]
PCU9955A
Product data sheet
Output current = Iref IREF_GRPx[7:0], where Iref is reference current. If REXT = 2 k, then Iref = 112.5 A,
or if REXT = 1 k, then Iref = 225 A.
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.8.5
GRAD_MODE_SEL0 to GRAD_MODE_SEL1, gradation mode select registers
Table 19.
GRAD_MODE_SEL[0:1] - Gradation mode select register for channel 15 to
channel 0 (address 38h, 39h) bit description
Legend: * default value.
Address
Register
38h
GRAD_MODE_SEL0 7:0
39h
7.3.8.6
Bit
GRAD_MODE_SEL1 7:0
Access
Value
Description[1][2]
W only
00*
Normal operation mode for
channel 7 to channel 0
FFh
Gradation operation mode for
channel 7 to channel 0
00*
Normal operation mode for
channel 15 to channel 8
FFh
Gradation operation mode for
channel 15 to channel 8
W only
[1]
Each bit represents one channel that can set either 0 for normal mode (use IREFx to set individual LED
output current), or 1 for gradation mode (use IREF_GRPx to set group LEDs output current.).
[2]
In gradation mode, it only affects the source of the IREF current level and does not affect the PWMx
operation or LEDOUTx register function. It is possible to use the gradation feature, individual PWMx and
group PWM simultaneously.
GRAD_GRP_SEL0 to GRAD_GRP_SEL3, gradation group select registers
Table 20.
GRAD_GRP_SEL[0:3] - Gradation group select register for channel 15 to
channel 0 (address 3Ah, 3Bh, 3Ch, 3Dh) bit description
Legend: * default value.
Access
Value Description[1]
GRAD_GRP_SEL0 7:6
W only
00*
Gradation group select for LED3 output
5:4
W only
00*
Gradation group select for LED2 output
3:2
W only
00*
Gradation group select for LED1 output
Address Register
3Ah
3Bh
3Ch
3Dh
[1]
PCU9955A
Product data sheet
Bit
1:0
W only
00*
Gradation group select for LED0 output
GRAD_GRP_SEL1 7:6
W only
01*
Gradation group select for LED7 output
5:4
W only
01*
Gradation group select for LED6 output
3:2
W only
01*
Gradation group select for LED5 output
1:0
W only
01*
Gradation group select for LED4 output
GRAD_GRP_SEL2 7:6
W only
10*
Gradation group select for LED11 output
5:4
W only
10*
Gradation group select for LED10 output
3:2
W only
10*
Gradation group select for LED9 output
1:0
W only
10*
Gradation group select for LED8 output
GRAD_GRP_SEL3 7:6
W only
11*
Gradation group select for LED15 output
5:4
W only
11*
Gradation group select for LED14 output
3:2
W only
11*
Gradation group select for LED13 output
1:0
W only
11*
Gradation group select for LED12 output
LED[3:0] outputs default assigned to group 0; LED[7:4] outputs default assigned to group 1;
LED[11:8] outputs default assigned to group 2; LED[15:12] outputs default assigned to group 3.
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.8.7
GRAD_CNTL, Gradation control register
Table 21.
GRAD_CNTL - Gradation control register for group 3 to group 0 (address 3Eh)
bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
3Eh
GRAD_CNTL
7
W only
0*
Gradation stop for group 3[1]
1
Gradation start for group 3[2]
6
5
4
3
2
1
0
PCU9955A
Product data sheet
W only
W only
W only
W only
W only
W only
W only
0*
Single shot operation for group 3
1
Continuous operation for group 3
0*
Gradation stop for group 2[1]
1
Gradation start for group 2[2]
0*
Single shot operation for group 2
1
Continuous operation for group 2
0*
Gradation stop for group 1[1]
1
Gradation start for group 1[2]
0*
Single shot operation for group 1
1
Continuous operation for group 1
0*
Gradation stop for group 0[1]
1
Gradation start for group 0[2]
0*
Single shot operation for group 0
1
Continuous operation for group 0
[1]
When the gradation operation is forced to stop by writing 0, the output current stops immediately and is
frozen at the last output level.
[2]
Writing 1 to this bit starts the gradation operation, and writing 0 to this bit forces the gradation operation to
stop when single mode is not completed or continuous mode is running.
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NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.8.8
Ramp control — equation and calculation example
IREF_GRPx
(max. = 255)
225 μA × 250 = 56.25 mA
250
200
150
s1
100
50
(step time)
(32 ms)
0
End with
current zero
t1
time
ramp-up
hold ON
ramp-down
hold OFF
(T = 192 ms)
(0.25 s)
(T = 192 ms)
(0.5 s)
Start from
current zero
Fig 7.
(step current)
(11.25 mA)
full cycle
002aah637
Ramp calculation example 1
• t1 (step time) = cycle time multiple factor, where:
– Cycle time = 0.5 ms (fast ramp) or 8 ms (slow ramp) in STEP_TIME_GRPx[6]
– Multiple factor = 6-bit, from 1 (00h) to 64 (3Fh) counts in STEP_TIME_GRPx[5:0]
• s1 (step current) = ramp_rate Iref, where:
– ramp_rate = 6-bit, from 1 (00h) to 64 (3Fh) counts in RAMP_RATE_GRPx[5:0]
– Iref = reference current either 112.5 A if REXT = 2 k, or 225 A if REXT = 1 k
• S (total steps) = (IREF_GRPx / ramp_rate), where:
– IREF_GRPx = output current gain setting, 8-bit, up to 255 counts
– ramp_rate = 6-bit, up to 64 counts in RAMP_RATE_GRPx[5:0]
– If it is not an integer, then round up to next integer number.
• T (ramp time) = (S (total steps) + 1) t1 (step time)
– Ramp-up time starts from zero current and ends at the maximum current
– Ramp-down time starts from the maximum current and ends at the zero current
Calculation example 1 (Figure 7):
• Assumption:
– Iref = 225 A if REXT = 1 k
– Output hold ON current = 225 A 250 = 56.25 mA (IREF_GRPx[7:0] = FAh)
– Cycle time = 0.5 ms (STEP_TIME_GRPx[6] = 0)
– Multiple factor = 64 (STEP_TIME_GRPx[5:0] = 3Fh)
– Ramp rate = 50 (RAMP_RATE_GRPx[5:0] = 31h)
– Hold ON = 0.25 s (HOLD_CNTL_GRPx[5:3] = 001)
– Hold OFF = 0.5 s (HOLD_CNTL_GRPx[2:0] = 010)
• t1 (step time) = cycle time (0.5 ms) multiple (64) = 32 ms
• Step current = ramp_rate Iref = 50 225 A = 11.25 mA
PCU9955A
Product data sheet
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
• S (total steps) = (IREF_GRPx ramp_rate) = (250 50) = 5 steps
• T (ramp time) = (S + 1) t1 = 6 32 ms = 192 ms
IREF_GRPx
(max. = 255)
240
(54 mA)
200
t1
(step time)
(32 ms)
150
190
140
s1
100
(step current)
90
50
(11.25 mA)
0
40
time
ramp-up
hold ON
ramp-down
hold OFF
(T = 192 ms)
(0.25 s)
(T = 192 ms)
(0.5 s)
full cycle
Fig 8.
002aah674
Ramp calculation example 2
Calculation example 2:
• Assumption:
– Iref = 225 A if REXT = 1 k
– Output hold ON current = 225 A 240 = 54 mA (IREF_GRPx[7:0] = F0h)
– Cycle time = 0.5 ms (STEP_TIME_GRPx[6] = 0)
– Multiple factor = 64 (STEP_TIME_GRPx[5:0] = 3Fh)
– Ramp rate = 50 (RAMP_RATE_GRPx[5:0] = 31h)
– Hold ON = 0.25 s (HOLD_CNTL_GRPx[5:3] = 001)
– Hold OFF = 0.5 s (HOLD_CNTL_GRPx[2:0] = 010)
• t1 (step time) = cycle time (0.5 ms) multiple (64) = 32 ms
• Step current = ramp_rate Iref = 50 225 A = 11.25 mA (except the last one)
• S (total steps) = IREF_GRPx ramp_rate = 240 50 = 4.8 steps (round up to next
integer) = 5 steps
• T (ramp time) = (S + 1) t1 = 6 32 ms = 192 ms
PCU9955A
Product data sheet
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
(enable bit)
Ramp UP
(enable bit)
Hold ON
(enable bit)
Ramp DOWN
(enable bit)
Hold OFF
1
0
0
0
0
2
1
0
0
0
3
0
1
0
0
4
1
1
0
0
5
0
0
1
0
6
1
0
1
0
7
0
1
1
0
8
1
1
1
0
9
0
0
0
1
10
1
0
0
1
11
0
1
0
1
12
1
1
0
1
13
0
0
1
1
14
1
0
1
1
15
0
1
1
1
16
1
1
1
1
Single shot waveform
Continuous waveform
wavefrom when initial current is not zero
the moment when START bit changes to 0
(single shot sequence ends)
Fig 9.
PCU9955A
Product data sheet
002aah740
Gradation output waveform in single shot or continuous mode
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PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.3.9 OFFSET — LEDn output delay offset register
Table 22. OFFSET - LEDn output delay offset register (address 3Fh) bit description
Legend: * default value.
Address
Register
3Fh
OFFSET
Bit
Access
Value
Description
7:4
-
0000*
not used (must write a logic 0)
3:0
W only
1000*
LEDn output delay offset factor
The PCU9955A can be programmed to have turn-on delay between LED outputs. This
helps to reduce peak current for the VDD supply and reduces EMI.
The order in which the LED outputs are enabled is always the same (channel 0 enables
first and channel 15 enables last).
OFFSET control register bits [3:0] determine the delay used between the turn-on times as
follows:
0000 = no delay between outputs (all on, all off at the same time)
0001 = delay of 1 clock cycle (125 ns) between successive outputs
0010 = delay of 2 clock cycles (250 ns) between successive outputs
0011 = delay of 3 clock cycles (375 ns) between successive outputs
:
1111 = delay of 15 clock cycles (1.875 s) between successive outputs
Example: If the value in the OFFSET register is 1000, the corresponding delay =
8 125 ns = 1 s delay between successive outputs.
channel 0 turns on at time 0 s
channel 1 turns on at time 1 s
channel 2 turns on at time 2 s
channel 3 turns on at time 3 s
channel 4 turns on at time 4 s
channel 5 turns on at time 5 s
channel 6 turns on at time 6 s
channel 7 turns on at time 7 s
channel 8 turns on at time 8 s
channel 9 turns on at time 9 s
channel 10 turns on at time 10 s
channel 11 turns on at time 11 s
channel 12 turns on at time 12 s
channel 13 turns on at time 13 s
channel 14 turns on at time 14 s
channel 15 turns on at time 15 s
PCU9955A
Product data sheet
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7.3.10 LED Sub Call I2C-bus addresses for PCU9955A
SUBADR1 to SUBADR3 - I2C-bus subaddress registers 1 to 3 (address 40h to
42h) bit description
Legend: * default value.
Table 23.
Address
Register
Bit
Symbol
Access Value
Description
40h
SUBADR1
7:1
A1[7:1]
W only
1110 110*
I2C-bus subaddress 1
0
A1[0]
-
0*
reserved (must write a logic 0)
A2[7:1]
W only
1110 110*
I2C-bus subaddress 2
41h
SUBADR2
7:1
0
A2[0]
-
0*
reserved (must write a logic 0)
42h
SUBADR3
7:1
A3[7:1]
W only
1110 110*
I2C-bus subaddress 3
0
A3[0]
-
0*
reserved (must write a logic 0)
Default power-up values are ECh, ECh, ECh. At power-up, SUBADR1 is enabled while
SUBADR2 and SUBADR3 are disabled. The power-up default bit subaddress of ECh
indicates that this device is a 16-channel LED driver.
All three subaddresses are programmable. Once subaddresses have been programmed
to their right values, SUBx bits must be set to logic 1 in order to have the device respond
to these addresses (bit[3:1], MODE1 register). When SUBx is set to logic 1, the
corresponding I2C-bus subaddress can be used during an I2C-bus write sequence.
7.3.11 ALLCALLADR, LED All Call I2C-bus address
ALLCALLADR - LED All Call I2C-bus address register (address 43h) bit
description
Legend: * default value.
Table 24.
Address
Register
Bit
Symbol
Access Value
Description
43h
ALLCALLADR
7:1
AC[7:1]
W only
1110 000*
ALLCALL I2C-bus
address register
0
AC[0]
-
0*
reserved
(must write a logic 0)
The LED All Call I2C-bus address allows all the PCU9955As on the bus to be
programmed at the same time (ALLCALL bit in register MODE1 must be equal to logic 1
[power-up default state]). This address is programmable through the I2C-bus and can be
used during an I2C-bus write sequence. The register address can also be programmed as
a Sub Call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in
ALLCALLADR register is set to 0.
If ALLCALL bit = 0 in MODE1 register, the device does not recognize the address
programmed in register ALLCALLADR.
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7.3.12 PWMALL — brightness control for all LEDn outputs
When programmed, the value in this register is used for PWM duty cycle for all the LEDn
outputs and is reflected in PWM0 through PWM15 registers.
Table 25.
PWMALL - brightness control for all LEDn outputs register (address 44h)
bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
44h
PWMALL
7:0
write only
0000 0000*
duty cycle for all LEDn outputs
Remark: Write to any of the PWM0 to PWM15 registers overwrites the value in
corresponding PWMn register programmed by PWMALL.
7.3.13 IREFALL register: output current value for all LED outputs
The output current setting for all outputs is held in this register. When this register is
written to or updated, all LED outputs are set to a current corresponding to this register
value.
Writes to IREF0 to IREF15 overwrite the output current settings.
Table 26. IREFALL - Output gain control for all LED outputs (address 45h) bit description
Legend: * default value.
Address
Register
Bit
Access
Value
Description
45h
IREFALL
7:0
write only
00h*
Current gain setting for all LED outputs.
7.3.14 LED driver constant current outputs
In LED display applications, PCU9955A provides nearly no current variations from
channel to channel and from device to device. The maximum current skew between
channels is less than 4 % and less than 6 % between devices.
7.3.14.1
Adjusting output current
The PCU9955A scales up the reference current (Iref) set by the external resistor (Rext) to
sink the output current (IO) at each output port. The maximum output current for the
outputs can be set using Rext. In addition, the constant value for current drive at each of
the outputs is independently programmable using command registers IREF0 to IREF15.
Alternatively, programming the IREFALL register allows all outputs to be set at one current
value determined by the value in IREFALL register.
Equation 4 and Equation 5 can be used to calculate the minimum and maximum constant
current values that can be programmed for the outputs for a chosen Rext.
900 mV 1
I O _LED_MIN = ------------------- --- minimum constant current
4
R ext
(4)
900 mV 255
I O _LED_MAX = 255 I O _LED_MIN = ------------------- ---------
R ext
4
(5)
900 mV 1
For a given IREFx setting, I O _LED = IREFx ------------------- --- .
4
R ext
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
002aag288
80
IREFx = 255
IO(LEDn)
(mA)
60
40
20
0
1
2
4
3
5
6
8
7
9
10
Rext (kΩ)
IO(LEDn) (mA) = IREFx (0.9 / 4) / Rext (k)
maximum IO(LEDn) (mA) = 255 (0.9 / 4) / Rext (k)
Remark: Default IREFx at power-up = 0.
Fig 10. Maximum ILED versus Rext
Example 1: If Rext = 1 k, IO_LED_MIN = 225 A, IO_LED_MAX = 57.375 mA (as shown
in Figure 11).
So each channel can be programmed with its individual IREFx in 256 steps and in 225 A
increments to a maximum output current of 57.375 mA independently.
002aah691
60
IO(target)
(mA)
50
57.375
40
30
20
10
0
0
32
64
96
128
160
192
224
255
IREFx[7:0] value
Fig 11. IO(target) versus IREFx value with Rext = 1 k
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Example 2: If Rext = 2 k, IO_LED_MIN = 112.5 A, IO_LED_MAX = 28.687 mA (as
shown in Figure 12).
So each channel can be programmed with its individual IREFx in 256 steps and in
112.5 A increments to a maximum output channel of 28.687 mA independently.
002aah667
30
IO(target)
(mA)
20
10
0
0
32
64
96
128
160
192
255
224
IREFx[7:0] value
Fig 12. IO(target) versus IREFx value with Rext = 2 k
7.3.15 Overtemperature protection
If the PCU9955A chip temperature exceeds its limit (Tth(otp) rising, see Table 29), all output
channels are disabled until the temperature drops below its limit minus a small hysteresis
(Tth(otp) hysteresis), see Table 29). Once the die temperature reduces below the Tth(otp)
rising Tth(otp) hysteresis, the chip returns to the same condition it was prior to the
overtemperature event.
7.4 Active LOW output enable input
The active LOW output enable (OE) pin on PCU9955A allows it to enable or disable all
the LED outputs at the same time.
• When a LOW level is applied to OE pin, all the LED outputs are enabled.
• When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.
The OE pin can be used as a synchronization signal to switch on/off several PCU9955A
devices at the same time when LED drive output state is set fully ON (LDRx = 01 in
LEDOUTx register) in these devices. This requires an external clock reference that
provides blinking period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it results in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it results in an undefined
dimming pattern.
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7.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCU9955A in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCU9955A registers and I2C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be pulled lower
than 1 V and stay LOW for longer than 20 s. The device resets itself, and allow 2 ms for
the device to wake up fully.
Remark: In order to guarantee a proper Power-On Reset operation for device, the rising
rate of VDD must be less than 3 ms per 1 V or less than 10 ms from 0 V to 3.3 V. Also,
VDD must return to 0 V for a minimum of 10 ms before rising again while VDD power is
re-cycling.
7.6 Hardware reset recovery
When a reset of PCU9955A is activated using an active LOW input on the RESET pin, a
reset pulse width of 2.5 s minimum is required. The maximum wait time after RESET pin
is released is 1.5 ms.
7.7 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to
the power-up state value through a specific formatted I2C-bus command. To be performed
correctly, it implies that the I2C-bus is functional and that there is no device hanging the
bus.
The maximum wait time after software reset is 1 ms.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call address ‘0000 000’ with the R/W bit set to ‘0’ (write only) is
sent by the I2C-bus master.
3. The PCU9955A device is a UFm write-only I2C-bus, no acknowledge is returned to
the I2C-bus master.
4. Once the General Call address has been sent, the master sends 1 byte with 1 specific
value (SWRST data byte 1): Byte 1 = 06h.
If more than 1 byte of data is sent, they are ignored by the PCU9955A.
5. Once the correct byte (SWRST data byte 1) has been sent, the master sends a STOP
condition to end the SWRST function: the PCU9955A then resets to the default value
(power-up value) and is ready to be addressed again within the specified bus free
time (tBUF).
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
General Call address
S
0
0
0
0
START condition
0
0
0
SWRST data byte 1
0
1
0
0
this bit
always = 1
0
0
0
1
1
0
1
P
this bit
always = 1
STOP
condition
002aah729
Fig 13. SWRST Call
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
7.8 Individual brightness control with group dimming/blinking
A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is
used to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 16 LED outputs LED0 to LED15).
• A lower 122 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
• A programmable frequency signal from 15 Hz to every 16.8 seconds (8 bits,
256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a
global blinking control.
1
2
3
4
5
6
7
8
9 10 11 12
251
252
253
254
255
256
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn)
N × 125 ns
with N = (0 to 255)
(PWMx Register)
M × 256 × 125 ns
with M = (0 to 255)
(GRPPWM Register)
256 × 125 ns = 32 μs
(31.25 kHz)
Group Dimming signal
256 × 256 × 125 ns = 8.19 ms (122 Hz)
1
2
3
4
5
6
7
8
resulting Brightness + Group Dimming signal
002aaf935
Minimum pulse width for LEDn Brightness Control is 125 ns.
Minimum pulse width for Group Dimming is 32 s.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has 1 pulse of the
LED Brightness Control signal (pulse width = N 125 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 8.
Fig 14. Brightness + Group Dimming signals
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
8. Characteristics of the PCU9955A Ultra Fast-mode I2C-bus
The PCU9955A LED controller uses the new Ultra Fast-mode (UFm) I2C-bus to
communicate with the UFm I2C-bus capable host controller. Like the Standard mode and
Fast-mode Plus (Fm+) I2C-bus, it uses two lines for communication. They are a serial data
line (USDA) and a serial clock line (USCL). The UFm is a unidirectional bus, which is
capable of higher frequency (up to 5 MHz). The UFm I2C-bus slave devices operate in
receive-only mode. That is, only I2C writes to PCU9955A are supported.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the USDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Figure 15).
USDA
USCL
data line
stable;
data valid
change
of data
allowed
002aaf113
Fig 15. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16).
USDA
USCL
S
P
START condition
STOP condition
002aaf114
Fig 16. Definition of START and STOP conditions
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 17).
USDA
MASTER UFm
TRANSMITTER
USCL
SLAVE UFm
RECEIVER
SLAVE UFm
RECEIVER
SLAVE UFm
RECEIVER
002aaf100
Fig 17. System configuration
8.3 Data transfer
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by 1 bit that is always
set to 1. The master generates an extra related clock pulse.
USDA data output by
master UFm transmitter
USCL clock from master
1
2
8
9
S
START
condition
002aaf101
Fig 18. Data transfer
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
9. Bus transactions
slave address(1)
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
1
X D6 D5 D4 D3 D2 D1 D0 1
register address(2)
write
only
data for register D[7:0]
Auto-Increment flag
1
this bit
always = 1
P
this bit
always = 1
this bit
always = 1
STOP
condition
002aah730
(1) See Table 5 for I2C-bus slave address.
(2) See Table 7 for register definition.
Fig 19. Write to a specific register
slave address
S A6 A5 A4 A3 A2 A1 A0 0
START condition
MODE1 register data(1)
control register
1
write
only
this bit
always = 1
1
0
0
0
0
0
0
0
MODE1
register selection
Auto-Increment on
1
this bit
always = 1
MODE2 register data
1
1
this bit
always = 1
this bit
always = 1
(cont.)
ALLCALLADR register data
(cont.)
1
P
this bit
always = 1
STOP
condition
002aah731
(1) AI1, AI0 = 00. See Table 6 for Auto-Increment options.
Remark: Care should be taken to load the appropriate value here in the AI1 and AI0 bits of the MODE1 register for
programming the part with the required Auto-Increment options.
Fig 20. Write to all registers using the Auto-Increment feature
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PCU9955A
Product data sheet
slave address
control register
START condition
1
0
0
0
1
0
0
0
PWM0
register selection
write
only
this bit
always = 1
PWM14 register data
(cont.)
1
PWM1 register data
1
this bit
always = 1
1
1
this bit
always = 1
this bit
always = 1
(cont.)
Auto-Increment on
register rollover
PWM15 register data
PWM0 register data
PWM14 register data
PWM15 register data
1
1
1
1
1
this bit
always = 1
this bit
always = 1
this bit
always = 1
this bit
always = 1
this bit
always = 1
P
STOP
condition
002aah732
Fig 21. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
PCU9955A
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This example assumes that AIF + AI[1:0] = 101b.
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Rev. 3.1 — 29 June 2015
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S A6 A5 A4 A3 A2 A1 A0 0
PWM0 register data
PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
slave address(1)
new LED All Call I2C address(2)
control register
sequence (A) S A6 A5 A4 A3 A2 A1 A0 0
START condition
1
1
1
0
0
0
0
1
1
ALLCALLADR
register selection
write
only
1
1
0
1
0
1
0
this bit
always = 1
0
1
0
START condition
1
0
1
1
write
only
this bit
always = 1
P
STOP condition
control register
0
1
multiple LEDs are on at the 9th bit(3)
LED All Call I2C address
1
X
this bit
always = 1
Auto-Increment on
this bit
always = 1
sequence (B) S
1
1
0
0
0
0
0
LEDOUT0 register (LED fully ON)
1
0
LEDOUT0
register selection
1
0
1
0
1
0
1
0
1
1 (cont.)
this bit
always = 1
this bit
always = 1
Auto-Increment on
multiple LEDs are on at the 9th bit(3)
LEDOUT3 register (LED fully ON)
(cont.)
0
1
0
1
0
1
0
1
1
this bit
always = 1
P
STOP condition
002aah733
(1) In this example, several PCU9955As are used and the same sequence (A) (above) is sent to each of them.
(2) ALLCALL bit in MODE1 register is previously set to 1 for this example.
(3) OCH bit in MODE2 register is previously set to 1 for this example.
Fig 22. LED All Call I2C-bus address programming and LED All Call sequence example
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
10. Application design-in information
VDD = 3.3 V or 5.0 V
10 kΩ(1)
UFm I2C-BUS/
SMBus MASTER
1.1 kΩ
(optional)
up to 20 V
VDD
USDA
USDA
USCL
USCL
OE
LED1
OE
RESET
LED0
LED2
RESET
LED3
LED4
PCU9955A
LED5
LED6
LED7
REXT
LED8
ISET
LED9
LED10
AD0(2)
LED11
AD1
AD2
LED12
LED13
LED14
VSS
LED15
VSS
C
10 μF
002aah734
(1) If control signal from the master is open-drain, then OE requires pull-up resistor.
(2) I2C-bus address = 1101001 when AD0, AD2 tied to VDD and AD1 tied to VSS (see Table 5).
Fig 23. Typical application
10.1 Thermal considerations
Since the PCU9955A device integrates 16 linear current sources, thermal considerations
should be taken into account to prevent overheating, which can cause the device to go
into thermal shutdown.
Perhaps the major contributor for device’s overheating is the LED forward voltage
mismatch. This is because it can cause significant voltage differences between the LED
strings of the same type (for example, 2 V to 3 V), which ultimately translates into higher
power dissipation in the device. The voltage drop across the LED channels of the device
is given by the difference between the supply voltage and the LED forward voltage of each
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
LED string. Reducing this to a minimum (for example, 0.8 V) helps to keep the power
dissipation down. Therefore LEDs binning is recommended to minimize LED voltage
forward variation and reduce power dissipation in the device.
In order to ensure that the device does not go into thermal shutdown when operating
under certain application conditions, its junction temperature (Tj) should be calculated to
ensure that is below the overtemperature threshold limit (130 C). The Tj of the device
depends on the ambient temperature (Tamb), device total power dissipation (Ptot), and
thermal resistance.
The device junction temperature can be calculated by using the following equation:
T j = T amb + R th j-a P tot
(6)
where:
Tj = junction temperature
Tamb = ambient temperature
Rth(j-a) = junction to ambient thermal resistance
Ptot = (device) total power dissipation
An example of this calculation is show below:
Conditions:
Tamb = 50 C
Rth(j-a) = 39 C/W (per JEDEC 51 standard for multilayer PCB)
ILED = 30 mA / channel
IDD(max) = 20 mA
VDD = 5 V
LEDs per channel = 5 LEDs / channel
LED VF(typ) = 3 V per LED (15 V total for 5 LEDs in series)
LED VF mismatch = 0.2 V per LED (1 V total for 5 LEDs in series)
Vreg(drv) = 0.8 V (This is present only in the LED string with the highest LED forward
voltage.)
Vsup = LED VF(typ) + LED VF mismatch + Vreg(drv) = 15 V + 1 V + 0.8 V = 16.8 V
Ptot calculation:
Ptot = IC_power + LED drivers_power;
IC_power = (IDD VDD)
IC_power = (0.02 A 5 V) = 0.1 W
LED drivers_power = [(16 1) (ILED) (LED VF mismatch + Vreg(drv))] +
(ILED Vreg(drv))
LED drivers_power = [15 0.03 A (1 V + 0.8 V)] + (0.03 A 0.8 V)] = 0.834 W
Ptot = 0.1 W + 0.834 W = 0.934 W
PCU9955A
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Tj calculation:
Tj = Tamb + Rth(j-a) Ptot
Tj = 50 C + (39 C/W 0.934 W) = 86.426 C
This confirms that the junction temperature is below the minimum overtemperature
threshold of 130 C, which ensures the device does not go into thermal shutdown under
these conditions.
It is important to mention that the value of the thermal resistance junction-to-ambient
(Rth(j-a)) strongly depends in the PCB design. Therefore, the thermal pad of the device
should be attached to a large enough PCB copper area to ensure proper thermal
dissipation (similar to JEDEC 51 standard). Several thermal vias in the PCB thermal pad
should be used as well to increase the effectiveness of the heat dissipation (for example,
15 thermal vias). The thermal vias should be distributed evenly in the PCB thermal pad.
Finally, it is important to point out that this calculation should be taken as a reference only
and therefore evaluations should still be performed under the application environment and
conditions to confirm proper system operation.
11. Limiting values
Table 27. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VDD
supply voltage
Conditions
0.5
+6.0
V
VI/O
voltage on an input/output pin
VSS 0.5
5.5
V
Vdrv(LED)
LED driver voltage
VSS 0.5
20
V
IO(LEDn)
output current on pin LEDn
-
65
mA
ISS
ground supply current
-
1.0
A
Ptot
total power dissipation
Tamb = 25 C
-
2.56
W
Tamb = 85 C
-
1.03
W
65
+150
C
40
+85
C
40
+125
C
Tstg
storage temperature
Tamb
ambient temperature
Tj
junction temperature
operating
12. Thermal characteristics
Table 28.
Symbol
Rth(j-a)
[1]
Thermal characteristics
Parameter
Conditions
thermal resistance from junction to ambient
HTSSOP28
[1]
Typ
Unit
39
C/W
Per JEDEC 51 standard for multilayer PCB and Wind Speed (m/s) = 0.
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13. Static characteristics
Table 29. Static characteristics
VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Min
Typ[1]
Max
Unit
3
-
5.5
V
Rext = 2 k; LED[15:0] = off;
IREFx = 00h
-
11
12
mA
Rext = 1 k; LED[15:0] = off;
IREFx = 00h
-
13
14
mA
Rext = 2 k; LED[15:0] = on;
IREFx = FFh
-
15
19
mA
Rext = 1 k; LED[15:0] = on;
IREFx = FFh
-
17
21
mA
VDD = 3.3 V
-
170
600
A
VDD = 5.5 V
-
170
700
A
-
2
-
V
-
1
-
V
-
+0.3VDD V
Conditions
Supply
VDD
supply voltage
IDD
supply current
Istb
VPOR
VPDR
standby current
power-on reset voltage
power-down reset voltage
on pin VDD; operating mode;
fSCL = 1 MHz
on pin VDD; no load; fSCL = 0 Hz;
MODE1[4] = 1; VI = VDD
no load; VI = VDD or VSS
no load; VI = VDD or VSS
[2]
Inputs USCL, USDA
VIL
LOW-level input voltage
0.5
VIH
HIGH-level input voltage
0.7VDD -
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
6
10
pF
VO = 0.8 V; IREFx = 80h; Rext = 1 k
25
-
30
mA
VO = 0.8 V; IREFx = FFh; Rext = 1 k
50
-
60
mA
5.5
V
Current controlled outputs (LED[15:0])
IO(LEDn)
output current on pin LEDn
IO
output current variation
VDD = 3.0 V; Tamb = 25 C; VO = 0.8 V;
IREFx = 80h; Rext = 1 k; guaranteed
by design
between bits (different ICs, same
channel)
[3]
-
-
6
%
between bits (2 channels, same IC)
[4]
-
-
4
%
Vreg(drv)
driver regulation voltage
minimum regulation voltage;
IREFx = FFh; Rext = 1 k
0.8
1
20
V
IL(off)
off-state leakage current
VO = 20 V
-
-
1
A
-
+0.3VDD V
OE input, RESET input
VIL
LOW-level input voltage
0.5
VIH
HIGH-level input voltage
0.7VDD -
5.5
V
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3.7
5
pF
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Table 29. Static characteristics …continued
VDD = 3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
voltage on an input pin
0.5
-
5.5
V
Address inputs AD2, AD1, AD0
VI
input voltage
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3.7
5
pF
rising
130
-
150
C
hysteresis
15
-
30
C
Overtemperature protection
Tth(otp)
overtemperature protection
threshold temperature
[1]
Typical limits at VDD = 3.3 V, Tamb = 25 C.
[2]
In order to reset part, VDD must be lowered to 1 V.
[3]
Part-to-part mismatch is calculated:
I O LED0 + I O LED1 + + I O LED14 + I O LED15
--------------------------------------------------------------------------------------------------------------------------- – ideal output current
16
% = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 100
ideal
output
current
where ‘ideal output current’ = 28.68 mA (Rext = 1 k, IREFx = 80h).
[4]
Channel-to-channel mismatch is calculated:
I O LEDn where n = 0 to 15
% = --------------------------------------------------------------------------------------------------------------------------------- – 1 100
I O LED0 + I O LED1 + + I O LED14 + I O LED15
--------------------------------------------------------------------------------------------------------------------------
16
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14. Dynamic characteristics
Table 30. Dynamic characteristics
All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 3 V 0.2 V and
5.5 V 0.3 V; Tamb = 40 C to +85 C; and refer to VIL and VIH with an input voltage of VSS to VDD.
Symbol
Parameter
Conditions
[1]
Min
Typ
Max
Unit
fUSCL
USCL clock frequency
0
-
5000
kHz
tBUF
bus free time between a STOP and START
condition
0.08
-
-
s
tHD;STA
hold time (repeated) START condition
0.05
-
-
s
tSU;STA
set-up time for a repeated START condition
0.05
-
-
s
tSU;STO
set-up time for STOP condition
0.05
-
-
s
tHD;DAT
data hold time
10
-
-
ns
-
-
-
ns
[2]
tVD;DAT
data valid time
tSU;DAT
data set-up time
30
-
-
ns
tLOW
LOW period of the USCL clock
50
-
-
ns
tHIGH
HIGH period of the USCL clock
50
-
-
ns
tf
fall time of both USDA and USCL signals
-
-
50
ns
tr
rise time of both USDA and USCL signals
-
-
50
ns
tSP
pulse width of spikes that must be suppressed
by the input filter
-
-
10
ns
[1]
Minimum USCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either USDA or USCL is
held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[2]
tVD;DAT is not applicable to the UFm I2C-bus slave device.
0.7 × VDD
USDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
USCL
0.3 × VDD
tHD;STA
P
S
tSU;STA
tHD;DAT
tHIGH
tSU;DAT
Sr
tSU;STO
P
002aag331
Fig 24. Definition of timing
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protocol
START
condition
(S)
tSU;STA
bit 7
MSB
tLOW
bit 1
(D1)
bit 6
tHIGH
(always set
to 1
by master)
bit 0
(D0)
STOP
condition
(P)
9th
clock
1 / fUSCL
0.7 × VDD
0.3 × VDD
USCL
tBUF
tf
tr
0.7 × VDD
0.3 × VDD
USDA
tSU;DAT
tHD;STA
tSU;STO
tHD;DAT
002aag332
Rise and fall times refer to VIL and VIH.
Fig 25. UFm I2C-bus timing diagram
15. Test information
VDD
PULSE
GENERATOR
VI
VO
RL
50 Ω
VDD or VLED
open
VSS
DUT
RT
CL
50 pF
002aag466
RL = Load resistor for LEDn.
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 26. Test circuitry for switching times
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
16. Package outline
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Fig 27. Package outline SOT1172-3 (HTSSOP28)
PCU9955A
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17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 31 and 32
Table 31.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 32.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 28.
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
19. Soldering: PCB footprints
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Fig 29. PCB footprint for SOT1172-3 (HTSSOP28); reflow soldering
PCU9955A
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16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
20. Abbreviations
Table 33.
Abbreviations
Acronym
Description
ACK
Acknowledge
CDM
Charged-Device Model
DAC
Digital-to-Analog Converter
DUT
Device Under Test
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
LED
Light Emitting Diode
LSB
Least Significant Bit
MCU
MicroController Unit
MSB
Most Significant Bit
NMOS
Negative-channel Metal-Oxide Semiconductor
PCB
Printed-Circuit Board
PMOS
Positive-channel Metal-Oxide Semiconductor
PWM
Pulse Width Modulation
RGB
Red/Green/Blue
RGBA
Red/Green/Blue/Amber
SMBus
System Management Bus
21. Revision history
Table 34.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCU9955A v.3.1
20150629
Product data sheet
-
PCU9955A v.3
Modifications:
PCU9955A v.3
Modifications:
•
•
Section 7.3.3 “LEDOUT0 to LEDOUT3, LED driver output state”: added remark.
Table 8 “MODE1 - Mode register 1 (address 00h) bit description”: added Table note [3].
20141014
•
Product data sheet
-
PCU9955A v.2
Section 7.5 “Power-on reset”: added remark.
PCU9955A v.2
20140522
Product data sheet
-
PCU9955A v.1
PCU9955A v.1
20140210
Preliminary data sheet
-
-
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22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
22.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCU9955A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 29 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
55 of 58
PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCU9955A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 29 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
56 of 58
PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
24. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.8.1
7.3.8.2
7.3.8.3
7.3.8.4
7.3.8.5
7.3.8.6
7.3.8.7
7.3.8.8
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Device addresses . . . . . . . . . . . . . . . . . . . . . . . 7
Regular I2C-bus slave address. . . . . . . . . . . . . 7
LED All Call I2C-bus address . . . . . . . . . . . . . 11
LED Sub Call I2C-bus addresses . . . . . . . . . . 12
Control register . . . . . . . . . . . . . . . . . . . . . . . . 12
Register definitions . . . . . . . . . . . . . . . . . . . . . 14
MODE1 — Mode register 1 . . . . . . . . . . . . . . 16
MODE2 — Mode register 2 . . . . . . . . . . . . . . 17
LEDOUT0 to LEDOUT3, LED driver output
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
GRPPWM, group duty cycle control . . . . . . . . 18
GRPFREQ, group frequency . . . . . . . . . . . . . 19
PWM0 to PWM15, individual brightness
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IREF0 to IREF15, LED output current value
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Gradation control . . . . . . . . . . . . . . . . . . . . . . 21
RAMP_RATE_GRP0 to RAMP_RATE_GRP3,
ramp rate control registers . . . . . . . . . . . . . . . 22
STEP_TIME_GRP0 to STEP_TIME_GRP3,
step time control registers . . . . . . . . . . . . . . . 22
HOLD_CNTL_GRP0 to HOLD_CNTL_GRP3,
hold ON and OFF control registers. . . . . . . . . 23
IREF_GRP0 to IREF_GRP3, output gain
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
GRAD_MODE_SEL0 to GRAD_MODE_SEL1,
gradation mode select registers . . . . . . . . . . . 24
GRAD_GRP_SEL0 to GRAD_GRP_SEL3,
gradation group select registers . . . . . . . . . . . 24
GRAD_CNTL, Gradation control register . . . . 25
Ramp control — equation and calculation
example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3.9
7.3.10
OFFSET — LEDn output delay offset register
LED Sub Call I2C-bus addresses for
PCU9955A . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.11
ALLCALLADR, LED All Call I2C-bus address
7.3.12
PWMALL — brightness control for all LEDn
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.13
IREFALL register: output current value for all
LED outputs . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.14
LED driver constant current outputs. . . . . . . .
7.3.14.1 Adjusting output current . . . . . . . . . . . . . . . . .
7.3.15
Overtemperature protection . . . . . . . . . . . . . .
7.4
Active LOW output enable input . . . . . . . . . .
7.5
Power-on reset. . . . . . . . . . . . . . . . . . . . . . . .
7.6
Hardware reset recovery . . . . . . . . . . . . . . . .
7.7
Software reset . . . . . . . . . . . . . . . . . . . . . . . .
7.8
Individual brightness control with group
dimming/blinking . . . . . . . . . . . . . . . . . . . . . .
8
Characteristics of the PCU9955A Ultra
Fast-mode I2C-bus . . . . . . . . . . . . . . . . . . . . .
8.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1
START and STOP conditions. . . . . . . . . . . . .
8.2
System configuration . . . . . . . . . . . . . . . . . . .
8.3
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . .
9
Bus transactions . . . . . . . . . . . . . . . . . . . . . . .
10
Application design-in information. . . . . . . . .
10.1
Thermal considerations . . . . . . . . . . . . . . . . .
11
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
12
Thermal characteristics . . . . . . . . . . . . . . . . .
13
Static characteristics . . . . . . . . . . . . . . . . . . .
14
Dynamic characteristics. . . . . . . . . . . . . . . . .
15
Test information . . . . . . . . . . . . . . . . . . . . . . .
16
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
17
Handling information . . . . . . . . . . . . . . . . . . .
18
Soldering of SMD packages . . . . . . . . . . . . . .
18.1
Introduction to soldering. . . . . . . . . . . . . . . . .
18.2
Wave and reflow soldering. . . . . . . . . . . . . . .
18.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
18.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
19
Soldering: PCB footprints . . . . . . . . . . . . . . .
20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
21
Revision history . . . . . . . . . . . . . . . . . . . . . . .
29
30
30
31
31
31
31
33
33
34
34
34
36
37
37
37
38
38
39
42
42
44
44
45
47
48
49
50
50
50
50
50
51
53
54
54
continued >>
PCU9955A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 29 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
57 of 58
PCU9955A
NXP Semiconductors
16-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver
22
22.1
22.2
22.3
22.4
23
24
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
55
55
55
56
56
57
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 29 June 2015
Document identifier: PCU9955A