Data Sheet

PCF8594C-2
512 × 8-bit CMOS EEPROM with I2C-bus interface
Rev. 05 — 25 October 2004
Product data
1. Description
The PCF8594C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 4 kbits (512 × 8-bit) non-volatile storage. By using an
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumption is low due to the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I2C-bus. Up to four
PCF8594C-2 devices may be connected to the I2C-bus. Chip select is accomplished
by two address inputs (A1 and A2).
Timing of the E/W cycle is carried out internally, thus no external components are
required. Programming Time Control (PTC), Pin 7, must be connected to either VDD
or left open-circuit. There is an option of using an external clock for timing the length
of an E/W cycle.
2. Features
■ Low power CMOS:
◆ 2.0 mA maximum operating current
◆ maximum standby current 10 µA (at 6.0 V), typical 4 µA
■ Non-volatile storage of 4 kbits organized as 512 × 8-bit
■ Single supply with full operation down to 2.5 V
■ On-chip voltage multiplier
■ Serial input/output I2C-bus
■ Write operations:
◆ byte write mode
◆ 8-byte page write mode (minimizes total write time per byte)
■ Read operations:
◆ sequential read
◆ random read
■ Internal timer for writing (no external components)
■ Internal power-on reset
■ 0 kHz to 100 kHz clock frequency
■ High reliability by using a redundant storage code
■ Endurance: 1,000,000 Erase/Write (E/W) cycles at Tamb = 22 °C
■ 10 years non-volatile data retention time
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
■ ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
■ Offered in DIP8 and SO8 packages.
3. Quick reference data
Table 1:
Quick reference data
Symbol
Parameter
VDD
supply voltage
IDDR
supply current read
IDDW
IDD(stb)
Conditions
Min
Typ
Max
Unit
2.5
-
6.0
V
fSCL = 100 kHz
supply current E/W
VDD = 2.5 V
-
-
60
µA
VDD = 6 V
-
-
200
µA
VDD = 2.5 V
-
-
0.6
mA
fSCL = 100 kHz
standby supply current
VDD = 6 V
-
-
2.0
mA
VDD = 2.5 V
-
-
3.5
µA
VDD = 6 V
-
-
10
µA
4. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PCF8594C-2P/02
DIP8
plastic dual in-line package; 8 leads (300 mil)
SOT97-1
PCF8594C-2T/02
SO8
plastic small outline package 8 leads (straight); SOT96-1
body width 3.9 mm
4.1 Ordering options
Table 3:
Ordering options
Type number
Topside mark
PCF8594C-2P/02
PCF8594C-2
PCF8594C-2T/02
8594C-2
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9397 750 14221
Product data
Rev. 05 — 25 October 2004
2 of 21
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INPUT
FILTER
5
1
I2C-BUS CONTROL LOGIC
WP
Philips Semiconductors
SCL
SDA
5. Block diagram
9397 750 14221
Product data
PCF8594C-2
6
n
ADDRESS
HIGH
REGISTER
BYTE
COUNTER
SEQUENCER
DIVIDER
( 128)
Rev. 05 — 25 October 2004
3
ADDRESS
SWITCH
A1
3
2
8
ADDRESS
POINTER
8
EEPROM
4
EE
CONTROL
TEST MODE DECODER
TIMER
( 16)
POWER-ON-RESET
OSCILLATOR
7
4
002aaa258
VSS
Fig 1. Block diagram.
PTC
PCF8594C-2
3 of 21
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
VDD
BYTE
LATCH
(8 bytes)
512 × 8-bit CMOS EEPROM with I2C-bus interface
A2
SHIFT
REGISTER
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
6. Pinning information
6.1 Pinning
WP
8 V DD
1
7
PTC
A2 3
6
SCL
VSS 4
5
SDA
A1 2
PCF8594C-2
002aaa259
Fig 2. Pin configuration.
6.2 Pin description
Table 4:
Pin description
Symbol
Pin
Description
WP
1
active-HIGH write protection input
A1
2
address input 1
A2
3
address input 2
VSS
4
negative supply voltage
SDA
5
serial data input/output (I2C-bus)
SCL
6
serial clock input (I2C-bus)
PTC
7
programming time control output
VDD
8
positive supply voltage
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
4 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
7. Device addressing
Table 5:
Device address code
Selection
Bit
Device
[1]
Device code
Chip Enable
R/W
b7[1]
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
A2
A1
A0
R/W
The Most Significant Bit (MSB) ‘b7’ is sent first.
A2 and A1 are hardware selectable pins and A0 is software selectable pin.
A system could have up to four PCF8594C-2 devices on the same I2C-bus,
equivalent to a 16 kbit EEPROM or 4 devices of 512 bytes of memory.
A0 selects the lower (logic level ‘0’) or the higher (logic level ‘1’) 256-byte page on the
selected device. The device is selected by bits A2 and A1. Figure 3 shows the various
address and page combinations.
I2C-BUS
PCF8594C-2
DEVICE 1
A2
A1
A0
HIGHER 256-BYTE PAGE
0
0
1
LOWER 256-BYTE PAGE
0
0
0
HIGHER 256-BYTE PAGE
0
1
1
LOWER 256-BYTE PAGE
0
1
0
HIGHER 256-BYTE PAGE
1
0
1
LOWER 256-BYTE PAGE
1
0
0
HIGHER 256-BYTE PAGE
1
1
1
LOWER 256-BYTE PAGE
1
1
0
PCF8594C-2
DEVICE 2
PCF8594C-2
DEVICE 3
PCF8594C-2
DEVICE 4
002aaa260
Fig 3. Device addressing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
5 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
8. Functional description
8.1 I2C-bus protocol
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The
serial bus consists of two bidirectional lines; one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is
HIGH. Changes in the data line while the clock line is HIGH will be interpreted as
control signals.
8.1.1
Bus conditions
The following bus conditions have been defined:
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line, from HIGH-to-LOW,
while the clock is HIGH, defines the START condition.
Stop data transfer — A change in the state of the data line, from LOW-to-HIGH,
while the clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
8.1.2
Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition. The number of the data bytes, transferred between the START and STOP
conditions is limited to 7 bytes in the E/W mode and 8 bytes in the Page E/W mode.
Data transfer is unlimited in the read mode. The information is transmitted in bytes
and each receiver acknowledges with a ninth bit.
Within the I2C-bus specifications, a standard-speed mode (100 kHz clock rate) and a
fast-speed mode (400 kHz clock rate) are defined. The PCF8594C-2 operates in only
the standard-speed mode.
By definition, a device that sends a signal is called a ‘transmitter’, and the device
which receives the signal is called a ‘receiver’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level,
put on the bus by the transmitter. The master generates an extra acknowledge related
clock pulse. The slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte.
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9397 750 14221
Product data
Rev. 05 — 25 October 2004
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PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
end of data to the slave transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
8.1.3
Device addressing
Following a START condition, the bus master must output the address of the slave it
is accessing. The address of the PCF8594C-2 is shown in Figure 4. To conserve
power, no internal pull-up resistors are incorporated on the hardware selectable pins
and they must be connected to either VDD or VSS.
1
0
1
0
FIXED
A2
A1
A0 R/W
SOFTWARE
SELECTABLE
HARDWARE
SELECTABLE
002aaa261
Fig 4. Slave address.
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read operation is selected, while a logic 0 selects a write operation.
8.1.4
Write operations
A write-protection input at Pin 1 (WP) allows disabling of write commands from the
master by a hardware signal. Write accesses are allowed to either the upper or lower
256 bytes of the EEPROM if the pin WP is LOW, or the lower 256 bytes of the
EEPROM if the pin WP is HIGH. When the pin WP is HIGH the upper 256 bytes of
the EEPROM are write-protected and no acknowledge will be given by the
PCF8594C-2 when data is sent. However, an acknowledge will be given after the
slave address and the word address.
Byte/word write: For a write operation, the PCF8594C-2 requires a second address
field. This address field is a word address providing access to the 256 words of
memory. Upon receipt of the word address, the PCF8594C-2 responds with an
acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition or transmit up to six more
bytes of data and then terminate by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is 10 ms per byte.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I2C-bus.
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9397 750 14221
Product data
Rev. 05 — 25 October 2004
7 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
acknowledge
from slave
acknowledge
from slave
S
0 A
SLAVE ADDRESS
A
WORD ADDRESS
acknowledge
from slave
DATA
acknowledge
from slave
DATA
A
A
P
R/W
auto increment
word address
auto increment
word address
MBA701
Fig 5. Auto-increment memory word address; two byte write.
Page write: The PCF8594C-2 is capable of an eight-byte page write operation. It is
initiated in the same manner as the byte write operation. The master can transit eight
data bytes within one transmission. After receipt of each byte, the PCF8594C-2 will
respond with an acknowledge. The typical E/W time in this mode is
9 × 3.5 ms = 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms
and sequential writing of these 8 bytes another typical 28 ms.
After the receipt of each data byte, the three low-order bits of the word address are
internally incremented. The high-order five bits of the address remain unchanged.
The slave acknowledges the reception of each data byte with an ACK. The I2C-bus
data transfer is terminated by the master after the 8th byte with a STOP condition. If
the master transmits more than eight bytes prior to generating the STOP condition,
no acknowledge will be given on the ninth (and following) data bytes and the whole
transmission will be ignored and no programming will be done. As in the byte write
operation, all inputs are disabled until completion of the internal write cycles.
acknowledge
from slave
S
SLAVE ADDRESS
0 A
acknowledge
from slave
WORD ADDRESS
A
acknowledge
from slave
DATA N
A
acknowledge
from slave
DATA N + 1
A
R/W
auto increment
word address
auto increment
word address
acknowledge
from slave
DATA N + 7
A
A
last byte
002aaa245
auto increment
word address
Fig 6. Page write operation; eight bytes.
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9397 750 14221
Product data
Rev. 05 — 25 October 2004
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PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
8.1.5
Read operations
Read operations are initiated in the same manner as write operations with the
exception that the LSB of the slave address is set to logic 1.
There are three basic read operations: current address read, random read, and
sequential read.
Remark: The lower 8 bits of the word address are incremented after each
transmission of a data byte (read or write). The MSB of the word address, which is
defined in the slave address, is not changed when the word address count overflows.
Thus, the word address overflows from 255 to 0, and from 511 to 256.
acknowledge
from slave
acknowledge
from slave
S
SLAVE ADDRESS
0 A
WORD ADDRESS
R/W
A
S
acknowledge
from slave
SLAVE ADDRESS
at this moment master
transmitter becomes
master receiver and
EEPROM slave receiver
becomes slave transmitter
1 A
R/W
acknowledge
from master
DATA
A
n bytes
auto increment
word address
no acknowledge
from master
DATA
1
P
last byte
auto increment
word address
MBA703
Fig 7. Master reads PCF8594C-2 slave after setting word address (write word address; read data);
sequential read.
acknowledge
from master
acknowledge
from slave
S
SLAVE ADDRESS
1 A
R/W
DATA
A
n bytes
no acknowledge
from master
DATA
1
P
last bytes
auto increment
word address
auto increment
word address
MBA704 - 1
Fig 8. Master reads PCF8594C-2 immediately after first byte (read mode); current address read.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
9 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
9. Limiting values
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
|Zi| > 500 Ω
Min
Max
Unit
−0.3
+6.5
V
Vi
input voltage on any input pin
VSS − 0.8
+6.5
V
Ii
input current on any input pin
-
1
mA
Io
output current
-
10
mA
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
−40
+85
°C
10. Characteristics
Table 7:
Characteristics
VDD = 2.5 V to 6.0 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.5
-
6.0
V
VDD = 2.5 V
-
-
60
µA
VDD = 6.0 V
-
-
200
µA
VDD = 2.5 V
-
-
0.6
mA
VDD = 6.0 V
-
-
2.0
mA
VDD = 2.5 V
-
-
3.5
µA
VDD = 6.0 V
-
-
10
µA
Supplies
VDD
supply voltage
IDDR
supply current read
IDDW
IDD(stb)
supply current E/W
standby supply current
fSCL = 100 kHz
fSCL = 100 kHz
PTC output (pin 7)
VIL
LOW level input voltage
−0.8
-
0.1VDD
V
VIH
HIGH level input voltage
0.9VDD
-
VDD + 0.8
V
SCL input (pin 6)
VIL
LOW level input voltage
−0.8
-
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD
-
+6.5
V
ILI
input leakage current
-
-
±1
µA
fSCL
clock input frequency
0
-
100
kHz
Ci
input capacitance
-
-
7
pF
VI = VDD or VSS
VI = VSS
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9397 750 14221
Product data
Rev. 05 — 25 October 2004
10 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
Table 7:
Characteristics…continued
VDD = 2.5 V to 6.0 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−0.8
-
0.3VDD
V
SDA input/output (pin 5)
VIL
LOW level input voltage
VIH
HIGH level input voltage
0.7VDD
-
+6.5
V
VOL
LOW level output voltage
IOL = 3 mA; VDD(min)
-
-
0.4
V
ILO
output leakage current
VOH = VDD
-
-
1
µA
Ci
input capacitance
VI = VSS
-
-
7
pF
Tamb = 55 °C
10
−
−
years
Data retention time
data retention time
tS
11. I2C-bus characteristics
Table 8:
I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol
Parameter
fSCL
Conditions
Min
Max
Unit
clock frequency
0
100
kHz
tBUF
bus free time between a STOP and
START condition
4.7
−
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
−
µs
tLOW
LOW level clock period
4.7
−
µs
tHIGH
HIGH level clock period
tSU;STA
set-up time for START condition
tHD;DAT
data hold time
repeated start
for bus compatible masters
4.0
−
µs
4.7
−
µs
5
−
µs
0
−
ns
tSU;DAT
data set-up time
250
−
ns
tr
SDA and SCL rise time
−
1
µs
tf
SDA and SCL fall time
−
300
ns
tSU;STO
set-up time for STOP condition
4.0
−
µs
[1]
for bus devices
[1]
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
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9397 750 14221
Product data
Rev. 05 — 25 October 2004
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PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
SDA
t BUF
SCL
P
t LOW
tf
t HD;STA
S
S
t HD;STA
tr
t HIGH
t HD;DAT
P
t SU;STA
t SU;DAT
MBA705
t SU;STO
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I2C-bus.
12. Write cycle limits
Table 9:
Write cycle limits
Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
internal oscillator
−
7
−
ms
external clock
4
−
10
ms
Tamb = −40 °C to +85 °C
100000
E/W cycle timing
tE/W
E/W cycle time
Endurance
NE/W
E/W cycle per byte
Tamb = 22 °C
−
−
cycles
1000000
−
cycles
13. External clock timing
td
PTC
tr
t HIGH
1
tf
t LOW
2
257
SDA
SCL
STOP
MBA697
Fig 10. One byte E/W cycle.
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9397 750 14221
Product data
Rev. 05 — 25 October 2004
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PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
tr
td
t HIGH
tf
t LOW
n x 256 + 1
PTC
1
2
SDA
SCL
STOP
MBA698
Fig 11. n bytes E/W cycle (n = 2 to 7).
tr
td
t HIGH
PTC
tf
t LOW
1
2
1153
SDA
SCL
STOP
MBA699
Fig 12. Page mode.
SLAVE ADDRESS
2
I C-bus S
HIGH
PTC
LOW
WORD ADDRESS
0A
A
DATA
A
DATA
A P (1)
undefined
undefined
negative edge
SCL 8-bit
1
1
1
td
2
2
2
257
513
1153
clock (2)
clock (3)
clock (4)
0
MBA700
(1) If an external clock is chosen, this information is latched internally by setting pin 7 (PTC) LOW after transmission of the
eighth bits of the word address (negative edge of SCL). Thus the state of pin 7 may be previously undefined. Leaving pin 7
LOW causes a higher standby current.
(2) 1-byte programming.
(3) 2-byte programming.
(4) One page (8 bytes) programming.
Fig 13. External clock.
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9397 750 14221
Product data
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PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
14. Package outline
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
ME
seating plane
D
A2
A
A1
L
c
Z
w M
b1
e
(e 1)
b
MH
b2
5
8
pin 1 index
E
1
4
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.14
0.53
0.38
1.07
0.89
0.36
0.23
9.8
9.2
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
1.15
inches
0.17
0.02
0.13
0.068
0.045
0.021
0.015
0.042
0.035
0.014
0.009
0.39
0.36
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.045
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT97-1
050G01
MO-001
SC-504-8
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 14. DIP8 package outline (SOT97-1).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
14 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 15. SO8 package outline (SOT96-1).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
15 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
15. Soldering
15.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs,
but it is not suitable for fine pitch SMDs. In these situations reflow soldering is
recommended. Driven by legislation and environmental forces the worldwide use of
lead-free solder pastes is increasing.
15.2 Through-hole mount packages
15.2.1
Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the
plastic body must not exceed the specified maximum storage temperature (Tstg(max)).
If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.
15.2.2
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron
bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit
temperature is between 300 and 400 °C, contact may be up to 5 seconds.
15.3 Surface mount packages
15.3.1
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all the BGA and SSOP-T packages
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
16 of 21
PCF8594C-2
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512 × 8-bit CMOS EEPROM with I2C-bus interface
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
15.3.2
Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
15.3.3
Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
17 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
15.4 Package related soldering information
Table 10:
Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Package[1]
Wave
Reflow[2]
Dipping
−
suitable
Through-hole
mount
DBS, DIP, HDIP, RDBS,
SDIP, SIL
suitable[3]
Through-holesurface mount
PMFP[4]
not suitable
not
suitable
−
Surface mount
BGA, LBGA, LFBGA,
SQFP, SSOP-T[5],
TFBGA, VFBGA
not suitable
suitable
−
DHVQFN, HBCC, HBGA,
HLQFP, HSQFP, HSOP,
HTQFP, HTSSOP,
HVQFN, HVSON, SMS
not suitable[6]
suitable
−
PLCC[7], SO, SOJ
suitable
suitable
−
suitable
−
suitable
−
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
recommended[7][8]
LQFP, QFP, TQFP
not
SSOP, TSSOP, VSO,
VSSOP
not recommended[9]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the
printed-circuit board.
Hot bar soldering or manual soldering is suitable for PMFP packages.
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Soldering method
Rev. 05 — 25 October 2004
18 of 21
PCF8594C-2
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512 × 8-bit CMOS EEPROM with I2C-bus interface
16. Revision history
Table 11:
Revision history
Rev Date
05
20041025
CPCN
Description
-
Product data (9397750 14221)
Modifications:
•
Section 8.1.2 “Data transfer” on page 6, third paragraph: change ‘high-speed’ to
‘standard-speed’ (2 places).
•
Section 8.1.4 “Write operations” on page 7 re-written.
04
20031007
-
Product data (9397 750 12046). ECN 853-2339 30407 dated 02 October 2003.
03
20030724
-
Product data (9397 750 11758); ECN 853-2339 30127 dated 18 July 2003.
02
20020531
-
Product data; (9397 750 09649). ECN 853-2339 28170 dated 2002 May 09.
Supersedes data in data sheet PCF85xxC-2 family dated 1997 Feb 13 (9397 750 01773).
01
19970213
-
Product data; initial version (as PCF85xxC-2 family, 9397 750 01773).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Product data
Rev. 05 — 25 October 2004
19 of 21
PCF8594C-2
Philips Semiconductors
512 × 8-bit CMOS EEPROM with I2C-bus interface
17. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
19. Disclaimers
20. Licenses
Purchase of Philips I2C components
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14221
Rev. 05 — 25 October 2004
20 of 21
Philips Semiconductors
PCF8594C-2
512 × 8-bit CMOS EEPROM with I2C-bus interface
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
9
10
11
12
13
14
15
15.1
15.2
15.2.1
15.2.2
15.3
15.3.1
15.3.2
15.3.3
15.4
16
17
18
19
20
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Device addressing . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus conditions . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device addressing . . . . . . . . . . . . . . . . . . . . . . 7
Write operations . . . . . . . . . . . . . . . . . . . . . . . . 7
Read operations . . . . . . . . . . . . . . . . . . . . . . . . 9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C-bus characteristics . . . . . . . . . . . . . . . . . . 11
Write cycle limits . . . . . . . . . . . . . . . . . . . . . . . 12
External clock timing . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Through-hole mount packages . . . . . . . . . . . . 16
Soldering by dipping or by solder wave . . . . . 16
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16
Surface mount packages . . . . . . . . . . . . . . . . 16
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17
Package related soldering information . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 25 October 2004
Document order number: 9397 750 14221