dm00030784

RM0089
Reference manual
SPEAr1340 address map and registers
Introduction
This document provides the address map and register descriptions for the SPEAr1340,
dual-core Cortex A9 HMI embedded MPU. Additional reference information is documented
in the manual RM0078, Reference manual, SPEAr1340 architecture and functionality.
November 2012
Doc ID 018904 Rev 3
1/1728
www.st.com
Contents
RM0089
Contents
1
IP groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
CPU subsystem (A9SM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
3.1
CORTEXA9ROM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
DAPROM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3
Clock manager (CMR) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4
Snoop control unit (SCU) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5
Generic interrupt controller (GIC) registers . . . . . . . . . . . . . . . . . . . . . . . 35
3.6
Global timer (GTIM) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7
Timer and watchdog (WDTIM) registers . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8
Interrupt controller dispatcher registers . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.9
CP14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10
Performance monitor unit (PMU) registers . . . . . . . . . . . . . . . . . . . . . . . . 43
3.11
L2 cache controller (PL310) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Multilayer interconnect matrix (BUSMATRIX) . . . . . . . . . . . . . . . . . . . . 47
4.1
2/1728
SMX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1.1
rt0.rt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1.2
ta_pcie0_c5.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1.3
ta_pciesata0_c6.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.1.4
rt0.si registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.1.5
ia_a9sm_10.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1.6
ia_a9sm_20.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.1.7
ia_dmac_40.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1.8
ia_dmac_50.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.1.9
ia_gpu_100.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1.10
ia_gmac_36.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.1.11
ia_venc_75.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.1.12
ia_clcd_60.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1.13
ia_pciesata0_35.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1.14
ia_vdec_55.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.1.15
ia_vip_72.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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Contents
4.2
5
4.1.16
ia_c3_70.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1.17
ia_mcif_71.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.18
ia_uoc_34.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.1.19
ia_uhc1_33.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.1.20
ia_uhc1_32.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.1.21
ia_uhc0_31.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.1.22
ia_uhc0_30.ia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1.23
ta_port_d11.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.1.24
ta_port_i.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.1.25
ta_i2s_a5.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.1.26
ta_mcif_c3.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.1.27
ta_mcif_c4.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
4.1.28
ta_a9sm_q.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.1.29
ta_mpmc_j.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
4.1.30
ta_mpmc_k.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.1.31
ta_mpmc_l.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.1.32
ta_mpmc_m.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.1.33
ta_mpmc_n.ta registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
S3220 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
System configuration registers (MISC) . . . . . . . . . . . . . . . . . . . . . . . . 185
5.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.3
Pad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
5.4
Compensation cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
5.5
5.4.1
Compensation for DDR pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
5.4.2
Compensation for IOTYPE1 and IOTYPE4 pads . . . . . . . . . . . . . . . . . 313
5.4.3
Compensation for IOTYPE2 and IOTYPE3 pads . . . . . . . . . . . . . . . . . 317
5.4.4
Recommendations to use the compensation cell . . . . . . . . . . . . . . . . 322
Inter-processor communication functionality . . . . . . . . . . . . . . . . . . . . . 323
6
Reset and clock generator (RCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
7
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8
Static RAMs (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
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9
One-time programmable antifuse (OTP) . . . . . . . . . . . . . . . . . . . . . . . 328
10
General purpose timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
11
12
10.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.2
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
11.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
11.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Direct memory access controllers (DMAC) . . . . . . . . . . . . . . . . . . . . . 342
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
4/1728
Channel#0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
12.1.1
Channel#0 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
12.1.2
Channel#0 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Channel#1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
12.2.1
Channel#1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
12.2.2
Channel#1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Channel#2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
12.3.1
Channel#2 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
12.3.2
Channel#2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Channel#3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
12.4.1
Channel#3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
12.4.2
Channel#3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Channel#4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
12.5.1
Channel#4 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
12.5.2
Channel#4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Channel#5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
12.6.1
Channel#5 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
12.6.2
Channel#5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Channel#6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
12.7.1
Channel#6 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
12.7.2
Channel#6 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Channel#7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
12.8.1
Channel#7 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
12.8.2
Channel#7 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
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12.9.1
Interrupt register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.9.2
Interrupt register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.10 Software handshake registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
12.10.1 Software handshake register summary . . . . . . . . . . . . . . . . . . . . . . . . 408
12.10.2 Software handshake registers descriptions . . . . . . . . . . . . . . . . . . . . . 409
12.11 Miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
12.11.1 Miscellaneous register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
12.11.2 Miscellaneous register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
13
Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
13.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
13.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
14
Temperature sensor (THSENS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
15
Multi-port DDR controller (MPMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16
17
18
15.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
15.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
16.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
16.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Serial NOR Flash controller (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
17.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
17.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Memory card interface (MCIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
18.1
18.2
18.3
SD Host controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
18.1.1
SD Host controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . 640
18.1.2
SD Host controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . 641
CF Host controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
18.2.1
CF Host controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . 675
18.2.2
CF Host controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . 676
xD Host controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
18.3.1
xD Host controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . 687
18.3.2
xD Host controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . 688
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18.4
19
19.2
19.3
20.2
22
18.4.2
CFxD Global Interrupt register descriptions . . . . . . . . . . . . . . . . . . . . . 702
GMAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
19.1.1
GMAC register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
19.1.2
GMAC register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
19.2.1
DMA register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
19.2.2
DMA register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
DMA_CH1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
19.3.1
DMA_CH1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
19.3.2
DMA_CH1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
EHCI block registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
20.1.1
EHCI block register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
20.1.2
EHCI block register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
OHCI block registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
20.2.1
OHCI block register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
20.2.2
OHCI block register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
USB OTG controller (UOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
21.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
21.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
PCI Express controller (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
22.1
6/1728
CFxD Global Interrupt register summary . . . . . . . . . . . . . . . . . . . . . . . 702
USB 2.0 host controllers (UHC)
20.1
21
18.4.1
Giga/Fast Ethernet port (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
19.1
20
CFxD Global Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
PCIe core registers: Endpoint register bank . . . . . . . . . . . . . . . . . . . . . 1355
22.1.1
PCI_CONFIG_HEADER registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
22.1.2
PWR_MAG_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
22.1.3
MSI_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
22.1.4
PCIE_CAP_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
22.1.5
VPD_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
22.1.6
ADERR_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
22.1.7
VC_CAP_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
22.1.8
PRT_LOG_R registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390
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22.2
23
24
25
26
27
28
29
PCIe core registers: Root-complex register bank . . . . . . . . . . . . . . . . . 1412
22.2.1
PCI_CONFIG_HEADER registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
22.2.2
PWR_MAG_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
22.2.3
MSI_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
22.2.4
PCIE_CAP_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
22.2.5
VPD_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
22.2.6
ADERR_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
22.2.7
VC_CAP_STRUC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
22.2.8
PRT_LOG_R registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
22.3
PCIe application control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
22.4
PIPE registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
Serial ATA controller (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
23.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
23.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
Asynchronous serial ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
24.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
24.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
25.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
25.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
I2C bus controllers (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
26.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
26.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567
General purpose I/O (GPIOAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
27.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
27.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
RAS Extended general purpose I/O (XGPIO) . . . . . . . . . . . . . . . . . . 1604
28.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
28.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
Keyboard controller (KBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
Doc ID 018904 Rev 3
7/1728
Contents
30
31
32
RM0089
29.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
29.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
PWM generators (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
30.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
30.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
31.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
31.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
HDMI CEC interfaces (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
32.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
32.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
33
Display controller (CLCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
34
Graphics processing unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
35
Video decoder (VDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
36
Video encoder (VENC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
37
Camera input interfaces (CAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
38
39
37.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
37.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
Video input parallel port (VIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
38.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
38.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
I2S digital audio interfaces (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
39.1
39.2
8/1728
Master interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
39.1.1
Master interface register summary . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
39.1.2
Master interface register descriptions . . . . . . . . . . . . . . . . . . . . . . . . 1655
Slave interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680
39.2.1
Slave interface register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680
39.2.2
Slave interface register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 1681
Doc ID 018904 Rev 3
RM0089
40
Contents
S/PDIF digital audio ports (SPDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
40.1
40.2
SPDIF in registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
40.1.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
40.1.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
SPDIF out registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
40.2.1
Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
40.2.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
Appendix A Copyright statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
Doc ID 018904 Rev 3
9/1728
IP groups
1
RM0089
IP groups
This document is structured according to the following IP groups:
Table 1.
SPEAr1340 IP groups
IP group
10/1728
Constituent IPs
Overview, processors, &
busses
CPU subsystem (A9SM)
Multilayer interconnect matrix (BUSMATRIX)
General device resources
Direct memory access controllers (DMAC)
General purpose timers (GPT)
One-time programmable antifuse (OTP)
Power management
Reset and clock generator (RCG)
Real-time clock (RTC)
Cryptographic co-processor (C3)
Static RAMs (SRAM)
System configuration registers (MISC)
Temperature sensor (THSENS)
Memory interfaces
Multi-port DDR controller (MPMC)
Memory card interface (MCIF)
Serial NOR Flash controller (SMI)
Static memory controller (FSMC)
Graphics, video, & audio
Camera input interfaces (CAM)
Display controller (CLCD)
Graphics processing unit (GPU)
I2S digital audio interfaces (I2S)
S/PDIF digital audio ports (SPDIF)
Video decoder (VDEC)
Video encoder (VENC)
Video input parallel port (VIP)
High-speed connectivity
Giga/Fast Ethernet port (GMAC)
PCI Express controller (PCIe)
Serial ATA controller (SATA)
PCIe/SATA physical interface (MiPHY)
USB 2.0 host controllers (UHC)
USB OTG controller (UOC)
Other connectivity
A/D converter (ADC)
Asynchronous serial ports (UART)
RAS Extended general purpose I/O (XGPIO)
General purpose I/O (GPIOAB)
HDMI CEC interfaces (CEC)
I2C bus controllers (I2C)
Keyboard controller (KBD)
PWM generators (PWM)
Synchronous serial port (SSP)
Doc ID 018904 Rev 3
Address map
RM0089
2
This chapter contains the address map table for SPEAr1340.
Note:
In Table 2, shaded rows indicate addresses used as an extension of the DDR memory area from 1 to 2 GB; this configuration is
selected by software (see Chapter 5: System configuration registers (MISC)). When using the 2 GB DDR configuration, the ACP
connection is not available.
Table 2.
SPEAr1340 address map
Slave index
IP
Description
Start
End
Base address name
Doc ID 018904 Rev 3
H
DDR memory access access (port 0)
0x00000000
0x3FFFFFFF
J
DDR memory access access (port 1)
0x00000000
0x3FFFFFFF
DDR memory access access (port 2)
0x00000000
0x3FFFFFFF
L
DDR memory access access (port 3)
0x00000000
0x3FFFFFFF
M
DDR memory access access (port 4)
0x00000000
0x3FFFFFFF
N
DDR memory access access (port 5)
0x00000000
0x3FFFFFFF
0x40000000
0x5FFFFFFF
—
K
MPMC
—
MPMC_controllerBaseAddress
Reserved
—
Q
A9SM
ACP
0x60000000
0x7FFFFFFF
—
C5
PCIE0
IO space and configuration space
0x80000000
0x8FFFFFFF
—
0x90000000
0x9FFFFFFF
—
NOR/SRAM memory space
0xA0000000
0xAFFFFFFF
—
Configuration registers
0xB0000000
0xB07FFFFF
NAND memory space
0xB0800000
0xB0FFFFFF
DBI registers
SATA AHCI generic registers
SATA AHCI port0 registers
0xB1000000
0xB17FFFFF
0xB1800000
0xB1FFFFFF
—
Reserved
A1_0
A0
FSMC
A1_1
11/1728
—
Reserved
—
FSMC_CONFIGBaseAddress
—
See Chapter 22: PCI Express controller
(PCIe) for PCIe-related base addresses.
SATABaseAddress
—
Address map
PCIE/SATA0(1)
C6
—
SPEAr1340 address map (continued)
Slave index
A5_0
IP
Description
I2S_S
Start
End
0xB2000000
0xB23FFFFF
0xB2400000
0xB27FFFFF
CF controller registers
0xB2800000
0xB28005FF
CFControllerBaseAddress
xD controller registers
0xB2800600
0xB2800703
xDControllerBaseAddress
Reserved
0xB2800704
0xB28007FF
CF/xD global interrupt registers
0xB2800800
0xB280008F
Reserved
0xB2800090
0xB2FFFFFF
SD/SDIO/MMC controller registers
0xB3000000
0xB30000FF
Reserved
0xB3000100
0xB37FFFFF
—
—
Configuration and data registers
A5_1
I2S_M
C3
MCIF
Base address name
Address map
12/1728
Table 2.
DW_apb_i2s_addr_block1BaseAddress
—
CFxDGlobalInterruptBaseAddress
—
Doc ID 018904 Rev 3
SDControllerBaseAddress
C4
A8
SYSRAM0
Standard shared RAM (32 KB)
0xB3800000
0xB3FFFFFF
D11_0
I2C1
Configuration and data registers
0xB4000000
0xB40FFFFF
DW_apb_i2c_addr_block1BaseAddress
D11_1
UART1
Configuration registers
0xB4100000
0xB41FFFFF
UARTBaseAddress
0xB4200000
0xCFFFFFFF
0xD0000000
0xD00FFFFF
SPEAr1340_SPDIF_OUTBaseAddress
SPEAr1340_SPDIF_INBaseAddress
—
I_8
Reserved
—
SPDIF OUT
—
Configuration and data registers
I_9
SPDIF IN
0xD0100000
0xD01FFFFF
I_4
CAM1
0xD0200000
0xD02FFFFF
I_5
CAM2
0xD0300000
0xD03FFFFF
Configuration and data registers
SPEAr1340_CAMIFBaseAddress
I_6
CAM3
0xD0400000
0xD04FFFFF
I_7
CAM4
0xD0500000
0xD05FFFFF
I_2
CEC0
0xD0600000
0xD06FFFFF
0xD0700000
0xD07FFFFF
0xD0800000
0xD08FFFFF
Configuration and data registers
CEC1
I_1
VIP
Configuration registers
SPEAr1340_CECBaseAddress
VIPBaseAddress
RM0089
I_3
SPEAr1340 address map (continued)
Slave index
I_0
IP
GPU
—
Reserved
Description
Configuration registers
—
Start
End
0xD0900000
0xD09FFFFF
0xD0A00000
0xDFFFFFFF
Base address name
See Chapter 34: Graphics processing unit
(GPU).
—
Doc ID 018904 Rev 3
A2
UART0
Configuration and data registers
0xE0000000
0xE007FFFF
UARTBaseAddress
A6
ADC
Configuration and data registers
0xE0080000
0xE00FFFFF
ADCBaseAddress
A3
SSP
Configuration and data registers
0xE0100000
0xE017FFFF
SSPBaseAddress
A7
PWM
Configuration and data registers
0xE0180000
0xE01FFFFF
SPEAr1340_PWMBaseAddress
0xE0200000
0xE027FFFF
—
Reserved
—
—
A4
I2C0
Configuration and data registers
0xE0280000
0xE02FFFFF
DW_apb_i2c_addr_block1BaseAddress
A9
KBD
Configuration and data registers
0xE0300000
0xE037FFFF
SPEAr1340_KBDBaseAddress
B4
GPT0
0xE0380000
0xE03FFFFF
B5
GPT1
0xE0400000
0xE047FFFF
Configuration registers
GPTBaseAddress
B15
GPT2
0xE0480000
0xE04FFFFF
B16
GPT3
0xE0500000
0xE057FFFF
B9
RTC
0xE0580000
0xE05FFFFF
B7
GPIOA
0xE0600000
0xE067FFFF
0xE0680000
0xE06FFFFF
0xE0700000
0xE077FFFF
Configuration registers
Configuration registers
B8
GPIOB
B10
MISC
Configuration registers
RM0089
Table 2.
RTC_RegistersBaseAddress
GPIOBaseAddress
SPEAr1340_MISC
Address map
13/1728
SPEAr1340 address map (continued)
Slave index
B0
IP
Description
Start
End
Base address name
DAPROM registers
0xE0780000
0xE078FFFF
A9SM_DAPROMBaseAddress
CORTEXA9ROM registers
0xE07A0000
0xE07AFFFF
A9SM_CORTEXA9ROMBaseAddress
CORE0 CP14 registers
0xE07B0000
0xE07BFFFF
A9SM_CP14_0BaseAddress
CORE0 PMU registers
0xE07B1000
0xE07B1FFF
A9SM_PMU0BaseAddress
CORE1 CP14 registers
0xE07B2000
0xE07B2FFF
A9SM_CP14_1BaseAddress
CORE1 PMU registers
0xE07B3000
0xE07BFFFF
A9SM_PMU1BaseAddress
A9SM_CMRBaseAddress
A9SM
Doc ID 018904 Rev 3
B1
A9SM
Clock manager registers
0xE07C0000
0xE07FFFFF
A10
SYSRAM1
Memory for Always-on support (4 KB) 0xE0800000
0xE0FFFFFF
C0
CLCD
Configuration registers
0xE1000000
0xE17FFFFF
LCDBaseAddress
C1
C3
Configuration registers
0xE1800000
0xE1FFFFFF
C3BaseAddress
Configuration registers
0xE2000000
0xE2000FFF
GMACBaseAddress
D0
GMAC
DMA registers
0xE2001000
0xE27FFFFF
DMABaseAddress
Configuration registers
0xE2800000
0xE2FFFFFF
XGPIOBaseAddress
0xE3000000
0xE37FFFFF
USB OTG controller registers
0xE3800000
0xE38FFFFF
UOCBaseAddress
USB OHCI0 controller registers
0xE4000000
0xE47FFFFF
OHCI0BaseAddress
USB EHCI0 controller registers
0xE4800000
0xE4FFFFFF
EHCI0BaseAddress
USB OHCI1 controller registers
0xE5000000
0xE57FFFFF
OHCI1BaseAddress
USB EHCI1 controller registers
0xE5800000
0xE5FFFFFF
EHCI1BaseAddress
NOR memory access
0xE6000000
0xE9FFFFFF
Configuration registers
0xEA000000
0xEA7FFFFF
D6
XGPIO
—
D5
Address map
14/1728
Table 2.
Reserved
UOC
D1
—
—
—
UHC0
D2
D3
UHC1
D4
B13
—
SMI
B3
SMIBaseAddress
RM0089
SPEAr1340 address map (continued)
Slave index
B6
IP
DMAC0
Doc ID 018904 Rev 3
B14
MIPHY
Start
End
Base address name
Channel 0 configuration registers
0xEA800000
0xEA000057
Channel#0BaseAddress
Channel 1 configuration registers
0xEA800058
0xEA8000AF
Channel#1BaseAddress
Channel 2 configuration registers
0xEA8000B0
0xEA800107
Channel#2BaseAddress
Channel 3 configuration registers
0xEA800108
0xEA80015F
Channel#3BaseAddress
Channel 4 configuration registers
0xEA800160
0xEA8001B7
Channel#4BaseAddress
Channel 5 configuration registers
0xEA8001B8
0xEA80020F
Channel#5BaseAddress
Channel 6 configuration registers
0xEA800210
0xEA800267
Channel#6BaseAddress
Channel 7 configuration registers
0xEA800268
0xEA8002BF
Channel#7BaseAddress
DMAC interrupt registers
0xEA8002C0
0xEA800367
Interrupt registersBaseAddress
DMAC software handshake registers
0xEA800368
0xEA800397
Software handshake registersBaseAddress
Miscellaneous DMAC registers
0xEA800398
0xEA8003FA
Miscellaneous registersBaseAddress
Channel 0 configuration registers
0xEB000000
0xEB000057
Channel#0BaseAddress
Channel 1 configuration registers
0xEB000058
0xEB0000AF
Channel#1BaseAddress
Channel 2 configuration registers
0xEB0000B0
0xEB000107
Channel#2BaseAddress
Channel 3 configuration registers
0xEB000108
0xEB00015F
Channel#3BaseAddress
Channel 4 configuration registers
0xEB000160
0xEB0001B7
Channel#4BaseAddress
Channel 5 configuration registers
0xEB0001B8
0xEB00020F
Channel#5BaseAddress
Channel 6 configuration registers
0xEB000210
0xEB000267
Channel#6BaseAddress
Channel 7 configuration registers
0xEB000268
0xEB0002BF
Channel#7BaseAddress
DMAC interrupt registers
0xEB0002C0
0xEB000367
Interrupt registersBaseAddress
DMAC software handshake registers
0xEB000368
0xEB000397
Software handshake registersBaseAddress
Miscellaneous DMAC registers
0xEB000398
0xEB0003FA
Miscellaneous registersBaseAddress
Programming port
0xEB800000
0xEBBFFFFF
SPEAr1340_MISC
Address map
15/1728
B12_0
DMAC1
Description
RM0089
Table 2.
SPEAr1340 address map (continued)
Slave index
IP
Description
Start
End
Base address name
B12_1
VENC
Programming port
0xEBC00000
0xEBCFFFFF
SPEAr1340_VIDEO_ENCODERBaseAddress
B12_2
VDEC
Programming port
0xEBD00000
0xEBDFFFFF
SPEAr1340_G1DecBaseAddress
0xEBE00000
0xEBFFFFFF
Configuration registers
0xEC000000
0xEC7FFFFF
MPMC_controllerBaseAddress
Snoop control unit registers
0xEC800000
0xEC8000FF
A9SM_SCUBaseAddress
Generic interrupt controller registers
0xEC800100
0xEC8001FF
A9SM_GICBaseAddress
Global timer registers
0xEC800200
0xEC8005FF
A9SM_GTIMBaseAddress
Timer and Watchdog registers
0xEC800600
0xEC800FFF
A9SM_WDTIMBaseAddress
Interrupt controller dispatcher registers 0xEC801000
0xECFFFFFF
A9SM_ICDBaseAddress
PL310 registers
0xED000000
0xED7FFFFF
A9SM_PL310BaseAddress
0xED800000
0xEFFFFFFF
0xEF800000
0xEF8007FF
0xEF800800
0xFEFFFFFF
—
0xFF000000
0xFFFFFFFF
—
—
B2
Reserved
MPMC
P0
—
Address map
16/1728
Table 2.
—
Doc ID 018904 Rev 3
A9SM
P1
—
Reserved
E1
BUSMATRIX
—
Reserved
B11
SYSROM
—
Configuration registers for S3220
—
Embedded ROM (32 KB)
—
laBaseAddress
1. Because PCIE and SATA are multiplexed, only one of these IPs can be used at a time. PCIE and SATA share the same base address; IP selection is determined by bit
pcie_sata_sel of PCIE_SATA_CFG miscellaneous register:
PCIE: pcie_sata_sel = 0
SATA: pcie_sata_sel = 1
Please refer to “PCIe/SATA physical interface (MiPHY)” chapter in RM0078, Reference manual, SPEAr1340 architecture and functionality for PCIE/SATA multiplexing
information.
RM0089
RM0089
3
CPU subsystem (A9SM)
CPU subsystem (A9SM)
●
CORTEXA9ROM registers on page 18
●
DAPROM registers on page 27
●
Clock manager (CMR) registers on page 32
●
Snoop control unit (SCU) registers on page 34
●
Generic interrupt controller (GIC) registers on page 35
●
Global timer (GTIM) registers on page 36
●
Timer and watchdog (WDTIM) registers on page 37
●
Interrupt controller dispatcher registers on page 38
●
CP14 registers on page 39
●
Performance monitor unit (PMU) registers on page 43
●
L2 cache controller (PL310) registers on page 45
Table 3.
A9CS memory map
CoreSight component
Base address
OFFSET from DAPROM
DAPROM
0xE0780000
0x00000
TPIU
0xE0781000
0x01000
CTI
0xE0782000
0x02000
ETB
0xE0783000
0x03000
FUNNEL TPIU
0xE0784000
0x04000
FUNNEL ETB
0xE0785000
0x05000
RESERVED
0xE0786000
0x06000
CORTEXA9 ROM
0xE07A0000
0x20000
RESERVED
0xE07A1000
0x21000
CORE0 CP14
0xE07B0000
0x30000
CORE0 PMU
0xE07B1000
0x31000
CORE1 CP14
0xE07B2000
0x32000
CORE1 PMU
0xE07B3000
0x33000
RESERVED
0xE07B4000
0x34000
CORE0 CTI
0xE07B8000
0x38000
CORE1 CTI
0xE07B9000
0x39000
RESERVED
0xE07BA000
0x3A000
CORE0 PTM
0xE07BC000
0x3C000
CORE1 PTM
0xE07BD000
0x3D000
RESERVED
0xE07BE000
0x3E000
Doc ID 018904 Rev 3
17/1728
CPU subsystem (A9SM)
3.1
RM0089
CORTEXA9ROM registers
Base address: 0xe07A0000
Table 4.
Offset
CORTEXA9ROM register list
Register name
Description
0x00000000
CORTEXA9ROM0
CORTEX-A9 ROM Entry 00
on page 18
0x00000004
CORTEXA9ROM1
CORTEX-A9 ROM Entry 01
on page 19
0x00000008
CORTEXA9ROM2
CORTEX-A9 ROM Entry 02
on page 19
0x0000000C
CORTEXA9ROM3
CORTEX-A9 ROM Entry 03
on page 20
0x00000010
CORTEXA9ROM4
CORTEX-A9 ROM Entry 04
on page 20
0x00000014
CORTEXA9ROM5
CORTEX-A9 ROM Entry 05
on page 21
0x00000018
CORTEXA9ROM6
CORTEX-A9 ROM Entry 06
on page 21
0x0000001C
CORTEXA9ROM7
CORTEX-A9 ROM Entry 07
on page 22
0x00000020
CORTEXA9ROM8
CORTEX-A9 ROM Entry 08
on page 22
0x00000024
CORTEXA9ROM9
CORTEX-A9 ROM Entry 09
on page 23
0x00000028
CORTEXA9ROM10
CORTEX-A9 ROM Entry 10
on page 23
0x0000002C
CORTEXA9ROM11
CORTEX-A9 ROM Entry 11
on page 24
0x00000030
CORTEXA9ROM12
CORTEX-A9 ROM Entry 12
on page 24
0x00000034
CORTEXA9ROM13
CORTEX-A9 ROM Entry 13
on page 25
0x00000038
CORTEXA9ROM14
CORTEX-A9 ROM Entry 14
on page 25
0x0000003C
CORTEXA9ROM15
CORTEX-A9 ROM Entry 15
on page 26
0x00000040
CORTEXA9ROM16
End of CORTEX-A9 ROM Entry table
on page 26
CORTEXA9ROM0
CORTEX-A9 ROM Entry 00
5
4
3
2
1
0
ENTRY_FORMAT
6
ENTRY_PRESENT
7
RESERVED
8
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000000
Type:
R
Reset:
0x0001 0003
CORTEX-A9 ROM Entry 00
[31:12] BASE_ADDR: CP14_0 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
18/1728
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Description:
Page
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
CORTEXA9ROM1
CORTEX-A9 ROM Entry 01
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000004
Type:
R
Reset:
0x0001 1003
Description:
CORTEX-A9 ROM Entry 01
[31:12] BASE_ADDR: PMU0 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM2
CORTEX-A9 ROM Entry 02
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000008
Type:
R
Reset:
0x0001 2003
Description:
CORTEX-A9 ROM Entry 02
[31:12] BASE_ADDR: CP14_1 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
Doc ID 018904 Rev 3
19/1728
CPU subsystem (A9SM)
RM0089
CORTEXA9ROM3
CORTEX-A9 ROM Entry 03
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x0000000C
Type:
R
Reset:
0x0001 3003
Description:
CORTEX-A9 ROM Entry 03
[31:12] BASE_ADDR: PMU1 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM4
CORTEX-A9 ROM Entry 04
5
4
3
2
1
0
ENTRY_FORMAT
6
ENTRY_PRESENT
7
RESERVED
8
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000010
Type:
R
Reset:
0x0001 4003
Description:
CORTEX-A9 ROM Entry 04
[31:12] BASE_ADDR: CP14_2 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
20/1728
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
CORTEXA9ROM5
CORTEX-A9 ROM Entry 05
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000014
Type:
R
Reset:
0x0001 5003
Description:
CORTEX-A9 ROM Entry 05
[31:12] BASE_ADDR: PMU2 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM6
CORTEX-A9 ROM Entry 06
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000018
Type:
R
Reset:
0x0001 6003
Description:
CORTEX-A9 ROM Entry 06
[31:12] BASE_ADDR: CP14_3 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
Doc ID 018904 Rev 3
21/1728
CPU subsystem (A9SM)
RM0089
CORTEXA9ROM7
CORTEX-A9 ROM Entry 07
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x0000001C
Type:
R
Reset:
0x0001 7003
Description:
CORTEX-A9 ROM Entry 07
[31:12] BASE_ADDR: PMU3 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM8
CORTEX-A9 ROM Entry 08
5
4
3
2
1
0
ENTRY_FORMAT
6
ENTRY_PRESENT
7
RESERVED
8
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000020
Type:
R
Reset:
0x0001 8003
Description:
CORTEX-A9 ROM Entry 08
[31:12] BASE_ADDR: CTI0 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
22/1728
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
CORTEXA9ROM9
CORTEX-A9 ROM Entry 09
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000024
Type:
R
Reset:
0x0001 9003
Description:
CORTEX-A9 ROM Entry 09
[31:12] BASE_ADDR: CTI1 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM10
CORTEX-A9 ROM Entry 10
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000028
Type:
R
Reset:
0x0001 A003
Description:
CORTEX-A9 ROM Entry 10
[31:12] BASE_ADDR: CTI2 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
Doc ID 018904 Rev 3
23/1728
CPU subsystem (A9SM)
RM0089
CORTEXA9ROM11
CORTEX-A9 ROM Entry 11
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x0000002C
Type:
R
Reset:
0x0001 B003
Description:
CORTEX-A9 ROM Entry 11
[31:12] BASE_ADDR: CTI3 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM12
CORTEX-A9 ROM Entry 12
5
4
3
2
1
0
ENTRY_FORMAT
6
ENTRY_PRESENT
7
RESERVED
8
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000030
Type:
R
Reset:
0x0001 C003
Description:
CORTEX-A9 ROM Entry 12
[31:12] BASE_ADDR: PTM0 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
24/1728
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
CORTEXA9ROM13
CORTEX-A9 ROM Entry 13
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000034
Type:
R
Reset:
0x0001 D003
Description:
CORTEX-A9 ROM Entry 13
[31:12] BASE_ADDR: PTM1 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM14
CORTEX-A9 ROM Entry 14
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000038
Type:
R
Reset:
0x0001 E003
Description:
CORTEX-A9 ROM Entry 14
[31:12] BASE_ADDR: PTM2 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
Doc ID 018904 Rev 3
25/1728
CPU subsystem (A9SM)
RM0089
CORTEXA9ROM15
CORTEX-A9 ROM Entry 15
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x0000003C
Type:
R
Reset:
0x0001 F003
Description:
CORTEX-A9 ROM Entry 15
[31:12] BASE_ADDR: PTM3 offset (absent)
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
CORTEXA9ROM16
End of CORTEX-A9 ROM Entry table
5
4
3
2
1
0
ENTRY_FORMAT
6
ENTRY_PRESENT
7
RESERVED
8
R
R
R
R
Address:
A9SM_CORTEXA9ROMBaseAddress + 0x00000040
Type:
R
Reset:
0x0000 0000
Description:
End of CORTEX-A9 ROM Entry table
[31:12] BASE_ADDR: No entry
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
26/1728
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
3.2
CPU subsystem (A9SM)
DAPROM registers
Base address: 0xE0780000
Table 5.
DAPROM register list
Offset
Register name
Description
Page
0x00000000
DAPROM0
DAP ROM Entry 00
on page 27
0x00000004
DAPROM1
DAP ROM Entry 01
on page 28
0x00000008
DAPROM2
DAP ROM Entry 02
on page 28
0x0000000C
DAPROM3
DAP ROM Entry 03
on page 29
0x00000010
DAPROM4
DAP ROM Entry 04
on page 29
0x00000014
DAPROM5
DAP ROM Entry 05
on page 30
0x00000018
DAPROM6
DAP ROM Entry 06
on page 30
0x0000001C
DAPROM7
End of DAP ROM Entry table
on page 31
DAPROM0
DAP ROM Entry 00
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x00000000
Type:
R
Reset:
0x0000 1003
Description:
DAP ROM Entry 00
[31:12] BASE_ADDR: TPIU offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
Doc ID 018904 Rev 3
27/1728
CPU subsystem (A9SM)
RM0089
DAPROM1
DAP ROM Entry 01
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x00000004
Type:
R
Reset:
0x0000 2003
Description:
DAP ROM Entry 01
[31:12] BASE_ADDR: CTI-TPIU offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
DAPROM2
DAP ROM Entry 02
5
4
3
2
1
0
ENTRY_FORMAT
6
ENTRY_PRESENT
7
RESERVED
8
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x00000008
Type:
R
Reset:
0x0000 3003
Description:
DAP ROM Entry 02
[31:12] BASE_ADDR: ETB offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
28/1728
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
DAPROM3
DAP ROM Entry 03
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x0000000C
Type:
R
Reset:
0x0000 4003
Description:
DAP ROM Entry 03
[31:12] BASE_ADDR: FUNNEL1 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
DAPROM4
DAP ROM Entry 04
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x00000010
Type:
R
Reset:
0x0000 5003
Description:
DAP ROM Entry 04
[31:12] BASE_ADDR: FUNNEL2 offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
Doc ID 018904 Rev 3
29/1728
CPU subsystem (A9SM)
RM0089
DAPROM5
DAP ROM Entry 05
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x00000014
Type:
R
Reset:
0x0002 0003
Description:
DAP ROM Entry 05
[31:12] BASE_ADDR: A9 DAPROM offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
DAPROM6
DAP ROM Entry 06
5
4
3
2
1
0
ENTRY_FORMAT
6
ENTRY_PRESENT
7
RESERVED
8
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x00000018
Type:
R
Reset:
0x0006 0003
Description:
DAP ROM Entry 06
[31:12] BASE_ADDR: External offset
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
30/1728
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
DAPROM7
End of DAP ROM Entry table
6
5
4
3
2
1
0
ENTRY_FORMAT
7
ENTRY_PRESENT
8
RESERVED
9
BASE_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
A9SM_DAPROMBaseAddress + 0x0000001C
Type:
R
Reset:
0x0000 0000
Description:
End of DAP ROM Entry table
[31:12] BASE_ADDR: No entry
[1] ENTRY_FORMAT: Format
[0] ENTRY_PRESENT: Entry present
Doc ID 018904 Rev 3
31/1728
CPU subsystem (A9SM)
3.3
RM0089
Clock manager (CMR) registers
Base address: 0xE07C0000
Table 6.
CMR register list
Offset
Register name
Description
Page
0x00000000
PR_REG
Power register
on page 32
0x00000004
DR_REG
Dap Power register
on page 32
0x00000008
RR_REG
Reset register
on page 33
0x0000000C
CR_REG
Counter register
on page 33
0x00000010
ID_REG
ID register
on page 33
PR_REG
Power register
8
7
6
5
4
3
2
1
0
CK_ACT
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
Address:
A9SM_CMRBaseAddress + 0x00000000
Type:
R/W
Reset:
0xXXXX XXX0
Description:
Power register
[0] CK_ACT: CoreSight clock activation
DR_REG
Dap Power register
6
5
4
3
2
1
0
PWRUP_REQ
7
R
A9SM_CMRBaseAddress + 0x00000004
Type:
R
Reset:
0xXXXX XXX0
Dap Power register
[0] PWRUP_REQ: Dap Power Up requested
32/1728
8
R
Address:
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
RR_REG
Reset register
7
6
5
4
3
2
1
0
RST_REQ
8
R
R/
W
Address:
A9SM_CMRBaseAddress + 0x00000008
Type:
R/W
Reset:
0xXXXX XXX0
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reset register
[0] RST_REQ: Reset request
CR_REG
Counter register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CNT_VAL
R/W
Address:
A9SM_CMRBaseAddress + 0x0000000C
Type:
R/W
Reset:
0x0000 1000
Description:
Counter register
[31:0] CNT_VAL: Reset request duration
ID_REG
ID register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ID
R
Address:
A9SM_CMRBaseAddress + 0x00000010
Type:
R
Reset:
0xC1A0 C1A0
Description:
ID register
[31:0] ID: Clock Manager peripheral ID
Doc ID 018904 Rev 3
33/1728
CPU subsystem (A9SM)
3.4
RM0089
Snoop control unit (SCU) registers
Base address: 0xec800000
These registers are not product-specific and a detailed specification is documented in
Cortex™-A9 MPCore Technical Reference Manual by ARM Ltd, Snoop Control Unit chapter.
Table 7.
Offset
34/1728
SCU register list
Register name
Description
0x00000000
Control
SCU Control Register
0x00000004
Configuration
SCU Configuration Register
0x00000008
Power
SCU CPU Power Status Register
0x0000000C
InvalidateAll
SCU Invalidate All Registers in Secure State
0x00000040
FilterStart
Filtering Start Address Register
0x00000044
FilterEnd
Filtering End Address Register
0x00000050
SAC
SCU Access Control Register
0x00000054
SNSAC
SCU Non-secure Access Control Register
Doc ID 018904 Rev 3
RM0089
3.5
CPU subsystem (A9SM)
Generic interrupt controller (GIC) registers
Base address: 0xec800100
These registers are not product-specific and a detailed specification is documented in
Cortex™-A9 MPCore Technical Reference Manual by ARM Ltd, Interrupt Controller chapter.
Table 8.
Offset
GIC register list
Register name
Description
0x00000000
ICCICR
Processor Interface Control Register
0x00000004
ICCPMR
Priority Mask Register
0x00000008
ICCBPR
Binary Point Register
0x0000000C
ICCIAR
Interrupt Acknowledge Register
0x00000010
ICCEOIR
End Of Interrupt Register
0x00000014
ICCRPR
Running Priority Register
0x00000018
ICCHPIR
Highest Pending Interrupt Register
0x0000001C
ICCABPR
Aliased Non-secure Binary Point Register
0x000000FC
ICCIIDR
Processor Interface Implementer Identification Register
Doc ID 018904 Rev 3
35/1728
CPU subsystem (A9SM)
3.6
RM0089
Global timer (GTIM) registers
Base address: 0xec800200
These registers are not product-specific and a detailed specification is documented in
Cortex™-A9 MPCore Technical Reference Manual by ARM Ltd, Global timer, Private timers,
and Watchdog registers chapter.
Table 9.
Offset
36/1728
GTIM register list
Register name
Description
0x00000000
GTimCounterL
Global Timer Counter Register (Lower)
0x00000004
GTimCounterU
Global Timer Counter Register (Upper)
0x00000008
GTimControl
Global Timer Control Register
0x0000000C
GTimIntStatus
Global Timer Interrupt Status Register
0x00000010
GTimCompValueL
Comparator Value Register (Lower)
0x00000014
GTimCompValueU
Comparator Value Register (Upper)
0x00000018
GTimAutoInc
Auto-increment Register
Doc ID 018904 Rev 3
RM0089
3.7
CPU subsystem (A9SM)
Timer and watchdog (WDTIM) registers
Base address: 0xec800600
These registers are not product-specific and a detailed specification is documented in
Cortex™-A9 MPCore Technical Reference Manual by ARM Ltd, Global timer, Private timers,
and Watchdog registers chapter.
Table 10.
Offset
WDTIM register list
Register name
Description
0x00000000
TimLoad
Private Timer Load Register
0x00000004
TimCounter
Private Timer Counter Register
0x00000008
TimControl
Private Timer Control Register
0x0000000C
TimIntStatus
Private Timer Interrupt Status Register
0x00000020
WDogLoad
Watchdog Load Register
0x00000024
WDogCounter
Watchdog Counter Register
0x00000028
WDogControl
Watchdog Control Register
0x0000002C
WDogIntStatus
Watchdog Interrupt Status Register
0x00000030
WDogResetStatus
Watchdog Reset Status Register
0x00000034
WDogDisable
Watchdog Disable Register
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CPU subsystem (A9SM)
3.8
RM0089
Interrupt controller dispatcher registers
Base address: 0xec801000
These registers are not product-specific and a detailed specification is documented in
Cortex™-A9 MPCore Technical Reference Manual by ARM Ltd, Interrupt Controller chapter.
Table 11.
ICD register list
Offset
38/1728
Register name
Description
0x00000000
ICDDCR
Distributor Control Register
0x00000004
ICDICTR
Interrupt Controller Type Register
0x00000008
ICDDIR
Distributor Implementer Identification Register
0x80:0x9C(0x4)
ICDISRx
Interrupt security registers
0x100:0x11C(0x4)
ICDISERx
Enable set registers
0x180:0x19C(0x4)
ICDICERx
Enable clear registers
0x200:0x21C(0x4)
ICDISPRx
Pending set registers
0x280:0x29C(0x4)
ICDICPRx
Pending clear registers
0x300:0x31C(0x4)
ICDABRx
Active status registers
0x400:0x4FC(0x4)
ICDIPRx
Priority level registers
0x800:0x8FC(0x4)
ICDIPTRx
SPI Target registers
0xC00:0xC3C(0x4)
ICDICFRx
Interrupt Configuration Registers
0x00000D00
ppi_status
PPI (Private Peripheral Interrupt) Status Register
0xD04:0xD1C(0x4)
spi_statusx
SPI (Shared Peripheral Interrupt) Status Registers
0x00000F00
ICDSGIR
Software Generated Interrupt Register
0x00000FD0
periph_id_4
Peripheral Identification Register 4
0x00000FD4
periph_id_5
Peripheral Identification Register 5
0x00000FD8
periph_id_6
Peripheral Identification Register 6
0x00000FDC
periph_id_7
Peripheral Identification Register 7
0x00000FE0
periph_id_0
Peripheral Identification Register 0
0x00000FE4
periph_id_1
Peripheral Identification Register 1
0x00000FE8
periph_id_2
Peripheral Identification Register 2
0x00000FEC
periph_id_3
Peripheral Identification Register 3
0x00000FF0
component_id_0
PrimeCell Identification Register 0
0x00000FF4
component_id_1
PrimeCell Identification Register 1
0x00000FF8
component_id_2
PrimeCell Identification Register 2
0x00000FFC
component_id_3
PrimeCell Identification Register 3
Doc ID 018904 Rev 3
RM0089
3.9
CPU subsystem (A9SM)
CP14 registers
Base address:
●
0xE07b0000 for CP14_0 (see Table 12)
●
0xE07b2000 for CP14_1 (see Table 13)
These registers are not product-specific and a detailed specification is documented in
Cortex™-A9 Revision: r2p2 Technical Reference Manual by ARM Ltd, Debug chapter.
Table 12.
CP14_0 register list
Offset
Register name
Description
0x00000000
DBGDIDR
Debug ID Register
0x00000018
DBGWFAR
Watchpoint Fault Address Register
0x0000001C
DBGVCR
Vector Catch Register
0x00000028
DBGDSCCR
Debug State Cache Control Register (not implemented)
0x00000080
DBGDTRRX_EXT
Host to Target Data Transfer Register
0x00000084
DBGPCSRITR
Program Counter Sampling & Instruction Transfer
Registers
0x00000088
DBGDSCR_EXT
Debug Status and Control Register
0x0000008C
DBGDTRTX_EXT
Target to Host Data Transfer Register
0x00000090
DBGDRCR
Debug Run Control Register
0x100:0x114(0x4)
DBGBVRnx
Breakpoint Value Registers
0x140:0x154(0x4)
DBGBCRnx
Breakpoint Control Registers
0x180:0x18C(0x4)
DBGWVRnx
Watchpoint Value Registers
0x1C0:0x1CC(0x4) DBGWCRnx
Watchpoint Control Registers
0x00000310
DBGPRCR
Device Power-down and Reset Control Register
0x00000314
DBGPRSR
Device Power-down and Reset Status Register
0x00000D00
CPUID
ID Code Register
0x00000D04
CTYPR
Cache Type Register
0x00000D0C
TTYPR
TLB Type Register
0x00000D20
ID_PFR0
Processor Feature Register 0
0x00000D24
ID_PFR1
Processor Feature Register 1
0x00000D28
ID_DFR0
Debug Feature Register 0
0x00000D2C
ID_AFR0
Auxiliary Feature Register 0
0x00000D30
ID_MMFR0
Memory Model Feature Register 0
0x00000D34
ID_MMFR1
Memory Model Feature Register 1
0x00000D38
ID_MMFR2
Memory Model Feature Register 2
0x00000D3C
ID_MMFR3
Memory Model Feature Register 3
0x00000D40
ID_ISAR0
Instruction Set Attribute Register 0
0x00000D44
ID_ISAR1
Instruction Set Attribute Register 1
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CPU subsystem (A9SM)
Table 12.
Offset
40/1728
RM0089
CP14_0 register list (continued)
Register name
Description
0x00000D48
ID_ISAR2
Instruction Set Attribute Register 2
0x00000D4C
ID_ISAR3
Instruction Set Attribute Register 3
0x00000D50
ID_ISAR4
Instruction Set Attribute Register 4
0x00000D58
ID_ISAR5
Instruction Set Attribute Register 5
0x00000FA0
DBGCLAIMSET
Claim Tag Set Register
0x00000FA4
DBGCLAIMCLR
Claim Tag Clear Register
0x00000FB0
DBGLAR
Lock Access Register
0x00000FB4
DBGLSR
Lock Status Register
0x00000FB8
DBGAUTHSTATUS
Authentication Status Register
0x00000FCC
DBGDEVTYPE
Device Type Register
0x00000FD0
PERIPHERALID4
Peripheral Identification Register 4
0x00000FE0
PERIPHERALID0
Peripheral Identification Register 0
0x00000FE4
PERIPHERALID1
Peripheral Identification Register 1
0x00000FE8
PERIPHERALID2
Peripheral Identification Register 2
0x00000FEC
PERIPHERALID3
Peripheral Identification Register 3
0x00000FF0
COMPONENTID0
Component Identification Register 0
0x00000FF4
COMPONENTID1
Component Identification Register 1
0x00000FF8
COMPONENTID2
Component Identification Register 2
0x00000FFC
COMPONENTID3
Component Identification Register 3
Doc ID 018904 Rev 3
RM0089
CPU subsystem (A9SM)
Table 13.
CP14_1 register list
Offset
Register name
Description
0x00000000
DBGDIDR
Debug ID Register
0x00000018
DBGWFAR
Watchpoint Fault Address Register
0x0000001C
DBGVCR
Vector Catch Register
0x00000028
DBGDSCCR
Debug State Cache Control Register (not implemented)
0x00000080
DBGDTRRX_EXT
Host to Target Data Transfer Register
0x00000084
DBGPCSRITR
Program Counter Sampling & Instruction Transfer
Registers
0x00000088
DBGDSCR_EXT
Debug Status and Control Register
0x0000008C
DBGDTRTX_EXT
Target to Host Data Transfer Register
0x00000090
DBGDRCR
Debug Run Control Register
0x100:0x114(0x4)
DBGBVRnx
Breakpoint Value Registers
0x140:0x154(0x4)
DBGBCRnx
Breakpoint Control Registers
0x180:0x18C(0x4)
DBGWVRnx
Watchpoint Value Registers
0x1C0:0x1CC(0x4) DBGWCRnx
Watchpoint Control Registers
0x00000310
DBGPRCR
Device Power-down and Reset Control Register
0x00000314
DBGPRSR
Device Power-down and Reset Status Register
0x00000D00
CPUID
ID Code Register
0x00000D04
CTYPR
Cache Type Register
0x00000D0C
TTYPR
TLB Type Register
0x00000D20
ID_PFR0
Processor Feature Register 0
0x00000D24
ID_PFR1
Processor Feature Register 1
0x00000D28
ID_DFR0
Debug Feature Register 0
0x00000D2C
ID_AFR0
Auxiliary Feature Register 0
0x00000D30
ID_MMFR0
Memory Model Feature Register 0
0x00000D34
ID_MMFR1
Memory Model Feature Register 1
0x00000D38
ID_MMFR2
Memory Model Feature Register 2
0x00000D3C
ID_MMFR3
Memory Model Feature Register 3
0x00000D40
ID_ISAR0
Instruction Set Attribute Register 0
0x00000D44
ID_ISAR1
Instruction Set Attribute Register 1
0x00000D48
ID_ISAR2
Instruction Set Attribute Register 2
0x00000D4C
ID_ISAR3
Instruction Set Attribute Register 3
0x00000D50
ID_ISAR4
Instruction Set Attribute Register 4
0x00000D58
ID_ISAR5
Instruction Set Attribute Register 5
0x00000FA0
DBGCLAIMSET
Claim Tag Set Register
0x00000FA4
DBGCLAIMCLR
Claim Tag Clear Register
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CPU subsystem (A9SM)
Table 13.
Offset
42/1728
RM0089
CP14_1 register list (continued)
Register name
Description
0x00000FB0
DBGLAR
Lock Access Register
0x00000FB4
DBGLSR
Lock Status Register
0x00000FB8
DBGAUTHSTATUS Authentication Status Register
0x00000FCC
DBGDEVTYPE
Device Type Register
0x00000FD0
PERIPHERALID4
Peripheral Identification Register 4
0x00000FE0
PERIPHERALID0
Peripheral Identification Register 0
0x00000FE4
PERIPHERALID1
Peripheral Identification Register 1
0x00000FE8
PERIPHERALID2
Peripheral Identification Register 2
0x00000FEC
PERIPHERALID3
Peripheral Identification Register 3
0x00000FF0
COMPONENTID0
Component Identification Register 0
0x00000FF4
COMPONENTID1
Component Identification Register 1
0x00000FF8
COMPONENTID2
Component Identification Register 2
0x00000FFC
COMPONENTID3
Component Identification Register 3
Doc ID 018904 Rev 3
RM0089
3.10
CPU subsystem (A9SM)
Performance monitor unit (PMU) registers
Base address:
●
0xE07b1000 for PMU0 (see Table 14)
●
0xE07b3000 for PMU1 (see Table 15)
These registers are not product-specific and a detailed specification is documented in
Cortex™-A9 Revision: r2p2 Technical Reference Manual by ARM Ltd, Performance
Monitoring Unit chapter.
Table 14.
Offset
PMU0 register list
Register name
Description
0x00000000
PMXEVCNTR0
Event Count Register 0
0x00000004
PMXEVCNTR1
Event Count Register 1
0x00000008
PMXEVCNTR2
Event Count Register 2
0x0000000C
PMXEVCNTR3
Event Count Register 3
0x00000010
PMXEVCNTR4
Event Count Register 4
0x00000014
PMXEVCNTR5
Event Count Register 5
0x0000007C
PMCCNTR
Cycle Count Register
0x00000400
PMXEVTYPER0
Event Type Select Register 0
0x00000404
PMXEVTYPER1
Event Type Select Register 1
0x00000408
PMXEVTYPER2
Event Type Select Register 2
0x0000040C
PMXEVTYPER3
Event Type Select Register 3
0x00000410
PMXEVTYPER4
Event Type Select Register 4
0x00000414
PMXEVTYPER5
Event Type Select Register 5
0x00000C00
PMCNTENSET
Count Enable Set Register
0x00000C20
PMCNTENCLR
Count Enable Clear Register
0x00000C40
PMINTENSET
Interrupt Enable Set Register
0x00000C60
PMINTENCLR
Interrupt Enable Clear Register
0x00000C80
PMOVSR
Overflow Flag Status Register
0x00000CA0
PMSWINC
Software Increment Register
0x00000E04
PMCR
Performance Monitor Control Register
0x00000E08
PMUSERENR
User Enable Register
Table 15.
Offset
PMU1 register list
Register name
Description
0x00000000
PMXEVCNTR0
Event Count Register 0
0x00000004
PMXEVCNTR1
Event Count Register 1
0x00000008
PMXEVCNTR2
Event Count Register 2
0x0000000C
PMXEVCNTR3
Event Count Register 3
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CPU subsystem (A9SM)
Table 15.
Offset
44/1728
RM0089
PMU1 register list (continued)
Register name
Description
0x00000010
PMXEVCNTR4
Event Count Register 4
0x00000014
PMXEVCNTR5
Event Count Register 5
0x0000007C
PMCCNTR
Cycle Count Register
0x00000400
PMXEVTYPER0
Event Type Select Register 0
0x00000404
PMXEVTYPER1
Event Type Select Register 1
0x00000408
PMXEVTYPER2
Event Type Select Register 2
0x0000040C
PMXEVTYPER3
Event Type Select Register 3
0x00000410
PMXEVTYPER4
Event Type Select Register 4
0x00000414
PMXEVTYPER5
Event Type Select Register 5
0x00000C00
PMCNTENSET
Count Enable Set Register
0x00000C20
PMCNTENCLR
Count Enable Clear Register
0x00000C40
PMINTENSET
Interrupt Enable Set Register
0x00000C60
PMINTENCLR
Interrupt Enable Clear Register
0x00000C80
PMOVSR
Overflow Flag Status Register
0x00000CA0
PMSWINC
Software Increment Register
0x00000E04
PMCR
Performance Monitor Control Register
0x00000E08
PMUSERENR
User Enable Register
Doc ID 018904 Rev 3
RM0089
3.11
CPU subsystem (A9SM)
L2 cache controller (PL310) registers
Base address: 0xed000000
These registers are not product-specific and a detailed specification is documented in
AMBA® Level 2 Cache Controller (L2C-310) Revision: r3p0 Technical Reference Manual.
Table 16.
PL310 register list
Offset
Register name
Description
0x00000000
ID
Cache ID Register
0x00000004
Type
Cache Type Register
0x00000100
Control
Control Register
0x00000104
AuxControl
Auxiliary Control Register
0x00000108
TagLatControl
Tag RAM Latency Control Register
0x0000010C
DataLatControl
Data RAM Latency Control Register
0x00000200
EventCountControl
Event Counter Control Register
0x00000204
EventCount1Conf
Event Counter Configuration Register 1
0x00000208
EventCount0Conf
Event Counter Configuration Register 0
0x0000020C
EventCount1Value
Event counter value register 1
0x00000210
EventCount0Value
Event counter value register 0
0x00000214
IntMask
Interrupt mask register
0x00000218
MaskedIntStatus
Interrupt mask status register
0x0000021C
RawIntStatus
Interrupt raw status register
0x00000220
IntClear
Interrupt clear register
0x00000730
CacheSync
Cache Maintenance Cache Sync Operation
register
0x00000770
InvalidateLine
Cache Maintenance Invalidate PA Operation
register
0x0000077C
InvalidateByWay
Cache Maintenance Invalidate Way Operation
register
0x000007B0
CleanLine
Cache Maintenance Clean PA Operation register
0x000007B8
CleanLineByWay
Cache Maintenance Clean Index Operation
register
0x000007BC
CleanByWay
Cache Maintenance Clean Way Operation
register
0x000007F0
CleanInvLine
Cache Maintenance Clean Invalidate PA
Operation register
0x000007F8
CleanInvLineByWay
Cache Maintenance Clean Invalidate Index
Operation register
0x000007FC
CleanInvByWay
Cache Maintenance Clean Invalidate Way
Operation register
0x00000900:
0x00000938 (0x8)
DataLockdownByWay_x
Cache lockdown Datax register
Doc ID 018904 Rev 3
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CPU subsystem (A9SM)
Table 16.
RM0089
PL310 register list (continued)
Offset
46/1728
Register name
Description
0x00000904:
0x0000093C (0x8)
InstLockdownByWay_x
Cache lockdown Instrx register
0x00000950
LockdownByLineEnable
Cache lockdown Lock by line Enable register
0x00000954
UnlockAllLinesByWay
Unlock all lines by way register
0x00000C00
AddrFilterStart
Address filtering start register
0x00000C04
AddrFilterEnd
Address filtering end register
0x00000F40
DebugControl
Debug Register
0x00000F60
PrefetchControl
Prefetch Control Register
0x00000F80
PwrCtrlOffset
Power Control Register
Doc ID 018904 Rev 3
RM0089
Multilayer interconnect matrix (BUSMATRIX)
4
Multilayer interconnect matrix (BUSMATRIX)
4.1
SMX registers
Table 17 lists the offsets for SMX register groups. These offsets are from the main SMX
registers base address (see Chapter 2: Address map).
In the following sections, the registers in each group are described in detail. The offsets
listed in these sections refer to the base address of the related group.
Table 17.
SMX group of registers address block
Base address
Address block
0x0
rt0.rt registers
0x400
ta_pcie0_c5.ta registers
0x800
ta_pciesata0_c6.ta registers
0x1c00
rt0.si registers
0x2000
ia_a9sm_10.ia registers
0x2400
ia_a9sm_20.ia registers
0x2800
ia_dmac_40.ia registers
0x2c00
ia_dmac_50.ia registers
0x3400
ia_gpu_100.ia registers
0x3800
ia_gmac_36.ia registers
0x3c00
ia_venc_75.ia registers
0x4000
ia_clcd_60.ia registers
0x4400
ia_pciesata0_35.ia registers
0x4800
ia_vdec_55.ia registers
0x4c00
ia_vip_72.ia registers
0x5000
ia_c3_70.ia registers
0x5400
ia_mcif_71.ia registers
0x6000
ia_uoc_34.ia registers
0x6400
ia_uhc1_33.ia registers
0x6800
ia_uhc1_32.ia registers
0x6c00
ia_uhc0_31.ia registers
0x7000
ia_uhc0_30.ia registers
0x7800
ta_port_d11.ta registers
0x7c00
ta_port_i.ta registers
0x8400
ta_i2s_a5.ta registers
0x8800
ta_mcif_c3.ta registers
0x8c00
ta_mcif_c4.ta registers
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Multilayer interconnect matrix (BUSMATRIX)
Table 17.
RM0089
SMX group of registers address block (continued)
Base address
Address block
0x9400
ta_a9sm_q.ta registers
0x9800
ta_mpmc_j.ta registers
0x9c00
ta_mpmc_k.ta registers
0xa000
ta_mpmc_l.ta registers
0xa400
ta_mpmc_m.ta registers
0xa800
ta_mpmc_n.ta registers
4.1.1
rt0.rt registers
Table 18.
rt0.rt register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
48
0x10
network
Interconnect identification
on page
49
0x70
initid_readback
Initiator ID read-back
on page
49
0x78
network_control
Control over interconnect-wide functions
on page
50
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
7
R
R
rt0.rtBaseAddress + 0x0
Type:
R
Reset:
0x0000000012006333
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
48/1728
8
rev
Address:
Description:
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
network
Interconnect identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
id
rev
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
R
Address:
rt0.rtBaseAddress + 0x10
Type:
R
Reset:
0x0000000000000000
Description:
Interconnect identification
[63:48] id: Unique interconnect ID
[47:32] rev: Revision code of the interconnect instance
initid_readback
Initiator ID read-back
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
initid
R
R
Address:
rt0.rtBaseAddress + 0x70
Type:
R
Reset:
0x0000000000000000
Description:
Initiator ID read-back
2
1
0
[7:0] initid: Returns initiator ID of core thread that initiated the read
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Multilayer interconnect matrix (BUSMATRIX)
network_control
RM0089
Control over interconnect-wide functions
RESERVED
clock_gate_disable
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
7
6
5
4
3
RESERVED
8
timeout_base
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
Address:
rt0.rtBaseAddress + 0x78
Type:
R/W
Reset:
0x0000000000000400
Description:
Control over interconnect-wide functions
2
1
[56] clock_gate_disable: Overrides fine-grained hardware clock gating
[10:8] timeout_base: Timeout base period in register target clock cycles
1: (rt.network_control.timeout_base.1) 26 cycles
10: (rt.network_control.timeout_base.2) 28 cycles
11: (rt.network_control.timeout_base.3) 210 cycles
100: (rt.network_control.timeout_base.4) 212 cycles
4.1.2
ta_pcie0_c5.ta registers
Table 19.
ta_pcie0_c5.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
51
0x18
core
Attached core identification
on page
51
0x20
agent_control
Control over agent functions
on page
52
0x28
agent_status
Observability of agent status
on page
52
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
53
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
53
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
54
50/1728
Doc ID 018904 Rev 3
0
RM0089
Table 19.
Multilayer interconnect matrix (BUSMATRIX)
ta_pcie0_c5.ta register list (continued)
Offset
Register name
Description
Page
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
54
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
55
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
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Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
2
1
0
core_reset
3
RESERVED
4
reject
5
RESERVED
6
req_timeout
7
RESERVED
8
req_timeout_rep
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R/W
R
R/
W
R
R/
W
Address:
ta_pcie0_c5.taBaseAddress + 0x20
Type:
R/W
Reset:
0x0000000002000000
Description:
Control over agent functions
[25] req_timeout_rep: Request timeout reporting
[10:8] req_timeout: Request timeout control
0: (ta.agent_control.req_timeout.0) no timeout
1: (ta.agent_control.req_timeout.1) 1 base cycle
10: (ta.agent_control.req_timeout.2) 4 base cycles
11: (ta.agent_control.req_timeout.3) 16 base cycles
100: (ta.agent_control.req_timeout.4) 64 base cycles
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
core_reset
R
R
burst
R
resp_active
4
readex
5
req_timeout
6
RESERVED
7
timebase
8
R
R
R
R
R
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
52/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_waiting
R
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Observability of agent status
[15:12] timebase: Observation of timebase signals for internal verification
[8] req_timeout: Request timeout status
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
2
1
0
Fractional bandwidth allocations per thread
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Doc ID 018904 Rev 3
2
1
0
53/1728
Multilayer interconnect matrix (BUSMATRIX)
Description:
RM0089
Fractional bandwidth allocations per thread
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
bandwidth_2
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
54/1728
9
fraction_13
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_pcie0_c5.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.3
ta_pciesata0_c6.ta registers
Table 20.
ta_pciesata0_c6.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
56
0x18
core
Attached core identification
on page
56
0x20
agent_control
Control over agent functions
on page
57
0x28
agent_status
Observability of agent status
on page
57
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
58
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
58
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
59
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
59
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
60
Doc ID 018904 Rev 3
55/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
56/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
2
1
0
core_reset
3
RESERVED
4
reject
5
RESERVED
6
req_timeout
7
RESERVED
8
req_timeout_rep
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R/W
R
R/
W
R
R/
W
Address:
ta_pciesata0_c6.taBaseAddress + 0x20
Type:
R/W
Reset:
0x0000000002000000
Description:
Control over agent functions
[25] req_timeout_rep: Request timeout reporting
[10:8] req_timeout: Request timeout control
0: (ta.agent_control.req_timeout.0) no timeout
1: (ta.agent_control.req_timeout.1) 1 base cycle
10: (ta.agent_control.req_timeout.2) 4 base cycles
11: (ta.agent_control.req_timeout.3) 16 base cycles
100: (ta.agent_control.req_timeout.4) 64 base cycles
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
core_reset
R
R
R
burst
4
resp_active
5
readex
6
req_timeout
7
RESERVED
8
timebase
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_waiting
R
R
R
R
R
R
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Doc ID 018904 Rev 3
3
2
1
0
57/1728
Multilayer interconnect matrix (BUSMATRIX)
Description:
RM0089
Observability of agent status
[15:12] timebase: Observation of timebase signals for internal verification
[8] req_timeout: Request timeout status
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
2
1
0
Fractional bandwidth allocations per thread
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
58/1728
9
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
bandwidth_2
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_13
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
Doc ID 018904 Rev 3
59/1728
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
RM0089
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_pciesata0_c6.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.4
rt0.si registers
Table 21.
rt0.si register list
Offset
Register name
Description
Page
0x20
control
Control of register and sideband interconnect
on page
60
0x110
flag_status_0
Composite flag status observation per composite flag
on page
61
control
Control of register and sideband interconnect
RESERVED
clock_gate_disable
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
Address:
rt0.siBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
60/1728
Doc ID 018904 Rev 3
9
8
7
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Control of register and sideband interconnect
[56] clock_gate_disable: Overrides fine-grained hardware clock gating in the register and sideband
interconnect
flag_status_0
Composite flag status observation per composite
flag
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
status
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
status
R
Address:
rt0.siBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Composite flag status observation per composite flag
[63:0] status: Status of sideband signals making up composite interconnect flag n
4.1.5
ia_a9sm_10.ia registers
Table 22.
ia_a9sm_10.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
62
0x18
core
Attached core identification
on page
62
0x20
agent_control
Control over agent functions
on page
63
0x28
agent_status
Observability of agent status
on page
63
0x68
core_flag
Enabling of core output flags
on page
64
0x100
bandwidth_0
Bandwidth weights per target group
on page
64
Doc ID 018904 Rev 3
61/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ia_a9sm_10.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_a9sm_10.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
62/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
ia_a9sm_10.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
RESERVED
core_reset
R
R
R
burst
5
resp_waiting
6
readex
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
R
Address:
ia_a9sm_10.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Doc ID 018904 Rev 3
3
2
1
0
63/1728
Multilayer interconnect matrix (BUSMATRIX)
Description:
RM0089
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[7] readex: Status of ReadEx/Write
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
core_flag
Enabling of core output flags
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
enable_0
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
Address:
ia_a9sm_10.iaBaseAddress + 0x68
Type:
R
Reset:
0x0000000000000001
Description:
Enabling of core output flags
[0] enable_0: Core output flag enable for core flag 0
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
5
4
3
target_group_0
6
target_group_1
7
target_group_2
8
R
R/W
R/W
R/W
Address:
ia_a9sm_10.iaBaseAddress + 0x100
Type:
R/W
64/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.6
ia_a9sm_20.ia registers
Table 23.
ia_a9sm_20.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
65
0x18
core
Attached core identification
on page
66
0x20
agent_control
Control over agent functions
on page
66
0x28
agent_status
Observability of agent status
on page
67
0x100
bandwidth_0
Bandwidth weights per target group
on page
67
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ia_a9sm_20.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
Doc ID 018904 Rev 3
65/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_a9sm_20.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
ia_a9sm_20.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
9
8
7
6
5
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
66/1728
Doc ID 018904 Rev 3
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
RESERVED
core_reset
R
R
R
burst
5
resp_waiting
6
readex
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
R
Address:
ia_a9sm_20.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[7] readex: Status of ReadEx/Write
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
Address:
ia_a9sm_20.iaBaseAddress + 0x100
Type:
R/W
Doc ID 018904 Rev 3
2
1
0
67/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.7
ia_dmac_40.ia registers
Table 24.
ia_dmac_40.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
68
0x18
core
Attached core identification
on page
69
0x20
agent_control
Control over agent functions
on page
69
0x28
agent_status
Observability of agent status
on page
70
0x58
error_log
Error log
on page
70
0x60
error_log_addr
Address for error log
on page
71
0x100
bandwidth_0
Bandwidth weights per target group
on page
71
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_dmac_40.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
68/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_dmac_40.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_dmac_40.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
69/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_dmac_40.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_dmac_40.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
70/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
RESERVED
8
R
R
Address:
ia_dmac_40.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
Address for error log
[31:3] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_dmac_40.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
71/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.8
ia_dmac_50.ia registers
Table 25.
ia_dmac_50.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
72
0x18
core
Attached core identification
on page
73
0x20
agent_control
Control over agent functions
on page
73
0x28
agent_status
Observability of agent status
on page
74
0x58
error_log
Error log
on page
74
0x60
error_log_addr
Address for error log
on page
75
0x100
bandwidth_0
Bandwidth weights per target group
on page
75
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_dmac_50.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
72/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_dmac_50.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_dmac_50.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
73/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_dmac_50.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_dmac_50.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
74/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
RESERVED
8
R
R
Address:
ia_dmac_50.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
Address for error log
[31:3] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_dmac_50.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
75/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.9
ia_gpu_100.ia registers
Table 26.
ia_gpu_100.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
76
0x18
core
Attached core identification
on page
77
0x20
agent_control
Control over agent functions
on page
77
0x28
agent_status
Observability of agent status
on page
78
0x100
bandwidth_0
Bandwidth weights per target group
on page
78
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_gpu_100.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
76/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_gpu_100.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
ia_gpu_100.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
77/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
RESERVED
core_reset
R
R
R
burst
5
resp_waiting
6
readex
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
R
Address:
ia_gpu_100.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[7] readex: Status of ReadEx/Write
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
5
4
3
target_group_0
6
RESERVED
7
target_group_2
8
R
R/W
R
R/W
Address:
ia_gpu_100.iaBaseAddress + 0x100
Type:
R/W
78/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.10
ia_gmac_36.ia registers
Table 27.
ia_gmac_36.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
79
0x18
core
Attached core identification
on page
80
0x20
agent_control
Control over agent functions
on page
80
0x28
agent_status
Observability of agent status
on page
81
0x100
bandwidth_0
Bandwidth weights per target group
on page
81
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_gmac_36.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
9
code
6
5
4
3
2
1
0
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
Doc ID 018904 Rev 3
79/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_gmac_36.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_gmac_36.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
80/1728
Doc ID 018904 Rev 3
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
RESERVED
core_reset
R
R
R
burst
5
resp_waiting
6
readex
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
R
Address:
ia_gmac_36.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[7] readex: Status of ReadEx/Write
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
Address:
ia_gmac_36.iaBaseAddress + 0x100
Type:
R/W
Doc ID 018904 Rev 3
2
1
0
81/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.11
ia_venc_75.ia registers
Table 28.
ia_venc_75.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
82
0x18
core
Attached core identification
on page
83
0x20
agent_control
Control over agent functions
on page
83
0x28
agent_status
Observability of agent status
on page
84
0x100
bandwidth_0
Bandwidth weights per target group
on page
84
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_venc_75.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
82/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_venc_75.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
ia_venc_75.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
83/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
RESERVED
core_reset
R
R
R
burst
5
resp_waiting
6
readex
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
R
Address:
ia_venc_75.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[7] readex: Status of ReadEx/Write
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
5
4
3
target_group_0
6
target_group_1
7
target_group_2
8
R
R/W
R/W
R/W
Address:
ia_venc_75.iaBaseAddress + 0x100
Type:
R/W
84/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.12
ia_clcd_60.ia registers
Table 29.
ia_clcd_60.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
85
0x18
core
Attached core identification
on page
86
0x20
agent_control
Control over agent functions
on page
86
0x28
agent_status
Observability of agent status
on page
87
0x100
bandwidth_0
Bandwidth weights per target group
on page
87
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ia_clcd_60.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
Doc ID 018904 Rev 3
85/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_clcd_60.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
ia_clcd_60.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
9
8
7
6
5
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
86/1728
Doc ID 018904 Rev 3
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
6
5
4
RESERVED
burst
resp_waiting
req_active
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
ia_clcd_60.iaBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
9
8
7
3
2
1
0
Observability of agent status
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
Address:
ia_clcd_60.iaBaseAddress + 0x100
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
2
1
0
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
Doc ID 018904 Rev 3
87/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
4.1.13
ia_pciesata0_35.ia registers
Table 30.
ia_pciesata0_35.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
88
0x18
core
Attached core identification
on page
88
0x20
agent_control
Control over agent functions
on page
89
0x28
agent_status
Observability of agent status
on page
89
0x100
bandwidth_0
Bandwidth weights per target group
on page
90
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ia_pciesata0_35.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
core_code
rev_code
R
R
Address:
ia_pciesata0_35.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
88/1728
9
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Attached core identification
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
ia_pciesata0_35.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
RESERVED
core_reset
R
R
R
burst
5
resp_waiting
6
readex
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
R
Address:
ia_pciesata0_35.iaBaseAddress + 0x28
Type:
R/W
Doc ID 018904 Rev 3
3
2
1
0
89/1728
Multilayer interconnect matrix (BUSMATRIX)
Reset:
0x0000000000000000
Description:
Observability of agent status
RM0089
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[7] readex: Status of ReadEx/Write
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
Address:
ia_pciesata0_35.iaBaseAddress + 0x100
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
2
1
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.14
ia_vdec_55.ia registers
Table 31.
ia_vdec_55.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
91
0x18
core
Attached core identification
on page
91
0x20
agent_control
Control over agent functions
on page
92
90/1728
Doc ID 018904 Rev 3
0
RM0089
Table 31.
Multilayer interconnect matrix (BUSMATRIX)
ia_vdec_55.ia register list (continued)
Offset
Register name
Description
Page
0x28
agent_status
Observability of agent status
on page
92
0x100
bandwidth_0
Bandwidth weights per target group
on page
93
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ia_vdec_55.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_vdec_55.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
Doc ID 018904 Rev 3
91/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
ia_vdec_55.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
RESERVED
core_reset
R
R
R
burst
5
resp_waiting
6
readex
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
R
Address:
ia_vdec_55.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
92/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[7] readex: Status of ReadEx/Write
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
Address:
ia_vdec_55.iaBaseAddress + 0x100
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
2
1
0
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.15
ia_vip_72.ia registers
Table 32.
ia_vip_72.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
94
0x18
core
Attached core identification
on page
94
0x20
agent_control
Control over agent functions
on page
95
Doc ID 018904 Rev 3
93/1728
Multilayer interconnect matrix (BUSMATRIX)
Table 32.
RM0089
ia_vip_72.ia register list (continued)
Offset
Register name
Description
Page
0x28
agent_status
Observability of agent status
on page
95
0x58
error_log
Error log
on page
96
0x60
error_log_addr
Address for error log
on page
97
0x100
bandwidth_0
Bandwidth weights per target group
on page
97
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ia_vip_72.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_vip_72.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
94/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_vip_72.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_vip_72.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Doc ID 018904 Rev 3
3
2
1
0
95/1728
Multilayer interconnect matrix (BUSMATRIX)
Description:
RM0089
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_vip_72.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
Description:
Error log
[32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
96/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
RESERVED
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
Address:
ia_vip_72.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
Address for error log
0
[31:3] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
target_group_0
7
RESERVED
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
Address:
ia_vip_72.iaBaseAddress + 0x100
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
2
1
0
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[7:0] target_group_0: Bandwidth weight for access to target group 8n
Doc ID 018904 Rev 3
97/1728
Multilayer interconnect matrix (BUSMATRIX)
4.1.16
ia_c3_70.ia registers
Table 33.
ia_c3_70.ia register list
Offset
RM0089
Register name
Description
Page
0x0
component
Component identification
on page
98
0x18
core
Attached core identification
on page
99
0x20
agent_control
Control over agent functions
on page
99
0x28
agent_status
Observability of agent status
on page
100
0x58
error_log
Error log
on page
100
0x60
error_log_addr
Address for error log
on page
101
0x100
bandwidth_0
Bandwidth weights per target group
on page
101
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
code
rev
R
R
Address:
ia_c3_70.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
98/1728
9
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_c3_70.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_c3_70.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
99/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_c3_70.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_c3_70.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
100/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
RESERVED
8
R
R
Address:
ia_c3_70.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address for error log
[31:2] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_c3_70.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
101/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.17
ia_mcif_71.ia registers
Table 34.
ia_mcif_71.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
102
0x18
core
Attached core identification
on page
103
0x20
agent_control
Control over agent functions
on page
103
0x28
agent_status
Observability of agent status
on page
104
0x58
error_log
Error log
on page
104
0x60
error_log_addr
Address for error log
on page
105
0x100
bandwidth_0
Bandwidth weights per target group
on page
105
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_mcif_71.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
102/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_mcif_71.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_mcif_71.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
103/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_mcif_71.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_mcif_71.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
104/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
RESERVED
8
R
R
Address:
ia_mcif_71.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address for error log
[31:2] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_mcif_71.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
105/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.18
ia_uoc_34.ia registers
Table 35.
ia_uoc_34.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
106
0x18
core
Attached core identification
on page
107
0x20
agent_control
Control over agent functions
on page
107
0x28
agent_status
Observability of agent status
on page
108
0x58
error_log
Error log
on page
108
0x60
error_log_addr
Address for error log
on page
109
0x100
bandwidth_0
Bandwidth weights per target group
on page
109
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_uoc_34.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
106/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_uoc_34.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_uoc_34.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
107/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_uoc_34.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_uoc_34.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
108/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
RESERVED
8
R
R
Address:
ia_uoc_34.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address for error log
[31:2] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_uoc_34.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
109/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.19
ia_uhc1_33.ia registers
Table 36.
ia_uhc1_33.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
110
0x18
core
Attached core identification
on page
111
0x20
agent_control
Control over agent functions
on page
111
0x28
agent_status
Observability of agent status
on page
112
0x58
error_log
Error log
on page
112
0x60
error_log_addr
Address for error log
on page
113
0x100
bandwidth_0
Bandwidth weights per target group
on page
113
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_uhc1_33.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
110/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_uhc1_33.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_uhc1_33.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
111/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_uhc1_33.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_uhc1_33.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
112/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
RESERVED
8
R
R
Address:
ia_uhc1_33.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address for error log
[31:2] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_uhc1_33.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
113/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.20
ia_uhc1_32.ia registers
Table 37.
ia_uhc1_32.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
114
0x18
core
Attached core identification
on page
115
0x20
agent_control
Control over agent functions
on page
115
0x28
agent_status
Observability of agent status
on page
116
0x58
error_log
Error log
on page
116
0x60
error_log_addr
Address for error log
on page
117
0x100
bandwidth_0
Bandwidth weights per target group
on page
117
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_uhc1_32.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
114/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_uhc1_32.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_uhc1_32.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
115/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_uhc1_32.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_uhc1_32.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
116/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
RESERVED
8
R
R
Address:
ia_uhc1_32.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address for error log
[31:2] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_uhc1_32.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
117/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.21
ia_uhc0_31.ia registers
Table 38.
ia_uhc0_31.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
118
0x18
core
Attached core identification
on page
119
0x20
agent_control
Control over agent functions
on page
119
0x28
agent_status
Observability of agent status
on page
120
0x58
error_log
Error log
on page
120
0x60
error_log_addr
Address for error log
on page
121
0x100
bandwidth_0
Bandwidth weights per target group
on page
121
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_uhc0_31.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
118/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_uhc0_31.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_uhc0_31.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
119/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_uhc0_31.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_uhc0_31.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
120/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
RESERVED
8
R
R
Address:
ia_uhc0_31.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address for error log
[31:2] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_uhc0_31.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
121/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.22
ia_uhc0_30.ia registers
Table 39.
ia_uhc0_30.ia register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
122
0x18
core
Attached core identification
on page
123
0x20
agent_control
Control over agent functions
on page
123
0x28
agent_status
Observability of agent status
on page
124
0x58
error_log
Error log
on page
124
0x60
error_log_addr
Address for error log
on page
125
0x100
bandwidth_0
Bandwidth weights per target group
on page
125
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ia_uhc0_30.iaBaseAddress + 0x0
Type:
R
Reset:
0x0000000010106333
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
122/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ia_uhc0_30.iaBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
RESERVED
inband_error_primary_rep
all_inband_error_rep
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ia_uhc0_30.iaBaseAddress + 0x20
Type:
R
Reset:
0x0000000018000000
Description:
Control over agent functions
9
8
7
6
5
4
3
2
1
0
[28] inband_error_primary_rep: Reporting of in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[27] all_inband_error_rep: Reporting of all in-band errors as out-of-band errors
Doc ID 018904 Rev 3
123/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
5
4
RESERVED
core_reset
R
R
R
burst
6
resp_waiting
7
RESERVED
8
inband_error_primary
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_active
R
R
R/
W
R
R
R
Address:
ia_uhc0_30.iaBaseAddress + 0x28
Type:
R/W
Reset:
0x0000000000000000
Description:
3
2
1
0
Observability of agent status
[28] inband_error_primary: Error status for in-band errors with MErrSteer indicating a primary
error (or if error steering is not enabled)
[6] burst: Status of open burst
[5] resp_waiting: Responses waiting
[4] req_active: Requests outstanding
[0] core_reset: Reset observation for agent and reset input from core interface 0 inactive 1 active
error_log
Error log
RESERVED
req_info
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
3
2
1
cmd
4
RESERVED
5
initid
6
RESERVED
7
code
8
RESERVED
9
multi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R
R
R
Address:
ia_uhc0_30.iaBaseAddress + 0x58
Type:
R/W
Reset:
0x0000000000000000
124/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Error log
[44:32] req_info: MReqInfo bits of command that caused the error
[31] multi: Multiple errors
[26:24] code: Error code
0: (ia.error_log.code.0) No error
1: (ia.error_log.code.1) Unsupported command
10: (ia.error_log.code.2) Address hole
100: (ia.error_log.code.4) In-band error
[13:8] initid: Initiator ID from which the command was launched
[2:0] cmd: Command that caused the error
error_log_addr
Address for error log
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
RESERVED
8
R
R
Address:
ia_uhc0_30.iaBaseAddress + 0x60
Type:
R
Reset:
0x0000000000000000
Description:
9
addr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address for error log
[31:2] addr: Address of command that caused the error after address fill-in
bandwidth_0
Bandwidth weights per target group
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
Address:
6
5
4
3
target_group_0
7
target_group_1
8
target_group_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
2
1
0
ia_uhc0_30.iaBaseAddress + 0x100
Doc ID 018904 Rev 3
125/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
Type:
R/W
Reset:
0x0101010101404040
Description:
Bandwidth weights per target group
[23:16] target_group_2: Bandwidth weight for access to target group 8n+2
[15:8] target_group_1: Bandwidth weight for access to target group 8n+1
[7:0] target_group_0: Bandwidth weight for access to target group 8n
4.1.23
ta_port_d11.ta registers
Table 40.
ta_port_d11.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
126
0x18
core
Attached core identification
on page
127
0x20
agent_control
Control over agent functions
on page
127
0x28
agent_status
Observability of agent status
on page
128
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
129
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
129
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
130
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
130
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
131
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
rev
R
R
Address:
ta_port_d11.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
126/1728
9
code
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Component identification
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_port_d11.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
2
1
0
core_reset
3
RESERVED
4
reject
5
RESERVED
6
req_timeout
7
RESERVED
8
req_timeout_rep
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R/W
R
R/
W
R
R/
W
Address:
ta_port_d11.taBaseAddress + 0x20
Type:
R/W
Reset:
0x0000000002000000
Doc ID 018904 Rev 3
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Multilayer interconnect matrix (BUSMATRIX)
Description:
RM0089
Control over agent functions
[25] req_timeout_rep: Request timeout reporting
[10:8] req_timeout: Request timeout control
0: (ta.agent_control.req_timeout.0) no timeout
1: (ta.agent_control.req_timeout.1) 1 base cycle
10: (ta.agent_control.req_timeout.2) 4 base cycles
11: (ta.agent_control.req_timeout.3) 16 base cycles
100: (ta.agent_control.req_timeout.4) 64 base cycles
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
core_reset
R
R
R
burst
4
resp_active
5
readex
6
req_timeout
7
RESERVED
8
timebase
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_waiting
R
R
R
R
R
R
R
R
Address:
ta_port_d11.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
[15:12] timebase: Observation of timebase signals for internal verification
[8] req_timeout: Request timeout status
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
128/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_port_d11.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_port_d11.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
Doc ID 018904 Rev 3
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Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_port_d11.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_port_d11.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
130/1728
9
fraction_13
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_port_d11.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.24
ta_port_i.ta registers
Table 41.
ta_port_i.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
132
0x18
core
Attached core identification
on page
132
0x20
agent_control
Control over agent functions
on page
133
0x28
agent_status
Observability of agent status
on page
133
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
134
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
134
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
135
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
135
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
136
Doc ID 018904 Rev 3
131/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_port_i.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_port_i.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
132/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_port_i.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
7
6
5
4
RESERVED
readex
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
Address:
ta_port_i.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
3
2
1
0
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
Doc ID 018904 Rev 3
133/1728
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_port_i.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_port_i.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
134/1728
9
fraction_5
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_port_i.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_13
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_port_i.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
Doc ID 018904 Rev 3
135/1728
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
RM0089
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_port_i.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.25
ta_i2s_a5.ta registers
Table 42.
ta_i2s_a5.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
137
0x18
core
Attached core identification
on page
137
0x20
agent_control
Control over agent functions
on page
138
0x28
agent_status
Observability of agent status
on page
138
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
139
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
139
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
140
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
140
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
141
136/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
Doc ID 018904 Rev 3
137/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
6
5
4
RESERVED
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
7
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
138/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
Doc ID 018904 Rev 3
139/1728
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
140/1728
9
fraction_13
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_i2s_a5.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.26
ta_mcif_c3.ta registers
Table 43.
ta_mcif_c3.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
142
0x18
core
Attached core identification
on page
142
0x20
agent_control
Control over agent functions
on page
143
0x28
agent_status
Observability of agent status
on page
143
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
144
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
144
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
145
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
145
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
146
Doc ID 018904 Rev 3
141/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
142/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
6
5
4
RESERVED
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
7
3
2
1
0
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
Doc ID 018904 Rev 3
143/1728
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
144/1728
9
fraction_5
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_13
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
Doc ID 018904 Rev 3
145/1728
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
RM0089
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_mcif_c3.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.27
ta_mcif_c4.ta registers
Table 44.
ta_mcif_c4.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
147
0x18
core
Attached core identification
on page
147
0x20
agent_control
Control over agent functions
on page
148
0x28
agent_status
Observability of agent status
on page
148
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
149
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
149
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
150
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
150
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
151
146/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
Doc ID 018904 Rev 3
147/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
6
5
4
RESERVED
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
7
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
148/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
Doc ID 018904 Rev 3
149/1728
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
150/1728
9
fraction_13
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_mcif_c4.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.28
ta_a9sm_q.ta registers
Table 45.
ta_a9sm_q.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
152
0x18
core
Attached core identification
on page
152
0x20
agent_control
Control over agent functions
on page
153
0x28
agent_status
Observability of agent status
on page
153
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
154
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
154
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
155
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
155
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
156
Doc ID 018904 Rev 3
151/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
152/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
2
1
0
core_reset
3
RESERVED
4
reject
5
RESERVED
6
req_timeout
7
RESERVED
8
req_timeout_rep
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R/W
R
R/
W
R
R/
W
Address:
ta_a9sm_q.taBaseAddress + 0x20
Type:
R/W
Reset:
0x0000000002000000
Description:
Control over agent functions
[25] req_timeout_rep: Request timeout reporting
[10:8] req_timeout: Request timeout control
0: (ta.agent_control.req_timeout.0) no timeout
1: (ta.agent_control.req_timeout.1) 1 base cycle
10: (ta.agent_control.req_timeout.2) 4 base cycles
11: (ta.agent_control.req_timeout.3) 16 base cycles
100: (ta.agent_control.req_timeout.4) 64 base cycles
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
core_reset
R
R
R
burst
4
resp_active
5
readex
6
req_timeout
7
RESERVED
8
timebase
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
req_waiting
R
R
R
R
R
R
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Doc ID 018904 Rev 3
3
2
1
0
153/1728
Multilayer interconnect matrix (BUSMATRIX)
Description:
RM0089
Observability of agent status
[15:12] timebase: Observation of timebase signals for internal verification
[8] req_timeout: Request timeout status
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
2
1
0
Fractional bandwidth allocations per thread
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
154/1728
9
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
bandwidth_2
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_13
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
Doc ID 018904 Rev 3
155/1728
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
RM0089
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_a9sm_q.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.29
ta_mpmc_j.ta registers
Table 46.
ta_mpmc_j.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
157
0x18
core
Attached core identification
on page
157
0x20
agent_control
Control over agent functions
on page
158
0x28
agent_status
Observability of agent status
on page
158
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
159
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
159
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
160
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
160
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
161
156/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
Doc ID 018904 Rev 3
157/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
7
6
5
4
RESERVED
readex
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
158/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
Doc ID 018904 Rev 3
159/1728
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
160/1728
9
fraction_13
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_mpmc_j.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.30
ta_mpmc_k.ta registers
Table 47.
ta_mpmc_k.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
162
0x18
core
Attached core identification
on page
162
0x20
agent_control
Control over agent functions
on page
163
0x28
agent_status
Observability of agent status
on page
163
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
164
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
164
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
165
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
165
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
166
Doc ID 018904 Rev 3
161/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
162/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
7
6
5
4
RESERVED
readex
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
3
2
1
0
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
Doc ID 018904 Rev 3
163/1728
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
164/1728
9
fraction_5
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_13
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
Doc ID 018904 Rev 3
165/1728
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
RM0089
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_mpmc_k.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.31
ta_mpmc_l.ta registers
Table 48.
ta_mpmc_l.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
167
0x18
core
Attached core identification
on page
167
0x20
agent_control
Control over agent functions
on page
168
0x28
agent_status
Observability of agent status
on page
168
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
169
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
169
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
170
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
170
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
171
166/1728
Doc ID 018904 Rev 3
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
Doc ID 018904 Rev 3
167/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
7
6
5
4
RESERVED
readex
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
168/1728
Doc ID 018904 Rev 3
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
Doc ID 018904 Rev 3
169/1728
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
170/1728
9
fraction_13
Doc ID 018904 Rev 3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_mpmc_l.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.32
ta_mpmc_m.ta registers
Table 49.
ta_mpmc_m.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
172
0x18
core
Attached core identification
on page
172
0x20
agent_control
Control over agent functions
on page
173
0x28
agent_status
Observability of agent status
on page
173
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
174
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
174
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
175
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
175
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
176
Doc ID 018904 Rev 3
171/1728
Multilayer interconnect matrix (BUSMATRIX)
RM0089
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
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2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
7
6
5
4
RESERVED
readex
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
3
2
1
0
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
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Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
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fraction_5
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1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_13
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
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Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
RM0089
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_mpmc_m.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
4.1.33
ta_mpmc_n.ta registers
Table 50.
ta_mpmc_n.ta register list
Offset
Register name
Description
Page
0x0
component
Component identification
on page
177
0x18
core
Attached core identification
on page
177
0x20
agent_control
Control over agent functions
on page
178
0x28
agent_status
Observability of agent status
on page
178
0x100
bandwidth_0
Fractional bandwidth allocations per thread
on page
179
0x108
bandwidth_1
Fractional bandwidth allocations per thread
on page
179
0x110
bandwidth_2
Fractional bandwidth allocations per thread
on page
180
0x118
bandwidth_3
Fractional bandwidth allocations per thread
on page
180
0x200
alloc_limit_0
Min and max allocation count limits per thread
on page
181
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RM0089
Multilayer interconnect matrix (BUSMATRIX)
component
Component identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x0
Type:
R
Reset:
0x0000000010206333
Description:
Component identification
6
5
4
3
2
1
0
[31:16] code: Component code
[15:0] rev: Revision of the component
core
Attached core identification
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
vendor_code
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
core_code
rev_code
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x18
Type:
R
Reset:
0x000050C500200001
Description:
Attached core identification
6
5
4
3
2
1
0
[47:32] vendor_code: Vendor code (see Open Core Protocol Specification Release 2.2)
[31:16] core_code: Core code (see Open Core Protocol Specification Release 2.2)
[15:0] rev_code: Revision code (see Open Core Protocol Specification Release 2.2)
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Multilayer interconnect matrix (BUSMATRIX)
RM0089
agent_control
Control over agent functions
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
6
5
4
3
2
1
0
core_reset
7
RESERVED
8
reject
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x20
Type:
R
Reset:
0x0000000000000000
Description:
Control over agent functions
[4] reject: Request rejection control
[0] core_reset: Reset control for agent and reset output on core interface
agent_status
Observability of agent status
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
7
6
5
4
RESERVED
readex
burst
resp_active
req_waiting
RESERVED
core_reset
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x28
Type:
R
Reset:
0x0000000000000000
Description:
Observability of agent status
9
8
[7] readex: Status of OCP ReadEx/Write
[6] burst: Status of OCP open bursts
[5] resp_active: OCP responses outstanding
[4] req_waiting: Requests waiting
[0] core_reset: Reset observation for agent and reset input from core interface
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2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
bandwidth_0
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_3
RESERVED
fraction_2
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_1
RESERVED
fraction_0
RESERVED
R
R
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x100
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_3: Fractional bandwidth allocation for thread 4n+3
[47:40] fraction_2: Fractional bandwidth allocation for thread 4n+2
[31:24] fraction_1: Fractional bandwidth allocation for thread 4n+1
[15:8] fraction_0: Fractional bandwidth allocation for thread 4n
bandwidth_1
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_7
RESERVED
fraction_6
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_5
RESERVED
fraction_4
RESERVED
R
R
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x108
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_7:
[47:40] fraction_6:
[31:24] fraction_5:
[15:8] fraction_4:
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Multilayer interconnect matrix (BUSMATRIX)
bandwidth_2
RM0089
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_11
RESERVED
fraction_10
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
fraction_9
RESERVED
fraction_8
RESERVED
R
R
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x110
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
2
1
0
[63:56] fraction_11:
[47:40] fraction_10:
[31:24] fraction_9:
[15:8] fraction_8:
bandwidth_3
Fractional bandwidth allocations per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
fraction_15
RESERVED
fraction_14
RESERVED
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
fraction_12
RESERVED
R
R
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x118
Type:
R
Reset:
0x0000000000000000
Description:
Fractional bandwidth allocations per thread
[63:56] fraction_15:
[47:40] fraction_14:
[31:24] fraction_13:
[15:8] fraction_12:
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fraction_13
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2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
alloc_limit_0
Min and max allocation count limits per thread
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
max_value_0
min_value_0
R
R
R
Address:
ta_mpmc_n.taBaseAddress + 0x200
Type:
R
Reset:
0x0000000000000000
Description:
Min and max allocation count limits per thread
1
0
[15:8] max_value_0: Maximum allocation count limit for thread 4n
[7:0] min_value_0: Minimum allocation count limit for thread 4n
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Multilayer interconnect matrix (BUSMATRIX)
4.2
S3220 registers
Table 51.
S3220 register list
Offset
RM0089
Register name
Description
Page
0x0
component
ID of the component
on page
182
0x10
network
ID of the interconnect
on page
182
0x18
initiator_info
Initiator subsystem information (read-only)
on page
183
0x20
network_control
Global network control function
on page
183
component
ID of the component
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
code
rev
R
R
Address:
laBaseAddress + 0x0
Type:
R
Reset:
0x0000000001006437
Description:
ID of the component
6
5
4
3
2
1
0
[31:16] code: Interconnect code
[15:0] rev: Sonics3220 revision
network
ID of the interconnect
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
id
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R
Address:
laBaseAddress + 0x10
Type:
R
Reset:
0x0000000100000000
Description:
ID of the interconnect
[63:32] id: Unique on-chip interconnect ID
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9
8
7
6
5
4
3
2
1
0
RM0089
Multilayer interconnect matrix (BUSMATRIX)
initiator_info
Initiator subsystem information (read-only)
RESERVED
threads
RESERVED
connid_width
RESERVED
byte_data_width_exp
RESERVED
addr_width
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
R
R
R
R
5
4
3
2
1
segments
6
RESERVED
7
number_regions
8
prot_groups
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
Address:
laBaseAddress + 0x18
Type:
R
Reset:
0x0004021F00250001
Description:
Initiator subsystem information (read-only)
0
[50:48] threads: Number of initiator threads
[46:44] connid_width: Initiator subsystem connID width
[42:40] byte_data_width_exp: Initiator subsystem data width
[37:32] addr_width: Initiator subsystem address width
[27:24] prot_groups: Number of protection groups
[23:16] number_regions: Number of regions
[3:0] segments: Number of segments
network_control
Global network control function
RESERVED
clock_gate_disable
RESERVED
thread0_pri
RESERVED
ext_clock
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
R
R
R
Address:
7
6
5
4
3
RESERVED
8
timeout_base
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
2
1
0
laBaseAddress + 0x20
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Multilayer interconnect matrix (BUSMATRIX)
Type:
R/W
Reset:
0x0000010000000000
Description:
Global network control function
RM0089
[56] clock_gate_disable: Overrides clock gating
[52] thread0_pri: Set thread priority
[40] ext_clock: Global external clock control
[10:8] timeout_base: Timeout period
0: (ta.network_control.timeout_base.0) timeout disabled
1: (ta.network_control.timeout_base.1) base cycles is set to 2^6 Sonics3220 clock cycles
10: (ta.network_control.timeout_base.2) base cycles is set to 2^8 Sonics3220 clock cycles
11: (ta.network_control.timeout_base.3) base cycles is set to 2^10 Sonics3220 clock cycles
100: (ta.network_control.timeout_base.4) base cycles is set to 2^12 Sonics3220 clock cycles
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RM0089
5
System configuration registers (MISC)
System configuration registers (MISC)
Using a 32-bit APB interface, the miscellaneous registers configure the SPEAr1340 global
parameters (such as clocks, resets, and pads) and peripherals.
Section 5.1: Register summary provides an overview of the miscellaneous registers.
Section 5.2: Register descriptions provides a detailed description of each register.
Section 5.3: Pad configuration shows how to configure the SPEAr1340 pads using the
miscellaneous registers.
Section 5.4: Compensation cells provides information on SPEAr1340 compensation cell.
Section 5.5: Inter-processor communication functionality: describes the functionality of
PRCx_LOCK_CTR and PRCx_IRQ_CTR registers.
5.1
Register summary
Table 52.
MISC register list
Offset
Register name
Description
Page
0x000
SOC_CFG
SOC Configuration Register
on page
195
0x004
BOOTSTRAP_CFG
Bootstrap register
on page
195
0x100
PCM_CFG
PCM configuration register
on page
196
0x104
PCM_WKUP_CFG
PCM wake-up configuration register
on page
197
0x108
SWITCH_CTR
Switch control register
on page
197
0x200
SYS_CLK_CTRL
System Clocks Register
on page
198
0x204
SYS_SW_RES
System SW reset
on page
200
0x208
SYS_CLK_PLLTIMER
TimerOut value for SLOW to NORMAL
switch
on page
200
0x20C
SYS_CLK_OSCITIMER
TimerOut value for DOZE to SLOW switch
on page
200
0x210
PLL_CFG
Pll sources configuration
on page
201
0x214
PLL1_CTR
Pll control register
on page
201
0x218
PLL1_FRQ
Pll frequency register
on page
202
0x21C
PLL1_MOD
Pll modulation parameter register
on page
203
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System configuration registers (MISC)
Table 52.
Offset
RM0089
MISC register list (continued)
Register name
Description
Page
0x220
PLL2_CTR
Pll control register
on page
204
0x224
PLL2_FRQ
Pll frequency register
on page
204
0x228
PLL2_MOD
Pll modulation parameter register
on page
205
0x22C
PLL3_CTR
Pll control register
on page
206
0x230
PLL3_FRQ
Pll frequency register
on page
206
0x234
PLL3_MOD
Pll modulation parameter register
on page
207
0x238
PLL4_CTR
Pll control register
on page
208
0x23C
PLL4_FRQ
Pll frequency register
on page
208
0x240
PLL4_MOD
Pll modulation parameter register
on page
209
0x244
PERIP_CLK_CFG
Peripheral clocks configuration
on page
210
0x248
GMAC_CLK_CFG
GMAC clocks configuration register
on page
211
0x24C
I2S_CLK_CFG
I2S_M clock configuration register
on page
211
0x250
C3_CLK_SYNT
C3 clock synthesizer configuration
on page
212
0x254
UART0_CLK_SYNT
UART0 clock synthesizer configuration
on page
213
0x258
UART1_CLK_SYNT
UART1 clock synthesizer configuration
on page
213
0x25C
GMAC_CLK_SYNT
GMAC clock synthesizer configuration
on page
214
0x260
MCIF_SD_CLK_SYNT
MCIF_SD clock synthesizer configuration
on page
214
0x264
MCIF_CFXD_CLK_SYNT
MCIF_CF_XD clock synthesizer
configuration
on page
215
0x270
ADC_CLK_SYNT
ADC converter clock synthesizer
configuration register
on page
215
0x274
AMBA_CLK_SSCG
SSCG6 configuration register
on page
216
0x278
AMBA_CLK_SSCG_MOD
SSCG6 modulation configuration
on page
217
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RM0089
Table 52.
Offset
System configuration registers (MISC)
MISC register list (continued)
Register name
Description
Page
0x27C
CLCD_CLK_SSCG
SSCG5 configuration
on page
217
0x280
CLCD_CLK_SSCG_MOD
SSCG5 modulation configuration
on page
218
0x284
SYS_CLK_SSCG
SSCG4 configuration
on page
219
0x288
SYS_CLK_SSCG_MOD
SSCG4 modulation configuration
on page
219
0x28C
GEN_CLK_SSCG0
SSCG0 configuration
on page
220
0x290
GEN_CLK_SSCG0_MOD
SSCG0 modulation configuration
on page
221
0x294
GEN_CLK_SSCG1
SSCG1 configuration
on page
221
0x298
GEN_CLK_SSCG1_MOD
SSCG1 modulation configuration
on page
222
0x29C
GEN_CLK_SSCG2
SSCG2 configuration
on page
223
0x300
GEN_CLK_SSCG2_MOD
SSCG2 modulation configuration
on page
223
0x304
GEN_CLK_SSCG3
SSCG3 configuration
on page
224
0x308
GEN_CLK_SSCG3_MOD
SSCG3 modulation configuration
on page
225
0x30C
PERIP1_CLK_ENB
Peripherial clock enable register
on page
225
0x310
PERIP2_CLK_ENB
Peripherial clock enable register
on page
227
0x314
PERIP3_CLK_ENB
Peripherial clock enable register
on page
228
0x318
PERIP1_SW_RST
Peripherial reset register
on page
230
0x31C
PERIP2_SW_RST
Peripherial reset register
on page
232
0x320
PERIP3_SW_RST
Peripherial reset register
on page
233
0x400
DMAC_HS_SEL
DMAC HandShake Selection register.
on page
234
0x404
DMAC_SEL
DMA Selection
on page
235
0x408
DMAC_FLOW_SEL
DMA flow selection
on page
236
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System configuration registers (MISC)
Table 52.
Offset
RM0089
MISC register list (continued)
Register name
Description
Page
0x40C
DMAC_DIR_SEL
DMA Peripherial Direction Selection
on page
236
0x410
ENDIANNESS_CFG
DMA Master endianness configuration
on page
237
0x414
USBPHY_GEN_CFG
USB Phy General configuration register
on page
238
0x418
USBPHY_P1_CFG
USB phy P1 configuration (UHC0)
on page
240
0x41C
USBPHY_P2_CFG
USB phy P2 configuration (UOC)
on page
241
0x420
USBPHY_P3_CFG
USB phy P3 configuration (UHC1)
on page
243
0x424
PCIE_SATA_CFG
PCIE - SATA configuration register
on page
245
0x428
PCIE_MIPHY_CFG
PCIE MIPHY configuration register
on page
246
0x42C
PERIP_CFG
Peripheral configuration register
on page
248
0x430
FSMC_CFG
FSMC configuration Register
on page
249
0x434
MPMC_CFG
MPMC Control Status Register
on page
250
0x438
MPMC_CTR_STS
MPMC Control Status Register
on page
250
0x43C
SATA_CORE_ID
SATA controller core id Register
on page
251
0x440
MALI_GEN_PURPOSE_1
Mali GPU general purpose register 1
on page
251
0x444
MALI_GEN_PURPOSE_2
Mali GPU general purpose register 2
on page
251
0x500
PRC1_LOCK_CTR
HW lock configuration register 1
on page
252
0x504
PRC2_LOCK_CTR
HW lock configuration register 2
on page
252
0x508
PRC1_IRQ_CTR
SW Interrupt register for inter-processor
communication
on page
253
0x51C
PRC2_IRQ_CTR
SW Interrupt register for inter-processor
communication
on page
254
0x600
PAD_PU_CFG_1
PAD Pull Up Configuration
on page
255
0x604
PAD_PU_CFG_2
PAD Pull Up Configuration
on page
255
188/1728
Doc ID 018904 Rev 3
RM0089
Table 52.
Offset
System configuration registers (MISC)
MISC register list (continued)
Register name
Description
Page
0x608
PAD_PU_CFG_3
PAD Pull Up Configuration
on page
255
0x60C
PAD_PU_CFG_4
PAD Pull Up Configuration
on page
256
0x610
PAD_PU_CFG_5
PAD Pull Up Configuration
on page
256
0x614
PAD_PU_CFG_6
PAD Pull Up Configuration
on page
256
0x618
PAD_PU_CFG_7
PAD Pull Up Configuration
on page
257
0x61C
PAD_PU_CFG_8
PAD Pull Up Configuration
on page
257
0x620
PAD_PD_CFG_1
PAD Pull Down Configuration
on page
257
0x624
PAD_PD_CFG_2
PAD Pull Down Configuration
on page
258
0x628
PAD_PD_CFG_3
PAD Pull Down Configuration
on page
258
0x62C
PAD_PD_CFG_4
PAD Pull Down Configuration
on page
258
0x630
PAD_PD_CFG_5
PAD Pull Down Configuration
on page
259
0x634
PAD_PD_CFG_6
PAD Pull Down Configuration
on page
259
0x638
PAD_PD_CFG_7
PAD Pull Down Configuration
on page
259
0x63C
PAD_PD_CFG_8
PAD Pull Down Configuration
on page
260
0x648
PAD_DRV_CFG_1
PAD Drive level Configuration
on page
260
0x64C
PAD_DRV_CFG_2
PAD Drive level Configuration
on page
260
0x650
PAD_DRV_CFG_3
PAD Drive level Configuration
on page
261
0x654
PAD_DRV_CFG_4
PAD Drive level Configuration
on page
261
0x65C
PAD_SLEW_CFG_1
PAD Slew level Configuration
on page
262
0x660
PAD_SLEW_CFG_2
PAD Slew level Configuration
on page
262
0x668
PAD_FUNCTION_EN_1
Pad Function selection
on page
262
Doc ID 018904 Rev 3
189/1728
System configuration registers (MISC)
Table 52.
Offset
RM0089
MISC register list (continued)
Register name
Description
Page
0x66C
PAD_FUNCTION_EN_2
Pad Function selection
on page
263
0x670
PAD_FUNCTION_EN_3
Pad Function selection
on page
263
0x674
PAD_FUNCTION_EN_4
Pad Function selection
on page
263
0x690
PAD_FUNCTION_EN_5
Pad Function selection
on page
264
0x694
PAD_FUNCTION_EN_6
Pad Function selection
on page
264
0x698
PAD_FUNCTION_EN_7
Pad Function selection
on page
264
0x69C
PAD_FUNCTION_EN_8
Pad Function selection
on page
265
0x6A0
PAD_SHARED_IP_EN_1
Pad Function selection
on page
265
0x6A8
DDR_PAD_CFG
DDR PAD Configuration
on page
265
0x700
COMPENSATION_1V8_3V3_1_CFG IO_COMP1_1V8_3V3 configuration
on page
266
0x704
COMPENSATION_1V8_3V3_2_CFG IO_COMP2_1V8_3V3 configuration
on page
267
0x708
COMPENSATION_3V3_1_CFG
IO_COMP1_3V3 configuration
on page
268
0x70C
COMPENSATION_3V3_2_CFG
IO_COMP2_3V3 configuration
on page
269
0x710
COMPENSATION_DDR_CFG
IO_COMP_DDR configuration
on page
269
0x714
COMPENSATION_2V5_3V3_1_CFG IO_COMP_2V5_3V3 configuration
on page
270
0x800
OTP_PROG_CTR
OTP configuration register for R/W
management
on page
271
0x804
OTP_WDATA1_1
Data to be written in OTP bank 1
on page
271
0x808
OTP_WDATA1_2
Data to be written in OTP bank 1
on page
272
0x80c
OTP_WDATA1_3
Data to be written in OTP bank 1
on page
272
0x810
OTP_WDATA1_4
Data to be written in OTP bank 1
on page
272
0x814
OTP_WDATA1_5
Data to be written in OTP bank 1
on page
273
190/1728
Doc ID 018904 Rev 3
RM0089
Table 52.
Offset
System configuration registers (MISC)
MISC register list (continued)
Register name
Description
Page
0x818
OTP_WDATA1_6
Data to be written in OTP bank 1
on page
273
0x81c
OTP_WDATA1_7
Data to be written in OTP bank 1
on page
273
0x820
OTP_WDATA1_8
Data to be written in OTP bank 1
on page
273
0x824
OTP_WDATA2_1
Data to be written in OTP bank 2
on page
274
0x828
OTP_WDATA2_2
Data to be written in OTP bank 2
on page
274
0x82c
OTP_WDATA2_3
Data to be written in OTP bank 2
on page
274
0x830
OTP_WDATA2_4
Data to be written in OTP bank 2
on page
275
0x834
OTP_WDATA2_5
Data to be written in OTP bank 2
on page
275
0x838
OTP_WDATA2_6
Data to be written in OTP bank 2
on page
275
0x83c
OTP_WDATA2_7
Data to be written in OTP bank 2
on page
275
0x840
OTP_WDATA2_8
Data to be written in OTP bank 2
on page
276
0x844
OTP_MASK_1
Data to be written in OTP bank m
on page
276
0x848
OTP_MASK_2
Data to be written in OTP bank m
on page
276
0x84c
OTP_MASK_3
Data to be written in OTP bank m
on page
277
0x850
OTP_MASK_4
Data to be written in OTP bank m
on page
277
0x854
OTP_MASK_5
Data to be written in OTP bank m
on page
277
0x858
OTP_MASK_6
Data to be written in OTP bank m
on page
277
0x85c
OTP_MASK_7
Data to be written in OTP bank m
on page
278
0x860
OTP_MASK_8
Data to be written in OTP bank m
on page
278
0x864
OTP_RDATA1_1
Data read from OTP bank 1
on page
278
0x868
OTP_RDATA1_2
Data read from OTP bank 1
on page
279
Doc ID 018904 Rev 3
191/1728
System configuration registers (MISC)
Table 52.
Offset
RM0089
MISC register list (continued)
Register name
Description
Page
0x86c
OTP_RDATA1_3
Data read from OTP bank 1
on page
279
0x870
OTP_RDATA1_4
Data read from OTP bank 1
on page
279
0x874
OTP_RDATA1_5
Data read from OTP bank 1
on page
279
0x878
OTP_RDATA1_6
Data read from OTP bank 1
on page
280
0x87c
OTP_RDATA1_7
Data read from OTP bank 1
on page
280
0x880
OTP_RDATA1_8
Data read from OTP bank 1
on page
280
0x884
OTP_RDATA2_1
Data read from OTP bank 2
on page
281
0x888
OTP_RDATA2_2
Data read from OTP bank 2
on page
281
0x88c
OTP_RDATA2_3
Data read from OTP bank 2
on page
281
0x890
OTP_RDATA2_4
Data read from OTP bank 2
on page
281
0x894
OTP_RDATA2_5
Data read from OTP bank 2
on page
282
0x898
OTP_RDATA2_6
Data read from OTP bank 2
on page
282
0x89c
OTP_RDATA2_7
Data read from OTP bank 2
on page
282
0x8a0
OTP_RDATA2_8
Data read from OTP bank 2
on page
282
0x8a4
OTP_RDATAM_1
Data read from OTP bank m
on page
283
0x8a8
OTP_RDATAM_2
Data read from OTP bank m
on page
283
0x8ac
OTP_RDATAM_3
Data read from OTP bank m
on page
283
0x8b0
OTP_RDATAM_4
Data read from OTP bank m
on page
284
0x8b4
OTP_RDATAM_5
Data read from OTP bank m
on page
284
0x8b8
OTP_RDATAM_6
Data read from OTP bank m
on page
284
0x8bc
OTP_RDATAM_7
Data read from OTP bank m
on page
284
192/1728
Doc ID 018904 Rev 3
RM0089
Table 52.
System configuration registers (MISC)
MISC register list (continued)
Offset
Register name
Description
Page
on page
285
0x8c0
OTP_RDATAM_8
Data read from OTP bank m
0x8c4
THSENS_CFG
THSENS configuration register for threshold on page
and correction settings
285
0x900
A9SM_CLUSTERID
A9SM ID register
on page
286
0x904
A9SM_STATUS
A9SM status register
on page
286
0x908
A9SM_DEBUG
A9SM debug register
on page
287
0x90C
A9SM_FILTER
A9SM address filtering register
on page
287
0x910
A9SM_PARITY_CFG
A9SM parity errors configuration register
on page
288
0x914
A9SM_PARITY_ERR
A9SM parity errors status register
on page
288
0xa00
DIE_ID_1
DIE ID Data 1
on page
289
0xa04
DIE_ID_2
DIE ID Data 2
on page
289
0xa08
DIE_ID_3
DIE ID Data 3
on page
290
0xa0C
DIE_ID_4
DIE ID Data 4
on page
290
0xc00
AXI_CACHE_USER_CTRL_0
Cache and User Info for PCIE0
on page
290
0xc04
AXI_CACHE_USER_CTRL_1
Cache and User Info for PCIE1
on page
290
0xc08
AXI_CACHE_USER_CTRL_2
Cache and User Info for PCIE2/SATA
on page
291
0xc0c
AXI_CACHE_USER_CTRL_3
Cache and User Info for GMAC
on page
291
0xc10
AHB_CACHE_USER_CTRL_0
Cache and User Info for DMAC0
on page
292
0xc14
AHB_CACHE_USER_CTRL_1
Cache and User Info for DMAC1
on page
292
0xc18
AHB_CACHE_USER_CTRL_2
Cache and User Info for UOC
on page
292
0xc1c
AHB_CACHE_USER_CTRL_3
Cache and User Info for UHC0
on page
293
0xc20
AHB_CACHE_USER_CTRL_4
Cache and User Info for UHC1
on page
293
Doc ID 018904 Rev 3
193/1728
System configuration registers (MISC)
Table 52.
Offset
RM0089
MISC register list (continued)
Register name
Description
Page
0xc24
AHB_CACHE_USER_CTRL_5
Cache and User Info for C3
on page
293
0xc28
AHB_CACHE_USER_CTRL_6
Cache and User Info for MCIF
on page
294
0xc2c
AHB_CACHE_USER_CTRL_7
Cache and User Info for EXPI
on page
294
0x1000
MIPHY_TEST
MIPHY debug register
on page
294
0x1004
USB_TEST
USB debug register
on page
295
0x1008
MISC_CFG
MISC configuration register
on page
295
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RM0089
System configuration registers (MISC)
5.2
Register descriptions
SOC_CFG
SOC Configuration Register
6
5
4
3
2
soc_cfg
7
RESERVED
8
gpt_dbg_en
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R
Address:
Misc_RegisterBaseAddress + 0x000
Type:
R/W
Reset:
0x0000 0000
Description:
SOC Configuration Register
1
0
[24:23] gpt_dbg_en: Disable clk_timer when CPUs are in debug state.
00 : clk_timer isn‘t disabled;
01 : clk_timer disable when CPU0 is in debug state;
10 : clk_timer disable when CPU1 is in debug state;
11 : clk_timer disable when either CPU0 or CPU1 are in debug state
[4:0] soc_cfg: Soc configuration.
It reflects the TEST[4:0] pad state
6
5
4
gmii_sel
flash_sel_16
flash_sel_8
boot_sel
Bootstrap register
RESERVED
BOOTSTRAP_CFG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
Address:
Misc_RegisterBaseAddress + 0x004
Type:
R
Reset:
0x0
Description:
Bootstrap register
9
8
7
3
2
1
0
[6] gmii_sel: Reflects the inverted logic value of pad STRAP6 at reset release.
Used to select the GMII/RGMII interface working at 3V3 or 2V5.
0 : 2V5 (STRAP6=1)
1 : 3V3 (STRAP6=0)
[5] flash_sel_16: Reflects the logic value of pad STRAP5 at reset release.
Used to select the NAND Flash 16 bit interface (along with CE1n) working at 3V3 or 1V8.
0 : 1V8
1 : 3V3
[4] flash_sel_8: Reflects the logic value of pad STRAP4 at reset release.
Used to select the NAND Flash 8 bit interface (along with CE0n) working at 3V3 or 1V8.
0 : 1V8
1 : 3V3
[3:0] boot_sel: Reflects the logic value of pads STRAP[3:0] at reset release.
Doc ID 018904 Rev 3
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System configuration registers (MISC)
RM0089
PCM_CFG
PCM configuration register
2
wakeup_en
3
wakeup_trig
4
sw_config
5
config_ack
6
config_bad
7
ack_power_state
8
ddr_phy_no_shutoff
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R/
W
R/W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x100
Type:
R/W
Reset:
0x107C00
Description:
PCM configuration register
1
0
[20] ddr_phy_no_shutoff: Selects whether the
DDRIO_VDD1V8_1V5_OFF,DDRPHY_VDD1V2_OFF pads are used as control lines for the
switching of DDRPHY external power supplies or as signals of GPIO_B block.
0 : DDRIO_VDD1V8_1V5_OFF,DDRPHY_VDD1V2_OFF are used as control for extern
DDRPHY power supplies.
DDRPHY_VDD1V2_OFF to control 1V2 power supply,DDRIO_VDD1V8_1V5_OFF to
control 1V8 power supply,
1 : DDRIO_VDD1V8_1V5_OFF,DDRPHY_VDD1V2_OFF are connected to the GPIO_B[6:5]
pins.
[19:16] ack_power_state: Current power state
[15] config_bad: that indicates that the current configuration could not be served (illegal
configuration), for debug purposes.The SW can only reset.posedge detect (RisingSet Write
Clear)
[14] config_ack: acknowledges that the current configuration is active.The SW can only reset
.posedge detect
[13:10] sw_config: represents the expected final state to be reached by PCM. Each bit represents the
ON(1) or OFF(0) condition for one of the available power domains (ARM; GPU; CODEC; BUS).
[9:5] wakeup_trig: identify which of the 5 possible wakeup sources has actually triggered the
wakeup of the system.The SW can only reset. Capture Posedge. The sources are :
wakeup_trig(4)
Ethernet (PMT interrupt)
wakeup_trig(3)
RTC
wakeup_trig(2)
GPIO (wakeup source on GPIO_WKUP_TRIG pad)
wakeup_trig(1)
UOC
wakeup_trig(0)
Reserved
[4:0] wakeup_en: that indicate which of the 5 possible wakeup sources are allowed to wakeup the
system.They are :
wakeup_en(4)
Ethernet
wakeup_en(3)
RTC
wakeup_en(2)
GPIO
wakeup_en(1)
UOC
wakeup_en(0)
Reserved
196/1728
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RM0089
System configuration registers (MISC)
PCM_WKUP_CFG
PCM wake-up configuration register
4
3
2
1
RESERVED
5
rtc_wkup_config
6
gpio_wkup_config
7
usbdev_wkup_config
8
ethernet_wkup_config
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R
Address:
Misc_RegisterBaseAddress + 0x104
Type:
R/W
Reset:
0x11115
Description:
PCM wake-up configuration register
0
[19:16] ethernet_wkup_config: Power island configuration to be reached when receiving wakeup
trigger from ETHERNET :
[ARM, GPU, CODEC, BUS]
for each bit, 1 = on; 0 = off
[15:12] usbdev_wkup_config: Power island configuration to be reached when receiving wakeup
trigger from USB DEVICE :
[ARM, GPU, CODEC, BUS]
for each bit, 1 = on; 0 = off
[11:8] gpio_wkup_config: Power island configuration to be reached when receiving wakeup trigger
from GPIO :
[ARM, GPU, CODEC, BUS]
for each bit, 1 = on; 0 = off
[7:4] rtc_wkup_config: Power island configuration to be reached when receiving wakeup trigger
from RTC :
[ARM, GPU, CODEC, BUS]
for each bit, 1 = on; 0 = off
SWITCH_CTR
Switch control register
1
0
pd1_ctrl0
2
pd1_ctrl1
3
pd2_ctrl0
4
pd2_ctrl1
5
pd3_ctrl0
6
pd3_ctrl1
7
pd4_ctrl0
8
pd4_ctrl1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x108
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
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System configuration registers (MISC)
Description:
RM0089
Switch control register
[7] pd4_ctrl1: controls the maximum current available through switch ring of pd4 (ARM) during its
powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
[6] pd4_ctrl0: controls the maximum current available through switch ring of pd4 (ARM) during its
powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
[5] pd3_ctrl1: controls the maximum current available through switch ring of pd3 (GPU) during its
powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
[4] pd3_ctrl0: controls the maximum current available through switch ring of pd3 (GPU) during its
powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
[3] pd2_ctrl1: controls the maximum current available through switch ring of pd2 (CODEC) during
its powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
[2] pd2_ctrl0: controls the maximum current available through switch ring of pd2 (CODEC) during
its powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
[1] pd1_ctrl1: controls the maximum current available through switch ring of pd1 (BUS) during its
powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
[0] pd1_ctrl0: controls the maximum current available through switch ring of pd1 (BUS) during its
powerup transient.
(ctrl1,ctrl0) = 00 : min current
(ctrl1,ctrl0) = 11 : max current
osci30_ok
osci32k_ok
sys_mode_req
RESERVED
plltimeout_en
sys_status
R/W
oscidiv_en
R/
W
oscidiv_cfg
R/
W
clksys_src
R
RESERVED
8
hclk_sel
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
xtaltimeout_en
System Clocks Register
RESERVED
SYS_CLK_CTRL
R
R/
W
R
R/W
R/W
R/
W
R
R
R
R
Address:
Misc_RegisterBaseAddress + 0x200
Type:
R/W
Reset:
0x0000 0000
198/1728
Doc ID 018904 Rev 3
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
Description:
System Clocks Register
[27] hclk_sel: hclk selector
0 : cpu_clk divided by 3
1 : SSCG6 (see AMBA_CLK_SSCG).
Pclk is always hclk divided by 2
[25:23] clksys_src: System clock source (sys_clk) in NORMAL mode
0XX : PLL1 (default)
10X : SSCG4 (see SYS_CLK_SSCG register)
110 : PLL2
111 : PLL3
CPU clock (cpu_clk)is always sys_clk divided by 2
[22:21] oscidiv_cfg: Osci1 divider factor in SLOW mode. Set the divider factor on osci1 clock in SLOW
mode.
00 : by 2
01 : by 4
10 : by 16
11 : by 32
[20] oscidiv_en: Enable osci1 divider in SLOW mode.
0 : divisor disabled.See oscidiv_cfg field.
1 : divisor enabled.Osci1 clock is used in SLOW mode
[19:16] sys_status: System Clock Status :
0000 : DOZE
1000 : XTALCNTRL
1010 : SWTOXTAL
1010 : SLOW
1110 : PLLCNTRL
1000 : SWFROMXTAL
1111 : SWTOPLL
1111 : NORMAL
1110 : SWFROMPLL
[9] osci30_ok: OSCI30 (24 MHz osci1 clock) status.
0 : osci clock isn‘t stable
1 : osci clock is stable
[8] osci32k_ok: OSCI32K (32KHz osci2 clock) status.
0 : osci clock isn‘t stable
1 : osci clock is stable
[4] xtaltimeout_en: XTAL Timer enable.
0 : the switch from DOZE to SLOW takes 5 DOZE clock pulses
1 : the switch from DOZE to SLOW mode happens after DOZE clock counts the for the value
stored in SYS_CLK_OSCITIMER register.
[3] plltimeout_en: PLL Timer enable.
0 : the switch from SLOW to DOZE takes 5 SLOW clock pulses
1 : the switch from SLOW to NORMAL mode happens after SLOW clock counts the value
stored in SYS_CLK_PLLTIMER register.
[2:0] sys_mode_req: Clock Mode Selector :
001 : DOZE : osci2 (32KHz), osci1.See PERIP_CLK_CFG[0] field.
010 : SLOW : osci1 (24 MHz)
100 : NORMAL : clock selected through clocksys_src
field
Doc ID 018904 Rev 3
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System configuration registers (MISC)
RM0089
SYS_SW_RES
System SW reset
5
4
3
2
1
0
sw_reset
6
sw_reset_clear
7
sw_reset_status
8
R
R
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x204
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
System SW reset
[2] sw_reset_status: reading ‘1‘ means system reset occurred
[1] sw_reset_clear: writing ‘1‘ clear sw_reset_status
[0] sw_reset: writing ‘1‘ cause system reset
SYS_CLK_PLLTIMER
TimerOut value for SLOW to NORMAL switch
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
pllcount
R
R/W
Address:
Misc_RegisterBaseAddress + 0x208
Type:
R/W
Reset:
0x0000 0000
Description:
9
8
7
6
5
4
3
2
1
0
TimerOut value for SLOW to NORMAL switch
[24:0] pllcount: TimerOut value for SLOW to NORMAL switch
SYS_CLK_OSCITIMER
TimerOut value for DOZE to SLOW switch
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
oscicount
R
R/W
Address:
Misc_RegisterBaseAddress + 0x20C
Type:
R/W
Reset:
0x0000 0000
Description:
TimerOut value for DOZE to SLOW switch
[24:0] oscicount: TimerOut value for DOZE to SLOW switch
200/1728
Doc ID 018904 Rev 3
9
8
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
PLL_CFG
Pll sources configuration
gen_sscg23_sel
gen_sscg01_sel
RESERVED
pll3_clk_sel
pll2_clk_sel
pll1_clk_sel
RESERVED
9
clcd_synth_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/W
R/W
R
R/W
R/W
R/W
R
Address:
Misc_RegisterBaseAddress + 0x210
Type:
R/W
Reset:
0x0000 0000
Description:
8
7
6
5
4
3
2
1
0
Pll sources configuration
[31] clcd_synth_sel: SSCG5 input clock source selector :
0: vco1div4 (VCO of pll1 divided by 4)
1: pll2out
[30:29] gen_sscg23_sel: SSCG[2,3] clock source selector :
00 : vco1div4
01 : vco2div2
10 : pll2out
[28:27] gen_sscg01_sel: SSCG[0,1] clock source selector :
00 : vco1div4
01 : vco3div2
10 : pll3out
[25:24] pll3_clk_sel: PLL3 input clock source selector :
00 : osci1 (24 MHz)
01 : osci3 (25 MHz)
10 : XGPIO132 pad
[23:22] pll2_clk_sel: PLL2 input clock source selector :
00 : osci1 (24 MHz)
01 : osci3 (25 MHz)
10 : XGPIO132 pad
[21:20] pll1_clk_sel: PLL1 input clock source selector :
00 : osci1 (24 MHz)
01 : osci3 (25 MHz)
10 : XGPIO90 pad
PLL1_CTR
Pll control register
4
3
2
1
0
pll_lock
5
pll_resetn
6
pll_enable
7
pll_control1
8
pll_control2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/
W
R/
W
R
Address:
Misc_RegisterBaseAddress + 0x214
Type:
R/W
Doc ID 018904 Rev 3
201/1728
System configuration registers (MISC)
Reset:
0x0000 3E00
Description:
Pll control register
RM0089
[13:9] pll_control2: Pll charge pump configuration
The Charge Pump current is :
C.P. current [uA] = 8 uA + pll_control2 * 0.5 uA.
[8:3] pll_control1: pll_control1[0]= sample :
0 : pll parameters sample
1: no action
pll_control1[2:1]= dither-mode :
00 : normal mode
01 : fractional-N
10 : dithering (DSM)
11 : dithering (SSM)
pll_control1[4:3]= sigma-delta order :
00 : 1st order
01 : 2nd order
1x : n.a.
pll_control1[5] = fbkclk_sel :
0 : internal feedback
1 : external feedback
[2] pll_enable: Pll enable :
0 : pll disabled
1 : pll enabled
[1] pll_resetn: Pll soft reset command :
0 : pll reset active
1 : pll reset disable
[0] pll_lock: Pll lock status :
0 : pll unlocked
1 : pll locked
PLL1_FRQ
Pll frequency register
5
4
3
pll_prediv_N
6
pll_postdiv_P
7
RESERVED
8
R/W
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x218
Type:
R/W
Reset:
0x6800 0005
202/1728
9
pll_fbkdiv_M
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
System configuration registers (MISC)
Description:
Pll frequency register
[31:16] pll_fbkdiv_M: Pll feedback divisor values.
The VCO frequency is
Fvco = Fref * 2 * M[15:8]
Fref is the frequency of pre divider output.
Range : M= 8,9,10, ....254,255.
When the PLL works in normal mode (see PLLx_CTR) only the 8 MSBs are used.In the other
modes (fractional and dithered) all 16 bits are used and VCO frequency is
Fvco = Fref * 2 * M / 256
VCO frequency range : [800 MHz , 1600 MHz]
[10:8] pll_postdiv_P: Pll post divisor values
The post divider use the VCO clock to generate the PLL output.
Fout= Fvco / 2^P
Range : P = 0,1,2,3,4,5,6
[7:0] pll_prediv_N: Pll pre divisor values.
The pre-divider generates the reference clock (Fref) for the VCO.
Fref = Fin / N
Use PLL_CFG to select Fin : osci1 by default
Range : N = 1,2,3,4,5,6,7
PLL1_MOD
Pll modulation parameter register
7
pll_slope
8
pll_modperiod
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x21C
Type:
R/W
Reset:
0x0
Description:
Pll modulation parameter register
6
5
4
3
2
1
0
[28:16] pll_modperiod: Pll modulation wave parameters
pll_modperiod = Fref/(4 * Fmod)
with Fref predivider output frequency in KHz ,
Fmod frequency of modulation wave in KHz
[15:0] pll_slope: Pll slope modulation wave parameters
pll_slope = (2^8 * md * M ) / pll_mod_period
with md modulation depth,
M = pll_fbkdiv_M
Doc ID 018904 Rev 3
203/1728
System configuration registers (MISC)
RM0089
PLL2_CTR
Pll control register
3
2
1
0
pll_lock
4
pll_resetn
5
pll_enable
6
pll_control1
7
pll_control2
8
R
R/W
R/W
R/
W
R/
W
R
Address:
Misc_RegisterBaseAddress + 0x220
Type:
R/W
Reset:
0x0000 3E00
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Pll control register
[13:9] pll_control2: Pll charge pump configuration
The Charge Pump current is :
C.P. current [uA] = 8 uA + pll_control2 * 0.5 uA.
[8:3] pll_control1: pll_control1[0]= sample :
0 : pll parameters sample
1: no action
pll_control1[2:1]= dither-mode :
00 : normal mode
01 : fractional-N
10 : dithering (DSM)
11 : dithering (SSM)
pll_control1[4:3]= sigma-delta order :
00 : 1st order
01 : 2nd order
1x : n.a.
pll_control1[5] = fbkclk_sel :
0 : internal feedback
1 : external feedback
[2] pll_enable: Pll enable :
0 : pll disabled
1 : pll enabled
[1] pll_resetn: Pll soft reset command :
0 : pll reset active
1 : pll reset disable
[0] pll_lock: Pll lock status :
0 : pll unlocked
1 : pll locked
PLL2_FRQ
Pll frequency register
Address:
204/1728
6
5
4
3
pll_prediv_N
7
pll_postdiv_P
8
RESERVED
9
pll_fbkdiv_M
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R/W
Misc_RegisterBaseAddress + 0x224
Doc ID 018904 Rev 3
2
1
0
RM0089
System configuration registers (MISC)
Type:
R/W
Reset:
0x6800 0305
Description:
Pll frequency register
[31:16] pll_fbkdiv_M: Pll feedback divisor values.
The VCO frequency is
Fvco = Fref * 2 * M[15:8]
Fref is the frequency of pre divider output.
Range : M= 8,9,10, ....254,255.
When the PLL works in normal mode (see PLLx_CTR) only the 8 MSBs are used.In the other
modes (fractional and dithered) all 16 bits are used and VCO frequency is
Fvco = Fref * 2 * M / 256
VCO frequency range : [800 MHz , 1600 MHz]
[10:8] pll_postdiv_P: Pll post divisor values
The post divider use the VCO clock to generate the PLL output.
Fout= Fvco / 2^P
Range : P = 0,1,2,3,4,5,6
[7:0] pll_prediv_N: Pll pre divisor values.
The pre-divider generates the reference clock (Fref) for the VCO.
Fref = Fin / N
Use PLL_CFG to select Fin : osci1 by default
Range : N = 1,2,3,4,5,6,7
PLL2_MOD
Pll modulation parameter register
7
pll_slope
8
pll_modperiod
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x228
Type:
R/W
Reset:
0x0
Description:
Pll modulation parameter register
6
5
4
3
2
1
0
[28:16] pll_modperiod: Pll modulation wave parameters
pll_modperiod = Fref/(4 * Fmod)
with Fref predivider output frequency in KHz ,
Fmod frequency of modulation wave in KHz
[15:0] pll_slope: Pll slope modulation wave parameters
pll_slope = (2^8 * md * M ) / pll_mod_period
with md modulation depth,
M = pll_fbkdiv_M
Doc ID 018904 Rev 3
205/1728
System configuration registers (MISC)
RM0089
PLL3_CTR
Pll control register
3
2
1
0
pll_lock
4
pll_resetn
5
pll_enable
6
pll_control1
7
pll_control2
8
R
R/W
R/W
R/
W
R/
W
R
Address:
Misc_RegisterBaseAddress + 0x22C
Type:
R/W
Reset:
0x0000 3E00
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Pll control register
[13:9] pll_control2: Pll charge pump configuration
The Charge Pump current is :
C.P. current [uA] = 8 uA + pll_control2 * 0.5 uA.
[8:3] pll_control1: pll_control1[0]= sample :
0 : pll parameters sample
1: no action
pll_control1[2:1]= dither-mode :
00 : normal mode
01 : fractional-N
10 : dithering (DSM)
11 : dithering (SSM)
pll_control1[4:3]= sigma-delta order :
00 : 1st order
01 : 2nd order
1x : n.a.
pll_control1[5] = fbkclk_sel :
0 : internal feedback
1 : external feedback
[2] pll_enable: Pll enable :
0 : pll disabled
1 : pll enabled
[1] pll_resetn: Pll soft reset command :
0 : pll reset active
1 : pll reset disable
[0] pll_lock: Pll lock status :
0 : pll unlocked
1 : pll locked
PLL3_FRQ
Pll frequency register
Address:
206/1728
6
5
4
3
pll_prediv_N
7
pll_postdiv_P
8
RESERVED
9
pll_fbkdiv_M
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R/W
Misc_RegisterBaseAddress + 0x230
Doc ID 018904 Rev 3
2
1
0
RM0089
System configuration registers (MISC)
Type:
R/W
Reset:
0x4100 0403
Description:
Pll frequency register
[31:16] pll_fbkdiv_M: Pll feedback divisor values.
The VCO frequency is
Fvco = Fref * 2 * M[15:8]
Fref is the frequency of pre divider output.
Range : M= 8,9,10, ....254,255.
When the PLL works in normal mode (see PLLx_CTR) only the 8 MSBs are used.In the other
modes (fractional and dithered) all 16 bits are used and VCO frequency is
Fvco = Fref * 2 * M / 256
VCO frequency range : [800 MHz , 1600 MHz]
[10:8] pll_postdiv_P: Pll post divisor values
The post divider use the VCO clock to generate the PLL output.
Fout= Fvco / 2^P
Range : P = 0,1,2,3,4,5,6
[7:0] pll_prediv_N: Pll pre divisor values.
The pre-divider generates the reference clock (Fref) for the VCO.
Fref = Fin / N
Use PLL_CFG to select Fin : osci1 by default
Range : N = 1,2,3,4,5,6,7
PLL3_MOD
Pll modulation parameter register
7
pll_slope
8
pll_modperiod
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x234
Type:
R/W
Reset:
0x0
Description:
Pll modulation parameter register
6
5
4
3
2
1
0
[28:16] pll_modperiod: Pll modulation wave parameters
pll_modperiod = Fref/(4 * Fmod)
with Fref predivider output frequency in KHz ,
Fmod frequency of modulation wave in KHz
[15:0] pll_slope: Pll slope modulation wave parameters
pll_slope = (2^8 * md * M ) / pll_mod_period
with md modulation depth,
M = pll_fbkdiv_M
Doc ID 018904 Rev 3
207/1728
System configuration registers (MISC)
RM0089
PLL4_CTR
Pll control register
3
2
1
0
pll_lock
4
pll_resetn
5
pll_enable
6
pll_control1
7
pll_control2
8
R
R/W
R/W
R/
W
R/
W
R
Address:
Misc_RegisterBaseAddress + 0x238
Type:
R/W
Reset:
0x0000 3E00
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Pll control register
[13:9] pll_control2: Pll charge pump configuration
The Charge Pump current is :
C.P. current [uA] = 8 uA + pll_control2 * 0.5 uA.
[8:3] pll_control1: pll_control1[0]= sample :
0 : pll parameters sample
1: no action
pll_control1[2:1]= dither-mode :
00 : normal mode
01 : fractional-N
10 : dithering (DSM)
11 : dithering (SSM)
pll_control1[4:3]= sigma-delta order :
00 : 1st order
01 : 2nd order
1x : n.a.
[2] pll_enable: Pll enable :
0 : pll disabled
1 : pll enabled
[1] pll_resetn: Pll soft reset command :
0 : pll reset active
1 : pll reset disable
[0] pll_lock: Pll lock status :
0 : pll unlocked
1 : pll locked
PLL4_FRQ
Pll frequency register
5
4
3
pll_prediv_N
6
pll_postdiv_P
7
RESERVED
8
R/W
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x23C
Type:
R/W
Reset:
0x0
208/1728
9
pll_fbkdiv_M
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
System configuration registers (MISC)
Description:
Pll frequency register
[31:16] pll_fbkdiv_M: Pll feedback divisor values.
The VCO frequency is
Fvco = Fref * 2 * M[15:8]
Fref is the frequency of pre divider output.
Range : M= 8,9,10, ....254,255.
When the PLL works in normal mode (see PLLx_CTR) only the 8 MSBs are used.In the other
modes (fractional and dithered) all 16 bits are used and VCO frequency is
Fvco = Fref * 2 * M / 256
VCO frequency range : [800 MHz , 1600 MHz]
[10:8] pll_postdiv_P: Pll post divisor values
The post divider use the VCO clock to generate the PLL output.
Fout= Fvco / 2^P
Range : P = 0,1,2,3,4,5,6
[7:0] pll_prediv_N: Pll pre divisor values.
The pre-divider generates the reference clock (Fref) for the VCO.
Fref = Fin / N
with Fin= F(osci1).
Range : N = 1,2,3,4,5,6,7
PLL4_MOD
Pll modulation parameter register
7
pll_slope
8
pll_modperiod
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x240
Type:
R/W
Reset:
0x0
Description:
Pll modulation parameter register
6
5
4
3
2
1
0
[28:16] pll_modperiod: Pll modulation wave parameters
pll_modperiod = Fref/(4 * Fmod)
with Fref predivider output frequency in KHz ,
Fmod frequency of modulation wave in KHz
[15:0] pll_slope: Pll slope modulation wave parameters
pll_slope = (2^8 * md * M ) / pll_mod_period
with md modulation depth,
M = pll_fbkdiv_M
Doc ID 018904 Rev 3
209/1728
System configuration registers (MISC)
RM0089
PERIP_CLK_CFG
Peripheral clocks configuration
uartclk1_sel
uartclk0_sel
clcdclk_sel
c3clk_sel
osci2_dis
0
gpt0_clk_sel
1
gpt1_clk_sel
2
Reserved
3
RESERVED
4
gpt2_clk_sel
5
R
R/
W
R/
W
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x244
Type:
R/W
Reset:
0x0000 0401
Description:
Peripheral clocks configuration
[15] spdifout_clk_sel: SPDIF_OUT clock selector
0 : the clock source is XGPIO102 pad
1 : the clock source is SSCG2
[14] spdifin_clk_sel: SPDIFIN clock selector
0 : pll2out is selected
1 : SSCG3 output is selected
[13] gpt3_clk_sel: GPT3 clk_timer selector
0 : clk_timer= osci1 (@24 MHz)
1 : clk_timer= pclk (synchronous )
[12] gpt2_clk_sel: GPT2 clk_timer selector
0 : clk_timer= osci1 (@24 MHz)
1 : clk_timer= pclk (synchronous )
[10] Reserved: Do not write
[9] gpt1_clk_sel: GPT1 clk_timer selector
0 : clk_timer= osci1 (@24 MHz)
1 : clk_timer= pclk (synchronous )
[8] gpt0_clk_sel: GPT0 clk_timer selector
0 : clk_timer= osci1 (@24 MHz)
1 : clk_timer= pclk (synchronous )
[7:6] uartclk1_sel: UART1 clock selector :
00 : 48 MHz coming from USB PHY
01 : 24 MHz from osci1
10 : clock synthesizer programmable through UART1_CLK_SYNT
[5:4] uartclk0_sel: UART0 clock selector :
00 : 48 MHz coming from USB PHY
01 : 24 MHz from OSCI1
10 : clock synthesizer programmable through UART0_CLK_SYNT
210/1728
6
gpt3_clk_sel
7
spdifin_clk_sel
8
spdifout_clk_sel
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
System configuration registers (MISC)
[3:2] clcdclk_sel: CLCD clock selector :
00 : 48 MHz coming from USB PHY
01 : SSCG5 clock programmable through CLCD_CLK_SSCG and PLL_CFG[31]
10 : XGPIO132 pad
11 : pll3out
[1] c3clk_sel: C3 clock selector :
0 : 48 MHz coming from USB PHY
1 : clock synthesizer programmable through C3_CLK_SYNT
[0] osci2_dis: disable osci2 as system clock source
0: osci2 is used in DOZE mode as source for system clock
1: osci2 is disabled. In this case osci1 is used in DOZE mode.
GMAC_CLK_CFG
GMAC clocks configuration register
6
5
4
3
2
1
0
clk_sel
7
synth_en
8
macphy_sel
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x248
Type:
R/W
Reset:
0x0000 0000
Description:
GMAC clocks configuration register
[5:3] macphy_sel: GMAC PHY Interface Selector :
000 : GMII/MII
001 : RGMII
100 : RMII
[2] synth_en: GMAC clock synthesizer source enable:
0: Disable GMAC synthesizer clock source.
GMAC clocks are provided in agree with the clk_sel source clock definitions.
1: Enable GMAC synthesizer clock source.
GMAC clocks are provided by clock synthesizer logic
[1:0] clk_sel: GMAC internal source clock definition :
00 : MAC_GTXCLK125 pad
01 : pll2out
10 : osci3 (25/100 MHz)
I2S_CLK_CFG
I2S_M clock configuration register
1
0
refout_div_src
2
refout_div_en
3
refout_div_sel
4
refout_div_y
5
refout_div_x
6
sclk_div_en
7
sclk_div_sel
8
sclk_div_y
9
sclk_div_x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/
W
R/
W
R/W
R/W
R/
W
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x24C
Doc ID 018904 Rev 3
211/1728
System configuration registers (MISC)
RM0089
Type:
R/W
Reset:
0x0000 0000
Description:
I2S_M clock configuration register
[31:27] sclk_div_x: I2S_M clock synthesizer X parameter
[26:22] sclk_div_y: I2S_M clock synthesizer Y parameter ; with X less than or equal to Y/2
[21] sclk_div_sel: I2S_M clock synthesizer Fout selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin = Fout(refout) when refout_div_en = 1 else it is one of the source selected by
refout_div_src
[20] sclk_div_en: I2S_M clock synthesizer enable
0: synthesizer disabled
1: synthesizer enabled
[19:12] refout_div_x: I2S refout clock X synthesizer parameter
[11:4] refout_div_y: I2S refout clock Y synthesizer parameter ; with X less than or equal to Y/2
[3] refout_div_sel: I2S refout clock synthesizer selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin selected by refout_div_src.
The refout clock is a reference clock and could be used by external I2S device as oversampling
clock. The clock is present on I2S_OUT_OVRSAMP_CLK pad
[2] refout_div_en: I2S refout clock synthesizer enable
0: synthesizer disabled
1: synthesizer enabled
[1:0] refout_div_src: I2S refout synthesizer source selection :
00 vco1div2
01 pll2out
10 pll3out
11 I2S_OUT_REFCLK pad.
The selected source drives the refout clock synthesizer
C3_CLK_SYNT
C3 clock synthesizer configuration
synt_ydiv
5
RESERVED
6
synt_xdiv
7
RESERVED
8
synt_clk_enb
9
synt_clkout_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x250
Type:
R/W
Reset:
0x0000 0000
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RM0089
System configuration registers (MISC)
Description:
C3 clock synthesizer configuration
[31] synt_clk_enb: Synthesizer enable :
0 : synthesizer disabled
1 : synthesizer enabled
[30] synt_clkout_sel: Output clock synthesizer selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin = vco1div2 (pll1 vco output divided by 2)
[27:16] synt_xdiv: X synthesizer parameter ; with X less than or equal to Y/2
[11:0] synt_ydiv: Y synthesizer parameter
UART0_CLK_SYNT
UART0 clock synthesizer configuration
synt_ydiv
5
RESERVED
6
synt_xdiv
7
RESERVED
8
synt_clk_enb
9
synt_clkout_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x254
Type:
R/W
Reset:
0x0000 0000
Description:
UART0 clock synthesizer configuration
4
3
2
1
0
[31] synt_clk_enb: Synthesizer enable :
0 : synthesizer disabled
1 : synthesizer enabled
[30] synt_clkout_sel: Output clock synthesizer selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin = vco1div2 (pll1 vco output divided by 2)
[27:16] synt_xdiv: X synthesizer parameter ; with X less than or equal to Y/2
[11:0] synt_ydiv: Y synthesizer parameter
UART1_CLK_SYNT
UART1 clock synthesizer configuration
synt_ydiv
5
RESERVED
6
synt_xdiv
7
RESERVED
8
synt_clk_enb
9
synt_clkout_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x258
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
4
3
2
1
0
213/1728
System configuration registers (MISC)
Description:
RM0089
UART1 clock synthesizer configuration
[31] synt_clk_enb: Synthesizer enable :
0 : synthesizer disabled
1 : synthesizer enabled
[30] synt_clkout_sel: Output clock synthesizer selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin = vco1div2 (pll1 vco output divided by 2)
[27:16] synt_xdiv: X synthesizer parameter ; with X less than or equal to Y/2
[11:0] synt_ydiv: Y synthesizer parameter
GMAC_CLK_SYNT
GMAC clock synthesizer configuration
synt_ydiv
5
RESERVED
6
synt_xdiv
7
RESERVED
8
synt_clk_enb
9
synt_clkout_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x25C
Type:
R/W
Reset:
0x0000 0000
Description:
GMAC clock synthesizer configuration
4
3
2
1
0
[31] synt_clk_enb: Synthesizer enable :
0 : synthesizer disabled
1 : synthesizer enabled
[30] synt_clkout_sel: Output clock synthesizer selection
0 : Fout = Fin * X / (2 * Y)
1 : Fout = Fin * X / Y
with Fin set by GMAC_CLK_CFG[2:1]
[27:16] synt_xdiv: X synthesizer parameter ; with X less than or equal to Y/2
[11:0] synt_ydiv: Y synthesizer parameter
MCIF_SD_CLK_SYNT
MCIF_SD clock synthesizer configuration
synt_ydiv
5
RESERVED
6
synt_xdiv
7
RESERVED
8
synt_clk_enb
9
synt_clkout_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x260
Type:
R/W
Reset:
0x0000 0000
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2
1
0
RM0089
System configuration registers (MISC)
Description:
MCIF_SD clock synthesizer configuration
[31] synt_clk_enb: Synthesizer enable :
0 : synthesizer disabled
1 : synthesizer enabled
[30] synt_clkout_sel: Output clock synthesizer selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin = vco1div2 (pll1 vco output divided by 2)
[27:16] synt_xdiv: X synthesizer parameter ; with X less than or equal to Y/2
[11:0] synt_ydiv: Y synthesizer parameter
MCIF_CFXD_CLK_SYNT
MCIF_CF_XD clock synthesizer configuration
synt_ydiv
5
RESERVED
6
synt_xdiv
7
RESERVED
8
synt_clk_enb
9
synt_clkout_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x264
Type:
R/W
Reset:
0x0000 0000
Description:
MCIF_CF_XD clock synthesizer configuration
4
3
2
1
0
[31] synt_clk_enb: Synthesizer enable :
0 : synthesizer disabled
1 : synthesizer enabled
[30] synt_clkout_sel: Output clock synthesizer selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin = vco1div2 (pll1 vco output divided by 2)
[27:16] synt_xdiv: X synthesizer parameter ; with X less than or equal to Y/2
[11:0] synt_ydiv: Y synthesizer parameter
ADC_CLK_SYNT
ADC converter clock synthesizer configuration
register
4
3
synt_ydiv
5
RESERVED
6
synt_xdiv
7
RESERVED
8
synt_clk_enb
9
synt_clkout_sel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x270
Type:
R/W
Doc ID 018904 Rev 3
2
1
0
215/1728
System configuration registers (MISC)
RM0089
Reset:
0x0000 0000
Description:
ADC converter clock synthesizer configuration register
[31] synt_clk_enb: Synthesizer enable :
0 : synthesizer disabled
1 : synthesizer enabled
[30] synt_clkout_sel: Output clock synthesizer selection
0 : Fout = Fin * X / (2 * Y) ( duty cycle 50%)
1 : Fout = Fin * X / Y
( duty cycle X/Y*100% )
with Fin = hclk frequency
Fout maximum value is 20 MHz
[23:16] synt_xdiv: X synthesizer parameter ; with X less than or equal to Y/2
[7:0] synt_ydiv: Y synthesizer parameter
AMBA_CLK_SSCG
SSCG6 configuration register
Tin_Tr
lock
swrst
To
8
RESERVED
9
StopMeas
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R
R
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x274
Type:
R/W
Reset:
0x000000
Description:
SSCG6 configuration register
7
6
5
4
[31] StopMeas: SSCG Measurement Unit disable :
0 : enabled
1 : disabled
[28:19] Tin_Tr: Tin/Tr value .
with Tin the input clock period and Tr the basic cell delay
It encodes internal block delay. Used only for debug purpose.
[18] lock: Lock status :
0 : the clock is not active
1 : the clock is active
[17] swrst: Active high software reset
[16:0] To: Division factor:
Tout = 2* To * Tin
with :
To : fixed point representation of division factor; the 3 MSBs are the integer part.
Tout : the period of output clock
Tin : the period of input clock . The input clock source is vco1div2.
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RM0089
System configuration registers (MISC)
AMBA_CLK_SSCG_MOD
SSCG6 modulation configuration
5
4
3
Dt
6
Fmod
7
mod_en
8
R
R/
W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x278
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
SSCG6 modulation configuration
[16] mod_en: Modulation enable
0 : modulation disabled
1 : triangular wave modulation enabled
[15:8] Fmod: Modulation frequency parameter
Fmod = Fm/Fin
where
Fm is the modulation frequency
Fin is the input clock frequency
[7:0] Dt: Modulation depth.
Dt= DT/Tin
where
DT is the desired period deviation
Tin is input clock period
CLCD_CLK_SSCG
SSCG5 configuration
Tin_Tr
lock
swrst
To
8
RESERVED
9
StopMeas
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R
R
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x27C
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
7
6
5
4
3
2
1
0
217/1728
System configuration registers (MISC)
Description:
RM0089
SSCG5 configuration
[31] StopMeas: SSCG Measurement Unit disable :
0 : enabled
1 : disabled
[28:19] Tin_Tr: Tin/Tr value .
with Tin the input clock period and Tr the basic cell delay
It encodes internal block delay. Used only for debug purpose.
[18] lock: Lock status :
0 : the clock is not active
1 : the clock is active
[17] swrst: Active high software reset
[16:0] To: Division factor:
Tout = 2* To * Tin
with :
To : fixed point representation of division factor; the 3 MSBs are the integer part.
Tout : the period of output clock
Tin : the period of input clock .
The input clock could be chosen between vco1div4 and pll2out (see PLL_CFG[31])
CLCD_CLK_SSCG_MOD
SSCG5 modulation configuration
5
4
3
Dt
6
Fmod
7
mod_en
8
R
R/
W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x280
Type:
R/W
Reset:
0x0000 0000
Description:
SSCG5 modulation configuration
[16] mod_en: Modulation enable
0 : modulation disabled
1 : triangular wave modulation enabled
[15:8] Fmod: Modulation frequency parameter
Fmod = Fm/Fin
where
Fm is the modulation frequency
Fin is the input clock frequency
[7:0] Dt: Modulation depth.
Dt= DT/Tin
where
DT is the desired period deviation
Tin is input clock period
218/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
System configuration registers (MISC)
SYS_CLK_SSCG
SSCG4 configuration
Tin_Tr
lock
swrst
To
8
RESERVED
9
StopMeas
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R
R
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x284
Type:
R/W
Reset:
0x0000 0000
Description:
7
6
5
4
3
2
1
0
SSCG4 configuration
[31] StopMeas: SSCG Measurement Unit disable :
0 : enabled
1 : disabled
[28:19] Tin_Tr: Tin/Tr value .
with Tin the input clock period and Tr the basic cell delay
It encodes internal block delay. Used only for debug purpose.
[18] lock: Lock status :
0 : the clock is not active
1 : the clock is active
[17] swrst: Active high software reset
[16:0] To: Division factor:
Tout = 2* To * Tin
with :
To : fixed point representation of division factor; the 3 MSBs are the integer part.
Tout : the period of output clock
Tin : the period of input clock .The input clock source is vco1div2.
SYS_CLK_SSCG_MOD
SSCG4 modulation configuration
6
5
4
3
Dt
7
Fmod
8
mod_en
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x288
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
2
1
0
219/1728
System configuration registers (MISC)
Description:
RM0089
SSCG4 modulation configuration
[16] mod_en: Modulation enable
0 : modulation disabled
1 : triangular wave modulation enabled
[15:8] Fmod: Modulation frequency parameter
Fmod = Fm/Fin
where
Fm is the modulation frequency
Fin is the input clock frequency
[7:0] Dt: Modulation depth.
Dt= DT/Tin
where
DT is the desired period deviation
Tin is input clock period
GEN_CLK_SSCG0
SSCG0 configuration
Tin_Tr
lock
swrst
To
8
RESERVED
9
StopMeas
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R
R
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x28C
Type:
R/W
Reset:
0x27EF
Description:
SSCG0 configuration
7
6
5
4
3
2
1
0
[31] StopMeas: SSCG Measurement Unit disable :
0 : enabled
1 : disabled
[28:19] Tin_Tr: Tin/Tr value .
with Tin the input clock period and Tr the basic cell delay
It encodes internal block delay. Used only for debug purpose.
[18] lock: Lock status :
0 : the clock is not active
1 : the clock is active
[17] swrst: Active high software reset
[16:0] To: Division factor:
Tout = 2* To * Tin
with :
To : fixed point representation of division factor; the 3 MSBs are the integer part.
Tout : the period of output clock
Tin : the period of input clock .
The input clock could be chosen between vco1div4,pll3 and vco3div2 (see PLL_CFG[28:27])
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RM0089
System configuration registers (MISC)
GEN_CLK_SSCG0_MOD
SSCG0 modulation configuration
5
4
3
Dt
6
Fmod
7
mod_en
8
R
R/
W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x290
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
SSCG0 modulation configuration
[16] mod_en: Modulation enable
0 : modulation disabled
1 : triangular wave modulation enabled
[15:8] Fmod: Modulation frequency parameter
Fmod = Fm/Fin
where
Fm is the modulation frequency
Fin is the input clock frequency
[7:0] Dt: Modulation depth.
Dt= DT/Tin
where
DT is the desired period deviation
Tin is input clock period
GEN_CLK_SSCG1
SSCG1 configuration
Tin_Tr
lock
swrst
To
8
RESERVED
9
StopMeas
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R
R
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x294
Type:
R/W
Reset:
0x27EF
Doc ID 018904 Rev 3
7
6
5
4
3
2
1
0
221/1728
System configuration registers (MISC)
Description:
RM0089
SSCG1 configuration
[31] StopMeas: SSCG Measurement Unit disable :
0 : enabled
1 : disabled
[28:19] Tin_Tr: Tin/Tr value .
with Tin the input clock period and Tr the basic cell delay
It encodes internal block delay. Used only for debug purpose.
[18] lock: Lock status :
0 : the clock is not active
1 : the clock is active
[17] swrst: Active high software reset
[16:0] To: Division factor:
Tout = 2* To * Tin
with :
To : fixed point representation of division factor; the 3 MSBs are the integer part.
Tout : the period of output clock
Tin : the period of input clock .
The input clock could be chosen between vco1div4,pll3 or vco3div2 (see PLL_CFG[28:27])
GEN_CLK_SSCG1_MOD
SSCG1 modulation configuration
5
4
3
Dt
6
Fmod
7
mod_en
8
R
R/
W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x298
Type:
R/W
Reset:
0x0000 0000
Description:
SSCG1 modulation configuration
[16] mod_en: Modulation enable
0 : modulation disabled
1 : triangular wave modulation enabled
[15:8] Fmod: Modulation frequency parameter
Fmod = Fm/Fin
where
Fm is the modulation frequency
Fin is the input clock frequency
[7:0] Dt: Modulation depth.
Dt= DT/Tin
where
DT is the desired period deviation
Tin is input clock period
222/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
System configuration registers (MISC)
GEN_CLK_SSCG2
SSCG2 configuration
Tin_Tr
lock
swrst
To
8
RESERVED
9
StopMeas
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R
R
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x29C
Type:
R/W
Reset:
0xD8B0
Description:
7
6
5
4
3
2
1
0
SSCG2 configuration
[31] StopMeas: SSCG Measurement Unit disable :
0 : enabled
1 : disabled
[28:19] Tin_Tr: Tin/Tr value .
with Tin the input clock period and Tr the basic cell delay
It encodes internal block delay. Used only for debug purpose.
[18] lock: Lock status :
0 : the clock is not active
1 : the clock is active
[17] swrst: Active high software reset
[16:0] To: Division factor:
Tout = 2* To * Tin
with :
To : fixed point representation of division factor; the 3 MSBs are the integer part.
Tout : the period of output clock
Tin : the period of input clock .
The input clock could be chosen between vco1div4,pll2 or vco2div2 (see PLL_CFG[30:29])
GEN_CLK_SSCG2_MOD
SSCG2 modulation configuration
6
5
4
3
Dt
7
Fmod
8
mod_en
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x300
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
2
1
0
223/1728
System configuration registers (MISC)
Description:
RM0089
SSCG2 modulation configuration
[16] mod_en: Modulation enable
0 : modulation disabled
1 : triangular wave modulation enabled
[15:8] Fmod: Modulation frequency parameter
Fmod = Fm/Fin
where
Fm is the modulation frequency
Fin is the input clock frequency
[7:0] Dt: Modulation depth.
Dt= DT/Tin
where
DT is the desired period deviation
Tin is input clock period
GEN_CLK_SSCG3
SSCG3 configuration
Tin_Tr
lock
swrst
To
8
RESERVED
9
StopMeas
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R
R
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x304
Type:
R/W
Reset:
0x27EF
Description:
SSCG3 configuration
7
6
5
4
3
2
1
[31] StopMeas: SSCG Measurement Unit disable :
0 : enabled
1 : disabled
[28:19] Tin_Tr: Tin/Tr value .
with Tin the input clock period and Tr the basic cell delay
It encodes internal block delay. Used only for debug purpose.
[18] lock: Lock status :
0 : the clock is not active
1 : the clock is active
[17] swrst: Active high software reset
[16:0] To: Division factor:
Tout = 2* To * Tin
with :
To : fixed point representation of division factor; the 3 MSBs are the integer part.
Tout : the period of output clock
Tin : the period of input clock .
The input clock could be chosen between vco1div4,pll2 or vco2div2 (see PLL_CFG[30:29])
224/1728
Doc ID 018904 Rev 3
0
RM0089
System configuration registers (MISC)
GEN_CLK_SSCG3_MOD
SSCG3 modulation configuration
5
4
3
Dt
6
Fmod
7
mod_en
8
R
R/
W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x308
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
SSCG3 modulation configuration
[16] mod_en: Modulation enable
0 : modulation disabled
1 : triangular wave modulation enabled
[15:8] Fmod: Modulation frequency parameter
Fmod = Fm/Fin
where
Fm is the modulation frequency
Fin is the input clock frequency
[7:0] Dt: Modulation depth.
Dt= DT/Tin
where
DT is the desired period deviation
Tin is input clock period
Peripherial clock enable register
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x30C
Type:
R/W
Reset:
0x0000 003F
Doc ID 018904 Rev 3
R/
W
R/
W
R/
W
R/
W
R/
W
1
0
bus_clken
R
2
sysrom_clken
R/
W
3
sysram1_clken
R
4
fsmc_clken
R/
W
5
sysram0_clken
R/
W
6
sd_clken
R/
W
7
smi_clken
uhc1_clken
R/
W
8
cf_xd_clken
uoc_clken
R/
W
9
uhc0_clken
pcie_sata_clken
R/
W
RESERVED
R/
W
uart0_clken
R/
W
RESERVED
gpt1_clken
R/
W
ssp_clken
gpioa_clken
R
i2c0_clken
gpiob_clken
R/
W
i2s_s_clken
dma_clken
R
gpt0_clken
RESERVED
R/
W
i2s_m_clken
clcd_clken
R/
W
c3_clken
R/
W
RESERVED
rtc_clken
adc_clken
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
gmac_clken
PERIP1_CLK_ENB
R/
W
R/
W
R/
W
R/
W
R/
W
225/1728
System configuration registers (MISC)
Description:
RM0089
Peripherial clock enable register
[31] rtc_clken: RTC APB clock enable :
0 : clock gated
1 : clock enabled
[30] adc_clken: ADC APB and Converter clock enable :
0 : clock gated
1 : clock enabled
[29] c3_clken: C3 AHB and clk48 clocks enable :
0 : clock gated
1 : clock enabled
[27] clcd_clken: CLCD AHB and clcdclk clocks enable :
0 : clock gated
1 : clock enabled
[25] dma_clken: DMA0, DMA1 AHB clock enable :
0 : clock gated
1 : clock enabled
[24] gpiob_clken: GPIO-B8 APB clock enable :
0 : clock gated
1 : clock enabled
[23] gpioa_clken: GPIO-B7 APB clock enable :
0 : clock gated
1 : clock enabled
[22] gpt1_clken: GPT-B5 APB and clk_timer clocks enable :
0 : clock gated
1 : clock enabled
[21] gpt0_clken: GPT-B4 APB and clk_timer clocks enable :
0 : clock gated
1 : clock enabled
[20] i2s_m_clken: I2S_M APB clock enable :
0 : clock gated
1 : clock enabled
[19] i2s_s_clken: I2S_S APB clock enable :
0 : clock gated
1 : clock enabled
[18] i2c0_clken: I2C0 APB and i2cclk clocks enable :
0 : clock gated
1 : clock enabled
[17] ssp_clken: SSP APB clock enable :
0 : clock gated
1 : clock enabled
[15] uart0_clken: UART0 APB and uartclk clock enable :
0 : clock gated
1 : clock enabled
[12] pcie_sata_clken: PCIE SATA AXI clock enable :
0 : clock gated
1 : clock enabled
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Doc ID 018904 Rev 3
RM0089
System configuration registers (MISC)
[11] uoc_clken: UOC AHB clock enable :
0 : clock gated
1 : clock enabled
[10] uhc1_clken: UHC1 AHB clock enable :
0 : clock gated
1 : clock enabled
[9] uhc0_clken: UHC0 AHB clock enable :
0 : clock gated
1 : clock enabled
[8] gmac_clken: GMAC AHB clock enable :
0 : clock gated
1 : clock enabled
[7] cf_xd_clken: MIF_CF_XD AHB and cf_xd_clk clocks enable :
0 : clock gated
1 : clock enabled
[6] sd_clken: MIF_SD AHB and sd_clk clocks enable :
0 : clock gated
1 : clock enabled
[5] smi_clken: SMI AHB clock enable :
0 : clock gated
1 : clock enabled
[4] fsmc_clken: FSMC AHB clock enable :
0 : clock gated
1 : clock enabled
[3] sysram0_clken: System RAM clock enable :
0 : clock gated
1 : clock enabled
[2] sysram1_clken: Always On RAM clock enable :
0 : clock gated
1 : clock enabled
[1] sysrom_clken: System ROM clock enable :
0 : clock gated
1 : clock enabled
[0] bus_clken: Busmatrix AHB-AXI clock enable :
0 : clock gated
1 : clock enabled
Peripherial clock enable register
Address:
1
0
mpmc_amba_clken
2
mpmc_ctrl_phy_clken
3
cpu_dbg_clken
R/
W
4
kbd_clken
R/
W
5
gpt2_clken
R
6
acp_clken
7
i2s_refout_clken
8
thsens_clken
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
gpt3_clken
PERIP2_CLK_ENB
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Misc_RegisterBaseAddress + 0x310
Doc ID 018904 Rev 3
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System configuration registers (MISC)
RM0089
Type:
R/W
Reset:
0x0
Description:
Peripherial clock enable register
[8] thsens_clken: Thermal sensor clock enable :
0 : clock gated
1 : clock enabled
[7] i2s_refout_clken: I2S reference clock enable :
0 : clock gated
1 : clock enabled on I2S_OUT_OVRSAMP_CLK
see I2S_CLK_CFG for i2s_refout settings
[6] acp_clken: ACP (HCLK) clock enable :
0 : clock gated
1 : clock enabled
[5] gpt3_clken: GPT-B16 APB and clk_timer clocks enable :
0 : clock gated
1 : clock enabled
[4] gpt2_clken: GPT-B15 APB and clk_timer clocks enable :
0 : clock gated
1 : clock enabled
[3] kbd_clken: Keyboard APB clock enable :
0 : clock gated
1 : clock enabled
[2] cpu_dbg_clken: CPU CoreSight clocks enable :
0 : clock gated
1 : clock enabled
[1] mpmc_ctrl_phy_clken: MPMC clk and clkd2 clocks enable :
0 : clock gated
1 : clock enabled
[0] mpmc_amba_clken: MPMC AMBA clock enable :
0 : clock gated
1 : clock enabled
Peripherial clock enable register
Address:
Misc_RegisterBaseAddress + 0x314
Type:
R/W
Reset:
0x0000 0000
228/1728
R/
W
R/
W
R/
W
Doc ID 018904 Rev 3
1
0
uart1_clken
R/
W
2
RESERVED
R/
W
3
i2c1_clken
R/
W
4
pwm_clken
cam4_clken
R/
W
5
cec1_clken
cam3_clken
R
6
gpu_clken
cam2_clken
R/
W
cam1_clken
venc_clken
R/
W
video_in_clken
vdec_clken
R
7
spdif_in_clken
RESERVED
R/
W
8
RESERVED
xgpio_clken
R
9
spdif_out_clken
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
cec0_clken
PERIP3_CLK_ENB
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R
RM0089
Description:
System configuration registers (MISC)
Peripherial clock enable register
[18] xgpio_clken: XGPIO clock enable :
0 : clock gated
1 : clock enabled
[16] vdec_clken: VIDEO DECODER clock enable :
0 : clock gated
1 : clock enabled
[15] venc_clken: VIDEO ENCODER clock enable :
0 : clock gated
1 : clock enabled
[13] spdif_out_clken: SPDIF_OUT clock enable :
0 : clock gated
1 : clock enabled
[12] spdif_in_clken: SPDIF_IN clock enable :
0 : clock gated
1 : clock enabled
[11] video_in_clken: VIDEO INPUT (VIP) clock enable :
0 : clock gated
1 : clock enabled
[10] cam1_clken: CAM1 clock enable :
0 : clock gated
1 : clock enabled
[9] cam2_clken: CAM2 clock enable :
0 : clock gated
1 : clock enabled
[8] cam3_clken: CAM3 clock enable :
0 : clock gated
1 : clock enabled
[7] cam4_clken: CAM4 clock enable :
0 : clock gated
1 : clock enabled
[6] gpu_clken: GPU clock enable :
0 : clock gated
1 : clock enabled
[5] cec0_clken: CEC0 clock enable :
0 : clock gated
1 : clock enabled
[4] cec1_clken: CEC1 clock enable :
0 : clock gated
1 : clock enabled
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System configuration registers (MISC)
RM0089
[3] pwm_clken: PWM clock enable :
0 : clock gated
1 : clock enabled
[2] i2c1_clken: I2C1 clock enable :
0 : clock gated
1 : clock enabled
[1] uart1_clken: UART1 clock enable :
0 : clock gated
1 : clock enabled
Peripherial reset register
R/
W
Address:
Misc_RegisterBaseAddress + 0x318
Type:
R/W
Reset:
0xFFFF FFC0
Description:
Peripherial reset register
[31] rtc_swrst: RTC APB soft reset :
0 : reset disabled
1 : reset active
[30] adc_swrst: ADC APB soft reset :
0 : reset disabled
1 : reset active
[29] c3_swrst: C3 AHB and rng soft reset :
0 : reset disabled
1 : reset active
[27] clcd_swrst: CLCD AHB soft reset :
0 : reset disabled
1 : reset active
[25] dma_swrst: DMA0, DMA1 AHB soft reset :
0 : reset disabled
1 : reset active
[24] gpiob_swrst: GPIO-B8 APB soft reset :
0 : reset disabled
1 : reset active
[23] gpioa_swrst: GPIO-B7 APB soft reset :
0 : reset disabled
1 : reset active
[22] gpt1_swrst: GPT-B5 APB soft reset :
0 : reset disabled
1 : reset active
230/1728
Doc ID 018904 Rev 3
R/
W
R/
W
R/
W
R/
W
R/
W
3
2
1
0
bus_swrst
R
4
RESERVED
R/
W
5
fsmc_swrst
R
6
sd_swrst
R/
W
7
smi_swrst
R/
W
8
cf_xd_swrst
R/
W
9
uhc0_swrst
R/
W
uoc_swrst
R/
W
uhc1_swrst
pcie_sata_swrst
R/
W
RESERVED
R/
W
uart0_swrst
R/
W
RESERVED
gpt1_swrst
R/
W
ssp_swrst
gpioa_swrst
R
i2c0_swrst
gpiob_swrst
R/
W
i2s_s_swrst
dma_swrst
R
gpt0_swrst
RESERVED
R/
W
i2s_m_swrst
clcd_swrst
R/
W
c3_swrst
R/
W
RESERVED
rtc_swrst
adc_swrst
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
gmac_swrst
PERIP1_SW_RST
R/
W
R/
W
R/
W
R
R/
W
RM0089
System configuration registers (MISC)
[21] gpt0_swrst: GPT-B4 APB soft reset :
0 : reset disabled
1 : reset active
[20] i2s_m_swrst: I2S_M APB soft reset :
0 : reset disabled
1 : reset active
[19] i2s_s_swrst: I2S_S APB soft reset :
0 : reset disabled
1 : reset active
[18] i2c0_swrst: I2C0 APB and i2crstn soft reset :
0 : reset disabled
1 : reset active
[17] ssp_swrst: SSP APB soft reset :
0 : reset disabled
1 : reset active
[15] uart0_swrst: UART0 APB and uartreset soft reset :
0 : reset disabled
1 : reset active
[12] pcie_sata_swrst: PCIE SATA AXI soft reset :
0 : reset disabled
1 : reset active
[11] uoc_swrst: UOC AHB soft reset :
0 : reset disabled
1 : reset active
[10] uhc1_swrst: UHC1 AHB soft reset :
0 : reset disabled
1 : reset active
[9] uhc0_swrst: UHC0 AHB soft reset :
0 : reset disabled
1 : reset active
[8] gmac_swrst: GMAC AHB soft reset :
0 : reset disabled
1 : reset active
[7] cf_xd_swrst: MIF_CF_XD AHB and cf_xd_clk soft reset :
0 : reset disabled
1 : reset active
[6] sd_swrst: MIF_SD AHB and sd_clk soft reset :
0 : reset disabled
1 : reset active
[5] smi_swrst: SMI AHB soft reset :
0 : reset disabled
1 : reset active
[4] fsmc_swrst: FSMC AHB soft reset :
0 : reset disabled
1 : reset active
[0] bus_swrst:
Doc ID 018904 Rev 3
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System configuration registers (MISC)
RM0089
Peripherial reset register
Misc_RegisterBaseAddress + 0x31C
Type:
R/W
Reset:
0xF
Description:
Peripherial reset register
[10] cpu2_swrst: CPU2 soft reset :
0 : reset disabled
1 : reset active
[9] cpu1_swrst: CPU1 soft reset :
0 : reset disabled
1 : reset active
[8] thsens_swrst: Thermal sensor soft reset :
0 : reset disabled
1 : reset active
[6] acp_swrst: ACP soft reset :
0 : reset disabled
1 : reset active
[5] gpt3_swrst: GPT-B16 APB soft reset :
0 : reset disabled
1 : reset active
[4] gpt2_swrst: GPT-B15 APB soft reset :
0 : reset disabled
1 : reset active
[3] kbd_swrst: Keyboard APB soft reset :
0 : reset disabled
1 : reset active
[2] cpu_dbg_swrst: CPU CoreSight soft reset :
0 : reset disabled
1 : reset active
[1] mpmc_ctrl_phy_swrst: MPMC controller phy soft reset :
0 : reset disabled
1 : reset active
[0] mpmc_amba_swrst: MPMC AMBA soft reset :
0 : reset disabled
1 : reset active
Doc ID 018904 Rev 3
0
mpmc_amba_swrst
1
mpmc_ctrl_phy_swrst
2
cpu_dbg_swrst
3
kbd_swrst
R/
W
4
gpt2_swrst
R/
W
5
acp_swrst
R/
W
6
gpt3_swrst
cpu1_swrst
R
thsens_swrst
7
cpu2_swrst
8
R
Address:
232/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PERIP2_SW_RST
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
RM0089
System configuration registers (MISC)
Peripherial reset register
Address:
Misc_RegisterBaseAddress + 0x320
Type:
R/W
Reset:
0x3FFFF
Description:
Peripherial reset register
R/
W
R/
W
R/
W
1
0
uart1_swrst
R/
W
2
RESERVED
R/
W
3
i2c1_swrst
R/
W
4
pwm_swrst
cam4_swrst
R/
W
5
cec1_swrst
cam3_swrst
R
6
gpu_swrst
cam2_swrst
R/
W
cam1_swrst
venc_swrst
R/
W
video_in_swrst
vdec_swrst
R
7
spdif_in_swrst
RESERVED
R/
W
8
RESERVED
xgpio_swrst
R
9
spdif_out_swrst
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
cec0_swrst
PERIP3_SW_RST
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R
[18] xgpio_swrst: XGPIO soft reset :
0 : reset disabled
1 : reset active
[16] vdec_swrst: VIDEO DECODER soft reset :
0 : reset disabled
1 : reset active
[15] venc_swrst: VIDEO ENCODER soft reset :
0 : reset disabled
1 : reset active
[13] spdif_out_swrst: SPDIF_OUT soft reset :
0 : reset disabled
1 : reset active
[12] spdif_in_swrst: SPDIF_IN soft reset :
0 : reset disabled
1 : reset active
[11] video_in_swrst: VIDEO INPUT (VIP) soft reset :
0 : reset disabled
1 : reset active
[10] cam1_swrst: CAM1 soft reset :
0 : reset disabled
1 : reset active
[9] cam2_swrst: CAM2 soft reset :
0 : reset disabled
1 : reset active
[8] cam3_swrst: CAM3 soft reset :
0 : reset disabled
1 : reset active
[7] cam4_swrst: CAM4 soft reset :
0 : reset disabled
1 : reset active
[6] gpu_swrst: GPU soft reset :
0 : reset disabled
1 : reset active
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System configuration registers (MISC)
RM0089
[5] cec0_swrst: CEC0 soft reset :
0 : reset disabled
1 : reset active
[4] cec1_swrst: CEC1 soft reset :
0 : reset disabled
1 : reset active
[3] pwm_swrst: PWM soft reset :
0 : reset disabled
1 : reset active
[2] i2c1_swrst: I2C1 soft reset :
0 : reset disabled
1 : reset active
[1] uart1_swrst: UART1 soft reset :
0 : reset disabled
1 : reset active
DMAC_HS_SEL
DMAC HandShake Selection register.
hs19_sel
hs18_sel
hs17_sel
hs16_sel
hs11_sel
hs10_sel
hs9_sel
hs8_sel
hs7_sel
hs6_sel
hs5_sel
hs4_sel
hs3_sel
hs2_sel
hs1_sel
hs0_sel
0
hs20_sel
1
hs21_sel
2
hs22_sel
3
hs23_sel
4
hs24_sel
5
hs25_sel
6
hs26_sel
7
hs27_sel
8
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x400
Type:
R/W
Reset:
0x0000 0000
Description:
DMAC HandShake Selection register.
[23] hs27_sel: Reserved : Do not Write
[22] hs26_sel: Reserved : Do not Write
[21] hs25_sel: Reserved : Do not Write
[20] hs24_sel: Reserved : Do not Write
[19] hs23_sel: Reserved : Do not Write
[18] hs22_sel: Reserved : Do not Write
[17] hs21_sel: Reserved : Do not Write
[16] hs20_sel: Reserved : Do not Write
[15] hs19_sel: Reserved : Do not Write
[14] hs18_sel: Reserved : Do not Write
[13] hs17_sel: Reserved : Do not Write
[12] hs16_sel: Reserved : Do not Write
[11] hs11_sel: Reserved : Do not Write
[10] hs10_sel: Reserved : Do not Write
234/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
System configuration registers (MISC)
[9] hs9_sel: Reserved : Do not Write
[8] hs8_sel: Reserved : Do not Write
[7] hs7_sel: Reserved : Do not Write
[6] hs6_sel: Reserved : Do not Write
[5] hs5_sel: Reserved : Do not Write
[4] hs4_sel: Reserved : Do not Write
[3] hs3_sel: Reserved : Do not Write
[2] hs2_sel: Reserved : Do not Write
[1] hs1_sel: Reserved : Do not Write
[0] hs0_sel: Reserved : Do not Write
DMAC_SEL
DMA Selection
hs2_18_map
hs1_17_map
hs0_16_map
0
hs3_19_map
1
hs4_20_map
2
hs5_21_map
3
hs6_22_map
4
hs7_23_map
5
hs8_24_map
6
hs9_25_map
7
hs10_26_map
8
hs11_27_map
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x404
Type:
R/W
Reset:
0x0000 0000
Description:
DMA Selection
[11] hs11_27_map:
0 : hs11 on DMA0 , hs27 on DMA1
1 : hs11 on DMA1 , hs27 on DMA0.
[10] hs10_26_map:
0 : hs10 on DMA0 , hs26 on DMA1
1 : hs10 on DMA1 , hs26 on DMA0.
[9] hs9_25_map:
0 : hs9 on DMA0 , hs25 on DMA1
1 : hs9 on DMA1 , hs25 on DMA0.
[8] hs8_24_map:
0 : hs8 on DMA0 , hs24 on DMA1
1 : hs8 on DMA1 , hs24 on DMA0.
[7] hs7_23_map:
0 : hs7 on DMA0 , hs23 on DMA1
1 : hs7 on DMA1 , hs23 on DMA0.
[6] hs6_22_map:
0 : hs6 on DMA0 , hs22 on DMA1
1 : hs6 on DMA1 , hs22 on DMA0
Doc ID 018904 Rev 3
235/1728
System configuration registers (MISC)
RM0089
[5] hs5_21_map:
0 : hs5 on DMA0 , hs21 on DMA1
1 : hs5 on DMA1 , hs21 on DMA0.
[4] hs4_20_map:
0 : hs4 on DMA0 , hs20 on DMA1
1 : hs4 on DMA1 , hs20 on DMA0.
[3] hs3_19_map:
0 : hs3 on DMA0 , hs19 on DMA1
1 : hs3 on DMA1 , hs19 on DMA0.
[2] hs2_18_map:
0 : hs2 on DMA0 , hs18 on DMA1
1 : hs2 on DMA1 , hs18 on DMA0.
[1] hs1_17_map:
0 : hs1 on DMA0 , hs17 on DMA1
1 : hs1 on DMA1 , hs17 on DMA0.
[0] hs0_16_map:
0 : hs0 on DMA0 , hs16 on DMA1
1 : hs0 on DMA1 , hs16 on DMA0
DMAC_FLOW_SEL
DMA flow selection
hs21_flow
hs20_flow
hs19_flow
hs18_flow
hs17_flow
hs16_flow
hs15_flow
hs14_flow
hs13_flow
hs12_flow
hs11_flow
hs10_flow
hs9_flow
hs8_flow
hs7_flow
hs6_flow
hs5_flow
hs4_flow
hs3_flow
hs2_flow
hs1_flow
hs0_flow
0
hs22_flow
1
hs23_flow
2
hs24_flow
3
hs25_flow
4
hs26_flow
5
hs27_flow
6
hs28_flow
7
hs29_flow
8
hs30_flow
9
hs31_flow
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x408
Type:
R/W
Reset:
0x0000 0000
Description:
DMA flow selection
[31:0] hs[31:0]_flow:
0: dma is flow controller. No need to program hs[n]_dir if single request is not used.
1 : peripheral is flow controller .No need to program hs[n]_dir
DMAC_DIR_SEL
DMA Peripherial Direction Selection
hs21_dir
hs20_dir
hs19_dir
hs18_dir
hs17_dir
hs16_dir
hs15_dir
hs14_dir
hs13_dir
hs12_dir
hs11_dir
hs10_dir
hs9_dir
hs8_dir
hs7_dir
hs6_dir
hs5_dir
hs4_dir
hs3_dir
hs2_dir
hs1_dir
hs0_dir
0
hs22_dir
1
hs23_dir
2
hs24_dir
3
hs25_dir
4
hs26_dir
5
hs27_dir
6
hs28_dir
7
hs29_dir
8
hs30_dir
9
hs31_dir
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x40C
Type:
R/W
Reset:
0x0000 0000
236/1728
Doc ID 018904 Rev 3
RM0089
System configuration registers (MISC)
Description:
DMA Peripherial Direction Selection
[31:0] hs[31:0]_dir:
0: peripherial is the source
1 : peripherial is the destination
DMA Master endianness configuration
Address:
Misc_RegisterBaseAddress + 0x410
Type:
R/W
Reset:
0x000
Description:
DMA Master endianness configuration
2
1
0
big_endian_dma0_master_40
R/
W
3
big_endian_dma0_master_50
R/
W
4
big_endian_dma1_master_40
R/
W
5
big_endian_uhc1
R
6
big_endian_dma1_master_50
7
big_endian_uotg
8
big_endian_gmac
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
big_endian_uhc2
ENDIANNESS_CFG
R/
W
R/
W
R/
W
R/
W
R/
W
[7] big_endian_gmac: GMAC Master endianness configuration :
0 : little endian
1 : big endian
[6] big_endian_uotg: UOC Master endianness configuration :
0 : little endian
1 : big endian
[5] big_endian_uhc2: UHC1 Master endianness configuration :
0 : little endian
1 : big endian
[4] big_endian_uhc1: UHC0 Master endianness configuration :
0 : little endian
1 : big endian
[3] big_endian_dma1_master_50: DMA1 Master 50 endianness configuration :
0 : little endian
1 : big endian
[2] big_endian_dma1_master_40: DMA1 Master 40 endianness configuration :
0 : little endian
1 : big endian
[1] big_endian_dma0_master_50: DMA0 Master 50 endianness configuration :
0 : little endian
1 : big endian
[0] big_endian_dma0_master_40: DMA0 Master 40 endianness configuration :
0 : little endian
1 : big endian
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System configuration registers (MISC)
RM0089
USBPHY_GEN_CFG
USB Phy General configuration register
ss_fladj_val
ss_autoppd_on_overcur
refclksel
refclkdiv
commononn
0
usb_phy_por
1
RESERVED
2
usb_utmi_rst0
3
usb_utmi_rst1
4
usb_utmi_rst2
5
RESERVED
6
usb_pll_lock
7
otg_tune
8
usbphy_siddq
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/W
R
R
R/
W
R/
W
R/
W
R
R/
W
R/W
R/
W
R/W
R/W
R/
W
Address:
Misc_RegisterBaseAddress + 0x414
Type:
R/W
Reset:
0x183B
Description:
USB Phy General configuration register
[28] usbphy_siddq: USB PHY IDDQ Low Power State Enable
1: The analog blocks are powered down.
0: The analog blocks are powered up.
[27:25] otg_tune: VBUS Valid Threshold Adjustment. This bus adjusts the voltage level for the VBUS
Valid threshold.
111: + 9%
110: + 6%
101: + 3%
100: Design default
011: 3%
010: 6%
001: 9%
000: 12%
[24] usb_pll_lock: USB 2.0 nanoPHY PLL lock signal
1 : PLL locked
0 : PLL unlocked
[16] usb_utmi_rst2: When asserted, this customer-specific signal resets the corresponding port
transmit and receive logic without disabling the clocks within the USB 2.0 nanoPHY (UHC2).
1: The transmit and receive finite state machines (FSMs) are reset, and the line_state logic
combinatorially reflects the state of the single-ended receivers.
0: The transmit and receive FSMs are operational, and the line_state logic becomes sequential
after 11 PHYCLOCK cycles.
[15] usb_utmi_rst1: When asserted, this customer-specific signal resets the corresponding port
transmit and receive logic without disabling the clocks within the USB 2.0 nanoPHY (UOC).
1: The transmit and receive finite state machines (FSMs) are reset, and the line_state logic
combinatorially reflects the state of the single-ended receivers.
0: The transmit and receive FSMs are operational, and the line_state logic becomes sequential
after 11 PHYCLOCK cycles.
[14] usb_utmi_rst0: When asserted, this customer-specific signal resets the corresponding port
transmit and receive logic without disabling the clocks within the USB 2.0 nanoPHY (UHC1).
1: The transmit and receive finite state machines (FSMs) are reset, and the line_state logic
combinatorially reflects the state of the single-ended receivers.
0: The transmit and receive FSMs are operational, and the line_state logic becomes sequential
after 11 PHYCLOCK cycles.
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RM0089
System configuration registers (MISC)
[12] usb_phy_por: Power-On Reset
Resets all test registers and state machines in the USB 2.0 nanoPHY. The POR signal must be
asserted for a minimum of 10 us.
Active : High
[11:6] ss_fladj_val: This feature adjusts any offset from the clock source that drives
the uSOF counter. The uSOF cycle time (number of uSOF counter clock
periods to generate a uSOF microframe length) is equal to 59,488 plus this
value. The default value is decimal 32 (0x20), which gives an SOF cycle
time of 60,000 (each microframe has 60,000 bit times).
Frame Length (decimal) FLADJ Value (decimal)
59488 0 (0x00)
59504 1 (0x01)
59520 2 (0x02)
... ...
59984 31 (0x1F)
60000 32 (0x20)
... ...
60496 63 (0x3F)
Note that this register must be modified only when the HCHalted bit in the USBSTS register is
set to 1; otherwise, the EHCI yields undefined results.The register must not be reprogrammed
by the USB system software unless the default or BIOS programmed values are incorrect, or
the system is restoring the register while returning from a suspended state.
[5] ss_autoppd_on_overcur: This field enables automatic port power disable in the
host controllers.
[4:3] refclksel: Reference Clock Select for PLL Block
Function: This signal selects the reference clock source for the PLL block.
11: The PLL uses CLKCORE as reference.
10: The PLL uses CLKCORE as reference.
01: The XO block uses an external, 2.5-V clock supplied on the XO pin.
00: The XO block uses the clock from a crystal.
[2:1] refclkdiv: Reference Clock Frequency Select
This bus selects the USB 2.0 nanoPHY reference clock frequency.
11: Reserved
10: Reserved
01: 24 MHz
00: 12 MHz
[0] commononn: Common Block Power-Down Control
It controls the power-down signals in the XO, Bias, and PLL blocks in USB 2.0 nanoPHY when
it is suspended.
1: The XO, Bias, and PLL blocks are powered down in Suspend mode.
0: The XO, Bias, and PLL blocks remain powered in Suspend mode.
Doc ID 018904 Rev 3
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System configuration registers (MISC)
RM0089
USBPHY_P1_CFG
USB phy P1 configuration (UHC0)
Address:
Misc_RegisterBaseAddress + 0x418
Type:
R/W
Reset:
0x0000 50E0
Description:
USB phy P1 configuration (UHC0)
5
4
3
2
1
compdistune
6
sqrxtune
R/W
7
txfslstune
txvreftune
R/W
8
txrisetune
txhsxvtune
R
9
txpreemphasistune
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/W
R/W
R/W
[17:16] txhsxvtune: I Transmitter High-Speed Crossover Adjustment
This bus adjusts the voltage at which the DP and DM signals cross while transmitting in HS
mode.
11: Reserved
10: The crossover voltage + 15 mV.
01: The crossover voltage - 15 mV.
00: Default setting
[15:12] txvreftune: HS DC Voltage Level Adjustment
This bus adjusts the high-speed DC level voltage.
1111: + 12.5%
1110: + 11.25%
1101: + 10%
1100: + 8.75%
1011: + 7.5%
1010: + 6.25%
1001: + 5%
1000: + 3.75%
0111: + 2.5%
0110: + 1.25%
0101: Design default
0100: - 1.25%
0011: - 2.5%
0010: - 3.75%
0001: - 5%
0000: - 6.25%
[11] txrisetune: HS Transmitter Rise/Fall Time Adjustment
This bus adjusts the rise/fall times of the high-speed waveform.
1: - 8%
0: Design default
[10] txpreemphasistune: HS Transmitter Pre-Emphasis Enable
This signal controls the pre-emphasis for a J-K or K-J state transition in HS mode.
1: The HS Transmitter pre-emphasis is enabled.
0 (design default): The HS Transmitter pre-emphasis is disabled.
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0
RM0089
System configuration registers (MISC)
[9:6] txfslstune: FS/LS Source Impedance Adjustment
This bus adjusts the low- and full-speed single-ended source
impedance while driving high. The following adjustment values are based on nominal process,
voltage, and temperature.
1111: - 5%
0111: - 2.5%
0011: Design default
0001: + 2.5%
0000: + 5%
All other bit settings are reserved.
[5:3] sqrxtune: Squelch Threshold Adjustment
Function: This bus adjusts the voltage level for the threshold used to detect
valid high-speed data.
111: - 15%
110: - 10%
101: - 5%
100: Design default
011: + 5%
010: + 10%
001: + 15%
000: + 20%
[2:0] compdistune: Disconnect Threshold Adjustment
Function: This bus adjusts the voltage level for the threshold used to detect a disconnect event
at the host.
111: + 10.5%
110: + 9%
101: + 7.5%
100: + 6%
011: + 4.5%
010: + 3%
001: + 1.5%
000: Design default
If this bus is not used, leave it at the default setting.
USBPHY_P2_CFG
USB phy P2 configuration (UOC)
Address:
Misc_RegisterBaseAddress + 0x41C
Type:
R/W
Reset:
0x0000 50E0
Doc ID 018904 Rev 3
5
4
3
2
1
compdistune
6
sqrxtune
R/W
7
txfslstune
txvreftune
R/W
8
txrisetune
txhsxvtune
R
9
txpreemphasistune
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/W
R/W
R/W
0
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System configuration registers (MISC)
Description:
RM0089
USB phy P2 configuration (UOC)
[17:16] txhsxvtune: I Transmitter High-Speed Crossover Adjustment
This bus adjusts the voltage at which the DP and DM signals cross while transmitting in HS
mode.
11: Reserved
10: The crossover voltage + 15 mV.
01: The crossover voltage - 15 mV.
00: Default setting
[15:12] txvreftune: HS DC Voltage Level Adjustment
This bus adjusts the high-speed DC level voltage.
1111: + 12.5%
1110: + 11.25%
1101: + 10%
1100: + 8.75%
1011: + 7.5%
1010: + 6.25%
1001: + 5%
1000: + 3.75%
0111: + 2.5%
0110: + 1.25%
0101: Design default
0100: - 1.25%
0011: - 2.5%
0010: - 3.75%
0001: - 5%
0000: - 6.25%
[11] txrisetune: HS Transmitter Rise/Fall Time Adjustment
This bus adjusts the rise/fall times of the high-speed waveform.
1: - 8%
0: Design default
[10] txpreemphasistune: HS Transmitter Pre-Emphasis Enable
This signal controls the pre-emphasis for a J-K or K-J state transition in HS mode.
1: The HS Transmitter pre-emphasis is enabled.
0 (design default): The HS Transmitter pre-emphasis is disabled.
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RM0089
System configuration registers (MISC)
[9:6] txfslstune: FS/LS Source Impedance Adjustment
This bus adjusts the low- and full-speed single-ended source
impedance while driving high. The following adjustment values are based on nominal process,
voltage, and temperature.
1111: - 5%
0111: - 2.5%
0011: Design default
0001: + 2.5%
0000: + 5%
All other bit settings are reserved.
[5:3] sqrxtune: Squelch Threshold Adjustment
Function: This bus adjusts the voltage level for the threshold used to detect
valid high-speed data.
111: - 15%
110: - 10%
101: - 5%
100: Design default
011: + 5%
010: + 10%
001: + 15%
000: + 20%
[2:0] compdistune: Disconnect Threshold Adjustment
Function: This bus adjusts the voltage level for the threshold used to detect a disconnect event
at the host.
111: + 10.5%
110: + 9%
101: + 7.5%
100: + 6%
011: + 4.5%
010: + 3%
001: + 1.5%
000: Design default
If this bus is not used, leave it at the default setting.
USBPHY_P3_CFG
USB phy P3 configuration (UHC1)
Address:
Misc_RegisterBaseAddress + 0x420
Type:
R/W
Reset:
0x0000 50E0
Doc ID 018904 Rev 3
5
4
3
2
1
compdistune
6
sqrxtune
R/W
7
txfslstune
txvreftune
R/W
8
txrisetune
txhsxvtune
R
9
txpreemphasistune
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/W
R/W
R/W
0
243/1728
System configuration registers (MISC)
Description:
RM0089
USB phy P3 configuration (UHC1)
[17:16] txhsxvtune: I Transmitter High-Speed Crossover Adjustment
This bus adjusts the voltage at which the DP and DM signals cross while transmitting in HS
mode.
11: Reserved
10: The crossover voltage + 15 mV.
01: The crossover voltage - 15 mV.
00: Default setting
[15:12] txvreftune: HS DC Voltage Level Adjustment
This bus adjusts the high-speed DC level voltage.
1111: + 12.5%
1110: + 11.25%
1101: + 10%
1100: + 8.75%
1011: + 7.5%
1010: + 6.25%
1001: + 5%
1000: + 3.75%
0111: + 2.5%
0110: + 1.25%
0101: Design default
0100: - 1.25%
0011: - 2.5%
0010: - 3.75%
0001: - 5%
0000: - 6.25%
[11] txrisetune: HS Transmitter Rise/Fall Time Adjustment
This bus adjusts the rise/fall times of the high-speed waveform.
1: - 8%
0: Design default
[10] txpreemphasistune: HS Transmitter Pre-Emphasis Enable
This signal controls the pre-emphasis for a J-K or K-J state transition in HS mode.
1: The HS Transmitter pre-emphasis is enabled.
0 (design default): The HS Transmitter pre-emphasis is disabled.
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RM0089
System configuration registers (MISC)
[9:6] txfslstune: FS/LS Source Impedance Adjustment
This bus adjusts the low- and full-speed single-ended source
impedance while driving high. The following adjustment values are based on nominal process,
voltage, and temperature.
1111: - 5%
0111: - 2.5%
0011: Design default
0001: + 2.5%
0000: + 5%
All other bit settings are reserved.
[5:3] sqrxtune: Squelch Threshold Adjustment
Function: This bus adjusts the voltage level for the threshold used to detect
valid high-speed data.
111: - 15%
110: - 10%
101: - 5%
100: Design default
011: + 5%
010: + 10%
001: + 15%
000: + 20%
[2:0] compdistune: Disconnect Threshold Adjustment
Function: This bus adjusts the voltage level for the threshold used to detect a disconnect event
at the host.
111: + 10.5%
110: + 9%
101: + 7.5%
100: + 6%
011: + 4.5%
010: + 3%
001: + 1.5%
000: Design default
If this bus is not used, leave it at the default setting.
PCIE - SATA configuration register
Address:
Misc_RegisterBaseAddress + 0x424
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
R/
W
R
2
1
0
pcie_sata_sel
R/
W
3
sata_pm_clk_en
R/
W
4
sata_pwr_rst_n
R/
W
5
sata_tx_clk_en
RESERVED
6
pcie_aux_clk_en
7
pcie_core_clk_en
8
pcie_device_present
R
9
pcie_power_up_rst_n
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
sata_rx_clk_en
PCIE_SATA_CFG
R/
W
R/
W
R/
W
R/
W
R/
W
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System configuration registers (MISC)
Description:
RM0089
PCIE - SATA configuration register
[11] pcie_device_present: Presence Detect State. Indicates whether or not a card is present in
PCIe slot:
0: Slot is empty
1: Card is present in the slot.
[10] pcie_power_up_rst_n: PCIe power up reset :
0 : reset active
1 : reset inactive
[9] pcie_core_clk_en: PCIe Core clock enable :
0 : clock disabled
1 : clock active
[8] pcie_aux_clk_en: PCIe auxiliary clock enable:
0 : clock disabled
1 : clock enabled
[4] sata_tx_clk_en: SATA tx clock enable
0 : clock disabled
1 : clock enabled
[3] sata_rx_clk_en: SATA rx clock enable
0 : clock disabled
1 : clock enabled
[2] sata_pwr_rst_n: SATA power reset
0 : reset active
1 : reset inactive
[1] sata_pm_clk_en: SATA pm clock enable
0 : clock disabled
1 : clock enabled
[0] pcie_sata_sel: PCIe - SATA selection bit.
0 PCIe selected
1 SATA selected
PCIE_MIPHY_CFG
PCIE MIPHY configuration register
RESERVED
miphy_p0_rx_lspd
RESERVED
miphy_osc_mode
miphy_p0_ena8b10b
RESERVED
miphy_pll_ratio_top
3
miphy_p0_tx_lspd
4
miphy_ssc_en
5
miphy_clk_osc_zo_en
6
miphy_clk_ref_div
7
Reserved
8
miphy_osc_bypass
9
miphy_osc_force_ext
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/W
R/
W
R/
W
R/
W
R
R/
W
R
R/W
R/
W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x428
Type:
R/W
Reset:
0x8000 0019
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2
1
0
RM0089
System configuration registers (MISC)
Description:
PCIE MIPHY configuration register
[31] miphy_osc_bypass: This signal controls selection of Reference clock to MIPHY PLL.
1: External Differential clock on MIPHY_XTAL1,2 to be used (Default option for PCIe with 100
Mhz input on xtal1 and xtal2)
0: Clock from crystal will be used.
[30] miphy_osc_force_ext: This signal controls selection of Reference clock to MIPHY PLL.
1 : Internally generated reference clock to be will be used
0 : External Differential clock on MIPHY_XTAL1,2 to be used (Default option for PCIe with 100
Mhz input on xtal1 and xtal2).
[29] Reserved: Do not write
[28:27] miphy_clk_ref_div: MIPHY PLL reference clock divider factor.
00: no division of PLL reference clock
01: PLL reference clock divided by 2
10: PLL reference clock divided by 4
11: PLL reference clock divided by 8
[26] miphy_clk_osc_zo_en: clk_osc_zo enable bit
0: Disable clk_osc_nzo output from MIPHY
1: Enable clk_osc_nzo output form miphy (needed for SATA low power mode).
clk_osc_zo MIPHY output is the osci3 clock
[25] miphy_ssc_en: Enables to PCIe PHY PLL to apply a Spread Spectrum Clocking (SSC)
modulation on the clock.
0: SSC Modulation is disabled
1: SSC modulation is enabled
[24] miphy_p0_tx_lspd: Sets Serializer mode for Power and Performance
1: TX low speed mode (reduction of power, )
0: TX high speed mode (high performance , higher power consumption)
[21] miphy_p0_rx_lspd: Sets De-Serializer mode for Power and Performance
1: RX low speed mode (reduction of power, )
0: RX high speed mode (high performance , higher power consumption)
[16:15] miphy_osc_mode: MIPHY oscillator settings (only if the oscillator is embedded).
osc_mode[1]:
1: Gm = 10 mS
0: Gm = 5 mS
osc_mode[0]:
1: miller capacitor enabled
0: miller capacitor disabled
[14] miphy_p0_ena8b10b: Controls 8b10b encoder in port 0 of PHY
0: Disable 8b10 encoder
1: Enables 8b10b encoder for both TX and RX.
[7:0] miphy_pll_ratio_top: Divider ratio for PLL of PCIe PHY.
Doc ID 018904 Rev 3
247/1728
System configuration registers (MISC)
RM0089
PERIP_CFG
Peripheral configuration register
uart0_sir_uart_sel
uart1_sir_uart_sel
mali_subsys_clk_gating_en
R
R
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x42C
Type:
R/W
Reset:
0x0000 0000
Description:
Peripheral configuration register
2
1
0
mcif_sel
cec0_en
R
3
spdif_out_device_en
cec0_wakeup
R
4
RESERVED
cec1_en
R
5
i2s_mode_m
cec1_wakeup
R/W
6
i2s_mode_s
RESERVED
R/
W
7
RESERVED
ssp_cs_en
R/
W
8
i2s_ws_delay
hs_ssp_en
R
hs_ssp_sw_cs
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/W
R/W
R
R/
W
R/W
[21] hs_ssp_en: SSP Chip Select SW enable:
0 : PAD SSP CS is controlled by the SSP controller
1 : PAD SSP CS is controlled by hs_ss_sw_cs
[20] hs_ssp_sw_cs: SSP sw control chip select. Active State: Low
[19:18] ssp_cs_en: Chip Select on PAD configuration.
00 CS routed on SSP_SS0n
01 CS routed on SSP_SS1n
10 CS routed on SSP_SS2n
11 CS routed on SSP_SS3n
CS is driven either by SSP or by hs_ssp_sw_cs depending on hs_ssp_en.
[16] cec1_wakeup: Wakeup from standby for CEC1
[15] cec1_en: Active low peripheral Tristate Enable for CEC1
[14] cec0_wakeup: Wakeup from standby for CEC0
[13] cec0_en: Active low peripheral Tristate Enable for CEC0
[12] uart0_sir_uart_sel: UART0 UART/SIR interface selector
0 : UART interface enabled
1 : SIR interface enabled
[11] uart1_sir_uart_sel: UART1 UART/SIR interface selector
0 : UART interface enabled
1 : SIR interface enabled
[10] mali_subsys_clk_gating_en: 1 Mali core clock is gated forcefully though bus clock is alive
0 Mali core clock is not gated at all when bus clock is alive but core clock would be OFF when
both mali 200 and mali gp2 would be in idle.
[8] i2s_ws_delay: Setting this bit WS signal of I2S_M controller is delayed by one clock cycle.
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RM0089
System configuration registers (MISC)
[7:6] i2s_mode_s: Mode bits define the number of Audio Channels the I2S_M controller is working
in.
It can have following values:
00: Audio Channels Upto 2.0
01: Audio Channels Upto 3.1
10: Audio Channels Upto 5.1
11: Audio Channels Upto 7.1
[5:4] i2s_mode_m: Mode bits define the number of Audio Channels the I2S_S controller is working
in.
It can have following values:
00: Audio Channels Upto 2.0
01: Audio Channels Upto 3.1
10: Audio Channels Upto 5.1
11: Audio Channels Upto 7.1
[2] spdif_out_device_en: This bit is used as a global enable for SPDIF_OUT block.
[1:0] mcif_sel: Memory card interface selection
00: no card
01: SD/SDIO/MMC active
10: CF active
11: xD active
FSMC_CFG
FSMC configuration Register
5
4
3
2
1
0
NAND_NOR_SRAM_sel
6
RESERVED
7
ExtDevWidth
8
R
R/
W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x430
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FSMC configuration Register
[4] ExtDevWidth:
0 : 8 bit ;
1 : 16 bit
[1:0] NAND_NOR_SRAM_sel: Device type selection
00 NOR
01 NAND
10 SRAM
Doc ID 018904 Rev 3
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System configuration registers (MISC)
RM0089
MPMC_CFG
MPMC Control Status Register
axi4_axi_cmd_threshold
axi3_axi_cmd_threshold
axi2_axi_cmd_threshold
axi1_axi_cmd_threshold
axi0_axi_cmd_threshold
1
axi5_axi_cmd_threshold
2
axi0_AWCOBUF
3
axi1_AWCOBUF
4
axi2_AWCOBUF
5
axi3_AWCOBUF
6
axi4_AWCOBUF
7
axi5_AWCOBUF
8
RESERVED
9
two_giga_mode_ctrl_o
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x434
Type:
R/W
Reset:
0x00FF FFFF
Description:
MPMC Control Status Register
0
[30] two_giga_mode_ctrl_o: Enable 2 gigabyte address space for DDR
[29:24] axi[5:0]_AWCOBUF: Enable coherent write to be applied to related port
[23:0] axi[5:0]_axi_cmd_threshold: Control for max number of AXI read commands manageable by
the related port
MPMC_CTR_STS
MPMC Control Status Register
mem_rst_valid
0
param_ecc_removed
1
srefresh_enter
2
srefresh_ack
3
controller_busy
4
refresh_in_process
5
RESERVED
6
q_almost_full
7
cke_status
8
port_busy
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R
R/
W
R
R
Address:
Misc_RegisterBaseAddress + 0x438
Type:
R/W
Reset:
0x0000 0000
Description:
MPMC Control Status Register
[19:14] port_busy: One bit per port bus: to indicate the busy status for each port
[13] cke_status: Indicates the memory devices are either in self-refresh or in power-down mode
[12] q_almost_full: Indicates the queue has reached the q-fullness parameter value
[5] refresh_in_process: High when controller is executing a refresh command
[4] controller_busy: Busy status signal for memory controller
[3] srefresh_ack: Acknowledge signal to indicate the memory devices are in self-refresh mode
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RM0089
System configuration registers (MISC)
[2] srefresh_enter: Initiates a self-refresh command to the DRAMs
[1] param_ecc_removed: Status signal to indicate ECC feature is removed
[0] mem_rst_valid: Indicates that the command queue is idle
SATA_CORE_ID
SATA controller core id Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
sata_core_id
R/W
Address:
Misc_RegisterBaseAddress + 0x43C
Type:
R/W
Reset:
0x0000 0000
Description:
SATA controller core id Register
[31:0] sata_core_id: SATA controller core id
MALI_GEN_PURPOSE_1
Mali GPU general purpose register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_31_0
R
Address:
Misc_RegisterBaseAddress + 0x440
Type:
R
Reset:
0x0
Description:
Mali GPU general purpose register 1
[31:0] data_31_0: data_31_0[11:1] = axi_id_compressor_fifo_elements
data_31_0[0] = axi_id_compressor_fifo_full
MALI_GEN_PURPOSE_2
Mali GPU general purpose register 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_63_32
R
Address:
Misc_RegisterBaseAddress + 0x444
Type:
R
Reset:
0x0
Description:
Mali GPU general purpose register 2
[31:0] data_63_32: data_63_32[1] = IDLE_mgp2, mali gp2 is in idle mode
data_63_32[0] = IDLE_m200, mali 200 is in idle mode
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System configuration registers (MISC)
RM0089
PRC1_LOCK_CTR
HW lock configuration register 1
sts_loc_lock_7
sts_loc_lock_6
sts_loc_lock_5
sts_loc_lock_4
sts_loc_lock_3
sts_loc_lock_2
sts_loc_lock_1
RESERVED
lock_reset
lock_request
1
sts_loc_lock_8
2
sts_loc_lock_9
3
sts_loc_lock_10
4
sts_loc_lock_11
5
sts_loc_lock_12
6
sts_loc_lock_13
7
sts_loc_lock_14
8
RESERVED
9
sts_loc_lock_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R
W
W
Address:
Misc_RegisterBaseAddress + 0x500
Type:
R/W
Reset:
0x0000 0000
Description:
HW lock configuration register 1
See Section 5.5: Inter-processor communication functionality
0
[30:16] sts_loc_lock_[15:1]: Local lock semaphores status; this field reports the current value for the
local lock semaphores.
0: Disable lock semaphore.
1: Active HW lock semaphore.
[7:4] lock_reset: Reset lock semaphores pulse command; when high reset the corresponding
sts_loc_lock bit.
0000 : no action
0001 : reset loc_lock_1
....
1111 : reset loc_lock_15
[3:0] lock_request: Request lock semaphores pulse command; locks the local resource when high
and the corresponding sts_loc_lock bit is low.
0000 : no action
0001 : request loc_lock_1
....
1111 : request loc_lock_15.
Before to use any shared resource a processor must become the owner of it, so first it books
the loc_lock[x] bit dynamically associated with each resources thought the bit set instruction
(on lock_request). The bit set will be ignored if the corresponding global_lock[x] (=
PRC1_LOCK_CTR.sts_loc_lock[x] OR PRC2_LOCK_CTR.sts_loc_lock[x]) is already busy.
Finally with the bit test instruction the processor check if it gains the resources exclusivity:
check for sts_loc_lock[x] = 1.
After using the resource the processor releases it through the lock_reset command.
PRC2_LOCK_CTR
HW lock configuration register 2
sts_loc_lock_7
sts_loc_lock_6
sts_loc_lock_5
sts_loc_lock_4
sts_loc_lock_3
sts_loc_lock_2
sts_loc_lock_1
RESERVED
lock_reset
lock_request
1
sts_loc_lock_8
2
sts_loc_lock_9
3
sts_loc_lock_10
4
sts_loc_lock_11
5
sts_loc_lock_12
6
sts_loc_lock_13
7
sts_loc_lock_14
8
RESERVED
9
sts_loc_lock_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R
W
W
Address:
Misc_RegisterBaseAddress + 0x504
Type:
R/W
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0
RM0089
System configuration registers (MISC)
Reset:
0x0000 0000
Description:
HW lock configuration register 2
See Section 5.5: Inter-processor communication functionality
[30:16] sts_loc_lock_[15:1]: Local lock semaphores status; this field reports the current value for the
local lock semaphores.
0: Disable lock semaphore.
1: Active HW lock semaphore.
[7:4] lock_reset: Reset lock semaphores pulse command; when high reset the
corresponding sts_loc_lock bit.
0000 : no action
0001 : reset loc_lock_1
....
1111 : reset loc_lock_15
[3:0] lock_request: Request lock semaphores pulse command; locks the local resource when high
and the corresponding sts_loc_lock bit is low.
0000 : no action
0001 : request loc_lock_1
....
1111 : request loc_lock_15.
Before to use any shared resource a processor must become the owner of it, so first it books
the loc_lock[x] bit dynamically associated with each resources thought the bit set instruction
(on lock_request). The bit set will be ignored if the corresponding global_lock[x] (=
PRC1_LOCK_CTR.sts_loc_lock[x] OR PRC2_LOCK_CTR.sts_loc_lock[x]) is already busy.
Finally with the bit test instruction the processor check if it gains the resources exclusivity:
check for sts_loc_lock[x] = 1.
After using the resource the processor releases it through the lock_reset command.
PRC1_IRQ_CTR
SW Interrupt register for inter-processor
communication
4
3
2
1
0
int2_req_prc1_1
5
int2_req_prc1_2
6
RESERVED
7
int1_req_prc2_1
8
int1_req_prc2_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x508
Type:
R/W
Reset:
0x0000 0000
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System configuration registers (MISC)
Description:
RM0089
SW Interrupt register for inter-processor communication
[17] int1_req_prc2_2: Interrupt clear on interrupt line ID[147].See PRC2_IRQ_CTR for interrupt
request
0 : no action
1 : interrupt clear
[16] int1_req_prc2_1: Interrupt clear on interrupt line ID[146].See PRC2_IRQ_CTR for interrupt
request
0 : no action
1 : interrupt clear
[1] int2_req_prc1_2: Interrupt request on interrupt line ID[145].See PRC2_IRQ_CTR for interrupt
clear.
0 : no action
1 : interrupt request
[0] int2_req_prc1_1: Interrupt request on interrupt line ID[144].See PRC2_IRQ_CTR for interrupt
clear.
0 : no action
1 : interrupt request
PRC2_IRQ_CTR
SW Interrupt register for inter-processor
communication
3
2
1
0
int1_req_prc2_1
4
int1_req_prc2_2
5
RESERVED
6
int2_req_prc1_1
7
int2_req_prc1_2
8
R
R/
W
R/
W
R
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x51C
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SW Interrupt register for inter-processor communication
[17] int2_req_prc1_2: Interrupt clear on interrupt line ID[145].See PRC1_IRQ_CTR for request
0 : no action
1 : interrupt clear
[16] int2_req_prc1_1: Interrupt clear on interrupt line ID[144].See PRC1_IRQ_CTR for request
0 : no action
1 : interrupt clear
[1] int1_req_prc2_2: Interrupt request on interrupt line ID[147].See PRC1_IRQ_CTR for interrupt
clear.
0 : no action
1 : interrupt request
[0] int1_req_prc2_1: Interrupt request on interrupt line ID[146].See PRC1_IRQ_CTR for interrupt
clear.
0 : no action
1 : interrupt request
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RM0089
System configuration registers (MISC)
PAD_PU_CFG_1
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x600
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
PAD_PU_CFG_2
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x604
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
PAD_PU_CFG_3
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x608
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
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System configuration registers (MISC)
RM0089
PAD_PU_CFG_4
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x60C
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
PAD_PU_CFG_5
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x610
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
PAD_PU_CFG_6
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x614
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
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7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
PAD_PU_CFG_7
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x618
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
PAD_PU_CFG_8
PAD Pull Up Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pu_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x61C
Type:
R/W
Reset:
0x0000 0000
Description:
PAD Pull Up Configuration
[31:0] pu_dis: See Table 53: Pad configuration options for more details.
0 : pull up active
1 : pull up disabled
Both pull up and pull down active are forbidden
PAD_PD_CFG_1
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x620
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
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System configuration registers (MISC)
RM0089
PAD_PD_CFG_2
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x624
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
PAD_PD_CFG_3
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x628
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
PAD_PD_CFG_4
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x62C
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
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7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
PAD_PD_CFG_5
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x630
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
PAD_PD_CFG_6
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x634
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
PAD_PD_CFG_7
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x638
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
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System configuration registers (MISC)
RM0089
PAD_PD_CFG_8
PAD Pull Down Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
pd_dis
R/W
Address:
Misc_RegisterBaseAddress + 0x63C
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Pull Down Configuration
[31:0] pd_dis: See Table 53: Pad configuration options for more details.
0 : pull down active
1 : pull down disabled
Both pull up and pull down active are forbidden
PAD_DRV_CFG_1
PAD Drive level Configuration
drv_5
drv_4
drv_3
drv_2
drv_1
drv_0
0
drv_6
1
drv_7
2
drv_8
3
drv_9
4
drv_10
5
drv_11
6
drv_12
7
drv_13
8
drv_14
9
drv_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x648
Type:
R/W
Reset:
0x5555 5555
Description:
PAD Drive level Configuration
[31:0] drv_[15:0]: Configure the pad drive strength
00 : 4 mA
01 : 8 mA
10 : 6 mA
11 : 10 mA
See Table 53: Pad configuration options for more details
PAD_DRV_CFG_2
PAD Drive level Configuration
drv_5
drv_4
drv_3
drv_2
drv_1
drv_0
0
drv_6
1
drv_7
2
drv_8
3
drv_9
4
drv_10
5
drv_11
6
drv_12
7
drv_13
8
drv_14
9
drv_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x64C
Type:
R/W
Reset:
0x5555 5555
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RM0089
System configuration registers (MISC)
Description:
PAD Drive level Configuration
[31:0] drv_[15:0]: Configure the pad drive strength
00 : 4 mA
01 : 8 mA
10 : 6 mA
11 : 10 mA
See Table 53: Pad configuration options for more details
PAD_DRV_CFG_3
PAD Drive level Configuration
drv_5
drv_4
drv_3
drv_2
drv_1
drv_0
0
drv_6
1
drv_7
2
drv_8
3
drv_9
4
drv_10
5
drv_11
6
drv_12
7
drv_13
8
drv_14
9
drv_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x650
Type:
R/W
Reset:
0x5555 5555
Description:
PAD Drive level Configuration
[31:0] drv_[15:0]: Configure the pad drive strength
00 : 4 mA
01 : 8 mA
10 : 6 mA
11 : 10 mA
See Table 53: Pad configuration options for more details
PAD_DRV_CFG_4
PAD Drive level Configuration
drv_5
drv_4
drv_3
drv_2
drv_1
drv_0
0
drv_6
1
drv_7
2
drv_8
3
drv_9
4
drv_10
5
drv_11
6
drv_12
7
drv_13
8
drv_14
9
drv_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0x654
Type:
R/W
Reset:
0x5555 5555
Description:
PAD Drive level Configuration
[31:0] drv_[15:0]: Configure the pad drive strength
00 : 4 mA
01 : 8 mA
10 : 6 mA
11 : 10 mA
See Table 53: Pad configuration options for more details
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System configuration registers (MISC)
RM0089
PAD_SLEW_CFG_1
PAD Slew level Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
slew
R/W
Address:
Misc_RegisterBaseAddress + 0x65C
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Slew level Configuration
[31:0] slew:
0 : nominal
1 : fast
See Table 53: Pad configuration options for more details
PAD_SLEW_CFG_2
PAD Slew level Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
slew
R/W
Address:
Misc_RegisterBaseAddress + 0x660
Type:
R/W
Reset:
0xFFFF FFFF
Description:
PAD Slew level Configuration
[31:0] slew:
0 : nominal
1 : fast
See Table 53: Pad configuration options for more details
PAD_FUNCTION_EN_1
Pad Function selection
7
6
5
4
3
2
1
0
dir_en
8
R/W
R/
W
Address:
Misc_RegisterBaseAddress + 0x668
Type:
R/W
Reset:
0x01FF FFFE
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ip_en
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
System configuration registers (MISC)
Description:
Pad Function selection
[31:1] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
[0] dir_en: PAD direction is applied to all programmable pad.
0 : PAD directions are set to input
1 : PAD directions are controlled by Ips
PAD_FUNCTION_EN_2
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x66C
Type:
R/W
Reset:
0xFFFF FFFF
Description:
Pad Function selection
[31:0] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
PAD_FUNCTION_EN_3
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x670
Type:
R/W
Reset:
0xFFFF FFFF
Description:
Pad Function selection
[31:0] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
PAD_FUNCTION_EN_4
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x674
Type:
R/W
Reset:
0xFFFF FFFF
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System configuration registers (MISC)
Description:
RM0089
Pad Function selection
[31:0] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
PAD_FUNCTION_EN_5
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x690
Type:
R/W
Reset:
0xFFFF FFFF
Description:
Pad Function selection
[31:0] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
PAD_FUNCTION_EN_6
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x694
Type:
R/W
Reset:
0xFFFF FFFF
Description:
Pad Function selection
[31:0] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
PAD_FUNCTION_EN_7
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x698
Type:
R/W
Reset:
0xFFFF FFFF
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9
8
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
Description:
Pad Function selection
[31:0] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
PAD_FUNCTION_EN_8
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x69C
Type:
R/W
Reset:
0xFFFF FFFF
Description:
Pad Function selection
[31:0] ip_en:
0 : pad routed to GPIO
1 : pad routed to IP
See Table 53: Pad configuration options for more details
PAD_SHARED_IP_EN_1
Pad Function selection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
shared_ip_en
R/W
Address:
Misc_RegisterBaseAddress + 0x6A0
Type:
R/W
Reset:
0x0000 0000
Description:
Pad Function selection
[31:0] shared_ip_en:
0 : pad routed to SHARED IP 1
1 : pad routed to SHARED IP 2
See Table 53: Pad configuration options for more details
DDR PAD Configuration
Address:
Misc_RegisterBaseAddress + 0x6A8
Type:
R/W
Doc ID 018904 Rev 3
1
0
ddr3_sw_sel
2
ddr3_pad_sel
3
ddr3_pad_sw_sel
4
ctrl_proga
5
ctrl_progb
6
clk_proga
7
clk_progb
8
data_proga
R
9
pad_vref
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
data_progb
DDR_PAD_CFG
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R
R/
W
265/1728
System configuration registers (MISC)
RM0089
Reset:
0x0000 0000
Description:
DDR PAD Configuration
[9] pad_vref: PADs voltage reference: 0-integrated reference voltage 1-external reference voltage
[8] data_progb: Output Buffer AC characteristics(for data pads) :
In case of DDR3 applications this bit must be set to 1.
In case of DDR2 applications it is recommended to set this bit to 1.
[7] data_proga: Output Buffer AC characteristics(for data pads) :
In case of DDR3 applications this bit must be set to 1.
In case of DDR2 applications it is recommended to set this bit to 1.
[6] clk_progb: Output Buffer AC characteristics(for clock pads) :
In case of DDR3 applications this bit must be set to 1.
In case of DDR2 applications it is recommended to set this bit to 1.
[5] clk_proga: Output Buffer AC characteristics(for clock pads) :
In case of DDR3 applications this bit must be set to 1.
In case of DDR2 applications it is recommended to set this bit to 1.
[4] ctrl_progb: Output Buffer AC characteristics(for ctrl/addr pads) :
In case of DDR3 applications this bit must be set to 1.
In case of DDR2 applications it is recommended to set this bit to 1.
[3] ctrl_proga: Output Buffer AC characteristics(for ctrl/addr pads) :
In case of DDR3 applications this bit must be set to 1.
In case of DDR2 applications it is recommended to set this bit to 1.
[2] ddr3_pad_sw_sel: Controllability mode for DDR pads voltage :
0: DDR_MEM_DDR2_3 pad used to configure the DDR (hw selection)
1: ddr3_sw_sel field used to configure the DDR (sw selection)
[1] ddr3_pad_sel: status of DDR_MEM_DDR2_3 pad:
0 : DDR2 mode selected
1 : DDR3 mode selected
[0] ddr3_sw_sel: software selection:
0 : DDR2 mode selected
1 : DDR3 mode selected
IO_COMP1_1V8_3V3 configuration
R
R
R/W
R/
W
Address:
Misc_RegisterBaseAddress + 0x700
Type:
R/W
Reset:
0x0000 0000
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0
tq
R
1
en
R/W
2
freeze
R
3
sts_ok
pad_tq
4
psw
5
RESERVED
6
nasrc
7
RESERVED
8
rasrc
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
accurate
COMPENSATION_1V8_3V3_1_CFG
R
R/
W
R/
W
R/
W
R/
W
RM0089
System configuration registers (MISC)
Description:
IO_COMP1_1V8_3V3 configuration
[30:24] rasrc: Writing code compensation parameter;
field sampled from compensation cell during Read Mode
[22:16] nasrc: Readcode compensation parameter;
this field is qualified from sts_ok active high
[7:6] psw: Reserved .Not used
[5] pad_tq: IDDQ command.
When high the Compensation enters in IDDQ mode
[4] sts_ok: Valid code compensation;
field active high in Normal Mode when the measured code is available on narsc
[3] accurate: Compensation cell internal/external resistance definition:
0 : Internal reference resistor
1 : External reference resistor
[2] freeze: Freeze command
When high freezes the current calculated value of compensation bus
[1] tq: Compensation cell COMTQ command
[0] en: Compensation cell COMEN command
IO_COMP2_1V8_3V3 configuration
R
R
R/W
R/
W
Address:
Misc_RegisterBaseAddress + 0x704
Type:
R/W
Reset:
0x0000 0000
Description:
0
tq
R
1
en
R/W
2
freeze
R
3
sts_ok
pad_tq
4
psw
5
RESERVED
6
nasrc
7
RESERVED
8
rasrc
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
accurate
COMPENSATION_1V8_3V3_2_CFG
R
R/
W
R/
W
R/
W
R/
W
IO_COMP2_1V8_3V3 configuration
[30:24] rasrc: Writing code compensation parameter;
field sampled from compensation cell during Read Mode
[22:16] nasrc: Readcode compensation parameter;
this field is qualified from sts_ok active high
[7:6] psw: Reserved .Not used
[5] pad_tq: IDDQ command.
When high the Compensation enters in IDDQ mode
[4] sts_ok: Valid code compensation;
field active high in Normal Mode when the measured code is available on narsc
[3] accurate: Compensation cell internal/external resistance definition:
0 : Internal reference resistor
1 : External reference resistor
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System configuration registers (MISC)
RM0089
[2] freeze: Freeze command
When high freezes the current calculated value of compensation bus
[1] tq: Compensation cell COMTQ command
[0] en: Compensation cell COMEN command
IO_COMP1_3V3 configuration
R
R
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x708
Type:
R/W
Reset:
0x0000 0000
Description:
IO_COMP1_3V3 configuration
R
R/
W
R/
W
R/
W
R/
W
[30:24] rasrc: Writing code compensation parameter;
field sampled from compensation cell during Read Mode
[22:16] nasrc: Readcode compensation parameter;
this field is qualified from sts_ok active high
[7] pad_chipsleep: Sets the 3V3 PADS in sleep mode .
[6] pad_sleepinhbt: Sets the 3V3 PADS in sleep mode .
[5] pad_tq: IDDQ command.
When high the Compensation enters in IDDQ mode
[4] sts_ok: Valid code compensation;
field active high in Normal Mode when the measured code is available on narsc
[3] accurate: Compensation cell internal/external resistance definition:
0 : Internal reference resistor
1 : External reference resistor
[2] freeze: Freeze command
When high freezes the current calculated value of compensation bus
[1] tq: Compensation cell COMTQ command
[0] en: Compensation cell COMEN command
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0
tq
R
1
en
R/W
2
freeze
pad_tq
R
3
sts_ok
pad_sleepinhbt
4
pad_chipsleep
5
RESERVED
6
nasrc
7
RESERVED
8
rasrc
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
accurate
COMPENSATION_3V3_1_CFG
RM0089
System configuration registers (MISC)
IO_COMP2_3V3 configuration
R
R
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x70C
Type:
R/W
Reset:
0x0000 0000
Description:
IO_COMP2_3V3 configuration
0
tq
R
1
en
R/W
2
freeze
pad_tq
R
3
sts_ok
pad_sleepinhbt
4
pad_chipsleep
5
RESERVED
6
nasrc
7
RESERVED
8
rasrc
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
accurate
COMPENSATION_3V3_2_CFG
R
R/
W
R/
W
R/
W
R/
W
[30:24] rasrc: Writing code compensation parameter;
field sampled from compensation cell during Read Mode
[22:16] nasrc: Readcode compensation parameter;
this field is qualified from sts_ok active high
[7] pad_chipsleep: Sets the 3V3 PADS in sleep mode
[6] pad_sleepinhbt: Sets the 3V3 PADS in sleep mode .
[5] pad_tq: IDDQ command.
When high the Compensation enters in IDDQ mode
[4] sts_ok: Valid code compensation;
field active high in Normal Mode when the measured code is available on narsc
[3] accurate: Compensation cell internal/external resistance definition:
0 : Internal reference resistor
1 : External reference resistor
[2] freeze: Freeze command
When high freezes the current calculated value of compensation bus
[1] tq: Compensation cell COMTQ command
[0] en: Compensation cell COMEN command
COMPENSATION_DDR_CFG
IO_COMP_DDR configuration
0
comzcrdy
1
RESERVED
2
comzcp_core
3
comzcn_core
4
enbcomzcin
5
enableb
6
updateZC
7
comzcpin
8
comzcnin
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/
W
R/
W
R/
W
R
R
R
R
Address:
Misc_RegisterBaseAddress + 0x710
Type:
R/W
Reset:
0x0000 0000
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System configuration registers (MISC)
Description:
RM0089
IO_COMP_DDR configuration
[20:17] comzcnin: Input bits to write the comzcn calibration code directly from the core.
There are 16 different possible compensation values
[16:13] comzcpin: Input bits to write the comzcp calibration code directly from the core.
There are 16 different possible compensation values.
[12] updateZC: When low:
1) Clear comzcrdy signal
2) FSM generates and updates a new code so comzcrdy goes to one.
3) No code was updated, so it remains at the last updated code.
When the high the code is updated, the FSM calculates a new code each
time. This configuration is not stable because the code is continually
updated. If you want to update the code, make sure that the RAM DDR
access is not enabled, then drive this pin high then low.
[11] enableb: When low, the compensation cell runs normally and generates the
compensation code if requested.
When high, disable the analog portion. The internal analog clock is
disabled. The previously generated codes remain comzcp and comzcn.
Note: To reactivate the analog part, reset the compensation through MPMC reset
[10] enbcomzcin: When high, the code is determined by the compensation block.
When low, the code is written by the core on the comzcpin/comzcnin bus,
even if a new code is computed by the compensation block (comzcrdy
goes to one).
[9:6] comzcn_core: Value of computed compensation value
[5:2] comzcp_core: Value of computed compensation value
[0] comzcrdy: When low, the code is not computed by the compensation block.
When high, the code is computed by the compensation block.
IO_COMP_2V5_3V3 configuration
R
R
R/W
R/
W
Address:
Misc_RegisterBaseAddress + 0x714
Type:
R/W
Reset:
0x0000 0000
Description:
IO_COMP_2V5_3V3 configuration
[30:24] rasrc: Writing code compensation parameter;
field sampled from compensation cell during Read Mode
[22:16] nasrc: Readcode compensation parameter;
this field is qualified from sts_ok active high
[7:6] psw: Reserved .Not used
[5] pad_tq: IDDQ command.
When high the Compensation enters in IDDQ mode
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0
tq
R
1
en
R/W
2
freeze
R
3
sts_ok
pad_tq
4
psw
5
RESERVED
6
nasrc
7
RESERVED
8
rasrc
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
accurate
COMPENSATION_2V5_3V3_1_CFG
R
R/
W
R/
W
R/
W
R/
W
RM0089
System configuration registers (MISC)
[4] sts_ok: Valid code compensation;
field active high in Normal Mode when the measured code is available on narsc
[3] accurate: Compensation cell internal/external resistance definition:
0 : Internal reference resistor
1 : External reference resistor
[2] freeze: Freeze command
When high freezes the current calculated value of compensation bus
[1] tq: Compensation cell COMTQ command
[0] en: Compensation cell COMEN command
8
7
6
5
4
3
write_finishedm
write_finished2
write_finished1
ready_mask
ready_data2
ready_data1
write_mask
write_data2
write_data1
OTP configuration register for R/W management
RESERVED
OTP_PROG_CTR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x800
Type:
R/W
Reset:
0x0000 0000
Description:
OTP configuration register for R/W management
9
2
1
0
[8] write_finishedm: “1“ means that write operation to bank m has finished
[7] write_finished2: “1“ means that write operation to bank 2 has finished
[6] write_finished1: “1“ means that write operation to bank 1 has finished
[5] ready_mask: “1“means that data stored inside the OTP bank m and mirrored here is stable
[4] ready_data2: “1“means that data stored inside the OTP bank 2 and mirrored here is stable
[3] ready_data1: “1“means that data stored inside the OTP bank 1 and mirrored here is stable
[2] write_mask: setting to “1“ triggers a write operation from registers 844>860 to OTP antifuse
bank m
[1] write_data2: setting to “1“ triggers a write operation from registers 824>840 to OTP antifuse
bank 2
[0] write_data1: setting to “1“ triggers a write operation from registers 804>820 to OTP antifuse
bank 1
OTP_WDATA1_1
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_31_0
R/W
Address:
Misc_RegisterBaseAddress + 0x804
Type:
R/W
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System configuration registers (MISC)
RM0089
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 1
[31:0] data_31_0: user defined
OTP_WDATA1_2
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_63_32
R/W
Address:
Misc_RegisterBaseAddress + 0x808
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 1
[31:0] data_63_32: user defined
OTP_WDATA1_3
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_95_64
R/W
Address:
Misc_RegisterBaseAddress + 0x80c
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 1
[31:0] data_95_64: user defined
OTP_WDATA1_4
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
data_127_96
R/W
Address:
Misc_RegisterBaseAddress + 0x810
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 1
[31:0] data_127_96: user defined
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9
8
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
OTP_WDATA1_5
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_159_128
R/W
Address:
Misc_RegisterBaseAddress + 0x814
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 1
[31:0] data_159_128: user defined
OTP_WDATA1_6
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_191_160
R/W
Address:
Misc_RegisterBaseAddress + 0x818
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 1
[31:0] data_191_160: user defined
OTP_WDATA1_7
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_223_192
R/W
Address:
Misc_RegisterBaseAddress + 0x81c
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 1
[31:0] data_223_192: user defined
OTP_WDATA1_8
Data to be written in OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_255_224
R/W
Address:
Misc_RegisterBaseAddress + 0x820
Type:
R/W
Reset:
0x0000 0000
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System configuration registers (MISC)
Description:
RM0089
Data to be written in OTP bank 1
[31:0] data_255_224: [31] : XXXX reserved for blowing at final test (hardwired function)
[30:0] : user defined
OTP_WDATA2_1
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_31_0
R/W
Address:
Misc_RegisterBaseAddress + 0x824
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 2
[31:0] data_31_0: user defined
OTP_WDATA2_2
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_63_32
R/W
Address:
Misc_RegisterBaseAddress + 0x828
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 2
[31:0] data_63_32: user defined
OTP_WDATA2_3
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
data_95_64
R/W
Address:
Misc_RegisterBaseAddress + 0x82c
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 2
[31:0] data_95_64: user defined
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9
8
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
OTP_WDATA2_4
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_127_96
R/W
Address:
Misc_RegisterBaseAddress + 0x830
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 2
[31:0] data_127_96: user defined
OTP_WDATA2_5
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_159_128
R/W
Address:
Misc_RegisterBaseAddress + 0x834
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 2
[31:0] data_159_128: user defined
OTP_WDATA2_6
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_191_160
R/W
Address:
Misc_RegisterBaseAddress + 0x838
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 2
[31:0] data_191_160: user defined
OTP_WDATA2_7
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_223_192
R/W
Address:
Misc_RegisterBaseAddress + 0x83c
Type:
R/W
Reset:
0x0000 0000
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System configuration registers (MISC)
Description:
RM0089
Data to be written in OTP bank 2
[31:0] data_223_192: user defined
OTP_WDATA2_8
Data to be written in OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_255_224
R/W
Address:
Misc_RegisterBaseAddress + 0x840
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank 2
[31:0] data_255_224: [31] : XXXX reserved for blowing at final test (hardwired function)
[30:0] : user defined
OTP_MASK_1
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_31_0
R/W
Address:
Misc_RegisterBaseAddress + 0x844
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_31_0: [31:16] :WP bits B2 8 bits + 8 redundancy for masking bank 2 (hardwired function)
[15:0] :WP bits B1 8 bits + 8 redundancy for masking bank 1 (hardwired function)
OTP_MASK_2
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
data_63_32
R/W
Address:
Misc_RegisterBaseAddress + 0x848
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_63_32: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
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0
RM0089
System configuration registers (MISC)
OTP_MASK_3
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_95_64
R/W
Address:
Misc_RegisterBaseAddress + 0x84c
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_95_64: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_MASK_4
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_127_96
R/W
Address:
Misc_RegisterBaseAddress + 0x850
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_127_96: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_MASK_5
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_159_128
R/W
Address:
Misc_RegisterBaseAddress + 0x854
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_159_128: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_MASK_6
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_191_160
R/W
Address:
Misc_RegisterBaseAddress + 0x858
Type:
R/W
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System configuration registers (MISC)
RM0089
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_191_160: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_MASK_7
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_223_192
R/W
Address:
Misc_RegisterBaseAddress + 0x85c
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_223_192: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_MASK_8
Data to be written in OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_255_224
R/W
Address:
Misc_RegisterBaseAddress + 0x860
Type:
R/W
Reset:
0x0000 0000
Description:
Data to be written in OTP bank m
[31:0] data_255_224: bit description :
[31] : XXXX reserved for blowing at final test (hardwired function)
[30:27] : reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
[26:25] : [J1,J0] 1 bit + 1 redundancy for JTAG disable (hardwired function)
[24:23] : [T1,T0] 1 bit + 1 redundancy for TEST disable (hardwired function)
[22:0] : reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_RDATA1_1
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
data_31_0
R
Address:
Misc_RegisterBaseAddress + 0x864
Type:
R
Reset:
0x0000 0000
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9
8
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
Description:
Data read from OTP bank 1
[31:0] data_31_0: user defined
OTP_RDATA1_2
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_63_32
R
Address:
Misc_RegisterBaseAddress + 0x868
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 1
[31:0] data_63_32: user defined
OTP_RDATA1_3
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_95_64
R
Address:
Misc_RegisterBaseAddress + 0x86c
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 1
[31:0] data_95_64: user defined
OTP_RDATA1_4
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_127_96
R
Address:
Misc_RegisterBaseAddress + 0x870
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 1
[31:0] data_127_96: user defined
OTP_RDATA1_5
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_159_128
R
Address:
Misc_RegisterBaseAddress + 0x874
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System configuration registers (MISC)
RM0089
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 1
[31:0] data_159_128: user defined
OTP_RDATA1_6
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_191_160
R
Address:
Misc_RegisterBaseAddress + 0x878
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 1
[31:0] data_191_160: user defined
OTP_RDATA1_7
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_223_192
R
Address:
Misc_RegisterBaseAddress + 0x87c
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 1
[31:0] data_223_192: user defined
OTP_RDATA1_8
Data read from OTP bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
data_255_224
R
Address:
Misc_RegisterBaseAddress + 0x880
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 1
[31:0] data_255_224:
[31] : XXXX reserved for blowing at final test (hardwired function)
[30:0] : user defined
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7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
OTP_RDATA2_1
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_31_0
R
Address:
Misc_RegisterBaseAddress + 0x884
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 2
[31:0] data_31_0: user defined
OTP_RDATA2_2
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_63_32
R
Address:
Misc_RegisterBaseAddress + 0x888
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 2
[31:0] data_63_32: user defined
OTP_RDATA2_3
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_95_64
R
Address:
Misc_RegisterBaseAddress + 0x88c
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 2
[31:0] data_95_64: user defined
OTP_RDATA2_4
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_127_96
R
Address:
Misc_RegisterBaseAddress + 0x890
Type:
R
Reset:
0x0000 0000
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System configuration registers (MISC)
Description:
RM0089
Data read from OTP bank 2
[31:0] data_127_96: user defined
OTP_RDATA2_5
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_159_128
R
Address:
Misc_RegisterBaseAddress + 0x894
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 2
[31:0] data_159_128: user defined
OTP_RDATA2_6
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_191_160
R
Address:
Misc_RegisterBaseAddress + 0x898
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 2
[31:0] data_191_160: user defined
OTP_RDATA2_7
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_223_192
R
Address:
Misc_RegisterBaseAddress + 0x89c
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 2
[31:0] data_223_192: user defined
OTP_RDATA2_8
Data read from OTP bank 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
data_255_224
R
Address:
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Misc_RegisterBaseAddress + 0x8a0
Doc ID 018904 Rev 3
9
8
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank 2
[31:0] data_255_224:
[31] : XXXX reserved for blowing at final test (hardwired function)
[30:0] : user defined
OTP_RDATAM_1
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_31_0
R
Address:
Misc_RegisterBaseAddress + 0x8a4
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_31_0:
[31:16] :WP bits B2 8 bits + 8 redundancy for masking bank 2 (hardwired function)
[15:0] :WP bits B1 8 bits + 8 redundancy for masking bank 1 (hardwired function)
OTP_RDATAM_2
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_63_32
R
Address:
Misc_RegisterBaseAddress + 0x8a8
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_63_32: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_RDATAM_3
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_95_64
R
Address:
Misc_RegisterBaseAddress + 0x8ac
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_95_64: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
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System configuration registers (MISC)
RM0089
OTP_RDATAM_4
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_127_96
R
Address:
Misc_RegisterBaseAddress + 0x8b0
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_127_96: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_RDATAM_5
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_159_128
R
Address:
Misc_RegisterBaseAddress + 0x8b4
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_159_128: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_RDATAM_6
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_191_160
R
Address:
Misc_RegisterBaseAddress + 0x8b8
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_191_160: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_RDATAM_7
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
data_223_192
R
Address:
Misc_RegisterBaseAddress + 0x8bc
Type:
R
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9
8
7
6
5
4
3
2
1
0
RM0089
System configuration registers (MISC)
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_223_192: reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
OTP_RDATAM_8
Data read from OTP bank m
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
data_255_224
R
Address:
Misc_RegisterBaseAddress + 0x8c0
Type:
R
Reset:
0x0000 0000
Description:
Data read from OTP bank m
[31:0] data_255_224: bit description :
[31] : XXXX reserved for blowing at final test (hardwired function)
[30:27] : reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
[26:25] : [J1,J0] 1 bit + 1 redundancy for JTAG disable (hardwired function)
[24:23] : [T1,T0] 1 bit + 1 redundancy for TEST disable (hardwired function)
[22:0] : reserved for boot code : see Bootrom chapter in RM0078, Reference manual,
SPEAr1340 architecture and functionality
Note : when J1(or J0)=1 and
OTP_RDATAM_8[31]=OTP_RDATA2_8[31]=OTP_RDATA1_8[31]=0 the JTAG is disabled
THSENS_CFG
THSENS configuration register for threshold and
correction settings
temp_owerflow
temp_value
3
temp_correct
4
temp_pdn
5
RESERVED
6
temp_lo_threshold
7
temp_lo_override
8
temp_hi_threshold
9
temp_hi_override
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/W
R/
W
R/W
R
R/
W
R/W
R
R
Address:
Misc_RegisterBaseAddress + 0x8c4
Type:
R/W
Reset:
0x0000 0000
Description:
THSENS configuration register for threshold and correction settings
2
1
0
[31] temp_hi_override: set to ‘1‘ to override interrupt when temperature exceeds
high threshold
[30:24] temp_hi_threshold: high temperature threshold.
THSENS generates an interrupt when T exceed high threshold
[23] temp_lo_override: set to ‘1‘ to override interrupt when temperature is lower
than low threshold
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System configuration registers (MISC)
RM0089
[22:16] temp_lo_threshold: low temperature threshold.
THSENS generates an interrupt when T is less then low threshold
[13] temp_pdn: when ‘0‘ powers down thermal sensor block
[12:8] temp_correct: correction offset for temperature read from thermal sensor (typical correction
value: 10)
[7] temp_owerflow: overflow bit. When ‘1‘, temperature exceeds range
[6:0] temp_value: temperature value read from thermal sensor (temperature measurement is
available 0.5msec after temp_pdn release, 22 clk_thsens cycles after software reset release,
controlled through PERIP2_SW_RST register)
A9SM_CLUSTERID
A9SM ID register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
clusterid
R
R/W
Address:
Misc_RegisterBaseAddress + 0x900
Type:
R/W
Reset:
0x0000 0000
Description:
A9SM ID register
[3:0] clusterid: ID for entire A9SM (Used for MultiSoc identification)
A9SM_STATUS
A9SM status register
2
1
0
dbgack
3
dbgcpudone
4
R
R
R
R
R
R
R
Address:
Misc_RegisterBaseAddress + 0x904
Type:
R
Reset:
0x0000 0000
Description:
A9SM status register
[11:10] ptmidlenack: Standby mode acknowledge for PTM CPU0/1 (0 = idle)
[9:8] smpnamp: Indicates if a CPU0,1 is in SMP(1)/AMP(0) mode
[7:6] standbywfi: Indicates that CPU0,1 is in Standby mode
[5:4] standbywfe: Indicates if a CPU0,1 is in WFE state
[3:2] dbgcpudone: Indicates that the CPU0,1 has executed a DSB
[1:0] dbgack: Indicates that the CPU0,1 is in DEBUG state
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5
standbywfe
6
standbywfi
7
smpnamp
8
ptmidlenack
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
System configuration registers (MISC)
A9SM_DEBUG
A9SM debug register
2
1
0
dbgen
3
spiden
4
niden
5
spniden
6
deviceen
7
edbgrq
8
R
R/W
R/
W
R/
W
R/
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x908
Type:
R/W
Reset:
0x0000 0013
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A9SM debug register
[6:5] edbgrq: Put the corresponding CPU is in DEBUG state (Default disabled)
[4] deviceen: When LOW it disables the APBDBGSYS access port (Default enabled)
[3] spniden: Secure Privileged Non-Invasive Debug Enable (Default disabled)
[2] niden: Non-Invasive Debug Enable (i.e. trace) (Default disabled)
[1] spiden: Secure Privileged Invasive Debug Enable (Default enabled)
[0] dbgen: Enables invasive debug (i.e. JTAG) (Default enabled)
A9SM_FILTER
A9SM address filtering register
5
filterend
6
RESERVED
7
filterstart
8
RESERVED
9
filteren
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R
R/W
Address:
Misc_RegisterBaseAddress + 0x90C
Type:
R/W
Reset:
0x0000 0000
Description:
A9SM address filtering register
4
3
2
1
0
[31] filteren: Enables AXI M1 address filtering
[27:16] filterstart: Start address filtering
[11:0] filterend: End address filtering
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System configuration registers (MISC)
RM0089
A9SM_PARITY_CFG
A9SM parity errors configuration register
4
3
2
1
0
l2_cfg
5
cpu_cfg
6
cpu_rst
7
l2_rst
8
R
W
W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x910
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A9SM parity errors configuration register
[3] l2_rst: Write 1 => cause reset of A9SM_PARITY_ERR[25:24]
[2] cpu_rst: Write 1 => cause reset of A9SM_PARITY_ERR[17:0]
[1] l2_cfg:
If 0 => L2 parity errors are “recoverable“ (IRQ)
If 1 => L2 parity errors are “non-recoverable“ (RESET)
[0] cpu_cfg:
If 0 => CPU parity errors are “recoverable“ (IRQ)
If 1 => CPU parity errors are “non-recoverable“ (RESET)
A9SM_PARITY_ERR
A9SM parity errors status register
3
parityfail0
4
parityfail1
5
parityscu
6
RESERVED
7
parityl2
8
R
R
R
R
R
R
Address:
Misc_RegisterBaseAddress + 0x914
Type:
R
Reset:
0x0000 0000
Description:
A9SM parity errors status register
[25:24] parityl2: L2 Parity error on Tag (24) and/or Data (25) ram
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9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
System configuration registers (MISC)
[17:16] parityscu: SCU parity error on CPU0 (16) and/or CPU1 (17)
[15:8] parityfail1: Parity fail on CPU1
Bit [7] BTAC
Bit [6] GHB
Bit [5] Instruction tag RAM
Bit [4] Instruction data RAM
Bit [3] Main TLB
Bit [2] D outer RAM
Bit [1] Data tag RAM
Bit [0] Data data RAM
[7:0] parityfail0: Parity fail on CPU0
Bit [7] BTAC
Bit [6] GHB
Bit [5] Instruction tag RAM
Bit [4] Instruction data RAM
Bit [3] Main TLB
Bit [2] D outer RAM
Bit [1] Data tag RAM
Bit [0] Data data RAM
DIE_ID_1
DIE ID Data 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
die_id_31_0
R
Address:
Misc_RegisterBaseAddress + 0xa00
Type:
R
Reset:
0x0000 0000
Description:
DIE ID Data 1
[31:0] die_id_31_0: DIE ID bits [31,0]
DIE_ID_2
DIE ID Data 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
die_id_63_32
R
Address:
Misc_RegisterBaseAddress + 0xa04
Type:
R
Reset:
0x0000 0000
Description:
DIE ID Data 2
[31:0] die_id_63_32: DIE ID bits [63,32]
Doc ID 018904 Rev 3
289/1728
System configuration registers (MISC)
RM0089
DIE_ID_3
DIE ID Data 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
die_id_95_64
R
Address:
Misc_RegisterBaseAddress + 0xa08
Type:
R
Reset:
0x0000 0000
Description:
DIE ID Data 3
[31:0] die_id_95_64: DIE ID bits [95,64]
DIE_ID_4
DIE ID Data 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
die_id_127_96
R
Address:
Misc_RegisterBaseAddress + 0xa0C
Type:
R
Reset:
0x0000 0000
Description:
DIE ID Data 4
[31:0] die_id_127_96: DIE ID bits [127,96]
AXI_CACHE_USER_CTRL_0
Cache and User Info for PCIE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
awuser
awcache
RESERVED
aruser
arcache
R
R/W
R/W
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc00
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for PCIE0
0
[24:20] awuser: AWUSER bus control for ACP connection
[19:16] awcache: AWCACHE bus control
[8:4] aruser: ARUSER bus control for ACP connection
[3:0] arcache: ARCACHE bus control
AXI_CACHE_USER_CTRL_1
Cache and User Info for PCIE1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
awuser
awcache
RESERVED
aruser
arcache
R
R/W
R/W
R
R/W
R/W
Address:
290/1728
Misc_RegisterBaseAddress + 0xc04
Doc ID 018904 Rev 3
0
RM0089
System configuration registers (MISC)
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for PCIE1
[24:20] awuser: AWUSER bus control for ACP connection
[19:16] awcache: AWCACHE bus control
[8:4] aruser: ARUSER bus control for ACP connection
[3:0] arcache: ARCACHE bus control
AXI_CACHE_USER_CTRL_2
Cache and User Info for PCIE2/SATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
awuser
awcache
RESERVED
aruser
arcache
R
R/W
R/W
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc08
Type:
R/W
Reset:
0x0000 0000
Description:
0
Cache and User Info for PCIE2/SATA
[24:20] awuser: AWUSER bus control for ACP connection
[19:16] awcache: AWCACHE bus control
[8:4] aruser: ARUSER bus control for ACP connection
[3:0] arcache: ARCACHE bus control
AXI_CACHE_USER_CTRL_3
Cache and User Info for GMAC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
awuser
awcache
RESERVED
aruser
arcache
R
R/W
R/W
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc0c
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for GMAC
0
[24:20] awuser: AWUSER bus control for ACP connection
[19:16] awcache: AWCACHE bus control
[8:4] aruser: ARUSER bus control for ACP connection
[3:0] arcache: ARCACHE bus control
Doc ID 018904 Rev 3
291/1728
System configuration registers (MISC)
RM0089
AHB_CACHE_USER_CTRL_0
Cache and User Info for DMAC0
6
5
4
3
2
1
acache
7
auser
8
RESERVED
9
ipn_misc
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc10
Type:
R/W
Reset:
0x0000 0000
Description:
0
Cache and User Info for DMAC0
[31] ipn_misc: If 0 => hprot comes from the IP
If 1 => enable full MISC controllability
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
AHB_CACHE_USER_CTRL_1
Cache and User Info for DMAC1
6
5
4
3
2
1
acache
7
auser
8
RESERVED
9
ipn_misc
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc14
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for DMAC1
0
[31] ipn_misc:
If 0 => hprot comes from the IP
If 1 => enable full MISC controllability
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
AHB_CACHE_USER_CTRL_2
Cache and User Info for UOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
2
1
auser
acache
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc18
Type:
R/W
Reset:
0x0000 0000
292/1728
9
RESERVED
Doc ID 018904 Rev 3
0
RM0089
Description:
System configuration registers (MISC)
Cache and User Info for UOC
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
AHB_CACHE_USER_CTRL_3
Cache and User Info for UHC0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
auser
acache
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc1c
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for UHC0
0
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
AHB_CACHE_USER_CTRL_4
Cache and User Info for UHC1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
auser
acache
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc20
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for UHC1
0
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
AHB_CACHE_USER_CTRL_5
Cache and User Info for C3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
2
1
auser
acache
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc24
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
0
Cache and User Info for C3
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
Doc ID 018904 Rev 3
293/1728
System configuration registers (MISC)
RM0089
AHB_CACHE_USER_CTRL_6
Cache and User Info for MCIF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
auser
acache
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc28
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for MCIF
0
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
AHB_CACHE_USER_CTRL_7
Cache and User Info for EXPI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
auser
acache
R
R/W
R/W
Address:
Misc_RegisterBaseAddress + 0xc2c
Type:
R/W
Reset:
0x0000 0000
Description:
Cache and User Info for EXPI
0
[8:4] auser: AUSER bus control for ACP connection
[3:0] acache: ACACHE bus control
MIPHY_TEST
MIPHY debug register
5
4
3
2
1
0
p1_tst_spdsel
6
p1_tst_lspd
7
p1_tst_pci
8
R
R/
W
R/
W
R/W
Address:
Misc_RegisterBaseAddress + 0x1000
Type:
R/W
Reset:
0x0000 0000
Description:
MIPHY debug register
[3] p1_tst_pci: Reserved . Not Used
[2] p1_tst_lspd: Reserved . Not Used
[1:0] p1_tst_spdsel: Reserved . Not Used
294/1728
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
System configuration registers (MISC)
USB_TEST
USB debug register
6
5
4
3
2
1
0
uhc1_sim_mode
7
uhc2_sim_mode
8
uotg_sim_mode
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/
W
R/
W
Address:
Misc_RegisterBaseAddress + 0x1004
Type:
R/W
Reset:
0x0000 0000
Description:
USB debug register
[3:2] uotg_sim_mode: Reserved . Do not write
[1:0] uhc[2:1]_sim_mode: Reserved . Do not write
MISC_CFG
MISC configuration register
8
7
6
5
4
3
2
1
0
read_wait
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
Address:
Misc_RegisterBaseAddress + 0x1008
Type:
R/W
Reset:
0x0000 0000
Description:
MISC configuration register
[0] read_wait: Wait state enabled on APB read operation
0 : no wait states on APB read operation
1 : three clock pulses wait states enabled on APB read operation
Doc ID 018904 Rev 3
295/1728
Pad configuration
The following figure shows the mechanism used to configure the SPEAr1340 pads using the miscellaneous registers. Refer to
Table 53 below for a complete description of the configuration options.
Figure 1.
Shared pad configuration
1’b1
1
en_from_core_SHARED_SIGNAL
0
ENABLE
1
0
0
0
ENABLE
1
Core
1
ENABLE
PAD_EN
PAD_IN
TOP MUX
Doc ID 018904 Rev 3
PAD_OUT
A
B
C
IP1
System configuration registers (MISC)
296/1728
5.3
OUTPUT
out_from_core_SHARED_SIGNAL
1
0
0
0
1
1
OUTPUT
OUTPUT
IP2
A
B
1
i_out_from_core_SHARED_SIGNAL
1
1’b0
1
TEST[4:0]
1’b0
INPUT
INPUT
Power
Always-on
A
B
RM0089
A: MISC : PAD_SHARED_IP_EN_x : shared_ip_en[31:0]
B: MISC : PAD_FUNCTION_EN_x : ip_en
C: MISC : PAD_FUNCTION_EN_1[0] : dir_en
0
0
INPUT
XGPIO
0
1’b0
Pad configuration options
Shared IP pins
GPIO/
XGPIO
RM0089
Table 53.
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
PUP PDN IO
0
0
x :Not allowed
0
1
1 :PU activated
1
0
0 :PD activated
1
1
x :PU/PD disabled
00: 4mA
01: 6mA
10: 8 mA
11: 10 mA
Default
Default
0: nominal
1 : fast
Default
BOOTSTRAP
_CFG
Default
0: pad routed to GPIO/
XGPIO
1: pad routed to shared IP
Pins
0: pad routed to IP pin 1
function
1: pad routed to IP pin 2
function
Doc ID 018904 Rev 3
FSMC_IO8
KBD_ROW0
1[0]
1[0]
PU
1[1:0]
1
1[0]
1
1[1]
1
1[0]
0
XGPIO1
FSMC_IO9
KBD_ROW1
1[1]
1[1]
PU
1[1:0]
1
1[0]
1
1[2]
1
1[0]
0
XGPIO2
FSMC_IO10
KBD_ROW2
1[2]
1[2]
PU
1[1:0]
1
1[0]
1
1[3]
1
1[0]
0
XGPIO3
FSMC_IO11
KBD_ROW3
1[3]
1[3]
PU
1[1:0]
1
1[0]
1
1[4]
1
1[0]
0
XGPIO4
FSMC_IO12
KBD_ROW4
1[4]
1[4]
PU
1[1:0]
1
1[0]
1
1[5]
1
1[0]
0
XGPIO5
FSMC_IO13
KBD_ROW5
1[5]
1[5]
PU
1[3:2]
1
1[1]
1
1[6]
1
1[0]
0
XGPIO6
FSMC_IO14
KBD_COL0
1[6]
1[6]
PU
1[3:2]
1
1[1]
1
1[7]
1
1[0]
0
XGPIO7
FSMC_IO15
KBD_COL1
1[7]
1[7]
PU
1[3:2]
1
1[1]
1
1[8]
1
1[0]
0
GPIO_A0
FSMC_CE1n
KBD_COL2
1[8]
1[8]
PU
1[3:2]
1
1[1]
1
1[9]
1
1[0]
0
GPIO_A1
FSMC_RWPR
T1n
KBD_COL3
1[9]
1[9]
PU
1[3:2]
1
1[1]
1
1[10]
1
1[0]
0
GPIO_A2
FSMC_RSTP
WDWN1
KBD_COL4
1[10]
1[10]
PU
1[3:2]
1
1[1]
1
1[11]
1
1[0]
0
GPIO_A3
UART0_RTSn
GPT1_TMR_C
PT2
1[11]
1[11]
PU
1[5:4]
1
1[2]
1
1[12]
1
1[1]
0
GPIO_A4
UART0_RIn
GPT0_TMR_C
PT2
1[12]
1[12]
PU
1[5:4]
1
1[2]
1
1[13]
1
1[1]
0
GPIO_A5
UART0_DSRn
GPT1_TMR_C
LK1
1[13]
1[13]
PU
1[5:4]
1
1[2]
1
1[14]
1
1[1]
0
GPIO_A6
UART0_DTRn
GPT1_TMR_C
PT1
1[14]
1[14]
PU
1[5:4]
1
1[2]
1
1[15]
1
1[1]
0
System configuration registers (MISC)
297/1728
XGPIO0
STRAP4/5/6
configuration
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
BOOTSTRAP
_CFG
Default
Doc ID 018904 Rev 3
GPIO_A7
UART0_DCDn
GPT1_TMR_C
LK2
1[15]
1[15]
PU
1[5:4]
1
1[2]
1
1[16]
1
1[1]
0
GPIO_B0
UART0_CTSn
GPT0_TMR_C
LK1
1[16]
1[16]
PU
1[5:4]
1
1[2]
1
1[17]
1
1[1]
0
GPIO_B1
PWM2
KBD_COL5
1[17]
1[17]
PU
1[7:6]
1
1[3]
1
1[18]
1
1[2]
0
GPIO_B2
I2C1_SDA
1[18]
1[18]
PU
1[9:8]
1
1[4]
1
1[19]
1
na
0
GPIO_B3
SPDIF_IN
1[19]
1[19]
PU
1[11:10]
1
1[5]
1
1[20]
1
na
0
GPIO_B4
VIP_B15
CAM4_VSYNC 1[20]
1[20]
PU
1[13:12]
1
1[6]
1
1[21]
1
1[6]
0
GPIO_B5
PWM3
GPT0_TMR_C
PT1
1[21]
1[21]
PU
1[15:14]
1
1[7]
1
1[22]
1
1[3]
0
GPIO_B6
PWM4
GPT0_TMR_C
LK2
1[22]
1[22]
PU
1[15:14]
1
1[7]
1
1[23]
1
1[4]
0
GPIO_B7
I2C1_SCL
1[23]
1[23]
PU
1[17:16]
1
1[8]
1
1[24]
1
na
0
XGPIO24
PWM1
SSP_SS1n
1[24]
1[24]
PU
1[19:18]
1
1[9]
1
1[25]
0
1[5]
0
XGPIO25
VIP_B10
CAM4_PIXCL
K
1[25]
1[25]
PU
1[21:20]
1
1[10]
1
1[26]
0
1[6]
0
XGPIO26
VIP_B11
CAM4_HSYNC 1[26]
1[26]
PU
1[21:20]
1
1[10]
1
1[27]
0
1[6]
0
XGPIO27
VIP_B12
CAM4_DATA0
1[27]
1[27]
PU
1[21:20]
1
1[10]
1
1[28]
0
1[6]
0
XGPIO28
VIP_B13
CAM4_DATA1
1[28]
1[28]
PU
1[21:20]
1
1[10]
1
1[29]
0
1[6]
0
XGPIO29
VIP_B14
CAM4_DATA2
1[29]
1[29]
PU
1[21:20]
1
1[10]
1
1[30]
0
1[6]
0
STRAP5
XGPIO30
VIP_B9
CAM4_DATA3
1[30]
1[30]
PU
1[23:22]
1
1[11]
1
1[31]
0
1[6]
0
STRAP6
XGPIO31
VIP_B8
CAM4_DATA
1[31]
1[31]
PU
1[23:22]
1
1[11]
1
2[0]
0
1[6]
0
XGPIO32
VIP_G15
CAM4_DATA6
2[0]
2[0]
PU
1[23:22]
1
1[11]
1
2[1]
1
1[6]
0
XGPIO33
VIP_G14
CAM4_DATA5
2[1]
2[1]
PU
1[23:22]
1
1[11]
1
2[2]
1
1[6]
0
XGPIO34
VIP_G13
CAM4_DATA4
2[2]
2[2]
PU
1[23:22]
1
1[11]
1
2[3]
1
1[6]
0
System configuration registers (MISC)
298/1728
Table 53.
STRAP4
RM0089
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
RM0089
Table 53.
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
Doc ID 018904 Rev 3
XGPIO35
VIP_G12
2[3]
2[3]
PU
1[25:24]
1
1[12]
1
2[4]
1
na
0
XGPIO36
VIP_B4
2[4]
2[4]
PU
1[25:24]
1
1[12]
1
2[5]
1
na
0
XGPIO37
VIP_B3
2[5]
2[5]
PU
1[25:24]
1
1[12]
1
2[6]
1
na
0
XGPIO38
VIP_R4
2[6]
2[6]
PU
1[25:24]
1
1[12]
1
2[7]
1
na
0
XGPIO39
VIP_R3
2[7]
2[7]
PU
1[25:24]
1
1[12]
1
2[8]
1
1[7]
0
XGPIO40
VIP_G11
2[8]
2[8]
PU
1[27:26]
1
1[13]
1
2[9]
1
na
0
CAM3_PIXCL
K
BOOTSTRAP
_CFG
VIP_B5
2[9]
2[9]
PU
1[27:26]
1
1[13]
1
2[10]
1
na
0
XGPIO42
VIP_B2
2[10]
2[10]
PU
1[27:26]
1
1[13]
1
2[11]
1
na
0
XGPIO43
VIP_R5
2[11]
2[11]
PU
1[27:26]
1
1[13]
1
2[12]
1
na
0
XGPIO44
VIP_R2
CAM3_HSYNC 2[12]
2[12]
PU
1[27:26]
1
1[13]
1
2[13]
1
1[7]
0
XGPIO45
VIP_G10
CAM3_DATA7
2[13]
2[13]
PU
1[29:28]
1
1[14]
1
2[14]
1
1[7]
0
XGPIO46
VIP_B6
CAM3_DATA5
2[14]
2[14]
PU
1[29:28]
1
1[14]
1
2[15]
1
1[7]
0
XGPIO47
VIP_B1
CAM3_DATA3
2[15]
2[15]
PU
1[29:28]
1
1[14]
1
2[16]
1
1[7]
0
XGPIO48
VIP_R6
CAM3_DATA0
2[16]
2[16]
PU
1[29:28]
1
1[14]
1
2[17]
1
1[7]
0
XGPIO49
VIP_R1
CAM3_VSYNC 2[17]
2[17]
PU
1[29:28]
1
1[14]
1
2[18]
1
1[7]
0
XGPIO50
VIP_G9
CAM3_DATA6
2[18]
2[18]
PU
1[31:30]
1
1[15]
1
2[19]
1
1[7]
0
XGPIO51
VIP_B7
CAM3_DATA4
2[19]
2[19]
PU
1[31:30]
1
1[15]
1
2[20]
1
1[7]
0
XGPIO52
VIP_B0
CAM3_DATA2
2[20]
2[20]
PU
1[31:30]
1
1[15]
1
2[21]
1
1[7]
0
XGPIO53
VIP_R7
CAM3_DATA1
2[21]
2[21]
PU
1[31:30]
1
1[15]
1
2[22]
1
1[7]
0
XGPIO54
VIP_R0
CAM2_PIXCL
K
2[22]
2[22]
PU
1[31:30]
1
1[15]
1
2[23]
1
1[8]
0
XGPIO55
VIP_G8
CAM2_DATA7
2[23]
2[23]
PU
2[1:0]
1
1[16]
1
2[24]
1
1[8]
0
XGPIO56
VIP_R8
CAM2_DATA5
2[24]
2[24]
PU
2[1:0]
1
1[16]
1
2[25]
1
1[8]
0
System configuration registers (MISC)
299/1728
XGPIO41
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
XGPIO57
VIP_G7
CAM2_DATA3
2[25]
2[25]
PU
2[1:0]
1
1[16]
1
2[26]
1
1[8]
0
XGPIO58
VIP_G0
CAM2_DATA0
2[26]
2[26]
PU
2[1:0]
1
1[16]
1
2[27]
1
1[8]
0
Doc ID 018904 Rev 3
VIP_DE
CAM2_HSYNC 2[27]
2[27]
PU
2[1:0]
1
1[16]
1
2[28]
1
1[8]
0
XGPIO60
VIP_R15
CAM2_DATA6
2[28]
2[28]
PU
2[3:2]
1
1[17]
1
2[29]
1
1[8]
0
XGPIO61
VIP_R9
CAM2_DATA4
2[29]
2[29]
PU
2[3:2]
1
1[17]
1
2[30]
1
1[8]
0
XGPIO62
VIP_G6
CAM2_DATA2
2[30]
2[30]
PU
2[3:2]
1
1[17]
1
2[31]
1
1[8]
0
XGPIO63
VIP_G1
CAM2_DATA1
2[31]
2[31]
PU
2[3:2]
1
1[17]
1
3[0]
1
1[8]
0
XGPIO64
VIP_VSYNC
CAM2_VSYNC 3[0]
3[0]
PU
2[3:2]
1
1[17]
1
3[1]
1
1[8]
0
XGPIO65
VIP_R14
CAM1_DATA7
3[1]
3[1]
PU
2[5:4]
1
1[18]
1
3[2]
1
1[9]
0
XGPIO66
VIP_R10
CAM1_DATA4
3[2]
3[2]
PU
2[5:4]
1
1[18]
1
3[3]
1
1[9]
0
XGPIO67
VIP_G5
CAM1_DATA2
3[3]
3[3]
PU
2[5:4]
1
1[18]
1
3[4]
1
1[9]
0
XGPIO68
VIP_G2
CAM1_DATA0
3[4]
3[4]
PU
2[5:4]
1
1[18]
1
3[5]
1
1[9]
0
XGPIO69
VIP_PIXCLK
CAM1_PIXCL
K
3[5]
3[5]
PU
2[5:4]
1
1[18]
1
3[6]
1
1[9]
0
XGPIO70
VIP_R13
CAM1_DATA6
3[6]
3[6]
PU
2[7:6]
1
1[19]
1
3[7]
1
1[9]
0
XGPIO71
VIP_R11
CAM1_DATA3
3[7]
3[7]
PU
2[7:6]
1
1[19]
1
3[8]
1
1[9]
0
XGPIO72
VIP_G4
CAM1_DATA1
3[8]
3[8]
PU
2[7:6]
1
1[19]
1
3[9]
1
1[9]
0
XGPIO73
VIP_G3
CAM1_VSYNC 3[9]
3[9]
PU
2[7:6]
1
1[19]
1
3[10]
1
1[9]
0
XGPIO74
VIP_HSYNC
CAM1_HSYNC 3[10]
3[10]
PU
2[7:6]
1
1[19]
1
3[11]
1
1[9]
0
XGPIO75
VIP_R12
CAM1_DATA5
3[11]
3[11]
PU
2[7:6]
1
1[19]
1
3[12]
1
1[9]
0
XGPIO76
SMI_DATAOUT
3[12]
3[12]
PU
2[9:8]
1
1[20]
1
3[13]
1
na
0
XGPIO77
SMI_DATAIN
3[13]
3[13]
PU
2[9:8]
1
1[20]
1
3[14]
1
na
0
XGPIO78
SMI_CLK
3[14]
3[14]
PU
2[9:8]
1
1[20]
1
3[15]
1
na
0
RM0089
XGPIO59
BOOTSTRAP
_CFG
System configuration registers (MISC)
300/1728
Table 53.
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
RM0089
Table 53.
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
Doc ID 018904 Rev 3
SMI_CS1n
3[15]
3[15]
PU
2[9:8]
1
1[20]
1
3[16]
1
na
0
XGPIO80
SSP_SS0n
3[16]
3[16]
PU
2[11:10]
1
1[21]
1
3[17]
1
na
0
XGPIO81
SSP_MOSI
3[17]
3[17]
PU
2[11:10]
1
1[21]
1
3[18]
1
na
0
XGPIO82
SSP_MISO
3[18]
3[18]
PU
2[11:10]
1
1[21]
1
3[19]
1
na
0
XGPIO83
SSP_SCK
3[19]
3[19]
PU
2[11:10]
1
1[21]
1
3[20]
1
na
0
XGPIO84
SMI_CS0n
3[20]
3[20]
PU
2[13:12]
1
1[22]
1
3[21]
1
na
0
XGPIO85
TOUCH_XY_S
EL
3[21]
3[21]
PU
2[15:14]
1
1[23]
1
3[22]
1
1[10]
0
XGPIO86
UART0_TXD
3[22]
3[22]
PU
2[17:16]
1
1[24]
1
3[23]
1
na
0
XGPIO87
UART0_RXD
3[23]
3[23]
PU
2[17:16]
1
1[24]
1
3[24]
1
na
0
XGPIO88
UART1_TXD
3[24]
3[24]
PU
2[17:16]
1
1[24]
1
3[25]
1
na
0
XGPIO89
UART1_RXD
3[25]
3[25]
PU
2[17:16]
1
1[24]
1
3[26]
1
na
0
XGPIO90
I2S_IN_DATA3
3[26]
3[26]
PU
2[19:18]
1
1[25]
1
3[27]
1
na
0
XGPIO91
I2S_IN_DATA2
3[27]
3[27]
PU
2[19:18]
1
1[25]
1
3[28]
1
na
0
XGPIO92
I2S_IN_DATA1
3[28]
3[28]
PU
2[19:18]
1
1[25]
1
3[29]
1
na
0
XGPIO93
I2S_IN_DATA0
3[29]
3[29]
PU
2[19:18]
1
1[25]
1
3[30]
1
na
0
XGPIO94
I2S_IN_WS
3[30]
3[30]
PU
2[19:18]
1
1[25]
1
3[31]
1
na
0
XGPIO95
I2S_OUT_DAT
A2
3[31]
3[31]
PU
2[21:20]
1
1[26]
1
4[0]
1
na
0
XGPIO96
I2S_OUT_DAT
A0
4[0]
4[0]
PU
2[21:20]
1
1[26]
1
4[1]
1
1[13]
0
XGPIO97
I2S_OUT_BIT
CLK
4[1]
4[1]
PU
2[21:20]
1
1[26]
1
4[2]
1
1[13]
0
XGPIO98
I2S_OUT_WS
4[2]
4[2]
PU
2[21:20]
1
1[26]
1
4[3]
1
1[13]
0
System configuration registers (MISC)
301/1728
XGPIO79
SSP_SS2n
BOOTSTRAP
_CFG
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
Doc ID 018904 Rev 3
I2S_IN_BITCL
K
4[3]
4[3]
PU
2[21:20]
1
1[26]
1
4[4]
1
1[13]
0
XGPIO100
I2S_OUT_DAT
A3
4[4]
4[4]
PU
2[23:22]
1
1[27]
1
4[5]
1
1[13]
0
XGPIO101
I2S_OUT_DAT
A1
4[5]
4[5]
PU
2[23:22]
1
1[27]
1
4[6]
1
1[13]
0
XGPIO102
I2S_OUT_REF
CLK
4[6]
4[6]
PU
2[23:22]
1
1[27]
1
4[7]
1
1[13]
0
XGPIO103
I2S_OUT_OVR
SAMP_CLK
4[7]
4[7]
PU
2[23:22]
1
1[27]
1
4[8]
1
1[13]
0
XGPIO104
MAC_TXCLK
4[8]
4[8]
PU
2[25:24]
1
1[28]
1
4[9]
1
na
0
XGPIO105
MAC_TXD0
4[9]
4[9]
PU
2[25:24]
1
1[28]
1
4[10]
1
na
0
XGPIO106
MAC_TXD1
4[10]
4[10]
PU
2[25:24]
1
1[28]
1
4[11]
1
na
0
XGPIO107
MAC_TXD2
4[11]
4[11]
PU
2[25:24]
1
1[28]
1
4[12]
1
na
0
XGPIO108
MAC_GTXCLK
125
4[12]
4[12]
PU
2[25:24]
1
1[28]
1
4[13]
1
na
0
XGPIO109
MAC_TXD3
4[13]
4[13]
PU
2[27:26]
1
1[29]
1
4[14]
1
na
0
XGPIO110
MAC_TXD4
4[14]
4[14]
PU
2[27:26]
1
1[29]
1
4[15]
1
na
0
XGPIO111
MAC_TXD5
4[15]
4[15]
PU
2[27:26]
1
1[29]
1
4[16]
1
na
0
XGPIO112
MAC_RXD0
4[16]
4[16]
PU
2[27:26]
1
1[29]
1
4[17]
1
na
0
XGPIO113
MAC_GTXCLK
4[17]
4[17]
PU
2[27:26]
1
1[29]
1
4[18]
1
na
0
XGPIO114
MAC_RXD1
4[18]
4[18]
PU
2[29:28]
1
1[30]
1
4[19]
1
na
0
XGPIO115
MAC_TXD6
4[19]
4[19]
PU
2[29:28]
1
1[30]
1
4[20]
1
na
0
XGPIO116
MAC_TXD7
4[20]
4[20]
PU
2[29:28]
1
1[30]
1
4[21]
1
na
0
XGPIO117
MAC_RXCLK
4[21]
4[21]
PU
2[29:28]
1
1[30]
1
4[22]
1
na
0
RM0089
XGPIO99
BOOTSTRAP
_CFG
System configuration registers (MISC)
302/1728
Table 53.
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
RM0089
Table 53.
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
BOOTSTRAP
_CFG
Default
Doc ID 018904 Rev 3
MAC_RXD2
4[22]
4[22]
PU
2[29:28]
1
1[30]
1
4[23]
1
na
0
XGPIO119
MAC_RXD3
4[23]
4[23]
PU
2[31:30]
1
1[31]
1
4[24]
1
na
0
XGPIO120
MAC_RXD4
4[24]
4[24]
PU
3[1:0]
1
2[0]
1
4[25]
1
na
0
XGPIO121
MAC_RXD5
4[25]
4[25]
PU
3[1:0]
1
2[0]
1
4[26]
1
na
0
XGPIO122
MAC_MDC
4[26]
4[26]
PU
3[3:2]
1
2[1]
1
4[27]
1
na
0
XGPIO123
MAC_MDIO
4[27]
4[27]
PU
3[3:2]
1
2[1]
1
4[28]
1
na
0
XGPIO124
MAC_RXD6
4[28]
4[28]
PU
3[5:4]
1
2[2]
1
4[29]
1
na
0
XGPIO125
MAC_RXD7
4[29]
4[29]
PU
3[5:4]
1
2[2]
1
4[30]
1
na
0
XGPIO126
MAC_COL
4[30]
4[30]
PU
3[5:4]
1
2[2]
1
4[31]
1
na
0
XGPIO127
MAC_RXDV
4[31]
4[31]
PU
3[7:6]
1
2[3]
1
5[0]
1
na
0
XGPIO128
MAC_RXER
5[0]
5[0]
PU
3[7:6]
1
2[3]
1
5[1]
1
na
0
XGPIO129
MAC_TXEN
5[1]
5[1]
PU
3[7:6]
1
2[3]
1
5[2]
1
na
0
XGPIO130
MAC_TXER
5[2]
5[2]
PU
3[7:6]
1
2[3]
1
5[3]
1
na
0
XGPIO131
MAC_CRS
5[3]
5[3]
PU
3[7:6]
1
2[3]
1
5[4]
1
na
0
XGPIO132
SSP_SS3n
5[4]
5[4]
PU
3[9:8]
1
2[4]
1
5[5]
1
1[13]
0
XGPIO133
I2C0_SDA
5[5]
5[5]
PU
3[11:10]
1
2[5]
1
5[6]
1
na
0
XGPIO134
I2C0_SCL
5[6]
5[6]
PU
3[11:10]
1
2[5]
1
5[7]
1
na
0
XGPIO135
CEC0
5[7]
5[7]
PU
3[13:12]
1
2[6]
1
5[8]
1
1[13]
0
XGPIO136
CEC1
5[8]
5[8]
PU
3[13:12]
1
2[6]
1
5[9]
1
1[13]
0
XGPIO137
SPDIF_OUT
5[9]
5[9]
PU
3[15:14]
1
2[7]
1
5[10]
1
1[13]
0
XGPIO138
LCD_B6
5[10]
5[10]
PU
3[17:16]
1
2[8]
1
5[11]
1
1[13]
0
XGPIO139
LCD_B5
5[11]
5[11]
PU
3[17:16]
1
2[8]
1
5[12]
1
1[13]
0
XGPIO140
LCD_B4
5[12]
5[12]
PU
3[17:16]
1
2[8]
1
5[13]
1
1[13]
0
System configuration registers (MISC)
303/1728
XGPIO118
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
Doc ID 018904 Rev 3
LCD_B3
5[13]
5[13]
PU
3[17:16]
1
2[8]
1
5[14]
1
1[13]
0
XGPIO142
LCD_B2
5[14]
5[14]
PU
3[17:16]
1
2[8]
1
5[15]
1
1[13]
0
XGPIO143
LCD_XR6
5[15]
5[15]
PU
3[19:18]
1
2[9]
1
5[16]
1
1[13]
0
XGPIO144
LCD_B7
5[16]
5[16]
PU
3[19:18]
1
2[9]
1
5[17]
1
1[13]
0
XGPIO145
LCD_B0
5[17]
5[17]
PU
3[19:18]
1
2[9]
1
5[18]
1
1[13]
0
XGPIO146
LCD_B1
5[18]
5[18]
PU
3[19:18]
1
2[9]
1
5[19]
1
1[13]
0
XGPIO147
LCD_G3
5[19]
5[19]
PU
3[19:18]
1
2[9]
1
5[20]
1
1[13]
0
XGPIO148
LCD_XR5
5[20]
5[20]
PU
3[21:20]
1
2[10]
1
5[21]
1
1[13]
0
XGPIO149
LCD_XR2
5[21]
5[21]
PU
3[21:20]
1
2[10]
1
5[22]
1
1[13]
0
XGPIO150
LCD_G7
5[22]
5[22]
PU
3[21:20]
1
2[10]
1
5[23]
1
1[13]
0
XGPIO151
LCD_G5
5[23]
5[23]
PU
3[21:20]
1
2[10]
1
5[24]
1
1[13]
0
XGPIO152
LCD_G2
5[24]
5[24]
PU
3[21:20]
1
2[10]
1
5[25]
1
1[13]
0
XGPIO153
LCD_XR4
5[25]
5[25]
PU
3[23:22]
1
2[11]
1
5[26]
1
1[13]
0
XGPIO154
LCD_XR1
5[26]
5[26]
PU
3[23:22]
1
2[11]
1
5[27]
1
1[13]
0
XGPIO155
LCD_G6
5[27]
5[27]
PU
3[23:22]
1
2[11]
1
5[28]
1
1[13]
0
XGPIO156
LCD_G4
5[28]
5[28]
PU
3[23:22]
1
2[11]
1
5[29]
1
1[13]
0
XGPIO157
LCD_G1
5[29]
5[29]
PU
3[23:22]
1
2[11]
1
5[30]
1
1[13]
0
XGPIO158
LCD_XR3
ARM_TRCCLK 5[30]
5[30]
PU
3[25:24]
1
2[12]
1
5[31]
1
1[12]
0
XGPIO159
LCD_XR0
ARM_TRCCTL 5[31]
5[31]
PU
3[25:24]
1
2[12]
1
6[0]
1
1[12]
0
XGPIO160
LCD_G0
ARM_TRCDAT
A0
6[0]
6[0]
PU
3[25:24]
1
2[12]
1
6[1]
1
1[12]
0
XGPIO161
LCD_R5
ARM_TRCDAT
A1
6[1]
6[1]
PU
3[25:24]
1
2[12]
1
6[2]
1
1[12]
0
RM0089
XGPIO141
BOOTSTRAP
_CFG
System configuration registers (MISC)
304/1728
Table 53.
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
RM0089
Table 53.
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
BOOTSTRAP
_CFG
Default
Doc ID 018904 Rev 3
LCD_R2
ARM_TRCDAT
A2
6[2]
6[2]
PU
3[25:24]
1
2[12]
1
6[3]
1
1[12]
0
XGPIO163
LCD_DE
ARM_TRCDAT
A3
6[3]
6[3]
PU
3[27:26]
1
2[13]
1
6[4]
1
1[12]
0
XGPIO164
LCD_PE
ARM_TRCDAT
A4
6[4]
6[4]
PU
3[27:26]
1
2[13]
1
6[5]
1
1[12]
0
XGPIO165
LCD_R7
ARM_TRCDAT
A5
6[5]
6[5]
PU
3[27:26]
1
2[13]
1
6[6]
1
1[12]
0
XGPIO166
LCD_R4
ARM_TRCDAT
A6
6[6]
6[6]
PU
3[27:26]
1
2[13]
1
6[7]
1
1[12]
0
XGPIO167
LCD_R1
ARM_TRCDAT
A7
6[7]
6[7]
PU
3[27:26]
1
2[13]
1
6[8]
1
1[12]
0
XGPIO168
LCD_VSYNC
ARM_TRCDAT
A8
6[8]
6[8]
PU
3[29:28]
1
2[14]
1
6[9]
1
1[12]
0
XGPIO169
LCD_PCLK
ARM_TRCDAT
A9
6[9]
6[9]
PU
3[29:28]
1
2[14]
1
6[10]
1
1[12]
0
XGPIO170
LCD_R6
ARM_TRCDAT
A10
6[10]
6[10]
PU
3[29:28]
1
2[14]
1
6[11]
1
1[12]
0
XGPIO171
LCD_R3
ARM_TRCDAT
A11
6[11]
6[11]
PU
3[29:28]
1
2[14]
1
6[12]
1
1[12]
0
XGPIO172
LCD_R0
ARM_TRCDAT
A12
6[12]
6[12]
PU
3[29:28]
1
2[14]
1
6[13]
1
1[12]
0
XGPIO173
LCD_HSYNC
ARM_TRCDAT
A13
6[13]
6[13]
PU
3[31:30]
1
2[15]
1
6[14]
1
1[12]
0
XGPIO174
LCD_XR7
ARM_TRCDAT
A14
6[14]
6[14]
PU
3[31:30]
1
2[15]
1
6[15]
1
1[12]
0
XGPIO175
LCD_XG0
ARM_TRCDAT
A15
6[15]
6[15]
PU
3[31:30]
1
2[15]
1
6[16]
1
1[12]
0
XGPIO176
LCD_XG1
ARM_TRCDAT
A16
6[16]
6[16]
PU
3[31:30]
1
2[15]
1
6[17]
1
1[12]
0
System configuration registers (MISC)
305/1728
XGPIO162
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
Doc ID 018904 Rev 3
LCD_XG2
ARM_TRCDAT
A17
6[17]
6[17]
PU
3[31:30]
1
2[15]
1
6[18]
1
1[12]
0
XGPIO178
LCD_LED_PW
M
ARM_TRCDAT
A18
6[18]
6[18]
PU
4[1:0]
1
2[16]
1
6[19]
1
1[12]
0
XGPIO179
LCD_XG3
ARM_TRCDAT
A19
6[19]
6[19]
PU
4[1:0]
1
2[16]
1
6[20]
1
1[12]
0
XGPIO180
LCD_XG4
ARM_TRCDAT
A20
6[20]
6[20]
PU
4[1:0]
1
2[16]
1
6[21]
1
1[12]
0
XGPIO181
LCD_XG5
ARM_TRCDAT
A21
6[21]
6[21]
PU
4[1:0]
1
2[16]
1
6[22]
1
1[12]
0
XGPIO182
LCD_XG6
ARM_TRCDAT
A22
6[22]
6[22]
PU
4[1:0]
1
2[16]
1
6[23]
1
1[12]
0
XGPIO183
LCD_XG7
ARM_TRCDAT
A23
6[23]
6[23]
PU
4[3:2]
1
2[17]
1
6[24]
1
1[12]
0
XGPIO184
LCD_XB0
ARM_TRCDAT
A24
6[24]
6[24]
PU
4[3:2]
1
2[17]
1
6[25]
1
1[12]
0
XGPIO185
LCD_XB1
ARM_TRCDAT
A25
6[25]
6[25]
PU
4[3:2]
1
2[17]
1
6[26]
1
1[12]
0
XGPIO186
LCD_XB2
ARM_TRCDAT
A26
6[26]
6[26]
PU
4[3:2]
1
2[17]
1
6[27]
1
1[12]
0
XGPIO187
LCD_XB3
ARM_TRCDAT
A27
6[27]
6[27]
PU
4[3:2]
1
2[17]
1
6[28]
1
1[12]
0
XGPIO188
LCD_XB4
ARM_TRCDAT
A28
6[28]
6[28]
PU
4[5:4]
1
2[18]
1
6[29]
1
1[12]
0
XGPIO189
LCD_XB5
ARM_TRCDAT
A29
6[29]
6[29]
PU
4[5:4]
1
2[18]
1
6[30]
1
1[12]
0
XGPIO190
LCD_XB6
ARM_TRCDAT
A30
6[30]
6[30]
PU
4[5:4]
1
2[18]
1
6[31]
1
1[12]
0
XGPIO191
LCD_XB7
ARM_TRCDAT
A31
6[31]
6[31]
PU
4[5:4]
1
2[18]
1
7[0]
1
1[12]
0
RM0089
XGPIO177
BOOTSTRAP
_CFG
System configuration registers (MISC)
306/1728
Table 53.
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
XGPIO192
FSMC_AD25
XGPIO193
FSMC_AD20
XGPIO194
XGPIO195
RM0089
Table 53.
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
BOOTSTRAP
_CFG
Default
Doc ID 018904 Rev 3
7[0]
PU
4[7:6]
1
2[19]
1
7[1]
1
1[11]
0
MCIF_DATA15
7[1]
7[1]
PU
4[7:6]
1
2[19]
1
7[2]
1
1[11]
0
FSMC_AD21
MCIF_DATA14
7[2]
7[2]
PU
4[7:6]
1
2[19]
1
7[3]
1
1[11]
0
FSMC_AD22
MCIF_DATA13
7[3]
7[3]
PU
4[7:6]
1
2[19]
1
7[4]
1
1[11]
0
XGPIO196
FSMC_AD23
MCIF_DATA12
7[4]
7[4]
PU
4[7:6]
1
2[19]
1
7[5]
1
1[11]
0
XGPIO197
FSMC_AD24
MCIF_DATA11
7[5]
7[5]
PU
4[9:8]
1
2[20]
1
7[6]
1
1[11]
0
XGPIO198
FSMC_AD13
MCIF_nCS1
7[6]
7[6]
PU
4[9:8]
1
2[20]
1
7[7]
1
1[11]
0
XGPIO199
FSMC_AD14
MCIF_nDMAC
K_nWP
7[7]
7[7]
PU
4[9:8]
1
2[20]
1
7[8]
1
1[11]
0
XGPIO200
FSMC_AD15
MCIF_DATA10
7[8]
7[8]
PU
4[9:8]
1
2[20]
1
7[9]
1
1[11]
0
XGPIO201
FSMC_AD18
MCIF_DATA9
7[9]
7[9]
PU
4[9:8]
1
2[20]
1
7[10]
1
1[11]
0
XGPIO202
FSMC_AD19
MCIF_DATA8
7[10]
7[10]
PU
4[11:10]
1
2[21]
1
7[11]
1
1[11]
0
XGPIO203
FSMC_AD8
MCIF_nIOWR_
7[11]
nWE
7[11]
PU
4[11:10]
1
2[21]
1
7[12]
1
1[11]
0
XGPIO204
FSMC_AD9
MCIF_nRESE
T_CF
7[12]
7[12]
PU
4[11:10]
1
2[21]
1
7[13]
1
1[11]
0
XGPIO205
FSMC_AD10
MCIF_nCS0_n
CE
7[13]
7[13]
PU
4[11:10]
1
2[21]
1
7[14]
1
1[11]
0
XGPIO206
FSMC_AD11
MCIF_CF_INT
R
7[14]
7[14]
PU
4[11:10]
1
2[21]
1
7[15]
1
1[11]
0
XGPIO207
FSMC_AD12
MCIF_IORDY
7[15]
7[15]
PU
4[13:12]
1
2[22]
1
7[16]
1
1[11]
0
XGPIO208
FSMC_AD3
MCIF_nCE_S
D_MMC
7[16]
7[16]
PU
4[13:12]
1
2[22]
1
7[17]
1
1[11]
0
XGPIO209
FSMC_AD4
MCIF_nCD_C
F1
7[17]
7[17]
PU
4[13:12]
1
2[22]
1
7[18]
1
1[11]
0
System configuration registers (MISC)
307/1728
7[0]
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
Doc ID 018904 Rev 3
FSMC_AD5
MCIF_nCD_C
F2
7[18]
7[18]
PU
4[13:12]
1
2[22]
1
7[19]
1
1[11]
0
XGPIO211
FSMC_AD6
MCIF_DATA_D
IR
7[19]
7[19]
PU
4[13:12]
1
2[22]
1
7[20]
1
1[11]
0
XGPIO212
FSMC_AD7
MCIF_nIORD_
nRE
7[20]
7[20]
PU
4[13:12]
1
2[22]
1
7[21]
1
1[11]
0
XGPIO213
MCIF_ADDR0
_ALE
7[21]
7[21]
PU
4[15:14]
1
2[23]
1
7[22]
1
na
0
XGPIO214
MCIF_nCD_xD
7[22]
7[22]
PU
4[15:14]
1
2[23]
1
7[23]
1
na
0
XGPIO215
FSMC_AD0
MCIF_ADDR2
7[23]
7[23]
PU
4[17:16]
1
2[24]
1
7[24]
1
1[11]
0
XGPIO216
FSMC_AD1
MCIF_nCE_CF 7[24]
7[24]
PU
4[17:16]
1
2[24]
1
7[25]
1
1[11]
0
XGPIO217
FSMC_AD2
MCIF_nCE_xD
7[25]
7[25]
PU
4[17:16]
1
2[24]
1
7[26]
1
1[11]
0
XGPIO218
MCIF_SD_CM
D
7[26]
7[26]
PU
4[19:18]
1
2[25]
1
7[27]
1
na
0
XGPIO219
MCIF_LEDS
7[27]
7[27]
PU
4[19:18]
1
2[25]
1
7[28]
1
na
0
XGPIO220
MCIF_DATA1
7[28]
7[28]
PU
4[19:18]
1
2[25]
1
7[29]
1
na
0
XGPIO221
MCIF_DATA2
7[29]
7[29]
PU
4[19:18]
1
2[25]
1
7[30]
1
na
0
XGPIO222
MCIF_DATA3
7[30]
7[30]
PU
4[19:18]
1
2[25]
1
7[31]
1
na
0
XGPIO223
MCIF_DATA6
7[31]
7[31]
PU
4[21:20]
1
2[26]
1
8[0]
1
na
0
XGPIO224
MCIF_DATA7
8[0]
8[0]
PU
4[21:20]
1
2[26]
1
8[1]
1
na
0
XGPIO225
MCIF_ADDR1
_CLE_CLK
8[1]
8[1]
PU
4[21:20]
1
2[26]
1
8[2]
1
na
0
XGPIO226
MCIF_nCD_S
D_MMC
8[2]
8[2]
PU
4[21:20]
1
2[26]
1
8[3]
1
na
0
XGPIO227
MCIF_DMARQ
_RnB_WP
8[3]
8[3]
PU
4[21:20]
1
2[26]
1
8[4]
1
na
0
RM0089
XGPIO210
BOOTSTRAP
_CFG
System configuration registers (MISC)
308/1728
Table 53.
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
RM0089
Table 53.
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
BOOTSTRAP
_CFG
Default
Doc ID 018904 Rev 3
MCIF_DATA1_
SD
8[4]
8[4]
PU
4[23:22]
1
2[27]
1
8[5]
1
na
0
XGPIO229
MCIF_DATA2_
SD
8[5]
8[5]
PU
4[23:22]
1
2[27]
1
8[6]
1
na
0
XGPIO230
MCIF_DATA3_
SD
8[6]
8[6]
PU
4[23:22]
1
2[27]
1
8[7]
1
na
0
XGPIO231
MCIF_DATA4
8[7]
8[7]
PU
4[23:22]
1
2[27]
1
8[8]
1
na
0
XGPIO232
MCIF_DATA5
8[8]
8[8]
PU
4[23:22]
1
2[27]
1
8[9]
1
na
0
XGPIO233
FSMC_IO2
8[9]
8[9]
PU
4[25:24]
1
2[28]
1
8[10]
1
na
0
XGPIO234
FSMC_IO1
8[10]
8[10]
PU
4[25:24]
1
2[28]
1
8[11]
1
na
0
XGPIO235
FSMC_IO0
8[11]
8[11]
PU
4[25:24]
1
2[28]
1
8[12]
1
na
0
XGPIO236
FSMC_RSTP
WDWN0
8[12]
8[12]
PU
4[25:24]
1
2[28]
1
8[13]
1
na
0
XGPIO237
MCIF_DATA0
8[13]
8[13]
PU
4[27:26]
1
2[29]
1
8[14]
1
na
0
XGPIO238
FSMC_IO7
8[14]
8[14]
PU
4[29:28]
1
2[30]
1
8[15]
1
na
0
XGPIO239
FSMC_IO6
8[15]
8[15]
PU
4[29:28]
1
2[30]
1
8[16]
1
na
0
XGPIO240
FSMC_IO5
8[16]
8[16]
PU
4[29:28]
1
2[30]
1
8[17]
1
na
0
XGPIO241
FSMC_IO4
8[17]
8[17]
PU
4[29:28]
1
2[30]
1
8[18]
1
na
0
XGPIO242
FSMC_IO3
8[18]
8[18]
PU
4[29:28]
1
2[30]
1
8[19]
1
na
0
XGPIO243
FSMC_ALE_A
D17
8[19]
8[19]
PU
4[31:30]
1
2[31]
1
8[20]
1
na
0
XGPIO244
FSMC_REn
8[20]
8[20]
PU
4[31:30]
1
2[31]
1
8[21]
1
na
0
XGPIO245
FSMC_WEn
8[21]
8[21]
PU
4[31:30]
1
2[31]
1
8[22]
1
na
0
XGPIO246
FSMC_RWPR
T0n
8[22]
8[22]
PU
4[31:30]
1
2[31]
1
8[23]
1
na
0
System configuration registers (MISC)
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XGPIO228
Pad configuration options (continued)
Shared IP pins
GPIO/
XGPIO
IP pin 1
IP pin 2
Miscellaneous registers to configure
PAD_PU
_CFG_x
PAD_PD
_CFG_x
Offset:
0x6000x61C
Offset:
0x6200x63C
x[bit]
Default
PAD_DRV_CFG_x
PAD_SLEW_CFG_x
PAD_FUNCTION_EN_x
PAD_SHARED_IP_EN_x
Offset:
0x648-0x658
Offset:
0x65C - 0x664
Offset:
0x668 - 0x69C
Offset:
0x6A0 - 0x6A4
x[bit]
x[bit]
x[bit]
x[bit]
Default
Default
Default
Default
XGPIO247
FSMC_RB0
8[23]
8[23]
PU
4[31:30]
1
2[31]
1
8[24]
1
na
0
XGPIO248
FSMC_CLE_A
D16
8[24]
8[24]
PU
4[31:30]
1
2[31]
1
8[25]
1
na
0
XGPIO249
FSMC_CE0n
8[25]
8[25]
PU
4[31:30]
1
2[31]
1
8[26]
1
na
0
BOOTSTRAP
_CFG
System configuration registers (MISC)
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Table 53.
Doc ID 018904 Rev 3
RM0089
RM0089
5.4
System configuration registers (MISC)
Compensation cells
This section describes the compensation cells used for SPEAr1340 different type of pads.
Note:
Please refer to Doc ID 023063, Data sheet, SPEAr1340, Dual-core Cortex A9 HMI
embedded MPU, “Ball characteristics” table for connections of each signal to the related
compensation cell.
5.4.1
Compensation for DDR pads
SPEAr1340 has one programmable compensation for all DDR pads: IO_COMP_DDR.
To use this compensation cell, you have to program the miscellaneous register
COMPENSATION_DDR_CFG (MISC base address + 0x710).
The following table describes in detail the bits used for this purpose.
Table 54.
COMPENSATION_DDR_CFG configuration for compensation
Bit
Description
updateZc
When low:
1) Clear comzcrdy signal
2) FSM generates and updates a new code so comzcrdy goes to one.
3) No code was updated, so it remains at the last updated code.
When the high the code is updated, the FSM calculates a new code each
time. This configuration is not stable because the code is continually
updated. If you want to update the code, make sure that the RAM DDR
access is not enabled, then drive this pin high then low.
enbcomzcin
– When high, the code is determined by the compensation block.
– When low, the code is written by the core on the comzcpin/comzcnin bus,
even if a new code is computed by the compensation block (comzcrdy
goes to one).
comzcpin
– Input bits to write the comzcp calibration code directly from the core.
There are 16 different possible compensation values.
comzcnin
– Input bits to write the comzcn calibration code directly from the core.
There are 16 different possible compensation values
enableb
– When low, the compensation cell runs normally and generates the
compensation code if requested.
– When high, disable the analog portion. The internal analog clock is
disabled. The previously generated codes remain comzcp and comzcn.
Note: To reactivate the analog part, reset the compensation through
MPMC reset
comzcrdy
RO register:
– When low, the code is not computed by the compensation block.
– When high, the code is computed by the compensation block.
comzcp_core
RO register: Value of computed compensation value
comzcp_core
RO register: Value of computed compensation value
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System configuration registers (MISC)
RM0089
To use the compensation block in automatic mode, set the following configuration:
Table 55.
Compensation block in automatic mode configuration
COMPENSATION_DDR_CFG bit
Access
Offset
Width
Description
comzcnin
RW
17
4
Indifferent
comzcpin
RW
13
4
Indifferent
updateZC
RW
12
1
Low
enableb
RW
11
1
Low
enbcomzcin
RW
10
1
High
If you want to update the code, make sure that the RAM DDR access is not enabled, drive
updateZC high then low, and check the bit comzcrdy.
You can read the compensated value from the following register, when comzcrdy is one:
Table 56.
Compensated values in automatic mode
COMPENSATION_DDR_CFG bit
Access
Offset
Width
comzcn_core
RO
6
4
comzcp_core
RO
2
4
comzcrdy
RO
0
1
To use the compensation block with a fixed value, set the following configuration:
Table 57.
Compensation block with fixed values configuration
COMPENSATION_DDR_CFG bit
Access
Offset
Width
Description
comzcnin
RW
17
4
Required code
comzcpin
RW
13
4
Required code
updateZC
RW
12
1
Indifferent
enableb
RW
11
1
Indifferent
enbcomzcin
RW
10
1
Low
This type of compensation has an ANAREXT pin which is connected to an external resistor.
●
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IO_COMP_DDR → DDRIO_COMP_REXT (ball AD5)
Doc ID 018904 Rev 3
RM0089
5.4.2
System configuration registers (MISC)
Compensation for IOTYPE1 and IOTYPE4 pads
SPEAr1340 has two compensations for IOTYPE1 and IOTYPE4 pads:
●
IO_COMP1_3V3
●
IO_COMP2_3V3
Each of them is used to generate a 7-bit thermometer code which represents the process,
voltage, and temperature (PVT) condition of the chip. This code is used to reduce the
spread of PVT-dependent circuit parameters, mainly current slew rate and output
impedance in IO buffers supporting this feature.
The compensation cell also generates analog reference signals to protect 50 Å devices from
stress, and digital signals to reduce power consumption in idle conditions.
To use these compensation cells, you have to program the following miscellaneous
registers:
●
COMPENSATION_3V3_1_CFG (MISC base address + 0x708)
●
COMPENSATION_3V3_2_CFG (MISC base address + 0x70C)
Table 58.
COMPENSATION_3V3_*_CFG configuration for compensation
Field name
Access type
Offset
Width
Description
-
RO
31
1
Reserved
rasrc
RW
24
7
7 bit digital code to be outputted
-
RO
23
1
Reserved
nasrc
RO
16
7
7 bit digital code to be read
-
RO
8
8
Reserved
pad_chipsleep
RW
7
1
Input sleep signal
pad_sleepinhbt
RW
6
1
Enable sleep mode
pad_tq
RW
5
1
Operation mode select
sts_ok
RO
4
1
Compensation status
accurate
RW
3
1
External resistor select pin
freeze
RW
2
1
Freeze mode enable
tq
RW
1
1
Operation mode select
en
RW
0
1
Operation mode select
Each type of this compensation has an ANA REF pin which is connected to an external
resistor.
●
IO_COMP1_3V3 → IO_COMP_REXT1_3V3 (ball AC21)
●
IO_COMP2_3V3 → IO_COMP_REXT2_3V3 (ball K19)
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System configuration registers (MISC)
RM0089
Functional description
The compensation cell can be programmed to operate in accurate or standard mode,
depending on the value set on the “accurate” bit in the COMPENSATION_3V3_*_CFG
register, as shown below:
Table 59.
Accurate and standard modes programming
Accurate bit value
Programming mode
1’b0
Standard mode (internal resistor used)
1’b1
Accurate mode (external resistor used)
Accurate mode
In this mode, the macro cell uses an off chip resistor for reference current generation. The
compensation cell generates accurate reference current and digital codes. This mode is
recommended to be used for high-performance applications.
This mode requires an external resistor to be connected to the ANAREXT pin.
Standard mode
In this mode, the compensation cell uses an on-chip resistor which is included inside the cell
for reference current generation. This mode should be used when slew and impedance
correction is not critical as it saves off-chip area and the cost of an external component.
In this mode, although the ANAREXT pin can be connected to the chip GROUND, it is
recommended that the pin remains unconnected.
Operating modes
Once programmed, the compensation cell can function in various modes of operation based
on logic values on the input pins. Table 60 shows how the COMPENSATION_3V3_*_CFG
register must be configured to select an operating mode.
The operating modes are described in the next sections.
Table 60.
Operating modes selection
COMPENSATION_3V3_*_CFG register bits
Operating mode
pad_tq
en
tq
freeze
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
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1’b0
1'b1
1'b1
1’b0
1'b1
1’b0
↑
pad_chipsleep
pad_sleepinhbt
-
1'b1
1’b0
1’b0
-
1'b1
1’b0
1’b0
-
1'b1
1’b0
1’b0
-
-
-
-
Doc ID 018904 Rev 3
sts_ok
1'b1
Normal mode
1’b0
Freeze mode
1’b0
Read mode
1’b0
High impedance
mode
RM0089
System configuration registers (MISC)
Table 60.
Operating modes selection (continued)
COMPENSATION_3V3_*_CFG register bits
Operating mode
Note:
pad_tq
en
tq
freeze
1’b0
1’b0
1'b1
-
pad_chipsleep
pad_sleepinhbt
-
1'b1
1’b0
1’b0
sts_ok
1’b0
Fixed code mode
1'b1
1’b0
1’b0
-
-
-
1’b0
IDDQ mode
1’b0
1’b0
1’b0
-
1'b1
1’b0
1’b0
Sleep mode
1
A hyphen (-) indicates any logic level, 0 or 1.
2
Any combinations of tq, pad_tq and en bits other than the ones listed in the table are not
allowed. They may lead to current consumption in IO.
3
↑ indicates that the compensation freezes in the 7-bit codes on the rising edge of freeze.
Normal mode
In this mode, the compensation cell constantly tracks the PVT condition of the chip and
generates 7-bit digital thermometer code. This 7-bit code is referred to as f(PVT) and it
represents current PVT state. The 7-bit code appears on the output pads and nasrc[6:0] bits
at the specified voltage levels. In normal mode, the internal reference current generators are
active and power consumption is higher than all other modes.
Freeze mode
The compensation cell enters this mode on the rising edge (logic low to high transition) of
the freeze bit. In this mode, the 7-bit code, at the time of rising edge of freeze, is latched and
presented on the output pads and nasrc[6:0] bits at the specified voltage levels.
Freeze mode allows capturing the compensation code and stopping the PVT measurement.
This mode is intended to be used to freeze the digital compensation codes when the data is
transferred from the compensated IOs on a chip to an external device burst mode. This
ensures signal integrity and eliminates the jitter caused due to modifications in IO driver
strength. The strength of the IO driver changes when compensation code alters during long
data transfer operations.
After the data transfer operation is complete, the compensation cell can be brought back to
normal mode by putting a logic low value on the freeze pin.
Note:
To ensure that valid 7-bit codes are latched properly, the freeze mode should be entered
only from normal mode when the sts_ok status bit is at at logic high.
Read mode
In this mode, it is possible to force the digital codes from the chip core logic. The digital logic
at rasrc[0:6] bits is presented at the compensation output at the specified voltage levels.
Note:
Non-thermometer codes should be avoided when using the cell in this mode as the IO cells
are not designed to be operated with non-thermometer codes.
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System configuration registers (MISC)
RM0089
High impedance mode
In this mode, the compensation output is tri-stated (put in high impedance). High impedance
mode is used when two or more compensation cells are sharing the same output pads.
Fixed code mode
The digital code is forced to a fixed value on the compensation output at the specified
voltage level. The fixed value same as the digital thermometer code is obtained at typical
PVT conditions and is equal to b0001111.
IDDQ mode
IDDQ mode shuts down all internal blocks consuming static currents. In this mode, there is
no static current consumption in the compensation cell except for leakage and it is used
during IDDQ testing. The digital code is forced to a fixed value, which is equal to b0001111
at the compensation output at the specified voltage levels.
Sleep mode
Sleep mode should be used when there is no activity on pad or in core. This reduces the
overall current consumption of IOs. The codes are latched to the bit pattern, which exists
before sleep mode is enabled. Sleep mode for the macro cell is only activated when the
entire chip is set in sleep mode, pad_chipsleep bit is high, and pad_sleepinhbt bit is low.
Sleep mode should be forced either from normal mode or freeze mode.
sts_ok bit
The logic value on this bit informs the user regarding the status of the 7-bit code availability
on the output pads.
The sts_ok bit indicates that the compensation cell has started generating valid codes which
are PVT-dependent and the cell is stabilized. It is recommended to latch 7-bit codes when
the sts_ok bit reaches at logic high.
Table 61.
sts_ok bit status
sts_ok
1'b1
Mode
Description
Normal mode
Signals that valid 7 bits code is available on the output pads and the
compensation cell is tracking f(PVT).
Normal mode
Occurs when the compensation cell enters the normal mode from
another mode and is in the process of generating the 7-bit code
representing f(PVT).
Freeze mode
1'b0
Read mode
High impedance
Fixed code
Signals that the 7-bit digital code available on output pads is not
generated by f(PVT) and that the compensation cell is in modes other
than normal mode.
IDDQ
Sleep
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RM0089
System configuration registers (MISC)
Power sequence and states
The compensation cell supports core-off mode, but not IO-off mode. The cell can be in
different states depending on the state of the power supplies.
It should be noted that the sts_ok bit is at logic low during Power Not OK and core-off states.
The status of compensation cell output in the power supply states is as shown below.
Table 62.
Note:
5.4.3
Compensation cell status in power supply states
Power supply state
sts_ok
Power Not OK
1’b0
Core-off
1’b0
1
At power-on for IO_COMP1_3V3 and IO_COMP2_3V3, it is recommended to program
them in accurate mode for more precision on the definition of digital code using the external
resistor.
2
For stable behavior on the pads and to avoid signal integrity degradation, it is recommended
to set the compensation in freeze mode after the sts_ok (MISC registers) goes high.
3
The default values of accurate and freeze fields on MISC are b0. For this reason, at the
beginning the compensations are in standard mode and do not work in freeze mode.
Compensation for IOTYPE2 and IOTYPE3 pads
SPEAr1340 has three programmable compensations for IOTYPE2 and IOTYPE3 pads:
●
IO_COMP1_1V8_3V3
●
IO_COMP2_1V8_3V3
●
IO_COMP_2V5_3V3
Each of them is used to generate a 7-bit thermometer code, which represents process,
voltage, and temperature (PVT) condition of the chip. This code is used to reduce the
spread of PVT-dependent circuit parameters mainly current slew rate and output impedance
in IO buffers.
To use these compensation cells, you have to program the following MISC registers:
●
COMPENSATION_1V8_3V3_1_CFG (MISC base address + 0x700)
●
COMPENSATION_1V8_3V3_2_CFG (MISC base address + 0x704)
●
COMPENSATION_2V5_3V3_1_CFG (MISC base address + 0x714)
Table 63.
Field name
COMPENSATION_*_CFG configuration for compensation
Access type
Offset
Width
-
RO
31
1
Reserved
rasrc
RW
24
7
7-bit digital code to be outputted
-
RO
23
1
Reserved
nasrc
RO
16
7
7 bit digital code to be read
-
RO
7
9
Reserved
psw
RW
6
2
Power supply select pin
Doc ID 018904 Rev 3
Description
317/1728
System configuration registers (MISC)
Table 63.
Field name
RM0089
COMPENSATION_*_CFG configuration for compensation (continued)
Access type
Offset
Width
Description
pad_tq
RW
5
1
Operation mode select
sts_ok
RO
4
1
Compensation status
accurate
RW
3
1
External resistor select pin
freeze
RW
2
1
Freeze mode enable
tq
RW
1
1
Operation mode select
en
RW
0
1
Operation mode select
Each type of this compensation has an ANAREXT pin which is connected to an external
resistor.
●
IO_COMP1_1V8_3V3 → IO_COMP_REXT1_1V8_3V3 (ball K12)
●
IO_COMP2_1V8_3V3 → IO_COMP_REXT2_1V8_3V3 (ball K15)
●
IO_COMP_2V5_3V3 → IO_COMP_REXT_2V5_3V3 (ball P19)
Functional description
The compensation cell can be programmed by putting a valid logic value at psw[1:0] and
accurate bits independent of each other. The psw bits are used to program for 1.8 V, 2.5 V,
or 3.3 V power supply while the accurate bit is used for accurate and standard modes.
Programming the cell for operating power supply
As mentioned above, the compensation cell can be programmed to operate at 1.8 V, 2.5 V,
or 3.3 V power supply by setting a valid logic level at the psw bits (see Table 64).
You must ensure that the voltage supplied to the macro cell is within the specified range for
a programming mode. The compensation cell generates wrong code if any other
combination of the psw bits besides what defined in Table 64 is used. In such a condition,
the cell does not work as intended, although there is no damage to the cell.
Programming for accurate or standard mode
The compensation cell can be programmed to operate in accurate or standard mode by
setting a valid logic level on the accurate bit. For mode programming information, see
Table 64 below.
Table 64.
Note:
Mode programming
psw[0]
psw[1]
accurate
Programming mode
1’b0
1’b0
X
1.8 V supply mode
1’b1
1’b0
X
2.5 V supply mode
1’b1
1’b1
X
3.3 V supply mode
X
X
1’b0
Standard mode (internal resistor used)
X
X
1’b1
Accurate mode (external resistor used)
1
X indicates any logic level, 0 or 1.
2
Any other combination of PSW1 and PSW2 is not allowed.
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RM0089
System configuration registers (MISC)
Accurate mode
In this mode, the macro cell uses an off-chip resistor for reference current generation. The
value of this resistance is subject to variations of process and temperature within +/- 1%. As
a result, the compensation cell generates accurate reference current and digital codes. This
mode is recommended to be used for high performance applications. This mode requires
more chip area, especially in pad-limited designs, as it needs an external resistor to be
connected to the ANAREXT pin through an additional analog and ground pad.
To use the compensation cell with 1.8 V power supply, the psw[1:0] bits should be at 2’b00.
To use the compensation cell with 2.5 V power supply, the psw[1:0] bits should be at 2’b01.
To use the compensation cell with 3.3 V power supply, the psw[1:0] bits should be at 2’b11.
Standard mode
In this mode, the macro cell uses an on-chip resistor, which is included inside the macro cell,
for reference current generation. The value of this resistance is subject to variations of
process and temperature usually within +/- 20 % that causes minor inaccuracy in generation
of digital codes. This mode should be used when slew and impedance correction is not
critical as it saves off-chip area and the cost of an external component.
In this mode, although the ANAREXT pin can be connected to the chip GROUND, it is
recommended that the pin remains unconnected.
To use the compensation cell with 1.8 V power supply, the psw[1:0] bits should be at 2’b00.
To use the compensation cell with 2.5 V power supply, the psw[1:0] bits should be at 2’b01.
To use the compensation cell with 3.3 V power supply, the psw[1:0] bits should be at 2’b11.
Operating modes
Once programmed, the compensation cell can function in various modes of operation based
on logic values on the input pins. Table 65 shows how COMPENSATION_*_CFG
miscellaneous registers must be configured to select an operating mode.
The operating modes are described in the next sections.
Table 65.
Operating modes selection
COMPENSATION_*_CFG register bits
Operating mode
pad_tq
en
tq
freeze
sts_ok
1’b0
1’b0
1’b0
1’b0
1’b1
Normal mode
1’b0
1’b0
1’b0
↑
1’b0
Freeze mode
1’b0
1’b1
1’b1
-
1’b0
Read mode
1’b0
1’b1
1’b0
-
1’b0
High impedance mode
1’b0
1’b0
1’b1
-
1’b0
Fixed code mode
1’b1
1’b0
1’b0
-
1’b0
IDDQ mode
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System configuration registers (MISC)
Note:
RM0089
1
A hyphen (-) indicates any logic level, 0 or 1.
2
Any combinations of tq, pad_tq and en bits other than the ones listed in the table are not
allowed. They may lead to current consumption in IO.
3
↑ indicates that the compensation freezes in the 7-bit codes on the rising edge of freeze.
Normal mode
In this mode, the compensation cell constantly tracks the PVT condition of the chip and
generates 7-bit digital thermometer code. This 7 bit code is referred to as f(PVT) and it
represents the current PVT state. The 7-bit code appears on the output pad and also on the
nasrc[6:0] bits at the specified voltage levels. In normal mode, the internal reference current
generators are active and power consumption is higher than all other modes.
Freeze mode
The compensation cell enters this mode on the rising edge (logic low to high transition) of
the freeze bit. In this mode, the 7-bit code, at the time of rising edge of freeze, is latched and
presented on the output pads and also on the nasrc[6:0] bits at the specified voltage levels.
Freeze mode allows capturing compensation code and stopping the PVT measurement.
This mode is intended to be used to freeze the digital compensation codes, when the data is
transferred from the compensated IOs on a chip to an external device during burst mode.
This ensures signal integrity and eliminates the jitter caused due to modification in IO driver
strength. The strength of the IO driver changes when compensation code alters during long
data transfer operations.
After the data transfer operation is complete, the compensation cell can be brought back to
normal mode by putting a logic low value on the freeze bit.
Note:
To ensure that valid 7-bit codes are latched properly, freeze mode should be entered only
from normal mode when sts_ok bit is at logic high.
Read mode
In this mode, it is possible to force the digital codes from the chip core logic. The digital logic
at inputs is presented on the output pads and also on the nasrc[6:0] bits at the specified
voltage levels.
Non-thermometer codes should be avoided when using the compensation cell in this mode
as the IO cells are not designed to be operated with non-thermometer codes.
High impedance mode
In this mode, the output is tri-stated (put in high impedance). High impedance mode is used
when two or more compensation cells are sharing the same output pads and another macro
takes over 7-bit code in the IO ring.
Fixed code mode
The digital code is forced to a fixed value on the output pads and nasrc[7:0] bits at the
specified voltage levels. The fixed value is same as the digital thermometer code is obtained
at typical PVT conditions and is equal to b0001111.
IDDQ mode
IDDQ mode shuts down all internal blocks consuming static currents. In this mode, there is
no static current consumption in the compensation cell except leakage and it is used during
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System configuration registers (MISC)
IDDQ testing. The digital code is forced to a fixed value, which is equal to b0001111 on the
output pads and nasrc[7:0] bits at the specified voltage levels.
sts_ok status signal
The logic value on this output pin informs the user regarding the status of the 7-bit code
available on the output pads and nasrc[7:0] bits.
Table 66.
sts_ok status
sts_ok
Mode
1'b1
Description
Normal mode
Signals that valid 7 bits code is available on the output pad and
nasrc[7:0] bits and the compensation cell is tracking f(PVT).
Normal mode
Occurs when the compensation cell enters the normal mode
from another mode and is in the process of generating the 7 bits
code representing f(PVT).
Freeze mode
1'b0
Read mode
Signals that the 7 bit digital code available on output pads and
nasrc[7:0] bits is not generated by f(PVT) and that the
compensation cell is in modes other than normal mode.
High impedance
Fixed code
IDDQ
Sleep
The sts_ok bit indicates that the compensation cell has started generating valid codes,
which are PVT-dependent and the cell is stabilized. It is recommended to latch 7-bit codes
when the sts_ok bit reaches at logic high.
Note:
For the power-up, correct compensation codes are available only 400 µs after the sts_ok bit
goes High ”H”.
Power sequence and states
The compensation cell supports both core-off and IO-off modes, therefore, there is no
specific power sequence. The cell can be in different states depending on the state of the
power supplies.
The sts_ok bit is at logic low during Power Not OK and core-off states. The status of macro
cell output in the power supply states is shown in the following table.
Table 67.
Compensation cell status in power supply states
Power supply state
sts_ok
Power Not OK
1’b0
Core-off
1’b0
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System configuration registers (MISC)
RM0089
5.4.4
Recommendations to use the compensation cell
Note:
This section is applicable for all the compensation cells except for the DDR one.
The compensation cell should generally be used in normal mode. The other modes of
operation should be used for debugging or when the chip has to be put in low power.
Note:
●
The compensation cell should be used in accurate mode to ensure high performance of
IO or high accuracy of code.
●
Standard mode can be used for low performance when +/-2 bit inaccuracy is
acceptable.
●
Freeze mode should always be used in normal mode and to latch the codes freeze
signal should go high only when sts_ok bit is high. There should be around 5 µm delay
between the time that sts_ok bit is high and the transmission of freeze. This mode
should be used only when the supply noise is too high.
●
Codes are latched on rising edge of freeze.
●
Always wait for few microseconds whenever the compensation cell enters from one
mode to another mode.
●
Accurate mode is applicable when the compensation cell is in normal or freeze mode.
●
The input pins should be at some logic level even if they are not used in an operating
mode.
●
The ANAREXT pin should be left unconnected if the compensation cell is in standard
mode. However, one can also ground this pin in standard mode.
●
The external resistor should have good accuracy (+/- 1 %).
●
The maximum permissible value of capacitance in ANAREXT mode should not be
more than 15 pF.
●
Non-thermometer code should not be forced in read mode.
●
Sleep mode should be used if there is no activity on the pad and core side inputs of IO.
●
Always force IDDQ mode through the compensation cell.
●
Never use the reference signals to sink or source the current.
1
At power-on for IO_COMP_1V8_3V3 and IO_COMP_2V5_3V3, it is recommended to
program them in accurate mode in order to have more precision on the definition of digital
code using the external resistor.
2
For stable pad behavior and to avoid signal integrity degradation it is recommended to set
the compensation in freeze mode 400 µs after sts_ok (available on the MISC register) goes
high.
3
The default values of accurate and freeze fields on MISC are 1’b0. For this reason, at the
beginning the compensations are in standard mode and do not work in freeze mode.
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5.5
System configuration registers (MISC)
Inter-processor communication functionality
PRC1-2_LOCK_CTR registers
PRC1-2_LOCK_CTR is a group of R/W registers used to configure the hardware lock
mechanism which regulates the exclusivity access of all the internal shared resources:
buffer pools, memory regions and peripherals in the same or different subsystems.
The mechanism to get the lock exclusivity is based on a strict execution of the two pair
instructions bit-set and bit-test. The atomic read/write operation through the ARM SWAP
instruction is not supported. Before using any shared resource, the processor must become
the owner of it. First, it books the lock bit dynamically associated with every common
resource through the bit-set instruction (up to 15 individual hardware lock semaphores are
available). The bit-set will be ignored if the corresponding global bit lock[x] is already busy.
After that, through the bit-test instruction the processor checks if it has gained the resources
exclusivity, and then it can use them.
The current lock implementation scheme supports a multiprocessor platform with up to two
processors and a maximum of 15 hardware lock semaphores. The lock mechanism is based
on two simple state machines (one for each processor) running in parallel, which control the
local semaphores setting and resetting functionality. The global lock semaphores reflect the
active status of all the correspondent local semaphores as shown in the following figure.
Figure 2.
Inter-processor interlock overview
Prc#2
Idle[1:15]
Prc#1
Idle[1:15]
Set_lock[x]=(Req_lock[x]=true
and Glock[x]=false
Prc#2
Lock[1:15]
Prc#1
Lock[1:15]
(+)
Global
Glock[1:15]
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System configuration registers (MISC)
RM0089
PRC1-2_IRQ_CTR registers
PRC1-2_IRQ_CTR is a group of R/W registers used to perform inter-processor
communication based on a notify interrupt crossing scheme. Each processor can assert a
couple of interrupt request lines towards the other processor which autonomously resets the
received interrupts without the intervention of the interrupter processor, ensuring a low
latency inter-processor communication mechanism.
The current implementation logic supports up to two processors, each one able to handle a
maximum of two notify interrupt events as shown in the following figure.
Figure 3.
Inter-processor interrupts overview
Proc#1
Proc#2
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6
Reset and clock generator (RCG)
Reset and clock generator (RCG)
Refer to Chapter 5: System configuration registers (MISC) for the registers related to reset
and clock configuration.
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Power management
7
RM0089
Power management
Refer to Chapter 5: System configuration registers (MISC) for the registers related to power
management.
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8
Static RAMs (SRAM)
Static RAMs (SRAM)
There are no registers for configuring the embedded static RAMs.
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One-time programmable antifuse (OTP)
9
RM0089
One-time programmable antifuse (OTP)
Refer to Chapter 5: System configuration registers (MISC) for the registers related to OTP
configuration.
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General purpose timers (GPT)
10
General purpose timers (GPT)
10.1
Register summary
Table 68.
GPT register list
Offset
Register name
Description
TIMERx Control Register
Page
on page
330
0x80:0x100 (0x80)
TIMER_CONTROLx
0x84:0x104 (0x80)
TIMER_STATUS_INT_ACKx TIMERx Status and Interrupt ACK Register
on page
330
0x88:0x108 (0x80)
TIMER_COMPAREx
TIMER_COMPAREx Register
on page
331
0x8C:0x10C (0x80)
TIMER_COUNTx
TIMERx Counter Register
on page
331
0x90:0x110 (0x80)
TIMER_REDG_CAPTx
TIMERx REDG Counter Register
on page
331
0x94:0x114 (0x80)
TIMER_FEDG_CAPTx
TIMERx FEDG Counter Register
on page
332
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General purpose timers (GPT)
10.2
RM0089
Register description
TIMER_CONTROLx
7
6
5
4
3
2
1
PRESCAL
8
MODE
9
ENAB
10
CAPT
11
MATCH_INT
12
FEDGE_INT
13
REDG_INT
14
RESERVED
15
TIMERx Control Register
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Address:
GPTBaseAddress + 0x80 + (x-1) * 0x80 (x=1 to 2)
Type:
R/W
Reset:
0x0000
Description:
TIMERx Control Register
0
[10] REDG_INT: If Set Enables interruption on rising edge capture . If Reset,diables the interrupt
[9] FEDGE_INT: If Set Enables interruption on falling edge capture. If Reset,diables the interrupt
[8] MATCH_INT: If Set Enables interruption when timer count matches with Timer Value Register .
If Reset,diables the interrupt
[7:6] CAPT: Defines capture configuration:-CAPT[1:0] FUNCTION
00 No capture
01 Capture on RISING edge
10 Capture on FALLING edge
11 Capture on RISING and FALLING edges
[5] ENAB: Enables TIMER When Set.If Reset,Diables TIMER
[4] MODE: When set single-shot mode is enabled. When reset auto-reload mode is enabled.
[3:0] PRESCAL: Prescaler configuration
PRESCAL[3:0] DIVISION
0000
/1
0001
/2
0010
/4
0011
/8
0100
/ 16
0101
/ 32
0110
/ 64
0111
/ 128
1000
/ 256
1001-1111 NOT ALLOWED
TIMER_STATUS_INT_ACKx
15
14
13
12
11
10
TIMERx Status and Interrupt ACK Register
9
8
7
6
5
RESERVED
R
Address:
GPTBaseAddress + 0x84 + (x-1) * 0x80 (x=1 to 2)
Type:
R/W
Reset:
0x0000
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4
3
2
1
0
REDG
FEDGE MATCH
E
R/W
R/W
R/W
RM0089
General purpose timers (GPT)
Description:
TIMERx Status and Interrupt ACK Register
[2] REDGE: Set when rising edge has been detected on capture unit/Clears REDGE interrupt
source by writing a 1
[1] FEDGE: Set when falling edge has been detected on capture unit/Clears FEDGE interrupt
source by writing a 1
[0] MATCH: Set when MATCH has occurred in the compare unit/Clears MATCH interrupt source by
writing a 1
TIMER_COMPAREx
15
14
13
12
TIMER_COMPAREx Register
11
10
9
8
7
6
5
4
3
2
1
0
COMPARE_VALUE
R/W
Address:
GPTBaseAddress + 0x88 + (x-1) * 0x80 (x=1 to 2)
Type:
R/W
Reset:
0xFFFF
Description:
TIMER_COMPAREx Register
[15:0] COMPARE_VALUE: This register allows the software to program the
timer period for TIMER 1 .In auto-reload mode, when the counter has reached the compare
value, it is cleared and restarts
incrementing.
TIMER_PERIOD = (COMPARE_VALUE - 1) x
COUNTER_PERIOD + 2 TIMER_CLK periods
TIMER_COUNTx
15
14
13
TIMERx Counter Register
12
11
10
9
8
7
6
5
4
3
2
1
0
COUNTER_VALUE
R
Address:
GPTBaseAddress + 0x8C + (x-1) * 0x80 (x=1 to 2)
Type:
R
Reset:
0x0
Description:
TIMERx Counter Register
[15:0] COUNTER_VALUE: TIMER1 internal current counter value
TIMER_REDG_CAPTx
15
14
13
12
TIMERx REDG Counter Register
11
10
9
8
7
6
5
4
3
2
1
0
COUNTER_VALUE_REDGE
R
Address:
GPTBaseAddress + 0x90 + (x-1) * 0x80 (x=1 to 2)
Type:
R
Reset:
0x0
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General purpose timers (GPT)
Description:
RM0089
TIMERx REDG Counter Register
[15:0] COUNTER_VALUE_REDGE: TIMER1 counter value captured when Rising edge detected on
Capture Pin
TIMER_FEDG_CAPTx
15
14
13
12
TIMERx FEDG Counter Register
11
10
9
8
7
6
5
4
3
2
1
0
COUNTER_VALUE_FEDGE
R
Address:
GPTBaseAddress + 0x94 + (x-1) * 0x80 (x=1 to 2)
Type:
R
Reset:
0x0
Description:
TIMERx FEDG Counter Register
[15:0] COUNTER_VALUE_FEDGE: TIMER1 counter value captured when Falling edge detected on
Capture Pin
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Real-time clock (RTC)
11
Real-time clock (RTC)
11.1
Register summary
Table 69.
Offset
RTC register list
Register name
Description
Page
0x000 TIME REGISTER
This register contains current value of TIME
on page 334
0x004 DATE REGISTER
This register contains current value of
DATE(CALENDER)
on page 334
0x008 ALARM TIME REGISTER
This register contains TIME for which
ALARM is programmed
on page 335
0x00C ALARM DATE REGISTER
This register contains DATE value for which
ALARM is programmed
on page 335
0x010 CONTROL REGISTER
Control Register
on page 336
0x014 STATUS REGISTER
Status Register.
on page 336
0x018 GP-REG-0
General purpose register 0
on page 337
0x01C GP-REG-1
General purpose register 1
on page 337
0x020 GP-REG-2
General purpose register 2
on page 337
0x024 GP-REG-3
General purpose register 3
on page 338
0x028 GP-REG-4
General purpose register 4
on page 338
0x02C GP-REG-5
General purpose register 5
on page 338
0x030 GP-REG-6
General purpose register 6
on page 338
0x034 GP-REG-7
General purpose register 7
on page 339
0x038 GP-REG-8
General purpose register 8
on page 339
0x03C GP-REG-9
General purpose register 9
on page 339
0x040 GP-REG-10
General purpose register 10
on page 339
0x044 GP-REG-11
General purpose register 11
on page 340
0x048 GP-REG-12
General purpose register 12
on page 340
0x04C GP-REG-13
General purpose register 13
on page 340
0x050 GP-REG-14
General purpose register 14
on page 340
0x054 GP-REG-15
General purpose register 15
on page 341
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Real-time clock (RTC)
11.2
RM0089
Register descriptions
TIME REGISTER
This register contains current value of TIME
1
SU
2
ST
3
RESERVED
4
MIU
5
MIT
6
RESERVED
7
HU
8
HT
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Address:
RTC_RegistersBaseAddress + 0x000
Type:
R/W
Reset:
0x0000 0000
Description:
This register contains current value of TIME
0
[21:20] HT: Current value of hours tens in BCD format.
[19:16] HU: Current value of hours units in BCD format
[14:12] MIT: Current value of minutes tens in BCD format.
[11:8] MIU: Current value of minutes units in BCD format.
[6:4] ST: Current value of seconds tens in BCD format.
[3:0] SU: Current value of seconds units in BCD format.
DATE REGISTER
This register contains current value of
DATE(CALENDER)
DU
1
DT
2
RESERVED
3
MU
4
MT
5
RESERVED
6
YU
7
YT
8
YH
9
YM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R
R/
W
R/W
R
R/W
R/W
Address:
RTC_RegistersBaseAddress + 0x004
Type:
R/W
Reset:
0x0000 0000
Description:
This register contains current value of DATE(CALENDER)
[31:28] YM: Current value of years millenium in BCD format.
[27:24] YH: Current value of years hundreds in BCD format
[23:20] YT: Current value of years tens in BCD format
[19:16] YU: Current value of years units in BCD format
[12] MT: Current value of months tens in BCD format.
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RM0089
Real-time clock (RTC)
[11:8] MU: Current value of months units in BCD format.
[5:4] DT: Current value of days tens in BCD format.
[3:0] DU: Current value of days units in BCD format.
ALARM TIME REGISTER
This register contains TIME for which ALARM is
programmed
1
SU
2
ST
3
RESERVED
4
MU
5
MT
6
RESERVED
7
HU
8
HT
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Address:
RTC_RegistersBaseAddress + 0x008
Type:
R/W
Reset:
0x0000 0000
Description:
This register contains TIME for which ALARM is programmed
0
[21:20] HT: ALARM TIME hours tens in BCD format.
[19:16] HU: ALARM TIME hours units in BCD format
[14:12] MT: ALARM TIME minutes tens in BCD format.
[11:8] MU: ALARM TIME minutes units in BCD format.
[6:4] ST: ALARM TIME seconds tens in BCD format.
[3:0] SU: ALARM TIME seconds units in BCD format.
ALARM DATE REGISTER
This register contains DATE value for which
ALARM is programmed
DU
1
DT
2
RESERVED
3
MU
4
MT
5
RESERVED
6
YU
7
YT
8
YH
9
YM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R
R/
W
R/W
R
R/W
R/W
Address:
RTC_RegistersBaseAddress + 0x00C
Type:
R/W
Reset:
0x0000 0000
Description:
This register contains DATE value for which ALARM is programmed
0
[31:28] YM: ALARM DATE years millenium in BCD format.
[27:24] YH: ALARM DATE years hundreds in BCD format
[23:20] YT: ALARM DATE years tens in BCD format
[19:16] YU: ALARM DATE years units in BCD format
[12] MT: ALARM DATE months tens in BCD format.
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Real-time clock (RTC)
RM0089
[11:8] MU: ALARM DATE months units in BCD format.
[5:4] DT: ALARM DATE days tens in BCD format.
[3:0] DU: ALARM DATE days units in BCD format.
CONTROL REGISTER
Control Register
Address:
RTC_RegistersBaseAddress + 0x010
Type:
R/W
Reset:
0x0000 0000
Description:
Control Register
1
0
MASK0
2
MASK1
3
MASK2
4
MASK3
5
MASK4
6
MASK5
7
RESERVED
R
8
TB
RESERVED
R/
W
9
PB
IE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
[31] IE: Interrupt enable: If set, interrupts generated by alarm logic are sent out.
[9] TB: Prescaler bypass. If set, it forces the time register ofthe RTC_32K block to be updated
every rising edge of C32K. Use for testing purpose only!
[8] PB: Prescaler bypass. If set, it forces the time register ofthe RTC_32K block to be updated
every rising edge of C32K. Use for testing purpose only!
[5] MASK5: MASK(5): if set, it forces years compare to true
[4] MASK4: MASK(4): if set, it forces months compare to true
[3] MASK3: MASK(3): if set, it forces days compare to true
[2] MASK2: MASK(2): if set, it forces hours compare to true
[1] MASK1: MASK(1): if set, it forces minutes compare to true
[0] MASK0: MASK(0): if set, it forces seconds compare to true
4
3
2
1
0
RC
R
R
R
LT
5
PD
6
LD
7
PGP
8
RESERVED
9
INT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Status Register.
PT
STATUS REGISTER
R/
W
R
R
R
R
R
Address:
RTC_RegistersBaseAddress + 0x014
Type:
R/W
Reset:
0x0000 0000
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Description:
Real-time clock (RTC)
Status Register.
[31] INT: Interrupt clear Read : Returns interrupt status.
[6] PGP: Pending write to General purpose register.
[5] LD: Write to date register Lost.
[4] LT: Write to time register Lost.
[3] PD: Pending write to Date register.
[2] PT: Pending write to Time register.
[0] RC: RTC_32K Connected.
GP-REG-0
General purpose register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x018
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 0
GP-REG-1
General purpose register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x01C
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 1
GP-REG-2
General purpose register 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x020
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 2
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Real-time clock (RTC)
RM0089
GP-REG-3
General purpose register 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x024
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 3
GP-REG-4
General purpose register 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x028
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 4
GP-REG-5
General purpose register 5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x02C
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 5
GP-REG-6
General purpose register 6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
Address:
RTC_RegistersBaseAddress + 0x030
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 6
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9
8
7
6
5
4
3
2
1
0
RM0089
Real-time clock (RTC)
GP-REG-7
General purpose register 7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x034
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 7
GP-REG-8
General purpose register 8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x038
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 8
GP-REG-9
General purpose register 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x03C
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 9
GP-REG-10
General purpose register 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x040
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 10
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Real-time clock (RTC)
RM0089
GP-REG-11
General purpose register 11
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x044
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 11
GP-REG-12
General purpose register 12
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x048
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 12
GP-REG-13
General purpose register 13
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x04C
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 13
GP-REG-14
General purpose register 14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
Address:
RTC_RegistersBaseAddress + 0x050
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 14
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9
8
7
6
5
4
3
2
1
0
RM0089
Real-time clock (RTC)
GP-REG-15
General purpose register 15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R/W
Address:
RTC_RegistersBaseAddress + 0x054
Type:
R/W
Reset:
0x0000 0000
Description:
General purpose register 15
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Direct memory access controllers (DMAC)
12
RM0089
Direct memory access controllers (DMAC)
Table 70 lists the offsets for DMAC register blocks. See also: Table 2: SPEAr1340 address
map on page 11.
Table 70.
Offset from base address
Address block
0x000
Channel#0
0x058
Channel#1
0x0B0
Channel#2
0x108
Channel#3
0x160
Channel#4
0x1B8
Channel#5
0x210
Channel#6
0x268
Channel#7
0x2C0
Interrupt registers
0x368
Software handshake registers
0x398
Miscellaneous registers
Table 71.
CTLx.SRC_TR_WIDTH and DST_TR_WIDTH decoding
SRC_TR_WIDTH / DST_TR_WIDTH
Size (bits)
000
8
001
16
010
32
011
64
Table 72.
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DMAC address block
CTLx.SRC_MSIZE and DST_MSIZE decoding
SRC_MSIZE / DST_MSIZE
No. of data items
000
1
001
4
010
8
011
16
100
32
101
64
110
128
111
256
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RM0089
Direct memory access controllers (DMAC)
Table 73.
CTLx.TT_FC decoding
TT_FC
Transfer Type
Flow Controller
000
Memory to memory
DMAC
001
Memory to peripheral
DMAC
010
Peripheral to memory
DMAC
011
Peripheral to peripheral
DMAC
100
Peripheral to memory
Peripheral
101
Peripheral to peripheral
Source peripheral
110
Memory to peripheral
Peripheral
111
Peripheral to peripheral
Destination peripheral
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Direct memory access controllers (DMAC)
RM0089
12.1
Channel#0 registers
12.1.1
Channel#0 register summary
Table 74.
Channel#0 register list
Offset
12.1.2
Register name
Description
Page
0x0
SAR0
Channel 0 source address
on page 344
0x8
DAR0
Channel 0 destination address
on page 345
0x10
LLP0
Channel 0 linked list pointer
on page 345
0x18
CTL0
Channel 0 control
on page 346
0x40
CFG0
Channel 0 configuration
on page 348
0x48
SGR0
Channel 0 source gather register
on page 349
0x50
DSR0
Channel 0 destination scatter register
on page 350
Channel#0 register descriptions
SAR0
Channel 0 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
SAR
R/W
Address:
Channel#0BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 0 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
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1
0
RM0089
Direct memory access controllers (DMAC)
DAR0
Channel 0 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#0BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 0 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
LLP0
Channel 0 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
LMS
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
Address:
Channel#0BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Channel 0 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
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Direct memory access controllers (DMAC)
RM0089
CTL0
Channel 0 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#0BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
Description:
3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 0 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP0.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP0.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
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Direct memory access controllers (DMAC)
[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
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Direct memory access controllers (DMAC)
RM0089
CFG0
Channel 0 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#0BaseAddress + 0x40
Type:
R/W
Reset:
0x400000C00
Description:
Channel 0 configuration
1
0
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 0 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 0 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the destination peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR0 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
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Direct memory access controllers (DMAC)
[30] RELOAD_SRC: Automatic source reload. The SAR0 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
[9] FIFO_EMPTY: Channel 0 FIFO empty status. Indicates if there is data left in the channel FIFO.
0: Channel FIFO not empty
1: Channel FIFO empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
SGR0
Channel 0 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#0BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 0 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL0.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL0.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
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Direct memory access controllers (DMAC)
RM0089
DSR0
Channel 0 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
DSC
DSI
R/W
R/W
Address:
Channel#0BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
Channel 0 destination scatter register
8
7
6
5
4
3
2
1
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL0.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL0.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
12.2
Channel#1 registers
12.2.1
Channel#1 register summary
Table 75.
Offset
350/1728
Channel#1 register list
Register name
Description
Page
0x0
SAR1
Channel 1 source address
on page 351
0x8
DAR1
Channel 1 destination address
on page 351
0x10
LLP1
Channel 1 linked list pointer
on page 352
0x18
CTL1
Channel 1 control
on page 352
0x40
CFG1
Channel 1 configuration
on page 354
0x48
SGR1
Channel 1 source gather register
on page 356
0x50
DSR1
Channel 1 destination scatter register
on page 356
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0
RM0089
12.2.2
Direct memory access controllers (DMAC)
Channel#1 register descriptions
SAR1
Channel 1 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SAR
R/W
Address:
Channel#1BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 1 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
DAR1
Channel 1 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#1BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 1 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
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Direct memory access controllers (DMAC)
RM0089
LLP1
Channel 1 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
LMS
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
Address:
Channel#1BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Channel 1 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
CTL1
Channel 1 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#1BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
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3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Direct memory access controllers (DMAC)
Description:
Channel 1 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP1.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP1.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
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Direct memory access controllers (DMAC)
RM0089
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
CFG1
Channel 1 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#1BaseAddress + 0x40
Type:
R/W
Reset:
0x400000C00
Description:
Channel 1 configuration
1
0
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 1 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 1 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
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[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the Destination Peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR1 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[30] RELOAD_SRC: Automatic source reload. The SAR1 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
[9] FIFO_EMPTY: Channel 1 FIFO empty status. Indicates if there is data left in the channel FIFO.
1: Channel FIFO empty
0: Channel FIFO not empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
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SGR1
Channel 1 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#1BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 1 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL1.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL1.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
DSR1
Channel 1 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DSI
R/W
R/W
Address:
Channel#1BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
9
DSC
8
7
6
5
4
3
2
1
Channel 1 destination scatter register
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL1.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL1.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
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Direct memory access controllers (DMAC)
12.3
Channel#2 registers
12.3.1
Channel#2 register summary
Table 76.
Channel#2 register list
Offset
12.3.2
Register name
Description
Page
0x0
SAR2
Channel 2 source address
on page 357
0x8
DAR2
Channel 2 destination address
on page 358
0x10
LLP2
Channel 2 linked list pointer
on page 358
0x18
CTL2
Channel 2 control
on page 359
0x40
CFG2
Channel 2 configuration
on page 360
0x48
SGR2
Channel 2 source gather register
on page 362
0x50
DSR2
Channel 2 destination scatter register
on page 362
Channel#2 register descriptions
SAR2
Channel 2 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SAR
R/W
Address:
Channel#2BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 2 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
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RM0089
DAR2
Channel 2 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#2BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 2 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
LLP2
Channel 2 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
LMS
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
Address:
Channel#2BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Channel 2 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
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Direct memory access controllers (DMAC)
CTL2
Channel 2 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#2BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
Description:
3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 2 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP2.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP2.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
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[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
CFG2
Channel 2 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#2BaseAddress + 0x40
Type:
R/W
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Reset:
0x400000C00
Description:
Channel 2 configuration
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 2 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 2 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the Destination Peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR2 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[30] RELOAD_SRC: Automatic source reload. The SAR2 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
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[9] FIFO_EMPTY: Channel 2 FIFO empty status. Indicates if there is data left in the channel FIFO.
1: Channel FIFO empty
0: Channel FIFO not empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
SGR2
Channel 2 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#2BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 2 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL2.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL2.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
DSR2
Channel 2 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DSI
R/W
R/W
Address:
Channel#2BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
9
DSC
8
7
6
5
4
3
2
1
Channel 2 destination scatter register
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL2.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL2.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
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Direct memory access controllers (DMAC)
12.4
Channel#3 registers
12.4.1
Channel#3 register summary
Table 77.
Channel#3 register list
Offset
12.4.2
Register name
Description
Page
0x0
SAR3
Channel 3 source address
on page 363
0x8
DAR3
Channel 3 destination address
on page 364
0x10
LLP3
Channel 3 linked list pointer
on page 364
0x18
CTL3
Channel 3 control
on page 365
0x40
CFG3
Channel 3 configuration
on page 366
0x48
SGR3
Channel 3 source gather register
on page 368
0x50
DSR3
Channel 3 destination scatter register
on page 368
Channel#3 register descriptions
SAR3
Channel 3 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SAR
R/W
Address:
Channel#3BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 3 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
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Direct memory access controllers (DMAC)
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DAR3
Channel 3 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#3BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 3 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
LLP3
Channel 3 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
LMS
8
R/W
R/W
Address:
Channel#3BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 3 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
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Direct memory access controllers (DMAC)
CTL3
Channel 3 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#3BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
Description:
3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 3 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP3.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP3.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
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[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
CFG3
Channel 3 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#3BaseAddress + 0x40
Type:
R/W
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Direct memory access controllers (DMAC)
Reset:
0x400000C00
Description:
Channel 3 configuration
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 3 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 3 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the Destination Peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR3 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[30] RELOAD_SRC: Automatic source reload. The SAR3 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
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Direct memory access controllers (DMAC)
RM0089
[9] FIFO_EMPTY: Channel 3 FIFO empty status. Indicates if there is data left in the channel FIFO.
1: Channel FIFO empty
0: Channel FIFO not empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
SGR3
Channel 3 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#3BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 3 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL3.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL3.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
DSR3
Channel 3 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
DSC
DSI
R/W
R/W
Address:
Channel#3BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
Channel 3 destination scatter register
8
7
6
5
4
3
2
1
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL3.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL3.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
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RM0089
Direct memory access controllers (DMAC)
12.5
Channel#4 registers
12.5.1
Channel#4 register summary
Table 78.
Channel#4 register list
Offset
12.5.2
Register name
Description
Page
0x0
SAR4
Channel 4 source address
on page 369
0x8
DAR4
Channel 4 destination address
on page 370
0x10
LLP4
Channel 4 linked list pointer
on page 370
0x18
CTL4
Channel 4 control
on page 371
0x40
CFG4
Channel 4 configuration
on page 373
0x48
SGR4
Channel 4 source gather register
on page 374
0x50
DSR4
Channel 4 destination scatter register
on page 375
Channel#4 register descriptions
SAR4
Channel 4 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SAR
R/W
Address:
Channel#4BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 4 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
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Direct memory access controllers (DMAC)
RM0089
DAR4
Channel 4 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#4BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 4 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
LLP4
Channel 4 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
LMS
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
Address:
Channel#4BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Channel 4 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
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Direct memory access controllers (DMAC)
CTL4
Channel 4 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#4BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
Description:
3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 4 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP4.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP4.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
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[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
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Direct memory access controllers (DMAC)
CFG4
Channel 4 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#4BaseAddress + 0x40
Type:
R/W
Reset:
0x400000C00
Description:
Channel 4 configuration
1
0
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 4 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 4 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the Destination Peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR4 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
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Direct memory access controllers (DMAC)
RM0089
[30] RELOAD_SRC: Automatic source reload. The SAR4 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
[9] FIFO_EMPTY: Channel 4 FIFO empty status. Indicates if there is data left in the channel FIFO.
1: Channel FIFO empty
0: Channel FIFO not empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
SGR4
Channel 4 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#4BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 4 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL4.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL4.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
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Direct memory access controllers (DMAC)
DSR4
Channel 4 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
DSC
DSI
R/W
R/W
Address:
Channel#4BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
Channel 4 destination scatter register
8
7
6
5
4
3
2
1
0
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL4.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL4.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
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RM0089
12.6
Channel#5 registers
12.6.1
Channel#5 register summary
Table 79.
Channel#5 register list
Offset
12.6.2
Register name
Description
Page
0x0
SAR5
Channel 5 source address
on page 376
0x8
DAR5
Channel 5 destination address
on page 377
0x10
LLP5
Channel 5 linked list pointer
on page 377
0x18
CTL5
Channel 5 control
on page 378
0x40
CFG5
Channel 5 configuration
on page 380
0x48
SGR5
Channel 5 source gather register
on page 382
0x50
DSR5
Channel 5 destination scatter register
on page 382
Channel#5 register descriptions
SAR5
Channel 5 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
SAR
R/W
Address:
Channel#5BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 5 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
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0
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Direct memory access controllers (DMAC)
DAR5
Channel 5 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#5BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 5 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
LLP5
Channel 5 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
LMS
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
Address:
Channel#5BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Channel 5 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
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CTL5
Channel 5 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#5BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
Description:
3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 5 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP5.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP5.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
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[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
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RM0089
CFG5
Channel 5 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#5BaseAddress + 0x40
Type:
R/W
Reset:
0x400000C00
Description:
Channel 5 configuration
1
0
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 5 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 5 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the Destination Peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR5 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
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Direct memory access controllers (DMAC)
[30] RELOAD_SRC: Automatic source reload. The SAR5 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
[9] FIFO_EMPTY: Channel 5 FIFO empty status. Indicates if there is data left in the channel FIFO.
1: Channel FIFO empty
0: Channel FIFO not empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
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RM0089
SGR5
Channel 5 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#5BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 5 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL5.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL5.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
DSR5
Channel 5 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DSI
R/W
R/W
Address:
Channel#5BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
9
DSC
8
7
6
5
4
3
2
1
Channel 5 destination scatter register
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL5.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL5.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
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Direct memory access controllers (DMAC)
12.7
Channel#6 registers
12.7.1
Channel#6 register summary
Table 80.
Channel#6 register list
Offset
12.7.2
Register name
Description
Page
0x0
SAR6
Channel 6 source address
on page 383
0x8
DAR6
Channel 6 destination address
on page 384
0x10
LLP6
Channel 6 linked list pointer
on page 384
0x18
CTL6
Channel 6 control
on page 385
0x40
CFG6
Channel 6 configuration
on page 387
0x48
SGR6
Channel 6 source gather register
on page 388
0x50
DSR6
Channel 6 destination scatter register
on page 389
Channel#6 register descriptions
SAR6
Channel 6 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SAR
R/W
Address:
Channel#6BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 6 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
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RM0089
DAR6
Channel 6 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#6BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 6 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
LLP6
Channel 6 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
LMS
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
Address:
Channel#6BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Channel 6 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
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Direct memory access controllers (DMAC)
CTL6
Channel 6 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#6BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
Description:
3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 6 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP6.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP6.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
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[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
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Direct memory access controllers (DMAC)
CFG6
Channel 6 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#6BaseAddress + 0x40
Type:
R/W
Reset:
0x400000C00
Description:
Channel 6 configuration
1
0
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 6 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 6 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the Destination Peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR6 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
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[30] RELOAD_SRC: Automatic source reload. The SAR6 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
[9] FIFO_EMPTY: Channel 6 FIFO empty status. Indicates if there is data left in the channel FIFO.
1: Channel FIFO empty
0: Channel FIFO not empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
SGR6
Channel 6 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#6BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 6 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL6.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL6.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
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Direct memory access controllers (DMAC)
DSR6
Channel 6 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
DSC
DSI
R/W
R/W
Address:
Channel#6BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
Channel 6 destination scatter register
8
7
6
5
4
3
2
1
0
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL6.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL6.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
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RM0089
12.8
Channel#7 registers
12.8.1
Channel#7 register summary
Table 81.
Channel#7 register list
Offset
12.8.2
Register name
Description
Page
0x0
SAR7
Channel 7 source address
on page 390
0x8
DAR7
Channel 7 destination address
on page 391
0x10
LLP7
Channel 7 linked list pointer
on page 391
0x18
CTL7
Channel 7 control
on page 392
0x40
CFG7
Channel 7 configuration
on page 394
0x48
SGR7
Channel 7 source gather register
on page 395
0x50
DSR7
Channel 7 destination scatter register
on page 396
Channel#7 register descriptions
SAR7
Channel 7 source address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
SAR
R/W
Address:
Channel#7BaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Channel 7 source address
[31:0] SAR: Current source address of DMA transfer. Updated after each source transfer.
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0
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Direct memory access controllers (DMAC)
DAR7
Channel 7 destination address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DAR
R/W
Address:
Channel#7BaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Channel 7 destination address
[31:0] DAR: Current destination address of DMA transfer. Updated after each destination transfer.
LLP7
Channel 7 linked list pointer
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
LMS
9
LOC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
Address:
Channel#7BaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Channel 7 linked list pointer
[31:2] LOC: Starting address in memory of next LLI if block chaining is enabled. Note that the two
LSBs of the starting address are not stored because the address is assumed to be aligned to a
32-bit boundary.
[1:0] LMS: List master select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides.
00: AHB master 1
01: AHB master 2
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Direct memory access controllers (DMAC)
RM0089
CTL7
Channel 7 control
RESERVED
BLOCK_TS
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
INT_EN
0
DST_TR_WIDTH
1
SRC_TR_WIDTH
2
R
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/
W
Address:
Channel#7BaseAddress + 0x18
Type:
R/W
Reset:
0x200304801
Description:
3
DINC
R/W
4
SINC
TT_FC
R/W
5
DEST_MSIZE
DMS
R/W
6
SRC_MSIZE
SMS
R/
W
7
SRC_GATHER_EN
LLP_DST_EN
R/
W
8
RESERVED
LLP_SRC_EN
R
9
DST_SCATTER_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Channel 7 control
[43:32] BLOCK_TS: Block transfer size. When the DMAC is the flow controller, the user writes this field
before the channel is enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single AMBA beat.
The width of the single transaction is determined by SRC_TR_WIDTH.
[28] LLP_SRC_EN: Block chaining is enabled on the destination side only if the LLP_SRC_EN field
is high and LLP7.LOC is non-zero.
[27] LLP_DST_EN: Block chaining is enabled on the destination side only if the LLP_DST_EN field
is high and LLP7.LOC is non-zero.
[26:25] SMS: Source master select. Identifies the master interface layer where the source device
resides.
00: AHB master 1
01: AHB master 2
[24:23] DMS: Destination master select. Identifies the master interface layer where the destination
device resides.
00: AHB master 1
01: AHB master 2
[22:20] TT_FC: Transfer type and flow control. Table 73 lists the decoding for this field.
[18] DST_SCATTER_EN: Destination scatter enable.
0: Disabled
1: Enabled
Scatter on the destination side is applicable only when the DINC field indicates an incrementing
or decrementing address control.
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Direct memory access controllers (DMAC)
[17] SRC_GATHER_EN: Source gather enable.
0: Disabled
1: Enabled
Gather on the source side is applicable only when the SINC field indicates an incrementing or
decrementing address control.
[16:14] SRC_MSIZE: Source transaction burst length. Number of data items, each of width
CTLx.SRC_TR_WIDTH, to be read from the source.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[13:11] DEST_MSIZE: Destination transaction burst length. Number of data items, each of width
CTLx.DST_TR_WIDTH, to be written to the destination.
Table 72 lists the decoding for this field.
Note: This value is not related to the AHB bus master HBURST bus.
[10:9] SINC: Source address direction control. Indicates whether to increment, decrement or
unchange the source address on every source transfer.
00: Increment
01: Decrement
1x: No change
[8:7] DINC: Destination address direction control. Indicates whether to increment, decrement or
unchange the destination address on every destination transfer.
00: Increment
01: Decrement
1x: No change
[6:4] SRC_TR_WIDTH: Source transfer width. Table 71 lists the decoding for this field. Mapped to
AHB bus HSIZE.
[3:1] DST_TR_WIDTH: Destination transfer width. Table 71 lists the decoding for this field. Mapped
to AHB bus HSIZE.
[0] INT_EN: Interrupt enable.
0: All interrupt-generating sources disabled
1: All interrupt-generating sources enabled
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RM0089
CFG7
Channel 7 configuration
RESERVED
DST_PER
SRC_PER
RESERVED
PROTCTL
FIFO_MODE
FCMODE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R/W
R/W
R
R/W
R/
W
R/
W
FIFO_EMPTY
CH_SUSP
CH_PRIOR
RESERVED
2
HS_SEL_DST
3
HS_SEL_SRC
4
RESERVED
5
DST_HS_POL
6
SRC_HS_POL
7
RESERVED
8
RELOAD_DST
9
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R
R/
W
R/
W
R/
W
R/
W
R/W
R
Address:
Channel#7BaseAddress + 0x40
Type:
R/W
Reset:
0x400000C00
Description:
Channel 7 configuration
1
0
[46:43] DST_PER: Destination hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the destination of channel 7 if the HS_SEL_DST field is 0; otherwise, this
field is ignored.
The channel can then communicate with the destination peripheral connected to that interface
through the assigned hardware handshaking interface.
[42:39] SRC_PER: Source hardware handshaking interface. Assigns a hardware handshaking
interface (0 - 15) to the source of channel 7 if the HS_SEL_SRC field is 0; otherwise, this field is
ignored.
The channel can then communicate with the source peripheral connected to that interface
through the assigned hardware handshaking interface.
[36:34] PROTCTL: Protection control. Used to drive the AHB HPROT[3:1]. The AMBA Specification
recommends that the default value of HPROT indicates a non-cached, non-buffered, privileged
data access.
HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches.
[33] FIFO_MODE: FIFO mode control. Determines how much space or data needs to be available
in the FIFO before a burst transaction request is serviced.
0: Space/data available for single AHB transfer of the specified transfer width.
1: Data available greater than or equal to half the FIFO depth for destination transfers and
space available greater than half the FIFO depth for source transfers.
[32] FCMODE: Flow control mode. Determines when source transaction requests are serviced
when the Destination Peripheral is the flow controller.
0: Source transaction requests serviced when they occur. Data pre-fetching enabled.
1: Source transaction requests not serviced until a destination transaction request occurs. Data
pre-fetching disabled.
[31] RELOAD_DST: Automatic destination reload. The DAR7 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
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Direct memory access controllers (DMAC)
[30] RELOAD_SRC: Automatic source reload. The SAR7 register can be automatically reloaded
from its initial value at the end of every block for multiblock transfers. A new block transfer is
then initiated.
[19] SRC_HS_POL: Source handshake interface polarity.
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshake interface polarity.
0: Active high
1: Active low
[11] HS_SEL_SRC: Source handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for source requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the source peripheral is memory, this bit is ignored.
[10] HS_SEL_DST: Destination handshake select. This field selects which of the handshaking
interfaces - hardware or software - is active for destination requests on this channel.
0: Hardware handshaking interface
1: Software handshaking interface
If the destination peripheral is memory, this bit is ignored.
[9] FIFO_EMPTY: Channel 7 FIFO empty status. Indicates if there is data left in the channel FIFO.
1: Channel FIFO empty
0: Channel FIFO not empty
[8] CH_SUSP: Channel suspend. Suspends all DMA data transfers from the source until this bit is
cleared. There is no guarantee that the current transaction will complete.
0: Not suspended
1: Suspended
[7:5] CH_PRIOR: Channel priority. A priority of 7 is the highest priority and 0 is the lowest.
SGR7
Channel 7 source gather register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
SGC
SGI
R/W
R/W
Address:
Channel#7BaseAddress + 0x48
Type:
R/W
Reset:
0x0
Description:
Channel 7 source gather register
8
7
6
5
4
3
2
1
0
[31:20] SGC: Source gather count. Specifies the number of contiguous source transfers of
CTL7.SRC_TR_WIDTH between successive gather boundaries.
[19:0] SGI: Source gather interval. Specifies the source address increment/decrement in multiples of
CTL7.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source
transfer.
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Direct memory access controllers (DMAC)
RM0089
DSR7
Channel 7 destination scatter register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
DSC
DSI
R/W
R/W
Address:
Channel#7BaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
Channel 7 destination scatter register
8
7
6
5
4
3
2
1
[31:20] DSC: Destination scatter count. Specifies the number of contiguous destination transfers of
CTL7.DST_TR_WIDTH between successive scatter boundaries.
[19:0] DSI: Destination scatter interval. Specifies the destination address increment/decrement in
multiples of CTL7.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for
the destination transfer.
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RM0089
Direct memory access controllers (DMAC)
12.9
Interrupt registers
12.9.1
Interrupt register summary
Table 82.
Offset
Interrupt register list
Register name
Description
Page
0x0
RawTfr
Raw status for IntTfr interrupt
on page 398
0x8
RawBlock
Raw status for IntBlock interrupt
on page 398
0x10
RawSrcTran
Raw status for IntSrcTran interrupt
on page 399
0x18
RawDstTran
Raw status for IntDstTran interrupt
on page 399
0x20
RawErr
Raw status for IntErr interrupt
on page 400
0x28
StatusTfr
Status for IntTfr interrupt
on page 400
0x30
StatusBlock
Status for IntBlock interrupt
on page 401
0x38
StatusSrcTran
Status for IntSrcTran interrupt
on page 401
0x40
StatusDstTran
Status for IntDstTran interrupt
on page 402
0x48
StatusErr
Status for IntErr interrupt
on page 402
0x50
MaskTfr
Mask for IntTfr interrupt
on page 403
0x58
MaskBlock
Mask for IntBlock interrupt
on page 403
0x60
MaskSrcTran
Mask for IntSrcTran interrupt
on page 404
0x68
MaskDstTran
Mask for IntDstTran interrupt
on page 404
0x70
MaskErr
Mask for IntErr interrupt
on page 405
0x78
ClearTfr
Clear for IntTfr interrupt
on page 405
0x80
ClearBlock
Clear for IntBlock interrupt
on page 406
0x88
ClearSrcTran
Clear for IntSrcTran interrupt
on page 406
0x90
ClearDstTran
Clear for IntDstTran interrupt
on page 407
0x98
ClearErr
Clear for IntErr interrupt
on page 407
0xa0
StatusInt
Status for each interrupt type
on page 408
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Direct memory access controllers (DMAC)
12.9.2
RM0089
Interrupt register descriptions
RawTfr
Raw status for IntTfr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
RAW
R
R/W
Address:
Interrupt registersBaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Raw status for IntTfr interrupt
2
1
0
[7:0] RAW: Raw interrupt status. Interrupt events are stored in this field before masking (one bit per
channel).
RawBlock
Raw status for IntBlock interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
RAW
R
R/W
Address:
Interrupt registersBaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
Raw status for IntBlock interrupt
2
1
0
[7:0] RAW: Raw interrupt status. Interrupt events are stored in this field before masking (one bit per
channel).
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Direct memory access controllers (DMAC)
RawSrcTran
Raw status for IntSrcTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
RAW
R
R/W
Address:
Interrupt registersBaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Raw status for IntSrcTran interrupt
2
1
0
[7:0] RAW: Raw interrupt status. Interrupt events are stored in this field before masking (one bit per
channel).
RawDstTran
Raw status for IntDstTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
RAW
R
R/W
Address:
Interrupt registersBaseAddress + 0x18
Type:
R/W
Reset:
0x0
Description:
Raw status for IntDstTran interrupt
2
1
0
[7:0] RAW: Raw interrupt status. Interrupt events are stored in this field before masking (one bit per
channel).
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Direct memory access controllers (DMAC)
RM0089
RawErr
Raw status for IntErr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
RAW
R
R/W
Address:
Interrupt registersBaseAddress + 0x20
Type:
R/W
Reset:
0x0
Description:
Raw status for IntErr interrupt
2
1
0
[7:0] RAW: Raw interrupt status. Interrupt events are stored in this field before masking (one bit per
channel).
StatusTfr
Status for IntTfr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
STAT
R
R
Address:
Interrupt registersBaseAddress + 0x28
Type:
R
Reset:
0x0
Description:
Status for IntTfr interrupt
2
[7:0] STAT: Interrupt status. Interrupt events are stored in this field after masking (one bit per
channel).
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0
RM0089
Direct memory access controllers (DMAC)
StatusBlock
Status for IntBlock interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
STAT
R
R
Address:
Interrupt registersBaseAddress + 0x30
Type:
R
Reset:
0x0
Description:
Status for IntBlock interrupt
2
1
0
[7:0] STAT: Interrupt status. Interrupt events are stored in this field after masking (one bit per
channel).
StatusSrcTran
Status for IntSrcTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
STAT
R
R
Address:
Interrupt registersBaseAddress + 0x38
Type:
R
Reset:
0x0
Description:
Status for IntSrcTran interrupt
2
1
0
[7:0] STAT: Interrupt status. Interrupt events are stored in this field after masking (one bit per
channel).
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Direct memory access controllers (DMAC)
RM0089
StatusDstTran
Status for IntDstTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
STAT
R
R
Address:
Interrupt registersBaseAddress + 0x40
Type:
R
Reset:
0x0
Description:
Status for IntDstTran interrupt
2
1
0
[7:0] STAT: Interrupt status. Interrupt events are stored in this field after masking (one bit per
channel).
StatusErr
Status for IntErr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
STAT
R
R
Address:
Interrupt registersBaseAddress + 0x48
Type:
R
Reset:
0x0
Description:
Status for IntErr interrupt
2
[7:0] STAT: Interrupt status. Interrupt events are stored in this field after masking (one bit per
channel).
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RM0089
Direct memory access controllers (DMAC)
MaskTfr
Mask for IntTfr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
MASK_WE
MASK
R
W
R/W
Address:
Interrupt registersBaseAddress + 0x50
Type:
R/W
Reset:
0x0
Description:
Mask for IntTfr interrupt
2
1
0
[15:8] MASK_WE: Interrupt mask write enable.
0: Write disabled
1: Write enabled
[7:0] MASK: Interrupt mask.
0: Masked
1: Unmasked
A bit of this field can be written only if the corresponding bit of MASK_WE field is asserted on
the same AHB cycle.
MaskBlock
Mask for IntBlock interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
MASK_WE
MASK
R
W
R/W
Address:
Interrupt registersBaseAddress + 0x58
Type:
R/W
Reset:
0x0
Description:
Mask for IntBlock interrupt
2
1
0
[15:8] MASK_WE: Interrupt mask write enable.
0: Write disabled
1: Write enabled
[7:0] MASK: Interrupt mask.
0: Masked
1: Unmasked
A bit of this field can be written only if the corresponding bit of MASK_WE field is asserted on
the same AHB cycle.
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Direct memory access controllers (DMAC)
RM0089
MaskSrcTran
Mask for IntSrcTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
MASK_WE
MASK
R
W
R/W
Address:
Interrupt registersBaseAddress + 0x60
Type:
R/W
Reset:
0x0
Description:
Mask for IntSrcTran interrupt
2
1
0
[15:8] MASK_WE: Interrupt mask write enable.
0: Write disabled
1: Write enabled
[7:0] MASK: Interrupt mask.
0: Masked
1: Unmasked
A bit of this field can be written only if the corresponding bit of MASK_WE field is asserted on
the same AHB cycle.
MaskDstTran
Mask for IntDstTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
MASK_WE
MASK
R
W
R/W
Address:
Interrupt registersBaseAddress + 0x68
Type:
R/W
Reset:
0x0
Description:
Mask for IntDstTran interrupt
2
1
0
[15:8] MASK_WE: Interrupt mask write enable.
0: Write disabled
1: Write enabled
[7:0] MASK: Interrupt mask.
0: Masked
1: Unmasked
A bit of this field can be written only if the corresponding bit of MASK_WE field is asserted on
the same AHB cycle.
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Direct memory access controllers (DMAC)
MaskErr
Mask for IntErr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
MASK_WE
MASK
R
W
R/W
Address:
Interrupt registersBaseAddress + 0x70
Type:
R/W
Reset:
0x0
Description:
Mask for IntErr interrupt
2
1
0
[15:8] MASK_WE: Interrupt mask write enable.
0: Write disabled
1: Write enabled
[7:0] MASK: Interrupt mask.
0: Masked
1: Unmasked
A bit of this field can be written only if the corresponding bit of MASK_WE field is asserted on
the same AHB cycle.
ClearTfr
Clear for IntTfr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
CLEAR
R
W
Address:
Interrupt registersBaseAddress + 0x78
Type:
W
Reset:
Undefined
Description:
Clear for IntTfr interrupt
2
1
0
[7:0] CLEAR: Interrupt clear.
0: No effect
1: Clear interrupt
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Direct memory access controllers (DMAC)
RM0089
ClearBlock
Clear for IntBlock interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
CLEAR
R
W
Address:
Interrupt registersBaseAddress + 0x80
Type:
W
Reset:
Undefined
Description:
Clear for IntBlock interrupt
2
1
0
[7:0] CLEAR: Interrupt clear.
0: No effect
1: Clear interrupt
ClearSrcTran
Clear for IntSrcTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
7
6
5
4
3
R
W
Interrupt registersBaseAddress + 0x88
Type:
W
Reset:
Undefined
Clear for IntSrcTran interrupt
[7:0] CLEAR: Interrupt clear.
0: No effect
1: Clear interrupt
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8
CLEAR
Address:
Description:
9
RESERVED
Doc ID 018904 Rev 3
2
1
0
RM0089
Direct memory access controllers (DMAC)
ClearDstTran
Clear for IntDstTran interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
CLEAR
R
W
Address:
Interrupt registersBaseAddress + 0x90
Type:
W
Reset:
Undefined
Description:
Clear for IntDstTran interrupt
2
1
0
[7:0] CLEAR: Interrupt clear.
0: No effect
1: Clear interrupt
ClearErr
Clear for IntErr interrupt
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
CLEAR
R
W
Address:
Interrupt registersBaseAddress + 0x98
Type:
W
Reset:
Undefined
Description:
9
RESERVED
2
1
0
Clear for IntErr interrupt
[7:0] CLEAR: Interrupt clear.
0: No effect
1: Clear interrupt
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Direct memory access controllers (DMAC)
RM0089
StatusInt
Status for each interrupt type
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4
3
2
1
0
RESERVED
ERR
DSTT
SRCT
BLOCK
TFR
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
Interrupt registersBaseAddress + 0xa0
Type:
R
Reset:
0x0
Description:
Status for each interrupt type
9
8
7
6
5
[4] ERR: OR of the contents of StatusErr register
[3] DSTT: OR of the contents of StatusDstTran register
[2] SRCT: OR of the contents of StatusSrcTran register
[1] BLOCK: OR of the contents of StatusBlock register
[0] TFR: OR of the contents of StatusTfr register
12.10
Software handshake registers
12.10.1
Software handshake register summary
Table 83.
Offset
408/1728
Software handshake register list
Register name
Description
Page
0x0
ReqSrcReg
Source software transaction request register
on page 409
0x8
ReqDstReg
Destination software transaction request register
on page 409
0x10
SglReqSrcReg
Source single transaction request register
on page 410
0x18
SglReqDstReg
Destination single transaction request register
on page 411
0x20
LstSrcReg
Source last transaction request register
on page 411
0x28
LstDstReg
Destination last transaction request register
on page 412
Doc ID 018904 Rev 3
RM0089
12.10.2
Direct memory access controllers (DMAC)
Software handshake registers descriptions
ReqSrcReg
Source software transaction request register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
SRC_REQ_WE
SRC_REQ
R
W
R/W
Address:
Software handshake registersBaseAddress + 0x0
Type:
R/W
Reset:
0x0
Description:
Source software transaction request register
2
1
0
[15:8] SRC_REQ_WE: Source request write enable.
0: Write disabled
1: Write enabled
[7:0] SRC_REQ: Source request. A bit of this field can be written only if the corresponding bit of
SRC_REQ_WE field is asserted on the same AHB cycle.
ReqDstReg
Destination software transaction request register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
DST_REQ_WE
DST_REQ
R
W
R/W
Address:
Software handshake registersBaseAddress + 0x8
Type:
R/W
Reset:
0x0
Description:
9
RESERVED
2
1
0
Destination software transaction request register
[15:8] DST_REQ_WE: Destination request write enable.
0: Write disabled
1: Write enabled
[7:0] DST_REQ: Destination request. A bit of this field can be written only if the corresponding bit of
DST_REQ_WE field is asserted on the same AHB cycle.
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Direct memory access controllers (DMAC)
SglReqSrcReg
RM0089
Source single transaction request register
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
SRC_SGLREQ
8
SRC_SGLREQ_WE
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R/W
Address:
Software handshake registersBaseAddress + 0x10
Type:
R/W
Reset:
0x0
Description:
Source single transaction request register
[15:8] SRC_SGLREQ_WE: Source single request write enable.
0: Write disabled
1: Write enabled
[7:0] SRC_SGLREQ: Source single request. A bit of this field can be written only if the
corresponding bit of SRC_SGLREQ_WE field is asserted on the same AHB cycle.
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1
0
RM0089
Direct memory access controllers (DMAC)
SglReqDstReg
Destination single transaction request register
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
DST_SGLREQ
8
DST_SGLREQ_WE
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R/W
Address:
Software handshake registersBaseAddress + 0x18
Type:
R/W
Reset:
0x0
Description:
Destination single transaction request register
2
1
0
[15:8] DST_SGLREQ_WE: Destination single request write enable.
0: Write disabled
1: Write enabled
[7:0] DST_SGLREQ: Destination single request. A bit of this field can be written only if the
corresponding bit of DST_SGLREQ_WE field is asserted on the same AHB cycle.
LstSrcReg
Source last transaction request register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
LSTSRC_WE
LSTSRC
R
W
R/W
Address:
Software handshake registersBaseAddress + 0x20
Type:
R/W
Reset:
0x0
Description:
9
RESERVED
2
1
0
Source last transaction request register
[15:8] LSTSRC_WE: Source last request write enable.
0: Write disabled
1: Write enabled
[7:0] LSTSRC: Source last request. A bit of this field can be written only if the corresponding bit of
LSTSRC_WE field is asserted on the same AHB cycle.
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Direct memory access controllers (DMAC)
LstDstReg
RM0089
Destination last transaction request register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
LSTDST_WE
LSTDST
R
W
R/W
Address:
Software handshake registersBaseAddress + 0x28
Type:
R/W
Reset:
0x0
Description:
Destination last transaction request register
2
1
0
[15:8] LSTDST_WE: Destination last request write enable.
0: Write disabled
1: Write enabled
[7:0] LSTDST: Destination last request. A bit of this field can be written only if the corresponding bit
of LSTDST_WE field is asserted on the same AHB cycle.
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Direct memory access controllers (DMAC)
12.11
Miscellaneous registers
12.11.1
Miscellaneous register summary
Table 84.
Offset
12.11.2
Miscellaneous register list
Register name
Description
Page
0x0
DmaCfgReg
DMA configuration register
on page 413
0x8
ChEnReg
Channel enable register
on page 414
0x10
DmaIdReg
DMA ID register
on page 414
0x18
DmaTestReg
DMA test register
on page 415
0x30
DMA_COMP_PARAMS_6
Component parameters registers
on page 416
0x38
DMA_COMP_PARAMS_5
Component parameters registers
on page 417
0x40
DMA_COMP_PARAMS_4
Component parameters registers
on page 418
0x48
DMA_COMP_PARAMS_3
Component parameters registers
on page 420
0x50
DMA_COMP_PARAMS_2
Component parameters registers
on page 422
0x58
DMA_COMP_PARAMS_1
Component parameters registers
on page 424
0x60
DmaCompID
DMA component ID register
on page 425
Miscellaneous register descriptions
DmaCfgReg
DMA configuration register
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
7
6
5
4
3
2
1
0
DMA_EN
8
R
R/
W
Address:
Miscellaneous registersBaseAddress + 0x0
Type:
R/W
Reset:
Undefined
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DMA configuration register
[0] DMA_EN: DMA global enable.
0: DMA disabled
1: DMA enabled
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Direct memory access controllers (DMAC)
RM0089
ChEnReg
Channel enable register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
CH_EN_WE
CH_EN
R
W
R/W
Address:
Miscellaneous registersBaseAddress + 0x8
Type:
R/W
Reset:
Undefined
Description:
Channel enable register
2
1
0
[15:8] CH_EN_WE: Channel enable write enable.
0: Write disabled
1: Write enabled
[7:0] CH_EN:
0: Disable the channel
1: Enable the channel
A bit of this field can be written only if the corresponding bit of CH_EN_WE field is asserted on
the same AHB cycle.
All bits of this field are cleared when DmaCfgReg.DMA_EN is 0.
The bit related to a channel is automatically cleared by hardware to disable it after the last
transfer to the destination has completed.
DmaIdReg
DMA ID register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DMAH_ID_NUM
R
Address:
Miscellaneous registersBaseAddress + 0x10
Type:
R
Reset:
0x0
Description:
DMA ID register
[31:0] DMAH_ID_NUM: Hardcoded DMAC peripheral ID.
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9
8
7
6
5
4
3
2
1
0
RM0089
Direct memory access controllers (DMAC)
DmaTestReg
DMA test register
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
8
7
6
5
4
3
2
1
0
TEST_SLV_IF
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
Address:
Miscellaneous registersBaseAddress + 0x18
Type:
R/W
Reset:
Undefined
Description:
DMA test register
[0] TEST_SLV_IF: AHB slave interface test mode.
0: normal mode
1: test mode
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Direct memory access controllers (DMAC)
RM0089
DMA_COMP_PARAMS_6
Component parameters registers
RESERVED
CH7_FIFO_DEPTH
CH7_SMS
CH7_LMS
CH7_DMS
CH7_MAX_MULT_SIZE
CH7_FC
CH7_HC_LLP
CH7_CTL_WB_EN
CH7_MULTI_BLK_EN
CH7_LOCK_EN
CH7_SRC_GAT_EN
CH7_DST_SCA_EN
CH7_STAT_SRC
CH7_STAT_DST
CH7_STW
CH7_DTW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
9
8
7
6
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
Address:
Miscellaneous registersBaseAddress + 0x30
Type:
R
Reset:
Undefined
Description:
Component parameters registers
[62:60] CH7_FIFO_DEPTH: DMAH_CH7_FIFO_DEPTH parameter.
[59:57] CH7_SMS: DMAH_CH7_SMS parameter.
[56:54] CH7_LMS: DMAH_CH7_LMS parameter.
[53:51] CH7_DMS: DMAH_CH7_DMS parameter.
[50:48] CH7_MAX_MULT_SIZE: DMAH_CH7_MAX_MULT_SIZE parameter.
[47:46] CH7_FC: DMAH_CH7_FC parameter.
[45] CH7_HC_LLP: DMAH_CH7_HC_LLP parameter.
[44] CH7_CTL_WB_EN: DMAH_CH7_CTL_WB_EN parameter.
[43] CH7_MULTI_BLK_EN: DMAH_CH7_MULTI_BLK_EN parameter.
[42] CH7_LOCK_EN: DMAH_CH7_LOCK_EN parameter.
[41] CH7_SRC_GAT_EN: DMAH_CH7_SRC_GAT_EN parameter.
[40] CH7_DST_SCA_EN: DMAH_CH7_DST_SCA_EN parameter.
[39] CH7_STAT_SRC: DMAH_CH7_STAT_SRC parameter.
[38] CH7_STAT_DST: DMAH_CH7_STAT_DST parameter.
[37:35] CH7_STW: DMAH_CH7_STW parameter.
[34:32] CH7_DTW: DMAH_CH7_DTW parameter.
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4
3
2
1
0
RM0089
Direct memory access controllers (DMAC)
DMA_COMP_PARAMS_5
Component parameters registers
RESERVED
CH5_FIFO_DEPTH
CH5_SMS
CH5_LMS
CH5_DMS
CH5_MAX_MULT_SIZE
CH5_FC
CH5_HC_LLP
CH5_CTL_WB_EN
CH5_MULTI_BLK_EN
CH5_LOCK_EN
CH5_SRC_GAT_EN
CH5_DST_SCA_EN
CH5_STAT_SRC
CH5_STAT_DST
CH5_STW
CH5_DTW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
CH6_MULTI_BLK_EN
CH6_LOCK_EN
CH6_SRC_GAT_EN
CH6_DST_SCA_EN
CH6_STAT_SRC
CH6_STAT_DST
CH6_STW
CH6_DTW
1
CH6_CTL_WB_EN
2
CH6_HC_LLP
3
CH6_FC
4
CH6_MAX_MULT_SIZE
5
CH6_DMS
6
CH6_LMS
7
CH6_SMS
8
CH6_FIFO_DEPTH
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Address:
Miscellaneous registersBaseAddress + 0x38
Type:
R
Reset:
Undefined
Description:
Component parameters registers
0
[62:60] CH5_FIFO_DEPTH: DMAH_CH5_FIFO_DEPTH parameter.
[59:57] CH5_SMS: DMAH_CH5_SMS parameter.
[56:54] CH5_LMS: DMAH_CH5_LMS parameter.
[53:51] CH5_DMS: DMAH_CH5_DMS parameter.
[50:48] CH5_MAX_MULT_SIZE: DMAH_CH5_MAX_MULT_SIZE parameter.
[47:46] CH5_FC: DMAH_CH5_FC parameter.
[45] CH5_HC_LLP: DMAH_CH5_HC_LLP parameter.
[44] CH5_CTL_WB_EN: DMAH_CH5_CTL_WB_EN parameter.
[43] CH5_MULTI_BLK_EN: DMAH_CH5_MULTI_BLK_EN parameter.
[42] CH5_LOCK_EN: DMAH_CH5_LOCK_EN parameter.
[41] CH5_SRC_GAT_EN: DMAH_CH5_SRC_GAT_EN parameter.
[40] CH5_DST_SCA_EN: DMAH_CH5_DST_SCA_EN parameter.
[39] CH5_STAT_SRC: DMAH_CH5_STAT_SRC parameter.
[38] CH5_STAT_DST: DMAH_CH5_STAT_DST parameter.
[37:35] CH5_STW: DMAH_CH5_STW parameter.
[34:32] CH5_DTW: DMAH_CH5_DTW parameter.
[30:28] CH6_FIFO_DEPTH: DMAH_CH6_FIFO_DEPTH parameter.
[27:25] CH6_SMS: DMAH_CH6_SMS parameter.
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Direct memory access controllers (DMAC)
RM0089
[24:22] CH6_LMS: DMAH_CH6_LMS parameter.
[21:19] CH6_DMS: DMAH_CH6_DMS parameter.
[18:16] CH6_MAX_MULT_SIZE: DMAH_CH6_MAX_MULT_SIZE parameter.
[15:14] CH6_FC: DMAH_CH6_FC parameter.
[13] CH6_HC_LLP: DMAH_CH6_HC_LLP parameter.
[12] CH6_CTL_WB_EN: DMAH_CH6_CTL_WB_EN parameter.
[11] CH6_MULTI_BLK_EN: DMAH_CH6_MULTI_BLK_EN parameter.
[10] CH6_LOCK_EN: DMAH_CH6_LOCK_EN parameter.
[9] CH6_SRC_GAT_EN: DMAH_CH6_SRC_GAT_EN parameter.
[8] CH6_DST_SCA_EN: DMAH_CH6_DST_SCA_EN parameter.
[7] CH6_STAT_SRC: DMAH_CH6_STAT_SRC parameter.
[6] CH6_STAT_DST: DMAH_CH6_STAT_DST parameter.
[5:3] CH6_STW: DMAH_CH6_STW parameter.
[2:0] CH6_DTW: DMAH_CH6_DTW parameter.
DMA_COMP_PARAMS_4
Component parameters registers
CH3_DMS
CH3_MAX_MULT_SIZE
CH3_FC
CH3_HC_LLP
CH3_CTL_WB_EN
CH3_MULTI_BLK_EN
CH3_LOCK_EN
CH3_SRC_GAT_EN
CH3_DST_SCA_EN
R
R
R
R
R
R
R
R
R
R
CH3_DTW
CH3_LMS
R
CH3_STW
CH3_SMS
R
CH3_STAT_DST
CH3_FIFO_DEPTH
R
CH3_STAT_SRC
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
CH4_DMS
CH4_MAX_MULT_SIZE
CH4_FC
CH4_HC_LLP
CH4_CTL_WB_EN
CH4_MULTI_BLK_EN
CH4_LOCK_EN
CH4_SRC_GAT_EN
CH4_DST_SCA_EN
CH4_STAT_SRC
CH4_STAT_DST
CH4_STW
CH4_DTW
1
CH4_LMS
2
CH4_SMS
3
CH4_FIFO_DEPTH
4
RESERVED
5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Address:
Miscellaneous registersBaseAddress + 0x40
Type:
R
Reset:
Undefined
Description:
Component parameters registers
[62:60] CH3_FIFO_DEPTH: DMAH_CH3_FIFO_DEPTH parameter.
[59:57] CH3_SMS: DMAH_CH3_SMS parameter.
[56:54] CH3_LMS: DMAH_CH3_LMS parameter.
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Direct memory access controllers (DMAC)
[53:51] CH3_DMS: DMAH_CH3_DMS parameter.
[50:48] CH3_MAX_MULT_SIZE: DMAH_CH3_MAX_MULT_SIZE parameter.
[47:46] CH3_FC: DMAH_CH3_FC parameter.
[45] CH3_HC_LLP: DMAH_CH3_HC_LLP parameter.
[44] CH3_CTL_WB_EN: DMAH_CH3_CTL_WB_EN parameter.
[43] CH3_MULTI_BLK_EN: DMAH_CH3_MULTI_BLK_EN parameter.
[42] CH3_LOCK_EN: DMAH_CH3_LOCK_EN parameter.
[41] CH3_SRC_GAT_EN: DMAH_CH3_SRC_GAT_EN parameter.
[40] CH3_DST_SCA_EN: DMAH_CH3_DST_SCA_EN parameter.
[39] CH3_STAT_SRC: DMAH_CH3_STAT_SRC parameter.
[38] CH3_STAT_DST: DMAH_CH3_STAT_DST parameter.
[37:35] CH3_STW: DMAH_CH3_STW parameter.
[34:32] CH3_DTW: DMAH_CH3_DTW parameter.
[30:28] CH4_FIFO_DEPTH: DMAH_CH4_FIFO_DEPTH parameter.
[27:25] CH4_SMS: DMAH_CH4_SMS parameter.
[24:22] CH4_LMS: DMAH_CH4_LMS parameter.
[21:19] CH4_DMS: DMAH_CH4_DMS parameter.
[18:16] CH4_MAX_MULT_SIZE: DMAH_CH4_MAX_MULT_SIZE parameter.
[15:14] CH4_FC: DMAH_CH4_FC parameter.
[13] CH4_HC_LLP: DMAH_CH4_HC_LLP parameter.
[12] CH4_CTL_WB_EN: DMAH_CH4_CTL_WB_EN parameter.
[11] CH4_MULTI_BLK_EN: DMAH_CH4_MULTI_BLK_EN parameter.
[10] CH4_LOCK_EN: DMAH_CH4_LOCK_EN parameter.
[9] CH4_SRC_GAT_EN: DMAH_CH4_SRC_GAT_EN parameter.
[8] CH4_DST_SCA_EN: DMAH_CH4_DST_SCA_EN parameter.
[7] CH4_STAT_SRC: DMAH_CH4_STAT_SRC parameter.
[6] CH4_STAT_DST: DMAH_CH4_STAT_DST parameter.
[5:3] CH4_STW: DMAH_CH4_STW parameter.
[2:0] CH4_DTW: DMAH_CH4_DTW parameter.
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Direct memory access controllers (DMAC)
RM0089
DMA_COMP_PARAMS_3
Component parameters registers
RESERVED
CH1_FIFO_DEPTH
CH1_SMS
CH1_LMS
CH1_DMS
CH1_MAX_MULT_SIZE
CH1_FC
CH1_HC_LLP
CH1_CTL_WB_EN
CH1_MULTI_BLK_EN
CH1_LOCK_EN
CH1_SRC_GAT_EN
CH1_DST_SCA_EN
CH1_STAT_SRC
CH1_STAT_DST
CH1_STW
CH1_DTW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
CH2_MULTI_BLK_EN
CH2_LOCK_EN
CH2_SRC_GAT_EN
CH2_DST_SCA_EN
CH2_STAT_SRC
CH2_STAT_DST
CH2_STW
CH2_DTW
1
CH2_CTL_WB_EN
2
CH2_HC_LLP
3
CH2_FC
4
CH2_MAX_MULT_SIZE
5
CH2_DMS
6
CH2_LMS
7
CH2_SMS
8
CH2_FIFO_DEPTH
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Address:
Miscellaneous registersBaseAddress + 0x48
Type:
R
Reset:
Undefined
Description:
Component parameters registers
[62:60] CH1_FIFO_DEPTH: DMAH_CH1_FIFO_DEPTH parameter.
[59:57] CH1_SMS: DMAH_CH1_SMS parameter.
[56:54] CH1_LMS: DMAH_CH1_LMS parameter.
[53:51] CH1_DMS: DMAH_CH1_DMS parameter.
[50:48] CH1_MAX_MULT_SIZE: DMAH_CH1_MAX_MULT_SIZE parameter.
[47:46] CH1_FC: DMAH_CH1_FC parameter.
[45] CH1_HC_LLP: DMAH_CH1_HC_LLP parameter.
[44] CH1_CTL_WB_EN: DMAH_CH1_CTL_WB_EN parameter.
[43] CH1_MULTI_BLK_EN: DMAH_CH1_MULTI_BLK_EN parameter.
[42] CH1_LOCK_EN: DMAH_CH1_LOCK_EN parameter.
[41] CH1_SRC_GAT_EN: DMAH_CH1_SRC_GAT_EN parameter.
[40] CH1_DST_SCA_EN: DMAH_CH1_DST_SCA_EN parameter.
[39] CH1_STAT_SRC: DMAH_CH1_STAT_SRC parameter.
[38] CH1_STAT_DST: DMAH_CH1_STAT_DST parameter.
[37:35] CH1_STW: DMAH_CH1_STW parameter.
[34:32] CH1_DTW: DMAH_CH1_DTW parameter.
[30:28] CH2_FIFO_DEPTH: DMAH_CH2_FIFO_DEPTH parameter.
[27:25] CH2_SMS: DMAH_CH2_SMS parameter.
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[24:22] CH2_LMS: DMAH_CH2_LMS parameter.
[21:19] CH2_DMS: DMAH_CH2_DMS parameter.
[18:16] CH2_MAX_MULT_SIZE: DMAH_CH2_MAX_MULT_SIZE parameter.
[15:14] CH2_FC: DMAH_CH2_FC parameter.
[13] CH2_HC_LLP: DMAH_CH2_HC_LLP parameter.
[12] CH2_CTL_WB_EN: DMAH_CH2_CTL_WB_EN parameter.
[11] CH2_MULTI_BLK_EN: DMAH_CH2_MULTI_BLK_EN parameter.
[10] CH2_LOCK_EN: DMAH_CH2_LOCK_EN parameter.
[9] CH2_SRC_GAT_EN: DMAH_CH2_SRC_GAT_EN parameter.
[8] CH2_DST_SCA_EN: DMAH_CH2_DST_SCA_EN parameter.
[7] CH2_STAT_SRC: DMAH_CH2_STAT_SRC parameter.
[6] CH2_STAT_DST: DMAH_CH2_STAT_DST parameter.
[5:3] CH2_STW: DMAH_CH2_STW parameter.
[2:0] CH2_DTW: DMAH_CH2_DTW parameter.
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RM0089
DMA_COMP_PARAMS_2
Component parameters registers
CH7_MULTI_BLK_TYPE
CH6_MULTI_BLK_TYPE
CH5_MULTI_BLK_TYPE
CH4_MULTI_BLK_TYPE
CH3_MULTI_BLK_TYPE
CH2_MULTI_BLK_TYPE
CH1_MULTI_BLK_TYPE
CH0_MULTI_BLK_TYPE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
R
R
R
R
CH0_MULTI_BLK_EN
CH0_LOCK_EN
CH0_SRC_GAT_EN
CH0_DST_SCA_EN
CH0_STAT_SRC
CH0_STAT_DST
CH0_STW
CH0_DTW
1
CH0_CTL_WB_EN
2
CH0_HC_LLP
3
CH0_FC
4
CH0_MAX_MULT_SIZE
5
CH0_DMS
6
CH0_LMS
7
CH0_SMS
8
CH0_FIFO_DEPTH
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Address:
Miscellaneous registersBaseAddress + 0x50
Type:
R
Reset:
Undefined
Description:
Component parameters registers
[63:60] CH7_MULTI_BLK_TYPE: DMAH_CH7_MULTI_BLK_TYPE parameter.
[59:56] CH6_MULTI_BLK_TYPE: DMAH_CH6_MULTI_BLK_TYPE parameter.
[55:52] CH5_MULTI_BLK_TYPE: DMAH_CH5_MULTI_BLK_TYPE parameter.
[51:48] CH4_MULTI_BLK_TYPE: DMAH_CH4_MULTI_BLK_TYPE parameter.
[47:44] CH3_MULTI_BLK_TYPE: DMAH_CH3_MULTI_BLK_TYPE parameter.
[43:40] CH2_MULTI_BLK_TYPE: DMAH_CH2_MULTI_BLK_TYPE parameter.
[39:36] CH1_MULTI_BLK_TYPE: DMAH_CH1_MULTI_BLK_TYPE parameter.
[35:32] CH0_MULTI_BLK_TYPE: DMAH_CH0_MULTI_BLK_TYPE parameter.
[30:28] CH0_FIFO_DEPTH: DMAH_CH0_FIFO_DEPTH parameter.
[27:25] CH0_SMS: DMAH_CH0_SMS parameter.
[24:22] CH0_LMS: DMAH_CH0_LMS parameter.
[21:19] CH0_DMS: DMAH_CH0_DMS parameter.
[18:16] CH0_MAX_MULT_SIZE: DMAH_CH0_MAX_MULT_SIZE parameter.
[15:14] CH0_FC: DMAH_CH0_FC parameter.
[13] CH0_HC_LLP: DMAH_CH0_HC_LLP parameter.
[12] CH0_CTL_WB_EN: DMAH_CH0_CTL_WB_EN parameter.
[11] CH0_MULTI_BLK_EN: DMAH_CH0_MULTI_BLK_EN parameter.
[10] CH0_LOCK_EN: DMAH_CH0_LOCK_EN parameter.
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[9] CH0_SRC_GAT_EN: DMAH_CH0_SRC_GAT_EN parameter.
[8] CH0_DST_SCA_EN: DMAH_CH0_DST_SCA_EN parameter.
[7] CH0_STAT_SRC: DMAH_CH0_STAT_SRC parameter.
[6] CH0_STAT_DST: DMAH_CH0_STAT_DST parameter.
[5:3] CH0_STW: DMAH_CH0_STW parameter.
[2:0] CH0_DTW: DMAH_CH0_DTW parameter.
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RM0089
DMA_COMP_PARAMS_1
Component parameters registers
STATIC_ENDIAN_SELECT
NUM_HS_INT
M4_HDATA_WIDTH
M3_HDATA_WIDTH
M2_HDATA_WIDTH
M1_HDATA_WIDTH
S_HDATA_WIDTH
NUM_MASTER_INT
NUM_CHANNELS
RESERVED
MAX_ABRST
INTR_IO
BIG_ENDIAN
R
ADD_ENCODED_PARAMS
RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
R
R
R
R
R
R
R
R
R
R
R
R
R
R
2
1
CH0_MAX_BLK_SIZE
3
CH1_MAX_BLK_SIZE
4
CH2_MAX_BLK_SIZE
5
CH3_MAX_BLK_SIZE
6
CH4_MAX_BLK_SIZE
7
CH5_MAX_BLK_SIZE
8
CH6_MAX_BLK_SIZE
9
CH7_MAX_BLK_SIZE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R
Address:
Miscellaneous registersBaseAddress + 0x58
Type:
R
Reset:
Undefined
Description:
Component parameters registers
[61] STATIC_ENDIAN_SELECT: DMAH_STATIC_ENDIAN_SELECT parameter.
[60] ADD_ENCODED_PARAMS: DMAH_ADD_ENCODED_PARAMS parameter.
[59:55] NUM_HS_INT: DMAH_NUM_HS_INT parameter.
[54:53] M4_HDATA_WIDTH: DMAH_M4_HDATA_WIDTH parameter.
[52:51] M3_HDATA_WIDTH: DMAH_M3_HDATA_WIDTH parameter.
[50:49] M2_HDATA_WIDTH: DMAH_M2_HDATA_WIDTH parameter.
[48:47] M1_HDATA_WIDTH: DMAH_M1_HDATA_WIDTH parameter.
[46:45] S_HDATA_WIDTH: DMAH_S_HDATA_WIDTH parameter.
[44:43] NUM_MASTER_INT: DMAH_NUM_MASTER_INT parameter.
[42:40] NUM_CHANNELS: DMAH_NUM_CHANNELS parameter.
[35] MAX_ABRST: DMAH_MAX_ABRST parameter.
[34:33] INTR_IO: DMAH_INTR_IO parameter.
[32] BIG_ENDIAN: DMAH_BIG_ENDIAN parameter.
[31:28] CH7_MAX_BLK_SIZE: DMAH_CH7_MAX_BLK_SIZE parameter.
[27:24] CH6_MAX_BLK_SIZE: DMAH_CH6_MAX_BLK_SIZE parameter.
[23:20] CH5_MAX_BLK_SIZE: DMAH_CH5_MAX_BLK_SIZE parameter.
[19:16] CH4_MAX_BLK_SIZE: DMAH_CH4_MAX_BLK_SIZE parameter.
[15:12] CH3_MAX_BLK_SIZE: DMAH_CH3_MAX_BLK_SIZE parameter.
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[11:8] CH2_MAX_BLK_SIZE: DMAH_CH2_MAX_BLK_SIZE parameter.
[7:4] CH1_MAX_BLK_SIZE: DMAH_CH1_MAX_BLK_SIZE parameter.
[3:0] CH0_MAX_BLK_SIZE: DMAH_CH0_MAX_BLK_SIZE parameter.
DmaCompID
DMA component ID register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DMA_COMP_VERSION
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DMA_COMP_TYPE
R
Address:
Miscellaneous registersBaseAddress + 0x60
Type:
R
Reset:
0x3231342A44571110
Description:
DMA component ID register
[63:32] DMA_COMP_VERSION: DMA component version - see release notes.
[31:0] DMA_COMP_TYPE: DMA component identifier - fixed at 0x44571110
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Cryptographic co-processor (C3)
RM0089
13
Cryptographic co-processor (C3)
13.1
Register summary
Table 85.
C3 register list
Offset
Register name
Description
Page
0x0
SYS_SCR
Status and control register
on page 428
0x4
SYS_STR
Channel status register
on page 430
0x3F0
SYS_VER
Hardware version and revision
on page 431
0x3FC
SYS_HWID
Hardware ID
on page 431
0x400:0x5FC
(0x04)
HIF_MP[0:127]
Memory page at address HIF_MPBAR+HIF_MP;
MP =[0x000-0x1FF]
on page 432
0x700
HIF_MSIZE
Memory size in bytes
on page 432
0x704
HIF_MBAR
Memory Base Address Register
on page 433
0x708
HIF_MCR
Memory Control Register
on page 433
0x70C
HIF_MPBAR
Memory Page Base Address Register
on page 434
0x710
HIF_MAAR
Memory Access Address Register
on page 435
0x714
HIF_MADR
Memory Access Data Register
on page 435
0x744
HIF_NBAR
Byte Bucket Base Address Register
on page 435
0x748
HIF_NCR
Byte Bucket Control register
on page 436
0x1000
ID0_SCR
Instruction Dispatcher #0 Status and Control Register
on page 436
0x1010
ID0_IP
Instruction Dispatcher #0 Instruction Pointer Register
on page 438
0x1020
ID0_IR0
Instruction Dispatcher #0 Instruction Word 0 Register
on page 439
0x1024
ID0_IR1
Instruction Dispatcher #0 Instruction Word 1 Register on page 439
0x1028
ID0_IR2
Instruction Dispatcher #0 Instruction Word 2 Register on page 439
0x102C
ID0_IR3
Instruction Dispatcher #0 Instruction Word 3 Register on page 440
0x1400
ID1_SCR
Instruction Dispatcher #1 Status and Control Register
on page 440
0x1410
ID1_IP
Instruction Dispatcher #1 Instruction Pointer Register
on page 442
0x1420
ID1_IR0
Instruction Dispatcher #1 Instruction Word 0 Register
on page 443
0x1424
ID1_IR1
Instruction Dispatcher #1 Instruction Word 1 Register on page 443
0x1428
ID1_IR2
Instruction Dispatcher #1 Instruction Word 2 Register on page 443
0x142C
ID1_IR3
Instruction Dispatcher #1 Instruction Word 3 Register on page 444
0x2200
MOVE_SCR
Status and Control register
on page 444
0x2210
MOVE_SRCR
Source Register (Read Pointer)
on page 445
0x2214
MOVE_DSTR
Destination Register (Write Pointer)
on page 445
0x2218
MOVE_CNTR
Count Register
on page 445
0x23FC
MOVE_IR
Channel ID
on page 446
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Doc ID 018904 Rev 3
RM0089
Table 85.
Offset
Cryptographic co-processor (C3)
C3 register list (continued)
Register name
Description
Page
0x2600
DES_SCR
Status and Control register
on page 446
0x27FC
DES_IR
Channel ID
on page 447
0x2A00
MPCM_SCR
Status and Control register
on page 447
0x2A10
MPCM_SRCR
Source Register (Read Pointer)
on page 447
0x2A14
MPCM_DSTR
Destination Register (Write Pointer)
on page 448
0x2A18
MPCM_CNTR
Count Register
on page 448
0x2BFC
MPCM_IR
Channel ID
on page 448
0x2E00
UHH_SCR
Status and Control register
on page 449
0x2FFC
UHH_IR
Channel ID
on page 449
0x3200
UHH2_SCR
Status and Control register
on page 449
0x33FC
UHH2_IR
Channel ID
on page 450
0x3600
PKA_SCR
Status and Control register
on page 450
0x3610
PKA_SRCR
Source Register (Read Pointer)
on page 451
0x3614
PKA_PSRCR
Source Register (Read Pointer) for the public
structure
on page 451
0x3618
PKA_DSTR
Destination Register (Write Pointer)
on page 451
0x361C
PKA_CNTR
Count Register
on page 452
0x37FC
PKA_IR
Channel ID
on page 452
0x3A00
RNG_SCR
Status and Control register
on page 452
0x3A14
RNG_DSTR
Destination Register (Write Pointer)
on page 453
0x3A18
RNG_CNTR
Count Register
on page 453
0x3BFC
RNG_IR
Channel ID
on page 453
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Cryptographic co-processor (C3)
13.2
RM0089
Register descriptions
SYS_SCR
Status and control register
C1S
C0S
0
C2S
1
C3S
2
C4S
3
C5S
W
4
C6S
ISD0
W
5
RESERVED
ISD1
R
6
ARST
RESERVED
R
7
BEND
IDS0
R
8
ISA
IDS1
R
9
CISR
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
W
R/
W
R/
W
W
R
R
R
R
R
R
R
R
Address:
C3BaseAddress + 0x0
Type:
R/W
Reset:
0xA002AAA
Description:
Status and control register
[27:26] IDS1: Status of Instruction Dispatcher ID1 (the same than the one in ID1_SCR)
IDS1[1:0]
0 0 Not Present: This Instruction Dispatcher does not exist in Hardware
0 1 Error: The Instruction Dispatcher has stopped the execution of a program because of an
error. Error cause can be analyzed using bits 29-24 of ID_SCR
1 0 Idle: The Instruction Dispatcher has successfully terminated the execution of a program and
is ready to accept a new Instruction Pointer
1 1 Run: The Instruction Dispatcher is executing a program.
[25:24] IDS0: Status of Instruction Dispatcher ID0 (the same than the one in ID0_SCR)
IDS0[1:0]
0 0 Not Present: This Instruction Dispatcher does not exist in Hardware
0 1 Error: The Instruction Dispatcher has stopped the execution of a program because of an
error. Error cause can be analyzed using bits 29-24 of ID_SCR
1 0 Idle: The Instruction Dispatcher has successfully terminated the execution of a program and
is ready to accept a new Instruction Pointer
1 1 Run: The Instruction Dispatcher is executing a program.
[21] ISD1: Interrupt States Instruction Dispatcher ID1 (the same than the one in ID1_SCR).
1 - The instruction dispatcher is requesting an interrupt
Interrupt Status (IS) of instruction dispatcher can be cleared writing 1 to this bit, 0 has no effect
[20] ISD0: Interrupt States Instruction Dispatcher ID0 (the same than the one in ID0_SCR).
1 - The instruction dispatcher is requesting an interrupt
Interrupt Status (IS) of instruction dispatcher can be cleared writing 1 to this bit, 0 has no effect
[19] ISA: The Interrupt Status of All Instruction Dispatchers (ISA) is the logical OR of bits ISD1ISD0. This bit represents the state of the Interrupt pin of the C3 component. Writing one to this
flag has the same effect as writing one in all ISD1-ISD0.
[18] CISR: If the Clear Interrupt Status on Read bit (CISR) is set, clearing of Interrupt States is
performed by reading the Status and Control Register of the System (SYS_SCR). The Status
and Control Register of Instruction Dispatchers (IDn_SCR) is not affected by this bit
[17] BEND: Not implemented. This bit should be set to zero.
[16] ARST: The whole C3 can be reset using this bit. The reset is done asynchronously in Hardware
guaranteeing a well known state after its execution. A special Hardware block takes care of
correct timings for the reset sequence. It takes about 6 clock cycles for the Hardware reset. The
Internal Memory may not be cleared.
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Cryptographic co-processor (C3)
[13:12] C6S: The C6S (Channel 6 Status) bits indicate in which state Channel 6 is (the same than the
one in IDn_SCR):
C6S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[11:10] C5S: The C5S (Channel 5Status) bits indicate in which state Channel 5 is (the same than the
one in IDn_SCR):
C5S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[9:8] C4S: The C4S (Channel 4 Status) bits indicate in which state Channel 4 is (the same than the
one in IDn_SCR):
C4S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[7:6] C3S: The C3S (Channel 3 Status) bits indicate in which state Channel 3 is (the same than the
one in IDn_SCR):
C3S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[5:4] C2S: The C2S (Channel 2 Status) bits indicate in which state Channel 2 is (the same than the
one in IDn_SCR):
C2S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[3:2] C1S: The C1S (Channel 1 Status) bits indicate in which state Channel 1 is. (the same than the
one in IDn_SCR):
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[1:0] C0S: The C0S (Channel 0 Status) bits indicate in which state Channel 0 is (the same than the
one in IDn_SCR):
C0S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
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RM0089
SYS_STR
Channel status register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
0
RESERVED
C6S
C5S
C4S
C3S
C2S
C1S
C0S
R
R
R
R
R
R
R
R
Address:
C3BaseAddress + 0x4
Type:
R/W
Reset:
0x2AAA
Description:
Channel status register
[13:12] C6S: The C6S (Channel 6 Status) bits indicate in which state Channel 6 is..
C6S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[11:10] C5S: The C5S (Channel 5Status) bits indicate in which state Channel 6 is..
C5S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[9:8] C4S: The C4S (Channel 4 Status) bits indicate in which state Channel 4 is..
C4S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[7:6] C3S: The C3S (Channel 3 Status) bits indicate in which state Channel 3 is..
C3S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
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Cryptographic co-processor (C3)
[5:4] C2S: The C2S (Channel 2 Status) bits indicate in which state Channel 2 is..
C2S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[3:2] C1S: The C1S (Channel 1 Status) bits indicate in which state Channel 1 is..
C1S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
[1:0] C0S: The C0S (Channel 0 Status) bits indicate in which state Channel 0 is..
C0S[1:0]
0 0 Not Present: The Channel does not exist in Hardware.
0 1 Error: The Channel is in error state, use Channel registers to know the cause.
1 0 The Channel is Idle and instructions can be dispatched to it
1 1 Busy: The Channel is executing instructions dispatched by an Instruction Dispatcher
SYS_VER
Hardware version and revision
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
HW_VER
HW_REV
HW_SRV
R
R
R
Address:
C3BaseAddress + 0x3F0
Type:
R
Reset:
0x3020000
Description:
6
5
4
3
2
1
0
Hardware version and revision
[31:24] HW_VER: This field contain the hardware version of the IP. This is always 3 (the v3 part in
C3v3)
[23:16] HW_REV: This field represent the RTL version
[15:0] HW_SRV: This field represent the RTL sub-version
SYS_HWID
Hardware ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
HWID
R
Address:
C3BaseAddress + 0x3FC
Type:
R
Reset:
0xFFFF 8000
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Cryptographic co-processor (C3)
Description:
RM0089
Hardware ID
[31:0] HWID: The Hardware ID register contains the Identifier of the Hardware. The Hardware ID has
no bit-field structure: the value is an index in a database table. There is currently no maintained
Hardware IDs Table. There are however a bunch of reserved Hardware IDs:
HWID Usage
0x0000000 Illegal value
0x12345678 Endianess test
0xFFFFxxxx Prototype on FPGA platform
HIF_MP[0:127]
Memory page at address HIF_MPBAR+HIF_MP;
MP =[0x000-0x1FF]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Internal Memory
R/W
Address:
C3BaseAddress + 0x400 + 0x04*x (x=0 to 127)
Type:
R/W
Reset:
0x0
Description:
Memory page at address HIF_MPBAR+HIF_MP; MP =[0x000-0x1FF]
[31:0] Internal Memory: A 512 Bytes page of the Internal Memory is mapped in the Memory Page
address range (0x000 to 0x1FF). The page number to be mapped is programmed using the
Memory Page Base Address Register (HIF_MPBAR). AHB Reads and Writes to the C3 Slave
Interface in this address space leads to Internal Memory access.
Accesses are always 32-bit wide - When there is no internal memory, any read access return a
null value. When a memory is present, it returns value inside memory which is unkown.
HIF_MSIZE
Memory size in bytes
6
5
4
3
2
1
0
RESERVED
7
MSIZE
8
R
R
R
Address:
C3BaseAddress + 0x700
Type:
R
Reset:
0x4000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Memory size in bytes
[16:2] MSIZE: This field represents the size of the internal Memory in Bytes. If an internal Memory
does not exist in Hardware this register will be zero. This is a way for the Software to know if an
internal Memory is there and what its size is. The maximum memory size is 64 kB so the
maximum value of MSIZE is 0x10000. The lower 2 bits of MSIZE are always zero (only 32 bit
wide memories are supported).
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Cryptographic co-processor (C3)
HIF_MBAR
Memory Base Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
MBAR
RESERVED
W
R
Address:
C3BaseAddress + 0x704
Type:
W
Reset:
0x0
Description:
Memory Base Address Register
6
5
4
3
2
1
0
[31:16] MBAR: 16-bit most significant part of internal Memory Base Address.
The Base Address of the Internal Memory can be programmed to any multiple of 64
kB.Channel and Instruction Dispatcher transactions that fall within a window of 64 kB starting
from MBAR are then routed to the Internal Memory (if enabled). The Internal Memory Base
Address can be changed at any time but the behaviour of the active transactions done in this
range is undefined. The Byte Bucket has priority if its Base Address (NBAR) is programmed
with the same value as MBAR
HIF_MCR
Memory Control Register
5
4
3
2
1
0
EMM
6
RESERVED
7
DAIW
8
DAIR
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R
R/
W
Address:
C3BaseAddress + 0x708
Type:
R/W
Reset:
0x0
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Description:
RM0089
Memory Control Register
[17] DAIR: Disable Auto Increment on Read
0 - Memory Access Address Register (HIF_MAAR) is auto incremented when an Internal
Memory location is read from AHB using the Memory Access Data Register (HIF_MADR).
1 - Memory Access Address Register (HIF_MAAR) auto increment is disabled on HIF_MADR
reads
[16] DAIW: Disable Auto Increment on Write
0 - Memory Access Address Register (HIF_MAAR) is auto incremented when an Internal
Memory location is written from AHB using the Memory Access Data Register (HIF_MADR).
1 - Memory Access Address Register (HIF_MAAR) auto increment is disabled on HIF_MADR
writes.
[0] EMM: Enable Memory Mapping
0 - Disable the Internal Memory. Transactions from Channels and Instruction Dispatchers go
either to the Bus or the Byte Bucket (if enabled). AHB slave accesses to the Internal Memory
are not affected by this bit: they are always enabled.
1 - Enable the Internal Memory
The Internal Memory must be enabled to allow Channels and Instruction Dispatchers to access
it. This is done using the Enable Memory Mapping bit (EMM). The correct procedure for the
Software to enable the Internal Memory is to first program its base address using HIF_MBAR
and then enable it by setting the EMM bit of HIF_MCR. The Internal Memory can be enabled or
disabled at any time but the behaviour of the active transactions done in this range is undefined.
Normally, when using the Address and Data registers pair (HIF_MAAR and HIF_MDAR) to
access Internal Memory locations from AHB, the Address register is auto incremented. To
disable this feature Disable Auto Increment on Read and Disable Auto Increment Write bits
(DAIR and DAIW) are offered.
HIF_MPBAR
Memory Page Base Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
PAGE
RESERVED
R
R/W
R
Address:
C3BaseAddress + 0x70C
Type:
R/W
Reset:
0x0
Description:
9
MBAR
2
1
0
Memory Page Base Address Register
[31:16] MBAR: This field report the base address value programmed inside the HIF_MBAR register
[15:9] PAGE: The value written in this field select which internal memory page (512 bytes) is mapped
inside the AHB memory space.
This 512 Bytes page of the Internal Memory is mapped on the AHB address space HIF_MP
(h000 to h01FF). The page is selected using bits P15-P9 of this registers.
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Cryptographic co-processor (C3)
HIF_MAAR
Memory Access Address Register
6
5
4
3
2
1
0
RESERVED
7
ADDRESS
8
R
R/W
R
Address:
C3BaseAddress + 0x710
Type:
R/W
Reset:
0x0
Description:
9
MBAR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Memory Access Address Register
[31:16] MBAR: This field report the base address value programmed inside the HIF_MBAR register
[15:2] ADDRESS: Address of the internal memory location used.
AHB slave accesses to the Memory Access Data Register (HIF_MADR) targets the Internal
Memory location programmed in the Memory Access Address Register (HIF_MAAR). Bits A15A2 are used for this. Address Register (HIF_MBAR). Bits 1-0 are always zero since only aligned
32 bit transactions are supported
HIF_MADR
Memory Access Data Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
HIF_MADR
R/W
Address:
C3BaseAddress + 0x714
Type:
R/W
Reset:
0x0
Description:
Memory Access Data Register
[31:0] HIF_MADR: The Internal Memory location which address is programmed in the Memory
Access Address Register (HIF_MAAR) can be accessed reading and writing the Memory
Access Data Register (HIF_MADR). By default, when reading or writing the Memory Access
Data Register, the Memory Access Address Register is auto incremented. This feature can be
disabled setting bits Disable Auto Increment on Read (DAIR) and/or Disable Auto Increment on
Write (DAIW) in the Memory Control Register (HIF_MCR)
HIF_NBAR
Byte Bucket Base Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
BB_BAR
RESERVED
W
R
Address:
C3BaseAddress + 0x744
Type:
W
Reset:
0x0
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
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Cryptographic co-processor (C3)
Description:
RM0089
Byte Bucket Base Address Register
[31:16] BB_BAR: Base Address of the Byte Bucket
The Base Address of the Byte Bucket can be programmed to any multiple of 64 kB. Bits 31-16
of NBAR are used for this. Channel and Instruction Dispatcher write transactions that fall within
a window of 64 kB starting from NBAR are then discarded by the Byte Bucket (if enabled). The
Byte Bucket Base Address can be changed at any time but the behaviour of the active
transactions done in this range is undefined. The Byte Bucket has priority if its Base Address
(NBAR) is programmed with the same value as the Memory Base Address (MBAR). Read
transactions are ignored by the Byte Bucket and are always routed either to the Bus or the
Memory
HIF_NCR
Byte Bucket Control register
Address:
C3BaseAddress + 0x748
Type:
R/W
Reset:
0x0
Description:
Byte Bucket Control register
8
7
6
5
4
3
2
1
0
ENM
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
[0] ENM: 0 - Disable the Byte Bucket. Transactions from Channels and Instruction Dispatchers go
either to the Bus or the Memory (if enabled).
1 - Enable the Byte Bucket
The Byte Bucket must be enabled to allow Channels and Instruction Dispatchers to discard
data using it. This is done using the Enable Byte Bucket Mapping bit (ENM). The correct
procedure for the Software to enable the Byte Bucket is to first program its base address using
HIF_NBAR and then enable it by setting the ENM bit of HIF_NCR. The Byte Bucket can be
enabled or disabled at any time but the behaviour of the active transactions done in this range is
undefined.
ID0_SCR
Instruction Dispatcher #0 Status and Control
Register
C2S
C1S
C0S
0
R/
W
R
R/
W
W
R
R
R
R
R
R
R
R
Address:
C3BaseAddress + 0x1000
Type:
R/W
Reset:
0x8000 2AAA
436/1728
1
C3S
R/
W
2
C4S
R/
W
3
C5S
R/
W
4
C6S
IES
R/
W
5
RESERVED
IS
R
6
RST
CDNX
R
7
IGR
CBSY
R
8
SSE
CERR
R
9
RESERVED
RESERVED
R
IER
BERR
R
SSC
IDS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Cryptographic co-processor (C3)
Description:
Instruction Dispatcher #0 Status and Control Register
[31:30] IDS: The IDS (Instruction Dispatcher Status) bits indicate the state in which the addressed
Instruction Dispatcher (ID) is.
IDS[1:0]
0 0 Not Present: This Instruction Dispatcher does not exist in Hardware
0 1 Error: The Instruction Dispatcher has stopped the execution of a program because of an
error. Error cause can be analyzed using bits 29-24 of ID_SCR
1 0 Idle: The Instruction Dispatcher has successfully terminated the execution of a program and
is ready to accept a new Instruction Pointer
1 1 Run: The Instruction Dispatcher is executing a program.
[29] BERR: Every module attached to the HIF receives its own Bus error signal. This signal is set by
the HIF if a bus error condition is detected for a Bus transaction initiated by the corresponding
module.This flag can be cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[26] CERR: Channels report their states to each Instruction Dispatcher. When the ID dispatches an
instruction to a Channel that is in error state or if the Channel goes to error state when it
executes the received instruction, the Instruction Dispatcher goes in turn in error state and this
bit is set.This flag can be cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[25] CBSY: Channel busy. Set when the Channel to which the current instruction was addressed is
busy. It is already running under control of another Instruction Dispatcher.This flag can be
cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[24] CDNX: Channel does not exist. The Channel to which the current instruction was addressed
does not exist in Hardware.This flag can be cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[23] IS: Interrupt status. This bit reflects the status of the Interrupt port of the Instruction Dispatcher.
Interrupt ports of every Instruction Dispatcher are ORed together to generate the final Interrupt
signal which drives the Interrupt Pin of the C3 component.This flag is cleared writing one to it,
resetting the Instruction Dispatcher or requesting an asynchronous master reset. Launching a
new program will not clear this flag. Writing zero has no effect.
[22] IES: Interrupt enable on stop.When set the Instruction Dispatcher generates an Interrupt on
normal
termination of a program execution (when the stop instruction executes). Clearing this bit will
not clear pending interrupt.
[21] IER: Interrupt enable on error. If set the Instruction Dispatcher generates an Interrupt when a
program encounters an error. The error cause can be analyzed through bits 29-24 of
ID_SCR.Clearing this bit will not clear pending interrupt.
Doc ID 018904 Rev 3
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Cryptographic co-processor (C3)
RM0089
[20] SSC: If the Instruction Dispatcher is put in Single Step Mode using bit SSE of ID_SCR it will
await for SSC to be set before executing/dispatching the next instruction. In this context, a
Single Step is defined as the execution/dispatching of the instruction and its argument. The first
instruction is not executed/dispatched launching a new program when SSE is set. Setting this
bit in Single Step Mode (SSE is set) executes/dispatches the next instruction. The bit bit is
cleared when the execution of the current single instruction terminates. Writing zero has no
effect
[19] SSE: Single Step Enable.
[17] IGR: Not implemented. This bit should be set to zero.
[16] RST: Each Instruction Dispatcher can be reset independently from each other using this bit. In
Hardware the reset is done synchronously and not all registers are affected by it. Following are
the effects of a synchronous reset: bits 29-16 of SCR are all cleared, the Instruction Dispatcher
goes in Idle state eventually aborting program execution and bits 31-30 (IDS) of SCR are set to
Idle. Writing one will Reset the instruction dispatcher. This bit is always read as zero
[13:12] C6S: Status of Channel 6 (the same than the one in SYS_SCR)
[11:10] C5S: Status of Channel 5 (the same than the one in SYS_SCR)
[9:8] C4S: Status of Channel 4 (the same than the one in SYS_SCR)
[7:6] C3S: Status of Channel 3 (the same than the one in SYS_SCR)
[5:4] C2S: Status of Channel 2 (the same than the one in SYS_SCR)
[3:2] C1S: Status of Channel 1 (the same than the one in SYS_SCR)
[1:0] C0S: Status of Channel 0 (the same than the one in SYS_SCR)
ID0_IP
Instruction Dispatcher #0 Instruction Pointer
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IP
R/W
Address:
C3BaseAddress + 0x1010
Type:
R/W
Reset:
0x0
Description:
Instruction Dispatcher #0 Instruction Pointer Register
[31:0] IP: The Instruction Pointer Register is used to store the pointer of the first instruction to be
fetched and to launch program execution. It can be read back at any time (particularly in Single
Step Mode) to know the address of the next instruction that will be executed. Effects of
changing Instruction Pointer while a program is running are unspecified. The Instruction Pointer
must be 32 bit aligned (the lower two bits are ignored and are always read zero). When an
Instruction Pointer is written the Instruction Dispatcher goes in run state, begins filling its
Instruction Queue and as soon as the first instruction is H1891available it executes/dispatches
it.
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RM0089
Cryptographic co-processor (C3)
ID0_IR0
Instruction Dispatcher #0 Instruction Word 0
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR0
R
Address:
C3BaseAddress + 0x1020
Type:
R
Reset:
0x0
Description:
Instruction Dispatcher #0 Instruction Word 0 Register
[31:0] IR0: Instruction Word 0 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
ID0_IR1
Instruction Dispatcher #0 Instruction Word 1
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR1
R
Address:
C3BaseAddress + 0x1024
Type:
R
Reset:
0x0
Description:
Instruction Dispatcher #0 Instruction Word 1 Register
[31:0] IR1: Instruction Word 1 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
ID0_IR2
Instruction Dispatcher #0 Instruction Word 2
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR2
R
Address:
C3BaseAddress + 0x1028
Type:
R
Reset:
0x0
Doc ID 018904 Rev 3
439/1728
Cryptographic co-processor (C3)
Description:
RM0089
Instruction Dispatcher #0 Instruction Word 2 Register
[31:0] IR2: Instruction Word 2 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
ID0_IR3
Instruction Dispatcher #0 Instruction Word 3
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR3
R
Address:
C3BaseAddress + 0x102C
Type:
R
Reset:
0x0
Description:
Instruction Dispatcher #0 Instruction Word 3 Register
[31:0] IR3: Instruction Word 3 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
ID1_SCR
Instruction Dispatcher #1 Status and Control
Register
C2S
C1S
C0S
0
R/
W
R
R/
W
W
R
R
R
R
R
R
R
R
Address:
C3BaseAddress + 0x1400
Type:
R/W
Reset:
0x8000 2AAA
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1
C3S
R/
W
2
C4S
R/
W
3
C5S
R/
W
4
C6S
IES
R/
W
5
RESERVED
IS
R
6
RST
CDNX
R
7
IGR
CBSY
R
8
SSE
CERR
R
9
RESERVED
RESERVED
R
IER
BERR
R
SSC
IDS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Cryptographic co-processor (C3)
Description:
Instruction Dispatcher #1 Status and Control Register
[31:30] IDS: The IDS (Instruction Dispatcher Status) bits indicate the state in which the addressed
Instruction Dispatcher (ID) is.
IDS[1:0]
0 0 Not Present: This Instruction Dispatcher does not exist in Hardware
0 1 Error: The Instruction Dispatcher has stopped the execution of a program because of an
error. Error cause can be analyzed using bits 29-24 of ID_SCR
1 0 Idle: The Instruction Dispatcher has successfully terminated the execution of a program and
is ready to accept a new Instruction Pointer
1 1 Run: The Instruction Dispatcher is executing a program.
[29] BERR: Every module attached to the HIF receives its own Bus error signal. This signal is set by
the HIF if a bus error condition is detected for a Bus transaction initiated by the corresponding
module.This flag can be cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[26] CERR: Channels report their states to each Instruction Dispatcher. When the ID dispatches an
instruction to a Channel that is in error state or if the Channel goes to error state when it
executes the received instruction, the Instruction Dispatcher goes in turn in error state and this
bit is set.This flag can be cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[25] CBSY: Channel busy. Set when the Channel to which the current instruction was addressed is
busy. It is already running under control of another Instruction Dispatcher.This flag can be
cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[24] CDNX: Channel does not exist. The Channel to which the current instruction was addressed
does not exist in Hardware.This flag can be cleared in three ways:
- resetting the Instruction Dispatcher
- launching a new program
- requesting an asynchronous master reset
[23] IS: Interrupt status. This bit reflects the status of the Interrupt port of the Instruction Dispatcher.
Interrupt ports of every Instruction Dispatcher are ORed together to generate the final Interrupt
signal which drives the Interrupt Pin of the C3 component.This flag is cleared writing one to it,
resetting the Instruction Dispatcher or requesting an asynchronous master reset. Launching a
new program will not clear this flag. Writing zero has no effect.
[22] IES: Interrupt enable on stop.When set the Instruction Dispatcher generates an Interrupt on
normal
termination of a program execution (when the stop instruction executes). Clearing this bit will
not clear pending interrupt.
[21] IER: Interrupt enable on error. If set the Instruction Dispatcher generates an Interrupt when a
program encounters an error. The error cause can be analyzed through bits 29-24 of
ID_SCR.Clearing this bit will not clear pending interrupt.
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Cryptographic co-processor (C3)
RM0089
[20] SSC: If the Instruction Dispatcher is put in Single Step Mode using bit SSE of ID_SCR it will
await for SSC to be set before executing/dispatching the next instruction. In this context, a
Single Step is defined as the execution/dispatching of the instruction and its argument. The first
instruction is not executed/dispatched launching a new program when SSE is set. Setting this
bit in Single Step Mode (SSE is set) executes/dispatches the next instruction. The bit bit is
cleared when the execution of the current single instruction terminates. Writing zero has no
effect
[19] SSE: Single Step Enable.
[17] IGR: Not implemented. This bit should be set to zero.
[16] RST: Each Instruction Dispatcher can be reset independently from each other using this bit. In
Hardware the reset is done synchronously and not all registers are affected by it. Following are
the effects of a synchronous reset: bits 29-16 of SCR are all cleared, the Instruction Dispatcher
goes in Idle state eventually aborting program execution and bits 31-30 (IDS) of SCR are set to
Idle. Writing one will Reset the instruction dispatcher. This bit is always read as zero
[13:12] C6S: Status of Channel 6 (the same than the one in SYS_SCR)
[11:10] C5S: Status of Channel 5 (the same than the one in SYS_SCR)
[9:8] C4S: Status of Channel 4 (the same than the one in SYS_SCR)
[7:6] C3S: Status of Channel 3 (the same than the one in SYS_SCR)
[5:4] C2S: Status of Channel 2 (the same than the one in SYS_SCR)
[3:2] C1S: Status of Channel 1 (the same than the one in SYS_SCR)
[1:0] C0S: Status of Channel 0 (the same than the one in SYS_SCR)
ID1_IP
Instruction Dispatcher #1 Instruction Pointer
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IP
R/W
Address:
C3BaseAddress + 0x1410
Type:
R/W
Reset:
0x0
Description:
Instruction Dispatcher #1 Instruction Pointer Register
[31:0] IP: The Instruction Pointer Register is used to store the pointer of the first instruction to be
fetched and to launch program execution. It can be read back at any time (particularly in Single
Step Mode) to know the address of the next instruction that will be executed. Effects of
changing Instruction Pointer while a program is running are unspecified. The Instruction Pointer
must be 32 bit aligned (the lower two bits are ignored and are always read zero). When an
Instruction Pointer is written the Instruction Dispatcher goes in run state, begins filling its
Instruction Queue and as soon as the first instruction is H1891available it executes/dispatches
it.
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RM0089
Cryptographic co-processor (C3)
ID1_IR0
Instruction Dispatcher #1 Instruction Word 0
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR0
R
Address:
C3BaseAddress + 0x1420
Type:
R
Reset:
0x0
Description:
Instruction Dispatcher #1 Instruction Word 0 Register
[31:0] IR0: Instruction Word 0 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
ID1_IR1
Instruction Dispatcher #1 Instruction Word 1
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR1
R
Address:
C3BaseAddress + 0x1424
Type:
R
Reset:
0x0
Description:
Instruction Dispatcher #1 Instruction Word 1 Register
[31:0] IR1: Instruction Word 1 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
ID1_IR2
Instruction Dispatcher #1 Instruction Word 2
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR2
R
Address:
C3BaseAddress + 0x1428
Type:
R
Reset:
0x0
Doc ID 018904 Rev 3
443/1728
Cryptographic co-processor (C3)
Description:
RM0089
Instruction Dispatcher #1 Instruction Word 2 Register
[31:0] IR2: Instruction Word 2 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
ID1_IR3
Instruction Dispatcher #1 Instruction Word 3
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IR3
R
Address:
C3BaseAddress + 0x142C
Type:
R
Reset:
0x0
Description:
Instruction Dispatcher #1 Instruction Word 3 Register
[31:0] IR3: Instruction Word 3 Register
Instruction Word Registers are used to read back the OP Code of the current executing
instruction. The instruction can be 1 to 4 words long. IR1-3 contents are undefined for 1 word
instructions, IR2-3 contents are undefined for 2 word instructions and, similarly, IR3 is
undefined for 3 word instructions. These register are used mainly in Single Step Mode to read
back the last executed instruction
MOVE_SCR
Status and Control register
MAEN
MAMD
SLEN
RESERVED
RST
RESERVED
R
7
RESERVED
R
8
IERR
PERR
R
9
AERR
BERR
R
DERR
CS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
W
R
Address:
C3BaseAddress + 0x2200
Type:
R/W
Reset:
0x8000 0000
Description:
Status and Control register
[31:30] CS: Channel status; 00 = Not present, 01 = Error, 10 = Idle, 11 = Busy
[29] BERR: Bus error status
[28] DERR: Dispatching protocol error status
[27] PERR: Couple and Chaining error status
[26] IERR: Instruction decode error bit
[25] AERR: Address/Count alignment error bit
[23] MAEN: Master enable
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5
4
3
2
1
0
RM0089
Cryptographic co-processor (C3)
[22] MAMD: Master mode: 0 for coupling, 1 for chaining
[21] SLEN: Slave enable
[16] RST: When set, it issues a soft reset to the Control Unit - Always read as zero
MOVE_SRCR
Source Register (Read Pointer)
8
7
6
5
4
3
2
1
0
RESERVED
9
MOVE_SRCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
Address:
C3BaseAddress + 0x2210
Type:
R/W
Reset:
0x0
Description:
Source Register (Read Pointer)
[31:2] MOVE_SRCR: Source Register (Read Pointer) - The two low significant bits cannot be written
and are always read as zero.
MOVE_DSTR
Destination Register (Write Pointer)
8
7
6
5
4
3
2
1
0
RESERVED
9
MOVE_DSTR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
Address:
C3BaseAddress + 0x2214
Type:
R/W
Reset:
0x0
Description:
Destination Register (Write Pointer)
[31:2] MOVE_DSTR: Destination Register (Write Pointer) - The two low significant bits cannot be
written and are always read as zero.
MOVE_CNTR
Count Register
7
6
5
4
3
2
1
0
RESERVED
8
MOVE_CNTR
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
Address:
C3BaseAddress + 0x2218
Type:
R/W
Doc ID 018904 Rev 3
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Cryptographic co-processor (C3)
Reset:
0x0
Description:
Count Register
RM0089
[15:2] MOVE_CNTR: Count Register - The two low significant bits cannot be written and are always
read as zero.
MOVE_IR
Channel ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MOVE_IR
R
Address:
C3BaseAddress + 0x23FC
Type:
R
Reset:
0x1020
Description:
Channel ID
[31:0] MOVE_IR: Channel ID
DES_SCR
Status and Control register
MAEN
MAMD
SLEN
RESERVED
RST
RESERVED
R
7
RESERVED
R
8
IERR
PERR
R
9
AERR
BERR
R
DERR
CS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
W
R
Address:
C3BaseAddress + 0x2600
Type:
R/W
Reset:
0x8000 0000
Description:
Status and Control register
6
5
[31:30] CS: Channel status; 00 = Not present, 01 = Error, 10 = Idle, 11 = Busy
[29] BERR: Bus error status
[28] DERR: Dispatching protocol error status
[27] PERR: Couple and Chaining error status
[26] IERR: Instruction decode error bit
[25] AERR: Address/Count alignment error bit
[23] MAEN: Master enable
[22] MAMD: Master mode: 0 for coupling, 1 for chaining
[21] SLEN: Slave enable
[16] RST: When set, it issues a soft reset to the Control Unit - Always read as zero
446/1728
Doc ID 018904 Rev 3
4
3
2
1
0
RM0089
Cryptographic co-processor (C3)
DES_IR
Channel ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DES_IR
R
Address:
C3BaseAddress + 0x27FC
Type:
R
Reset:
0x2001
Description:
Channel ID
[31:0] DES_IR: Channel ID
MPCM_SCR
Status and Control register
MAEN
MAMD
SLEN
RESERVED
RST
RESERVED
R
7
RESERVED
R
8
IERR
PERR
R
9
AERR
BERR
R
DERR
CS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
W
R
Address:
C3BaseAddress + 0x2A00
Type:
R/W
Reset:
0x8000 0000
Description:
Status and Control register
6
5
4
3
2
1
0
[31:30] CS: Channel status; 00 = Not present, 01 = Error, 10 = Idle, 11 = Busy
[29] BERR: Bus error status
[28] DERR: Dispatching protocol error status
[27] PERR: Couple and Chaining error status
[26] IERR: Instruction decode error bit
[25] AERR: Address/Count alignment error bit
[23] MAEN: Master enable
[22] MAMD: Master mode: 0 for coupling, 1 for chaining
[21] SLEN: Slave enable
[16] RST: When se it issues a soft reset of the Control Unit
MPCM_SRCR
Source Register (Read Pointer)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPCM_SRCR
R/W
Address:
C3BaseAddress + 0x2A10
Type:
R/W
Reset:
0x0
Doc ID 018904 Rev 3
447/1728
Cryptographic co-processor (C3)
Description:
RM0089
Source Register (Read Pointer)
[31:0] MPCM_SRCR: Source Register (Read Pointer)
MPCM_DSTR
Destination Register (Write Pointer)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPCM_DSTR
R/W
Address:
C3BaseAddress + 0x2A14
Type:
R/W
Reset:
0x0
Description:
Destination Register (Write Pointer)
[31:0] MPCM_DSTR: Destination Register (Write Pointer)
MPCM_CNTR
Count Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
RESERVED
MPCM_CNTR
R
R/W
Address:
C3BaseAddress + 0x2A18
Type:
R/W
Reset:
0x0
Description:
Count Register
5
4
3
2
1
0
[15:0] MPCM_CNTR: Count Register
MPCM_IR
Channel ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MPCM_IR
R
Address:
C3BaseAddress + 0x2BFC
Type:
R
Reset:
0xE000
Description:
Channel ID
[31:0] MPCM_IR: Channel ID
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Doc ID 018904 Rev 3
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8
7
6
5
4
3
2
1
0
RM0089
Cryptographic co-processor (C3)
UHH_SCR
Status and Control register
MAEN
MAMD
SLEN
RESERVED
RST
RESERVED
R
7
RESERVED
R
8
IERR
PERR
R
9
AERR
BERR
R
DERR
CS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
W
R
Address:
C3BaseAddress + 0x2E00
Type:
R/W
Reset:
0x8000 0000
Description:
6
5
4
3
2
1
0
Status and Control register
[31:30] CS: Channel status; 00 = Not present, 01 = Error, 10 = Idle, 11 = Busy
[29] BERR: Bus error status
[28] DERR: Dispatching protocol error status
[27] PERR: Couple and Chaining error status
[26] IERR: Instruction decode error bit
[25] AERR: Address/Count alignment error bit
[23] MAEN: Master enable
[22] MAMD: Master mode: 0 for coupling, 1 for chaining
[21] SLEN: Slave enable
[16] RST: When se it issues a soft reset of the Control Unit
UHH_IR
Channel ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
UH_IR
R
Address:
C3BaseAddress + 0x2FFC
Type:
R
Reset:
0x4014
Description:
Channel ID
[31:0] UH_IR: Channel ID
UHH2_SCR
Status and Control register
Address:
MAEN
MAMD
SLEN
RESERVED
RST
RESERVED
R
7
RESERVED
R
8
IERR
PERR
R
9
AERR
BERR
R
DERR
CS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
W
R
6
5
4
3
2
1
0
C3BaseAddress + 0x3200
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Cryptographic co-processor (C3)
RM0089
Type:
R/W
Reset:
0x8000 0000
Description:
Status and Control register
[31:30] CS: Channel status; 00 = Not present, 01 = Error, 10 = Idle, 11 = Busy
[29] BERR: Bus error status
[28] DERR: Dispatching protocol error status
[27] PERR: Couple and Chaining error status
[26] IERR: Instruction decode error bit
[25] AERR: Address/Count alignment error bit
[23] MAEN: Master enable
[22] MAMD: Master mode: 0 for coupling, 1 for chaining
[21] SLEN: Slave enable
[16] RST: When se it issues a soft reset of the Control Unit
UHH2_IR
Channel ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
UHH2_IR
R
Address:
C3BaseAddress + 0x33FC
Type:
R
Reset:
0x11001
Description:
Channel ID
[31:0] UHH2_IR: Channel ID
PKA_SCR
Status and Control register
MAEN
MAMD
SLEN
RESERVED
RST
RESERVED
R
7
RESERVED
R
8
IERR
PERR
R
9
AERR
BERR
R
DERR
CS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
W
R
Address:
C3BaseAddress + 0x3600
Type:
R/W
Reset:
0x8000 0000
Description:
Status and Control register
[31:30] CS: Channel status; 00 = Not present, 01 = Error, 10 = Idle, 11 = Busy
[29] BERR: Bus error status
[28] DERR: Dispatching protocol error status
[27] PERR: Couple and Chaining error status
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6
5
4
3
2
1
0
RM0089
Cryptographic co-processor (C3)
[26] IERR: Instruction decode error bit
[25] AERR: Address/Count alignment error bit
[23] MAEN: Master enable
[22] MAMD: Master mode: 0 for coupling, 1 for chaining
[21] SLEN: Slave enable
[16] RST: When se it issues a soft reset of the Control Unit
PKA_SRCR
Source Register (Read Pointer)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PKA_SRCR
R/W
Address:
C3BaseAddress + 0x3610
Type:
R/W
Reset:
0x0
Description:
Source Register (Read Pointer)
[31:0] PKA_SRCR: Source Register (Read Pointer)
PKA_PSRCR
Source Register (Read Pointer) for the public
structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PKA_PSRCR
R/W
Address:
C3BaseAddress + 0x3614
Type:
R/W
Reset:
0x0
Description:
Source Register (Read Pointer) for the public structure
[31:0] PKA_PSRCR: Source Register (Read Pointer) for the public structure
PKA_DSTR
Destination Register (Write Pointer)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PKA_DSTR
R/W
Address:
C3BaseAddress + 0x3618
Type:
R/W
Reset:
0x0
Description:
Destination Register (Write Pointer)
[31:0] PKA_DSTR: Destination Register (Write Pointer)
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Cryptographic co-processor (C3)
RM0089
PKA_CNTR
Count Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
RESERVED
PKA_CNTR
R
R/W
Address:
C3BaseAddress + 0x361C
Type:
R/W
Reset:
0x0
Description:
Count Register
6
5
4
3
2
1
0
[15:0] PKA_CNTR: Count Register
PKA_IR
Channel ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PKA_IR
R
Address:
C3BaseAddress + 0x37FC
Type:
R
Reset:
0x6001
Description:
Channel ID
[31:0] PKA_IR: Channel ID
RNG_SCR
Status and Control register
RESERVED
OEC3
OEC2
OEC1
OEC0
0
RST
1
RESERVED
2
SLEN
3
MAMD
4
R
R
R
R
R
R
W
R
R
R
R
R
C3BaseAddress + 0x3A00
Type:
R/W
Reset:
0x8000 0000
Status and Control register
[31:30] CS: Channel status; 00 = Not present, 01 = Error, 10 = Idle, 11 = Busy
[29] BERR: Bus error status
[28] DERR: Dispatching protocol error status
[27] PERR: Couple and Chaining error status
[26] IERR: Instruction decode error bit
[25] AERR: Address/Count alignment error bit
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5
R
Address:
Description:
6
MAEN
R
7
OERR
R
8
IERR
PERR
R
9
AERR
BERR
R
DERR
CS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Cryptographic co-processor (C3)
[24] OERR: The RNG Channel goes in error state and this bit is set if an error condition is detected
that does not fit in any of the above described flags (bits 29 to 25). Bits 3 to 0 (OEC3 to OEC0)
can be used to get more information.
[23] MAEN: Master enable
[22] MAMD: Master mode: 0 for coupling, 1 for chaining
[21] SLEN: Slave enable
[16] RST: When se it issues a soft reset of the Control Unit
[3] OEC3: Fault in the bit sequence, raised by the Entropy Monitor.
[2] OEC2: The internal clock for the RNG core is not revealed.
[1] OEC1: The RNG core is busy.
[0] OEC0: The bit OEC0 reveals if the RNG core is disabled. The RNG core can be
enabled/disabled for power saving purposes.
RNG_DSTR
Destination Register (Write Pointer)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RNG_DSTR
R/W
Address:
C3BaseAddress + 0x3A14
Type:
R/W
Reset:
0x0
Description:
Destination Register (Write Pointer)
[31:0] RNG_DSTR: Destination Register (Write Pointer)
RNG_CNTR
Count Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
RNG_CNTR
R
R/W
Address:
C3BaseAddress + 0x3A18
Type:
R/W
Reset:
0x0
Description:
9
RESERVED
6
5
4
3
2
1
0
Count Register
[15:0] RNG_CNTR: Count Register
RNG_IR
Channel ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RNG_IR
R
Address:
C3BaseAddress + 0x3BFC
Type:
R
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453/1728
Cryptographic co-processor (C3)
Reset:
0xF000
Description:
Channel ID
RM0089
[31:0] RNG_IR: Channel ID
454/1728
Doc ID 018904 Rev 3
RM0089
14
Temperature sensor (THSENS)
Temperature sensor (THSENS)
Refer to Chapter 5: System configuration registers (MISC) for the registers related to
THSENS configuration.
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Multi-port DDR controller (MPMC)
RM0089
15
Multi-port DDR controller (MPMC)
Note:
In the original documentation from IP vendor registers are named with prefix
"DENALI_CTL_"
15.1
Register summary
Table 86.
MPMC_controller register list
Offset
Register name
Description
Page
0x000
MPMC_CTRL_REG_00
Controller configuration register 0
on page 464
0x004
MPMC_CTRL_REG_01
Controller configuration register 1
on page 464
0x008
MPMC_CTRL_REG_02
Controller configuration register 2 (rfu)
on page 465
0x00C
MPMC_CTRL_REG_03
Controller configuration register 3
on page 465
0x010
MPMC_CTRL_REG_04
Controller configuration register 4
on page 466
0x014
MPMC_CTRL_REG_05
Controller configuration register 5
on page 467
0x018
MPMC_CTRL_REG_06
Controller configuration register 6
on page 467
0x01C
MPMC_CTRL_REG_07
Controller configuration register 7
on page 468
0x020
MPMC_CTRL_REG_08
Controller configuration register 8
on page 468
0x024
MPMC_CTRL_REG_09
Controller configuration register 9
on page 469
0x028
MPMC_CTRL_REG_10
Controller configuration register 10
on page 469
0x02C
MPMC_CTRL_REG_11
Controller configuration register 11
on page 470
0x030
MPMC_CTRL_REG_12
Controller configuration register 12
on page 471
0x034
MPMC_CTRL_REG_13
Controller configuration register 13
on page 472
0x038
MPMC_CTRL_REG_14
Controller configuration register 14
on page 473
0x03C
MPMC_CTRL_REG_15
Controller configuration register 15
on page 473
0x040
MPMC_CTRL_REG_16
Controller configuration register 16
on page 474
0x044
MPMC_CTRL_REG_17
Controller configuration register 17
on page 475
0x048
MPMC_CTRL_REG_18
Controller configuration register 18
on page 475
0x04C
MPMC_CTRL_REG_19
Controller configuration register 19
on page 476
0x050
MPMC_CTRL_REG_20
Controller configuration register 20
on page 477
0x054
MPMC_CTRL_REG_21
Controller configuration register 21
on page 478
0x058
MPMC_CTRL_REG_22
Controller configuration register 22
on page 479
0x05C
MPMC_CTRL_REG_23
Controller configuration register 23
on page 480
0x060
MPMC_CTRL_REG_24
Controller configuration register 24
on page 480
0x064
MPMC_CTRL_REG_25
Controller configuration register 25
on page 481
0x068
MPMC_CTRL_REG_26
Controller configuration register 26
on page 481
0x06C
MPMC_CTRL_REG_27
Controller configuration register 27
on page 482
456/1728
Doc ID 018904 Rev 3
RM0089
Table 86.
Offset
Multi-port DDR controller (MPMC)
MPMC_controller register list (continued)
Register name
Description
Page
0x070
MPMC_CTRL_REG_28
Controller configuration register 28
on page 483
0x074
MPMC_CTRL_REG_29
Controller configuration register 29
on page 483
0x078
MPMC_CTRL_REG_30
Controller configuration register 30
on page 484
0x07C
MPMC_CTRL_REG_31
Controller configuration register 31
on page 485
0x080
MPMC_CTRL_REG_32
Controller configuration register 32
on page 485
0x084
MPMC_CTRL_REG_33
Controller configuration register 33
on page 486
0x088
MPMC_CTRL_REG_34
Controller configuration register 34
on page 487
0x08C
MPMC_CTRL_REG_35
Controller configuration register 35
on page 487
0x090
MPMC_CTRL_REG_36
Controller configuration register 36
on page 488
0x094
MPMC_CTRL_REG_37
Controller configuration register 37
on page 489
0x098
MPMC_CTRL_REG_38
Controller configuration register 38
on page 489
0x09C
MPMC_CTRL_REG_39
Controller configuration register 39
on page 490
0x0A0
MPMC_CTRL_REG_40
Controller configuration register 40
on page 491
0x0A4
MPMC_CTRL_REG_41
Controller configuration register 41
on page 491
0x0A8
MPMC_CTRL_REG_42
Controller configuration register 42
on page 492
0x0AC
MPMC_CTRL_REG_43
Controller configuration register 43
on page 493
0x0B0
MPMC_CTRL_REG_44
Controller configuration register 44
on page 493
0x0B4
MPMC_CTRL_REG_45
Controller configuration register 45
on page 494
0x0B8
MPMC_CTRL_REG_46
Controller configuration register 46
on page 495
0x0BC
MPMC_CTRL_REG_47
Controller configuration register 47
on page 495
0x0C0
MPMC_CTRL_REG_48
Controller configuration register 48
on page 496
0x0C4
MPMC_CTRL_REG_49
Controller configuration register 49
on page 497
0x0C8
MPMC_CTRL_REG_50
Controller configuration register 50
on page 498
0x0CC
MPMC_CTRL_REG_51
Controller configuration register 51
on page 499
0x0D0
MPMC_CTRL_REG_52
Controller configuration register 52
on page 499
0x0D4
MPMC_CTRL_REG_53
Controller configuration register 53
on page 500
0x0D8
MPMC_CTRL_REG_54
Controller configuration register 54
on page 501
0x0DC
MPMC_CTRL_REG_55
Controller configuration register 55
on page 501
0x0E0
MPMC_CTRL_REG_56
Controller configuration register 56 (rfu)
on page 502
0x0E4
MPMC_CTRL_REG_57
Controller configuration register 57
on page 502
0x0E8
MPMC_CTRL_REG_58
Controller configuration register 58
on page 503
0x0EC
MPMC_CTRL_REG_59
Controller configuration register 59
on page 503
0x0F0
MPMC_CTRL_REG_60
Controller configuration register 60
on page 504
0x0F4
MPMC_CTRL_REG_61
Controller configuration register 61
on page 504
0x0F8
MPMC_CTRL_REG_62
Controller configuration register 62
on page 504
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457/1728
Multi-port DDR controller (MPMC)
Table 86.
Offset
RM0089
MPMC_controller register list (continued)
Register name
Description
Page
0x0FC
MPMC_CTRL_REG_63
Controller configuration register 63
on page 505
0x100
MPMC_CTRL_REG_64
Controller configuration register 63
on page 505
0x104
MPMC_CTRL_REG_65
Controller configuration register 65
on page 505
0x108
MPMC_CTRL_REG_66
Controller configuration register 66
on page 506
0x10C
MPMC_CTRL_REG_67
Controller configuration register 67
on page 506
0x110
MPMC_CTRL_REG_68
Controller configuration register 68
on page 507
0x114
MPMC_CTRL_REG_69
Controller configuration register 69
on page 507
0x118
MPMC_CTRL_REG_70
Controller configuration register 70
on page 508
0x11C
MPMC_CTRL_REG_71
Controller configuration register 71
on page 508
0x120
MPMC_CTRL_REG_72
Controller configuration register 72
on page 509
0x124
MPMC_CTRL_REG_73
Controller configuration register 73
on page 510
0x128
MPMC_CTRL_REG_74
Controller configuration register 74
on page 511
0x12C
MPMC_CTRL_REG_75
Controller configuration register 75
on page 512
0x130
MPMC_CTRL_REG_76
Controller configuration register 76
on page 512
0x134
MPMC_CTRL_REG_77
Controller configuration register 77
on page 513
0x138
MPMC_CTRL_REG_78
Controller configuration register 78
on page 513
0x13C
MPMC_CTRL_REG_79
Controller configuration register 79 (rfu)
on page 514
0x140
MPMC_CTRL_REG_80
Controller configuration register 80 (rfu)
on page 514
0x144
MPMC_CTRL_REG_81
Controller configuration register 81
on page 514
0x148
MPMC_CTRL_REG_82
Controller configuration register 82
on page 515
0x14C
MPMC_CTRL_REG_83
Controller configuration register 83
on page 515
0x150
MPMC_CTRL_REG_84
Controller configuration register 84 (rfu)
on page 515
0x154
MPMC_CTRL_REG_85
Controller configuration register 85 (rfu)
on page 516
0x158
MPMC_CTRL_REG_86
Controller configuration register 86
on page 516
0x15C
MPMC_CTRL_REG_87
Controller configuration register 87
on page 516
0x160
MPMC_CTRL_REG_88
Controller configuration register 88
on page 517
0x164
MPMC_CTRL_REG_89
Controller configuration register 89 (rfu)
on page 517
0x168
MPMC_CTRL_REG_90
Controller configuration register 90 (rfu)
on page 518
0x16C
MPMC_CTRL_REG_91
Controller configuration register 91 (rfu)
on page 518
0x170
MPMC_CTRL_REG_92
Controller configuration register 92 (rfu)
on page 518
0x174
MPMC_CTRL_REG_93
Controller configuration register 93 (rfu)
on page 518
0x178
MPMC_CTRL_REG_94
Controller configuration register 94 (rfu)
on page 519
0x17C
MPMC_CTRL_REG_95
Controller configuration register 95 (rfu)
on page 519
0x180
MPMC_CTRL_REG_96
Controller configuration register 96
on page 519
0x184
MPMC_CTRL_REG_97
Controller configuration register 97
on page 520
458/1728
Doc ID 018904 Rev 3
RM0089
Table 86.
Offset
Multi-port DDR controller (MPMC)
MPMC_controller register list (continued)
Register name
Description
Page
0x188
MPMC_CTRL_REG_98
Controller configuration register 98
on page 520
0x18C
MPMC_CTRL_REG_99
Controller configuration register 99
on page 520
0x190
MPMC_CTRL_REG_100 Controller configuration register 100
on page 521
0x194
MPMC_CTRL_REG_101 Controller configuration register 101
on page 521
0x198
MPMC_CTRL_REG_102 Controller configuration register 102
on page 522
0x19C
MPMC_CTRL_REG_103 Controller configuration register 103
on page 522
0x1A0
MPMC_CTRL_REG_104 Controller configuration register 104
on page 522
0x1A4
MPMC_CTRL_REG_105 Controller configuration register 105
on page 523
0x1A8
MPMC_CTRL_REG_106 Controller configuration register 106 (rfu)
on page 524
0x1AC
MPMC_CTRL_REG_107
Controller configuration register 107: PHY conf reg 8 for
data slice 0
on page 524
0x1B0
MPMC_CTRL_REG_108
Controller configuration register 108: PHY conf reg 8 for
data slice 1
on page 525
0x1B4
MPMC_CTRL_REG_109
Controller configuration register 109: PHY conf reg 8 for
data slice 2
on page 525
0x1B8
MPMC_CTRL_REG_110
Controller configuration register 110: PHY conf reg 8 for
data slice 3
on page 526
0x1BC
MPMC_CTRL_REG_111
Controller configuration register 111: PHY conf reg 8 for
data slice 4
on page 527
0x1C0
MPMC_CTRL_REG_112 Controller configuration register 112
on page 528
0x1C4
MPMC_CTRL_REG_113 Controller configuration register 113
on page 528
0x1C8
MPMC_CTRL_REG_114 Controller configuration register 114
on page 529
0x1CC
MPMC_CTRL_REG_115
Controller configuration register 115: DLL reg 0 for data
slice 0
on page 529
0x1D0
MPMC_CTRL_REG_116
Controller configuration register 116: DLL reg 0 for data
slice 1
on page 530
0x1D4
MPMC_CTRL_REG_117
Controller configuration register 117: DLL reg 0 for data
slice 2
on page 531
0x1D8
MPMC_CTRL_REG_118
Controller configuration register 118: DLL reg 0 for data
slice 3
on page 532
0x1DC
MPMC_CTRL_REG_119
Controller configuration register 119: DLL reg 0 for data
slice 4
on page 533
0x1E0
MPMC_CTRL_REG_120
Controller configuration register 120: DLL reg 0 for addr/ctrl
slice
on page 534
0x1E4
MPMC_CTRL_REG_121 Controller configuration register 121
on page 535
0x1E8
MPMC_CTRL_REG_122 Controller configuration register 122
on page 535
0x1EC
MPMC_CTRL_REG_123 Controller configuration register 123 (rfu)
on page 536
0x1F0
MPMC_CTRL_REG_124
Controller configuration register 124: PHY conf reg 0 for
data slice 0
Doc ID 018904 Rev 3
on page 536
459/1728
Multi-port DDR controller (MPMC)
Table 86.
Offset
RM0089
MPMC_controller register list (continued)
Register name
Description
Page
0x1F4
MPMC_CTRL_REG_125
Controller configuration register 125: PHY conf reg 0 for
data slice 1
on page 537
0x1F8
MPMC_CTRL_REG_126
Controller configuration register 126: PHY conf reg 0 for
data slice 2
on page 538
0x1FC
MPMC_CTRL_REG_127
Controller configuration register 127: PHY conf reg 0 for
data slice 3
on page 539
0x200
MPMC_CTRL_REG_128
Controller configuration register 128: PHY conf reg 0 for
data slice 4
on page 540
0x204
MPMC_CTRL_REG_129
Controller configuration register 129: PHY conf reg 10 for
addr/ctrl slice
on page 541
0x208
MPMC_CTRL_REG_130
Controller configuration register 130: PHY conf reg 1 for
data slice 0
on page 542
0x20C
MPMC_CTRL_REG_131
Controller configuration register 131: PHY conf reg 1 for
data slice 1
on page 544
0x210
MPMC_CTRL_REG_132
Controller configuration register 132: PHY conf reg 1 for
data slice 2
on page 545
0x214
MPMC_CTRL_REG_133
Controller configuration register 133: PHY conf reg 1 for
data slice 3
on page 547
0x218
MPMC_CTRL_REG_134
Controller configuration register 134: PHY conf reg 1 for
data slice 4
on page 549
0x21C
MPMC_CTRL_REG_135
Controller configuration register 135: PHY conf reg 2 for
data slice 0
on page 551
0x220
MPMC_CTRL_REG_136
Controller configuration register 136: PHY conf reg 2 for
data slice 1
on page 552
0x224
MPMC_CTRL_REG_137
Controller configuration register 137: PHY conf reg 2 for
data slice 2
on page 553
0x228
MPMC_CTRL_REG_138
Controller configuration register 138: PHY conf reg 2 for
data slice 3
on page 554
0x22C
MPMC_CTRL_REG_139
Controller configuration register 139: PHY conf reg 2 for
data slice 4
on page 555
0x230
MPMC_CTRL_REG_140
Controller configuration register 140: PHY conf reg 3 for
data slice 0
on page 556
0x234
MPMC_CTRL_REG_141
Controller configuration register 141: PHY conf reg 3 for
data slice 1
on page 557
0x238
MPMC_CTRL_REG_142
Controller configuration register 142: PHY conf reg 3 for
data slice 2
on page 558
0x23C
MPMC_CTRL_REG_143
Controller configuration register 143: PHY conf reg 3 for
data slice 3
on page 559
0x240
MPMC_CTRL_REG_144
Controller configuration register 144: PHY conf reg 3 for
data slice 4
on page 560
0x244
MPMC_CTRL_REG_145
Controller configuration register 145: PHY conf reg 4 for
data slice 0
on page 561
460/1728
Doc ID 018904 Rev 3
RM0089
Table 86.
Offset
Multi-port DDR controller (MPMC)
MPMC_controller register list (continued)
Register name
Description
Page
0x248
MPMC_CTRL_REG_146
Controller configuration register 146: PHY conf reg 4 for
data slice 1
on page 562
0x24C
MPMC_CTRL_REG_147
Controller configuration register 147: PHY conf reg 4 for
data slice 2
on page 562
0x250
MPMC_CTRL_REG_148
Controller configuration register 148: PHY conf reg 4 for
data slice 3
on page 563
0x254
MPMC_CTRL_REG_149
Controller configuration register 149: PHY conf reg 4 for
data slice 4
on page 564
0x258
MPMC_CTRL_REG_150
Controller configuration register 150: PHY conf reg 5 for
data slice 0
on page 565
0x25C
MPMC_CTRL_REG_151
Controller configuration register 151: PHY conf reg 5 for
data slice 1
on page 566
0x260
MPMC_CTRL_REG_152
Controller configuration register 152: PHY conf reg 5 for
data slice 2
on page 567
0x264
MPMC_CTRL_REG_153
Controller configuration register 153: PHY conf reg 5 for
data slice 3
on page 568
0x268
MPMC_CTRL_REG_154
Controller configuration register 154: PHY conf reg 5 for
data slice 4
on page 569
0x26C
MPMC_CTRL_REG_155
Controller configuration register 155: PHY conf reg 6 for
data slice 0
on page 570
0x270
MPMC_CTRL_REG_156
Controller configuration register 156: PHY conf reg 6 for
data slice 1
on page 571
0x274
MPMC_CTRL_REG_157
Controller configuration register 157: PHY conf reg 6 for
data slice 2
on page 573
0x278
MPMC_CTRL_REG_158
Controller configuration register 158: PHY conf reg 6 for
data slice 3
on page 574
0x27C
MPMC_CTRL_REG_159
Controller configuration register 159: PHY conf reg 6 for
data slice 4
on page 576
0x280
MPMC_CTRL_REG_160
Controller configuration register 160: PHY conf reg 7 for
data slice 0
on page 577
0x284
MPMC_CTRL_REG_161
Controller configuration register 161: PHY conf reg 7 for
data slice 1
on page 579
0x288
MPMC_CTRL_REG_162
Controller configuration register 162: PHY conf reg 7 for
data slice 2
on page 581
0x28C
MPMC_CTRL_REG_163
Controller configuration register 163: PHY conf reg 7 for
data slice 3
on page 582
0x290
MPMC_CTRL_REG_164
Controller configuration register 164: PHY conf reg 7 for
data slice 4
on page 584
0x294
MPMC_CTRL_REG_165
Controller configuration register 165: PHY conf reg 9 for
data slice 0
on page 586
0x298
MPMC_CTRL_REG_166
Controller configuration register 166: PHY conf reg 9 for
data slice 1
on page 587
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Multi-port DDR controller (MPMC)
Table 86.
Offset
RM0089
MPMC_controller register list (continued)
Register name
Description
Page
0x29C
MPMC_CTRL_REG_167
Controller configuration register 167: PHY conf reg 9 for
data slice 2
on page 587
0x2A0
MPMC_CTRL_REG_168
Controller configuration register 168: PHY conf reg 9 for
data slice 3
on page 588
0x2A4
MPMC_CTRL_REG_169
Controller configuration register 169: PHY conf reg 9 for
data slice 4
on page 589
0x2A8
MPMC_CTRL_REG_170
Controller configuration register 170: PHY obs reg 0 for data
slice 0
on page 589
0x2AC
MPMC_CTRL_REG_171
Controller configuration register 171: PHY obs reg 0 for data
slice 1
on page 590
0x2B0
MPMC_CTRL_REG_172
Controller configuration register 172: PHY obs reg 0 for data
slice 2
on page 591
0x2B4
MPMC_CTRL_REG_173
Controller configuration register 173: PHY obs reg 0 for data
slice 3
on page 591
0x2B8
MPMC_CTRL_REG_174
Controller configuration register 174: PHY obs reg 0 for data
slice 4
on page 592
0x2BC
MPMC_CTRL_REG_175
Controller configuration register 175: PHY obs reg 1 for data
slice 0
on page 593
0x2C0
MPMC_CTRL_REG_176
Controller configuration register 176: PHY obs reg 1 for data
slice 1
on page 593
0x2C4
MPMC_CTRL_REG_177
Controller configuration register 177: PHY obs reg 1 for data
slice 2
on page 593
0x2C8
MPMC_CTRL_REG_178
Controller configuration register 178: PHY obs reg 1 for data
slice 3
on page 594
0x2CC
MPMC_CTRL_REG_179
Controller configuration register 179: PHY obs reg 1 for data
slice 4
on page 594
0x2D0
MPMC_CTRL_REG_180
Controller configuration register 180: PHY addr/ctrl
loopback reg
on page 595
0x2D4
MPMC_CTRL_REG_181
Controller configuration register 181: PHY addr/ctrl
calibration reg
on page 595
0x2D8
MPMC_CTRL_REG_182 Controller configuration register 182(rfu)
on page 596
0x2DC
MPMC_CTRL_REG_183 Controller configuration register 183 (rfu)
on page 596
0x2E0
MPMC_CTRL_REG_184 Controller configuration register 184 (rfu)
on page 596
0x2E4
MPMC_CTRL_REG_185 Controller configuration register 185 (rfu)
on page 597
0x2E8
MPMC_CTRL_REG_186 Controller configuration register 186
on page 597
0x2EC
MPMC_CTRL_REG_187 Controller configuration register 187
on page 597
0x2F0
MPMC_CTRL_REG_188 Controller configuration register 188
on page 598
0x2F4
MPMC_CTRL_REG_189 Controller configuration register 189
on page 598
0x2F8
MPMC_CTRL_REG_190 Controller configuration register 190
on page 598
0x2FC
MPMC_CTRL_REG_191 Controller configuration register 191
on page 599
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RM0089
Table 86.
Offset
Multi-port DDR controller (MPMC)
MPMC_controller register list (continued)
Register name
Description
Page
0x300
MPMC_CTRL_REG_192 Controller configuration register 192
on page 599
0x304
MPMC_CTRL_REG_193 Controller configuration register 193
on page 600
0x308
MPMC_CTRL_REG_194 Controller configuration register 194
on page 600
0x30C
MPMC_CTRL_REG_195 Controller configuration register 195 (rfu)
on page 600
0x310
MPMC_CTRL_REG_196 Controller configuration register 196 (rfu)
on page 601
0x314
MPMC_CTRL_REG_197 Controller configuration register 197 (rfu)
on page 601
0x318
MPMC_CTRL_REG_198 Controller configuration register 198
on page 601
0x31C
MPMC_CTRL_REG_199 Controller configuration register 199
on page 602
0x320
MPMC_CTRL_REG_200 Controller configuration register 200 (rfu)
on page 602
0x324
MPMC_CTRL_REG_201 Controller configuration register 201
on page 602
0x328
MPMC_CTRL_REG_202 Controller configuration register 202
on page 603
0x32C
MPMC_CTRL_REG_203 Controller configuration register 203
on page 603
0x330
MPMC_CTRL_REG_204 Controller configuration register 204
on page 604
0x334
MPMC_CTRL_REG_205 Controller configuration register 205
on page 605
0x338
MPMC_CTRL_REG_206 Controller configuration register 206
on page 606
0x33C
MPMC_CTRL_REG_207 Controller configuration register 207
on page 607
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Multi-port DDR controller (MPMC)
15.2
RM0089
Register descriptions
MPMC_CTRL_REG_00
Controller configuration register 0
2
1
0
rfu
3
RESERVED
4
addr_cmp_en
5
RESERVED
6
ap
7
RESERVED
8
arefresh
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x000
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 0
[24] arefresh: Initiates an automatic refresh to the DRAM devices based on the setting of the
auto_refresh_mode parameter. If there are any open banks when this parameter is set, the
Memory Controller will automatically close these banks before issuing the auto-refresh
command. This parameter will always read back as 0x0.
0 = No action
1 = Issue refresh to the DRAM devices
[16] ap: Enables auto pre-charge mode for DRAM devices.
Note: This parameter may not be modified after the start parameter has been asserted.
0 = Auto pre-charge mode disabled. Memory banks will stay open until another request
requires this bank, the maximum open time (tras_max) has elapsed, or a refresh
command closes all the banks.
1 = Auto pre-charge mode enabled. All read and write transactions must be terminated
by an auto pre-charge command. If a transaction consists of multiple read or write
bursts, only the last command is issued with an auto precharge
[8] addr_cmp_en: Enables address collision/data coherency detection as a condition when using
the placement logic to fill the command queue.
0 = Disabled
1 = Enabled
[0] rfu: Reserved for future use: it is mandatory to set this parameter to 0.
MPMC_CTRL_REG_01
Controller configuration register 1
1
0
auto_refresh_mode
2
RESERVED
3
bank_split_en
4
RESERVED
5
concurrentap
6
RESERVED
7
rfu
8
R
R/
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x004
Type:
R/W
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Multi-port DDR controller (MPMC)
Reset:
0x0000 0000
Description:
Controller configuration register 1
[24] rfu: Reserved for future use: it is mandatory to set this parameter to 0.
[16] concurrentap: Enables concurrent auto pre-charge. Some DRAM devices do not allow one
bank to be auto pre-charged while another bank is reading or writing. The JEDEC standard
allows concurrent auto pre-charge. The user should set this parameter if the DRAM device
supports this feature.
0 = Concurrent auto pre-charge disabled.
1 = Concurrent auto pre-charge enabled.
[8] bank_split_en: Enables bank splitting as a condition when using the placement logic to fill the
command queue.
0 = Disabled
1 = Enabled
[0] auto_refresh_mode: Sets the mode for when the automatic refresh will occur. If the
auto_refresh_mode parameter is set and a refresh is required to memory, the memory
controller will delay this refresh until the end of the current transaction (if the transaction is fully
contained inside a single page), or until the current transaction hits the end of the current page.
0 = Issue refresh on the next DRAM burst boundary, even if the current command is not
complete.
1 = Issue refresh on the next command boundary.
MPMC_CTRL_REG_02
Controller configuration register 2 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x008
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 2 (rfu)
[31:0] rfu: Reserved for future use: it is mandatory to set this parameter to 0x00000000.
MPMC_CTRL_REG_03
Controller configuration register 3
4
3
2
1
0
ecc_disable_w_uc_error
5
RESERVED
6
eight_bank_mode
7
RESERVED
8
enable_quick_srefresh
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x00C
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 3
[16] enable_quick_srefresh: When this bit is set to 1, the memory initialization sequence may be
interrupted and the memory may enter self-refresh mode. This is used to place the memory
devices into self-refresh mode when a power loss is detected during the initialization process.
0 = Continue memory initialization.
1 = Interrupt memory initialization and enter self-refresh mode.
[8] eight_bank_mode: Indicates that the memory devices have eight banks.
0 = Memory devices have 4 banks.
1 = Memory devices have 8 banks.
[0] ecc_disable_w_uc_error: Disables automatic corruption of the ECC codes for an entire user
word when the read portion of a read/modify/write operation has an un-correctable error. If this
is not disabled, the corruption will occur even if the erroneous byte is overwritten with new data.
0 = Allow the ECC codes for the entire user word to be corrupted. (Default)
1 = Disable the corruption. The ECC codes written to memory will match the new write data
written to memory.
MPMC_CTRL_REG_04
Controller configuration register 4
2
1
0
fwc
3
RESERVED
4
rfu_0
5
RESERVED
6
rfu_1
7
RESERVED
8
rfu_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
R/
W
R
W
Address:
MPMC_controllerBaseAddress + 0x010
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 4
[24] rfu_2: Reserved for future use: it is mandatory to set this parameter to 0x0.
[16] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0x0.
[8] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0x0.
[0] fwc: Forces a write check. When this bit is set, the memory controller will XOR the
xor_check_bits parameter with the generated checksum bits from the next word to be written to
the memory. This parameter will always read back as 0.
0 = No action
1 = Force a write check
Once the next write operation has been completed, the memory controller will automatically
clear this bit to 0.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_05
Controller configuration register 5
2
1
0
no_cmd_init
3
RESERVED
4
rfu
5
RESERVED
6
placement_en
7
RESERVED
8
power_down
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x014
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 5
[24] power_down: When this parameter is set to 1, the memory controller will complete processing
of the current burst for the current transaction (if any), issue a precharge all command and then
disable the clock enable signal to the DRAM devices. Any subsequent commands in the
command queue will be suspended until this parameter is cleared to 0.
0 = Enable full power state.
1 = Disable the clock enable and power down the memory controller.
[16] placement_en: Enables using the placement logic to fill the command queue.
0 = Placement logic is disabled. The command queue is a straight FIFO.
1 = Placement logic is enabled. The command queue will be filled according to the placement
logic factors.
[8] rfu: Reserved for future use: it is mandatory to set this parameter to 0.
[0] no_cmd_init: Disables DRAM commands until DLL initialization is complete and tdll has
expired.
0 = Issue only REF and PRE commands during DLL initialization of the DRAM devices. If PRE
commands are issued before DLL initialization is complete, the command will be executed
immediately, and then the DLL initialization will continue.
1 = Do not issue any type of command during DLL initialization of the DRAM devices. If any
other commands are issued during the initialization time, they will be held off until DLL
initialization is complete.
MPMC_CTRL_REG_06
Controller configuration register 6
2
1
0
priority_en
3
RESERVED
4
pwrup_srefresh_exit
5
RESERVED
6
rfu_0
7
RESERVED
8
rfu_1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x018
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 6
[24] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0
[16] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0
[8] pwrup_srefresh_exit: Allows controller to exit power-down mode by executing a self-refresh
exit instead of the full memory initialization. This parameter provides a means to skip full
initialization when the DRAM devices are in a known self-refresh state.
0 = Disabled
1 = Enabled
[0] priority_en: Enables priority as a condition when using the placement logic to fill the command
queue.
0 = Disabled
1 = Enabled
MPMC_CTRL_REG_07
Controller configuration register 7
2
1
0
rdlvl_edge
3
RESERVED
4
rfu_0
5
RESERVED
6
rfu_1
7
RESERVED
8
rfu_2
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x01C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 7
[24] rfu_2: Reserved for future use: it is mandatory to set this parameter to 0.
[16] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0.
[8] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0.
[0] rdlvl_edge: Specifies the read DQS edge to be used for the read leveling operation.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
0 = Positive edge
1 = Negative edge
MPMC_CTRL_REG_08
Controller configuration register 8
1
0
rdlvl_gate_reg_en
2
RESERVED
3
rfu_0
4
RESERVED
5
rfu_1
6
RESERVED
7
rfu_2
8
R
R/
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x020
Type:
R/W
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Multi-port DDR controller (MPMC)
Reset:
0x0000 0000
Description:
Controller configuration register 8
[24] rfu_2: Reserved for future use, it is mandatory to set this parameter to 0.
[16] rfu_1: Reserved for future use, it is mandatory to set this parameter to 0.
[8] rfu_0: Reserved for future use, it is mandatory to set this parameter to 0.
[0] rdlvl_gate_reg_en: Enables direct control of the dfi_rdlvl_gate_delay_X signals through the
rdlvl_gate_delay_X parameters. This is used out the inizialization sequence and the sw leveling
procedure.
MPMC_CTRL_REG_09
Controller configuration register 9
2
1
0
rfu_0
3
RESERVED
4
rfu_1
5
RESERVED
6
rfu_2
7
RESERVED
8
rdlvl_reg_en
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x024
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 9
[24] rdlvl_reg_en: Enables direct control of the dfi_rdlvl_delay_X signals through the rdlvl_delay_X
parameters. This is used out the inizialization sequence and the sw leveling procedure.
[16] rfu_2: Reserved for future use, it is mandatory to set this parameter to 0.
[8] rfu_1: Reserved for future use, it is mandatory to set this parameter to 0.
[0] rfu_0: Reserved for future use, it is mandatory to set this parameter to 0.
MPMC_CTRL_REG_10
Controller configuration register 10
2
1
0
rfu
3
RESERVED
4
reduc
5
RESERVED
6
reg_dimm_enable
7
RESERVED
8
resync_dll
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R/
W
R
R/
W
R
W
Address:
MPMC_controllerBaseAddress + 0x028
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 10
[24] resync_dll: Initiates a re-synchronization of the DLL.
This parameter is write-only.
[16] reg_dimm_enable: Enables registered DIMM operations to control the address and command
pipeline of the memory controller.
0 = Normal operation
1 = Enable registered DIMM operation
[8] reduc: Controls the width of the memory datapath. When enabled, the upper half of the
memory buses (DQ, DQS and DM) are unused and relevant data only exists in the lower half of
the buses. This parameter expands the Memory Controller for use with memory devices of the
configured width or half of the configured width.
Note: The entire user datapath is used regardless of this setting. For more information on half
datapath mode, refer to the Other Memory Controller Features paragraph in RM0078,
Reference manual, SPEAr1340 architecture and functionality.
0 = Standard operation using full memory bus.
1 = Memory datapath width is half of the maximum size. The upper half of the
data_byte_disable bus will be driven to 1.
[0] rfu: Reserved for future use: it is mandatory to set this parameter to 0.
MPMC_CTRL_REG_11
Controller configuration register 11
1
0
resync_dll_per_aref_en
2
RESERVED
3
rw_same_en
4
RESERVED
5
srefresh
6
RESERVED
7
start
8
R
R/
W
R
R/
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x02C
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
Controller configuration register 11
[24] start: With this parameter is cleared to 0, the memory controller will not issue any commands to
the DRAM devices or respond to any signal activity except for reading and writing parameters.
Once this parameter is set to 1, the memory controller will respond to inputs from the system.
When set, the memory controller begins its initialization routine.
Note: Until the initialization complete bit is set in the int_status parameter and the
dfi_init_complete signal is asserted from the PHY, commands will not be accepted into
the Memory Controller core command queue.
0 = Controller is not in active mode.
1 = Initiate active mode for the memory controller.
[16] srefresh: When this parameter is set to 1, the DRAM device(s) will be placed in self refresh
mode. For this, the current burst for the current transaction (if any) will complete, all banks will
be closed, the self-refresh command will be issued to the DRAM, and the clock enable signal
will be de-asserted. The system will remain in self-refresh mode until this parameter is cleared
to 0. The DRAM devices will return to normal operating mode after the self-refresh exit time (the
txsr parameter) of the device and any DLL initialization time for the DRAM is reached. The
memory controller will resume processing of the commands from the interruption point.
This parameter will be updated with an assertion of the srefresh_enter pin, regardless of the
behavior on the register interface. To disable self-refresh again after a srefresh_enter pin
assertion, the user will need to clear the parameter to 0.
0 = Disable self-refresh mode.
1 = Initiate self-refresh of the DRAM devices.
Note : the srefresh_enter pin is controlled by the MISC register MPMC_CTR_STS[2] (register
offset 0x334)
[8] rw_same_en: Enables read/write grouping as a condition when using the placement logic to fill
the command queue.
0 = Disabled
1 = Enabled
[0] resync_dll_per_aref_en: Enables an automatic re-synchronization of the DLL after every
refresh.
MPMC_CTRL_REG_12
Controller configuration register 12
2
1
0
swap_en
3
RESERVED
4
rfu
5
RESERVED
6
swlvl_exit
7
RESERVED
8
swlvl_load
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x030
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 12
[24] swlvl_load: Triggers the delays to be loaded into the PHY delay lines and initiate a read burst
or write strobe for software leveling.
0 = No action
1 = Load delays and start software leveling
[16] swlvl_exit: User request to exit software leveling.
0 = No action
1 = Exit software leveling
[8] rfu: Reserved for future use: it is mandatory to set this parameter to 0.
[0] swap_en: Enables swapping of the active command for a new higher-priority command when
using the placement logic.
0 = Disabled
1 = Enabled
MPMC_CTRL_REG_13
Controller configuration register 13
2
1
0
swlvl_op_done
3
RESERVED
4
swlvl_start
5
RESERVED
6
tras_lockout
7
RESERVED
8
tref_enable
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
W
R
R
Address:
MPMC_controllerBaseAddress + 0x034
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 13
[24] tref_enable: Enables refresh commands. If command refresh mode is configured, then refresh
commands will be automatically issued based on the tref parameter value and any refresh
commands sent through the command interface or the register interface. Refreshes will still
occur even if the DRAM devices have been placed in power down state by the assertion of the
power_down parameter.
0 = Refresh commands disabled.
1 = Refresh commands enabled.
[16] tras_lockout: Defines the tRAS lockout setting for the DRAM device. tRAS lockout allows the
memory controller to execute auto precharge commands before the tras_min parameter has
expired.
0 = tRAS lockout not supported by memory device.
1 = tRAS lockout supported by memory device.
[8] swlvl_start: Initiates the software leveling operation defined in the sw_leveling_mode
parameter.
0 = No Action
1 = Initiate software leveling operation
[0] swlvl_op_done: Reports on status of the software leveling operation. This signal will be driven
low during initiation, load or exit operations.
0 = Operation in process
1 = Operation completed
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_14
Controller configuration register 14
4
3
2
1
0
weighted_round_robin_latency_control
5
RESERVED
6
write_interp
7
RESERVED
8
rfu
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R/
W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x038
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 14
[24] rfu: Reserved for future use: it is mandatory to set this parameter to 0.
[8] write_interp: Defines whether the memory controller can interrupt a write burst with a read
command. Some memory devices do not allow this functionality. For both DDR2 and DDR3
memory devices, this parameter must be cleared to 0.
0 = The device does not support read commands interrupting write commands.
1 = The device does support read commands interrupting write commands.
[0] weighted_round_robin_latency_control: Controls the weighted round-robin latency option.
0 = Counters only count when their port has a command waiting to be processed.
1 = Counters are always running.
MPMC_CTRL_REG_15
Controller configuration register 15
3
RESERVED
4
wrlvl_reg_en
5
RESERVED
6
rfu
7
RESERVED
8
zqcs_rotate
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R
R/
W
R
R/
W
R
Address:
MPMC_controllerBaseAddress + 0x03C
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 15
[24] zqcs_rotate: Defines the behavior of short ZQ calibrations. If this parameter is set to 1, a
ZQCS request will only be issued to one chip select on each request, regardless of the source
of the request. The MC will maintain a counter such that the chip selects are calibrated in a
fixed rotating sequence.
This option can be used to minimize the overhead of periodic ZQ calibrations. If the total time to
calibrate all chip selects is acceptable offline time, the user may disable the zqcs_rotate
parameter.
Note: If this parameter is set to 1, the user should program the refresh_per_zq parameter to
the total time allowed between ZQCS commands divided by the number of chip selects.
If this parameter is cleared to 0, the user should program the refresh_per_zq parameter
to the time between ZQCS commands for all chip selects.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
0 = Calibrate all chip selects on each ZQCS request.
1 = Calibrate only one chip select on the next ZQCS request.
[16] rfu: Reserved for future use: it is mandatory to set this parameter to 0.
[8] wrlvl_reg_en: Enables direct control of the dfi_wrlvl_delay_X signals through the
wrlvl_delay_X parameters. This is used out the inizialization sequence and the sw leveling
procedure.
MPMC_CTRL_REG_16
Controller configuration register 16
2
1
R
R/W
R
R/W
R
R/W
R
R
Address:
MPMC_controllerBaseAddress + 0x040
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 16
[25:24] axi1_fifo_type_reg: Sets the relativity of the clock domains between AXI port 1 and the
Memory Controller core clock.
Note: It is mandatory to set this parameter to 00: Asynchronous mode
[17:16] axi0_fifo_type_reg: Sets the relativity of the clock domains between AXI port 0 and the
Memory Controller core clock.
Note: It is mandatory to set this parameter to 00: Asynchronous mode
[9:8] address_mirroring: Indicates which chip selects support address mirroring. Bit [8] controls
CS0, Bit [9] controls CS1, etc.
0 = Standard pinout
1 = Mirrored wiring
[0] zq_in_progress: Indicates that a ZQ command is currently in progress. If a ZQ command is
requested while this parameter is set to 1, the new ZQ request will be ignored.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
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0
zq_in_progress
3
RESERVED
4
address_mirroring
5
RESERVED
6
axi0_fifo_type_reg
7
RESERVED
8
axi1_fifo_type_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_17
Controller configuration register 17
2
1
0
axi2_fifo_type_reg
3
RESERVED
4
axi3_fifo_type_reg
5
RESERVED
6
axi4_fifo_type_reg
7
RESERVED
8
axi5_fifo_type_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x044
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 17
[25:24] axi5_fifo_type_reg: Sets the relativity of the clock domains between AXI port 5 and the
Memory Controller core clock.
Note: It is mandatory to set this parameter to 00: Asynchronous mode
[17:16] axi4_fifo_type_reg: Sets the relativity of the clock domains between AXI port 4 and the
Memory Controller core clock.
Note: It is mandatory to set this parameter to 00: Asynchronous mode
[9:8] axi3_fifo_type_reg: Sets the relativity of the clock domains between AXI port 3 and the
Memory Controller core clock.
Note: It is mandatory to set this parameter to 00: Asynchronous mode
[1:0] axi2_fifo_type_reg: Sets the relativity of the clock domains between AXI port 2 and the
Memory Controller core clock.
Note: It is mandatory to set this parameter to 00: Asynchronous mode
MPMC_CTRL_REG_18
Controller configuration register 18
2
1
0
cs_map
3
RESERVED
4
ctrl_raw
5
RESERVED
6
dram_clk_disable
7
RESERVED
8
max_cs_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x048
Type:
R/W
Reset:
0x0200 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 18
[25:24] max_cs_reg: Displays the maximum number of chip selects configured for this memory
controller. This parameter is read-only.
[17:16] dram_clk_disable: Sets value for the DFI output signal dfi_dram_clk_disable. Bit [16] controls
CS0, Bit [17] controls CS1. For each bit:
0 = Memory clock/s should be active.
1 = Memory clock/s should be disabled.
[9:8] ctrl_raw: Controls ECC error reporting (single-bit and double-bit errors) and correcting
(single-bit errors). Refer to the ECC Option paragraph in RM0078, Reference manual,
SPEAr1340 architecture and functionality for more information.
00 = ECC not being used.
01 = ECC reporting is on, but no attempts to correct.
10 = No ECC RAM storage available. The data_byte_disable signal bits associated with ECC
will be driven to 1.
11 = ECC reporting and correcting on.
Note: the setting 10 set the param_ecc_removed signal connected to the MISCELLANEOUS
register MPMC_CTR_STS[1] (register offset 0x334)
[1:0] cs_map: Sets the mask that determines which chip select pins are active, with each bit
representing a different chip select. The user address chip select field will be mapped into the
active chip selects indicated by this parameter in ascending order from lowest to highest. This
allows the memory controller to map the entire contiguous user address into any group of chip
selects. Bit [0] of this parameter corresponds to chip select [0], bit [1] corresponds to chip select
[1], etc.
MPMC_CTRL_REG_19
Controller configuration register 19
2
1
0
odt_rd_map_cs0
3
RESERVED
4
odt_rd_map_cs1
5
RESERVED
6
odt_wr_map_cs0
7
RESERVED
8
odt_wr_map_cs1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x04C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 19
[25:24] odt_wr_map_cs1: Sets up which (if any) chip(s) will have their ODT termination active while a
write occurs on chip select 1.
Bit[1] = CS1 will have active ODT termination when chip select 1 is performing a write.
Bit[0] = CS0 will have active ODTtermination when chip select 1 is performing a write.
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Multi-port DDR controller (MPMC)
[17:16] odt_wr_map_cs0: Sets up which (if any) chip(s) will have their ODT termination active while a
write occurs on chip select 0.
Bit[1] = CS1 will have active ODT termination when chip select 0 is performing a write.
Bit[0] = CS0 will have active ODTtermination when chip select 0 is performing a write.
[9:8] odt_rd_map_cs1: Sets up which (if any) chip(s) will have their ODT termination active while a
read occurs on chip select 1.
Bit[1] = CS1 will have active ODT termination when chip select 1 is performing a read.
Bit[0] = CS0 will have active ODTtermination when chip select 1 is performing a read.
[1:0] odt_rd_map_cs0: Sets up which (if any) chip(s) will have their ODT termination active while a
read occurs on chip select 0.
Bit[1] = CS1 will have active ODT termination when chip select 0 is performing a read
Bit[0] = CS0 will have active ODTtermination when chip select 0 is performing a read
MPMC_CTRL_REG_20
Controller configuration register 20
3
RESERVED
4
sw_leveling_mode
5
RESERVED
6
zq_on_sref_exit
7
RESERVED
8
zq_req
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R/W
R
R/W
R
Address:
MPMC_controllerBaseAddress + 0x050
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 20
[25:24] zq_req: Triggers a user-requested ZQ operation. This parameter is write-only and any writes
will be cleared once the process is initiated.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
Bit [25] = Triggers a long ZQ calibration to all chip selects in the system.
Bit [24] = Triggers a short ZQ calibration.
If the zqcs_rotate parameter is set to 1, only one chip select will be calibrated (in
round-robin fashion). If the zqcs_rotate parameter is cleared to 0, all chip selects
defined in the parameter cs_map will be calibrated.
[17:16] zq_on_sref_exit: Issues a ZQ command when exiting selfrefresh mode. This is a one-hot
parameter which determines the type of operation performed on self-refresh exit.
Note: It is recommended to set this parameter to execute a ZQCL on selfrefresh exit. By
setting this parameter this way, a ZQCL will be issued before any other commands are
permitted to execute. If this parameter is set to any other setting, the system must
manage self-refresh exit and ZQ calibration. If using the ZQCS option, Denali
advisesthat the rotate function should be disabled (the parameter zqcs_rotate should be
cleared to 0) to calibrate all chip selects.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
Bit [17] = Triggers a long ZQ calibration to all chip selects in the system on selfrefresh
exit.
Bit [16] = Triggers a short ZQ calibration.
If the zqcs_rotate parameter is set to 1, only one chip select will be calibrated (in
round-robin fashion). If the zqcs_rotate parameter is cleared to 0, all chip selects
defined in the parameter cs_map will be calibrated.
[9:8] sw_leveling_mode: Defines the type of leveling operation performed during the next software
leveling operation.
00 = No Leveling
01 = Write Leveling
10 = Read Leveling
11 = Gate Training
MPMC_CTRL_REG_21
Controller configuration register 21
2
1
addr_pins
3
RESERVED
4
axi0_port_ordering
5
RESERVED
6
axi0_r_priority
7
RESERVED
8
axi0_w_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x054
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
Controller configuration register 21
[26:24] axi0_w_priority: Sets the priority of write commands from AXI port 0. A value of 0 is the
highest priority.
[18:16] axi0_r_priority: Sets the priority of read commands from AXI port 0. A value of 0 is the highest
priority.
[10:8] axi0_port_ordering: Reassigned port order for port 0: used in weighted round-robin arbitration
to modify the order than the ports are scanned when multiple commands are at the same
priority level and have the same relative priorities.
[2:0] addr_pins: Defines the difference between the maximum number of address pins configured
(15) and the actual number of pins being used. The user address is automatically shifted so
that the user address space is mapped contiguously into the memory map based on the value
of this parameter. For details, refer to the Address Mapping paragraph in RM0078, Reference
manual, SPEAr1340 architecture and functionality.
MPMC_CTRL_REG_22
Controller configuration register 22
2
1
axi1_port_ordering
3
RESERVED
4
axi1_r_priority
5
RESERVED
6
axi1_w_priority
7
RESERVED
8
axi2_port_ordering
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x058
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 22
0
[26:24] axi2_port_ordering: Reassigned port order for port 2: used in weighted round-robin arbitration
to modify the order than the ports are scanned when multiple commands are at the same
priority level and have the same relative priorities.
[18:16] axi1_w_priority: Sets the priority of write commands from AXI port 1. A value of 0 is the
highest priority.
[10:8] axi1_r_priority: Sets the priority of read commands from AXI port 1. A value of 0 is the highest
priority.
[2:0] axi1_port_ordering: Reassigned port order for port 1: used in weighted round-robin arbitration
to modify the order than the ports are scanned when multiple commands are at the same
priority level and have the same relative priorities.
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Multi-port DDR controller (MPMC)
RM0089
MPMC_CTRL_REG_23
Controller configuration register 23
2
1
axi2_r_priority
3
RESERVED
4
axi2_w_priority
5
RESERVED
6
axi3_port_ordering
7
RESERVED
8
axi3_r_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x05C
Type:
R/W
Reset:
0x0000 0000
Description:
0
Controller configuration register 23
[26:24] axi3_r_priority: Sets the priority of read commands from AXI port 3. A value of 0 is the highest
priority.
[18:16] axi3_port_ordering: Reassigned port order for port 3: used in weighted round-robin arbitration
to modify the order than the ports are scanned when multiple commands are at the same
priority level and have the same relative priorities.
[10:8] axi2_w_priority: Sets the priority of write commands from AXI port 2. A value of 0 is the
highest priority.
[2:0] axi2_r_priority: Sets the priority of read commands from AXI port 2. A value of 0 is the highest
priority.
MPMC_CTRL_REG_24
Controller configuration register 24
2
1
axi3_w_priority
3
RESERVED
4
axi4_port_ordering
5
RESERVED
6
axi4_r_priority
7
RESERVED
8
axi4_w_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x060
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 24
0
[26:24] axi4_w_priority: Sets the priority of write commands from AXI port 4. A value of 0 is the
highest priority.
[18:16] axi4_r_priority: Sets the priority of read commands from AXI port 4. A value of 0 is the highest
priority.
[10:8] axi4_port_ordering: Reassigned port order for port 4: used in weighted round-robin arbitration
to modify the order than the ports are scanned when multiple commands are at the same
priority level and have the same relative priorities.
[2:0] axi3_w_priority: Sets the priority of write commands from AXI port 3. A value of 0 is the
highest priority.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_25
Controller configuration register 25
2
1
axi5_port_ordering
3
RESERVED
4
axi5_r_priority
5
RESERVED
6
axi5_w_priority
7
RESERVED
8
bstlen
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x064
Type:
R/W
Reset:
0x0000 0000
Description:
0
Controller configuration register 25
[26:24] bstlen: Defines the burst length encoding that will be programmed into the DRAM devices at
initialization. The mode is programmed in the dram_class parameter.
Note: Due to the nature of the high-speed controller clocking, programming the memory
controller and memory device to operate in burst length of 4 may reduce bandwidth as
the controller has limited opportunities to maintain bank activity and issue memory
commands. Burst length of 8 is recommended
010 = 4 memory words
011 = 8 memory words
All other settings are Reserved
[18:16] axi5_w_priority: Sets the priority of write commands from AXI port 5. A value of 0 is the
highest priority.
[10:8] axi5_r_priority: Sets the priority of read commands from AXI port 5. A value of 0 is the highest
priority.
[2:0] axi5_port_ordering: Reassigned port order for port 5: used in weighted round-robin arbitration
to modify the order than the ports are scanned when multiple commands are at the same
priority level and have the same relative priorities.
MPMC_CTRL_REG_26
Controller configuration register 26
2
1
cke_delay
3
RESERVED
4
column_size
5
RESERVED
6
rfu
7
RESERVED
8
port_data_error_type
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x068
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 26
[26:24] port_data_error_type: Defines the type of error and the access type that caused the port data
error condition. If multiple bits are set to 1, then multiple errors were found. This parameter is
read-only.
Bit [26] = A double-bit un-correctable ECC event occurred on the read data. This bit will only be
used when a double-bit un-correctable error occurs and ECC error reporting is enabled in the
ctrl_raw parameter.
Bit [25] = Reserved.
Bit [24] = Reserved.
[18:16] rfu: Reserved for future use: this parameter is read-only and will always read back as 0x00
[10:8] column_size: Shows the difference between the maximum column width available (14) and the
actual number of column pins being used. The user address is automatically shifted so that the
user address space is mapped contiguously into the memory map based on the value of this
parameter. For details, refer to the Address Mapping paragraph in RM0078, Reference manual,
SPEAr1340 architecture and functionality.
[2:0] cke_delay: Sets the number of additional cycles of delay to include in the CKE signal
cke_status for status reporting. The default delay is 0 cycles.
Note: the cke_status is connected to MISCELLANEOUS Register MPMC_CTR_STS[13]
(register offset 0x334)
MPMC_CTRL_REG_27
Controller configuration register 27
2
1
q_fullness
3
RESERVED
4
r2r_diffcs_dly
5
RESERVED
6
r2r_samecs_dly
7
RESERVED
8
r2w_diffcs_dly
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x06C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 27
0
[26:24] r2w_diffcs_dly: Defines the number of additional clocks of delay to insert from a read
command to one chip select to a write command to a different chip select.
[18:16] r2r_samecs_dly: Defines the number of additional clocks of delay to insert between two read
commands to the same chip select.
[10:8] r2r_diffcs_dly: Defines the number of additional clocks of delay to insert from a read command
to one chip select to a read command to a different chip select.
[2:0] q_fullness: Defines quantity of data that will be considered full for the command queue. When
this value is reached, the q_almost_full signal will be driven to high.
Note: the signal q_almost_full is connected to the MISCELLANEOUS register
MPMC_CTR_STS[[12] (register offset 0x334)
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_28
Controller configuration register 28
3
2
1
r2w_samecs_dly
4
RESERVED
5
tbst_int_interval
6
RESERVED
7
tcke
8
RESERVED
9
trrd
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x070
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 28
0
[31:24] trrd: Defines the DRAM activate to activate delay for different banks, in cycles.
[18:16] tcke: Defines the minimum CKE pulse width, in cycles.
[10:8] tbst_int_interval: Defines the burst interrupt interval. This parameter is only relevant if the
burst has not completed. This value is loaded into a parameter when a burst is issued and
another command may only interrupt the current burst when this counter value hits 0. If the
counter value hits 0 and the burst has not completed, the counter will be reset with
tbst_int_interval value. If a command is in progress and the burst has not completed, another
command may only be issued on cycles after the parameter tccd value cycles have elapsed
since the last CAS command and this counter value hits 0.
For example, if the burst length (the bstlen parameter) is 8, tccd is 2, tbst_int_interval is 2 and a
CAS command was issued on cycle 0, another CAS command could interrupt the current burst
on cycle 2. After cycle 3, the current burst will complete and this parameter would not be
relevant.
If instead the tbst_int_interval was 1 for the same system, then the command could interrupt on
cycles 2 or 3.
[2:0] r2w_samecs_dly: Defines the number of additional clocks of delay to insert from a read
command to a write command to the same chip select.
MPMC_CTRL_REG_29
Controller configuration register 29
2
1
trtp
3
RESERVED
4
w2r_diffcs_dly
5
RESERVED
6
w2r_samecs_dly
7
RESERVED
8
w2w_diffcs_dly
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x074
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 29
[26:24] w2w_diffcs_dly: Defines the number of additional clocks of delay to insert from a write
command to one chip select to a write command to a different chip select.
[18:16] w2r_samecs_dly: Defines the number of additional clocks of delay to insert from a write
command to a read command to the same chip select.
[10:8] w2r_diffcs_dly: Defines the number of additional clocks of delay to insert from a write
command to one chip select to a read command to a different chip select.
[3:0] trtp: Defines the DRAM tRTP (read to precharge time) parameter, in cycles.
MPMC_CTRL_REG_30
Controller configuration register 30
2
1
w2w_samecs_dly
3
RESERVED
4
weighted_round_robin_weigth_sharing
5
RESERVED
6
rfu
7
RESERVED
8
add_odt_clk_sametype_diffcs
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x078
Type:
R/W
Reset:
0x0000 0000
Description:
0
Controller configuration register 30
[27:24] add_odt_clk_sametype_diffcs: Defines the number of additional clocks of delay to insert
between commands of the same type (read to read, write to write) to different chip selects to
meet ODT timing requirements.
[19:16] rfu: Reserved for future use: it is mandatory to set this parameter to 0x0.
[10:8] weighted_round_robin_weigth_sharing: Indicates that the port pair is tied together in
arbitration decisions in weighted roundrobin arbitration. Bit [8] represents ports 0 and 1, bit [9]
represents ports 2 and 3, etc. Each bit setting is as follows:
0 = The represented ports are treated independently in arbitration.
1 = The represented ports are tied together for arbitration.
[2:0] w2w_samecs_dly: Defines the number of additional clocks of delay to insert between two write
commands to the same chip select.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_31
Controller configuration register 31
2
1
aprebit
3
RESERVED
4
axi0_priority0_relative_priority
5
RESERVED
6
axi0_priority1_relative_priority
7
RESERVED
8
axi0_priority2_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x07C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 31
0
[27:24] axi0_priority2_relative_priority: Holds the relative priority of the AXI port 0 for priority 2
commands in weighted round robin arbitration.
[19:16] axi0_priority1_relative_priority: Holds the relative priority of the AXI port 0 for priority 1
commands in weighted round robin arbitration.
[11:8] axi0_priority0_relative_priority: Holds the relative priority of the AXI port 0 for priority 0
commands in weighted round robin arbitration.
[3:0] aprebit: Defines the location of the auto pre-charge bit in the DRAM address in decimal
encoding.
MPMC_CTRL_REG_32
Controller configuration register 32
2
1
axi0_priority3_relative_priority
3
RESERVED
4
axi0_priority4_relative_priority
5
RESERVED
6
axi0_priority5_relative_priority
7
RESERVED
8
axi0_priority6_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x080
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 32
[27:24] axi0_priority6_relative_priority: Holds the relative priority of the AXI port 0 for priority 6
commands in weighted round robin arbitration.
[19:16] axi0_priority5_relative_priority: Holds the relative priority of the AXI port 0 for priority 5
commands in weighted round robin arbitration.
[11:8] axi0_priority4_relative_priority: Holds the relative priority of the AXI port 0 for priority 4
commands in weighted round robin arbitration.
[3:0] axi0_priority3_relative_priority: Holds the relative priority of the AXI port 0 for priority 3
commands in weighted round robin arbitration.
MPMC_CTRL_REG_33
Controller configuration register 33
2
1
axi0_priority7_relative_priority
3
RESERVED
4
axi1_priority0_relative_priority
5
RESERVED
6
axi1_priority1_relative_priority
7
RESERVED
8
axi1_priority2_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x084
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 33
[27:24] axi1_priority2_relative_priority: Holds the relative priority of the AXI port 1 for priority 2
commands in weighted round robin arbitration.
[19:16] axi1_priority1_relative_priority: Holds the relative priority of the AXI port 1 for priority 1
commands in weighted round robin arbitration.
[11:8] axi1_priority0_relative_priority: Holds the relative priority of the AXI port 1 for priority 0
commands in weighted round robin arbitration.
[3:0] axi0_priority7_relative_priority: Holds the relative priority of the AXI port 0 for priority 7
commands in weighted round robin arbitration.
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RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_34
Controller configuration register 34
2
1
axi1_priority3_relative_priority
3
RESERVED
4
axi1_priority4_relative_priority
5
RESERVED
6
axi1_priority5_relative_priority
7
RESERVED
8
axi1_priority6_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x088
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 34
0
[27:24] axi1_priority6_relative_priority: Holds the relative priority of the AXI port 1 for priority 6
commands in weighted round robin arbitration.
[19:16] axi1_priority5_relative_priority: Holds the relative priority of the AXI port 1 for priority 5
commands in weighted round robin arbitration.
[11:8] axi1_priority4_relative_priority: Holds the relative priority of the AXI port 1 for priority 4
commands in weighted round robin arbitration.
[3:0] axi1_priority3_relative_priority: Holds the relative priority of the AXI port 1 for priority 3
commands in weighted round robin arbitration.
MPMC_CTRL_REG_35
Controller configuration register 35
2
1
axi1_priority7_relative_priority
3
RESERVED
4
axi2_priority0_relative_priority
5
RESERVED
6
axi2_priority1_relative_priority
7
RESERVED
8
axi2_priority2_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x08C
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 35
[27:24] axi2_priority2_relative_priority: Holds the relative priority of the AXI port 2 for priority 2
commands in weighted round robin arbitration.
[19:16] axi2_priority1_relative_priority: Holds the relative priority of the AXI port 2 for priority 1
commands in weighted round robin arbitration.
[11:8] axi2_priority0_relative_priority: Holds the relative priority of the AXI port 2 for priority 0
commands in weighted round robin arbitration.
[3:0] axi1_priority7_relative_priority: Holds the relative priority of the AXI port 2 for priority 7
commands in weighted round robin arbitration.
MPMC_CTRL_REG_36
Controller configuration register 36
2
1
axi2_priority3_relative_priority
3
RESERVED
4
axi2_priority4_relative_priority
5
RESERVED
6
axi2_priority5_relative_priority
7
RESERVED
8
axi2_priority6_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x090
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 36
[27:24] axi2_priority6_relative_priority: Holds the relative priority of the AXI port 2 for priority 6
commands in weighted round robin arbitration.
[19:16] axi2_priority5_relative_priority: Holds the relative priority of the AXI port 2 for priority 5
commands in weighted round robin arbitration.
[11:8] axi2_priority4_relative_priority: Holds the relative priority of the AXI port 2 for priority 4
commands in weighted round robin arbitration.
[3:0] axi2_priority3_relative_priority: Holds the relative priority of the AXI port 3 for priority 3
commands in weighted round robin arbitration.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_37
Controller configuration register 37
2
1
axi2_priority7_relative_priority
3
RESERVED
4
axi3_priority0_relative_priority
5
RESERVED
6
axi3_priority1_relative_priority
7
RESERVED
8
axi3_priority2_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x094
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 37
0
[27:24] axi3_priority2_relative_priority: Holds the relative priority of the AXI port 3 for priority 2
commands in weighted round robin arbitration.
[19:16] axi3_priority1_relative_priority: Holds the relative priority of the AXI port 3 for priority 1
commands in weighted round robin arbitration.
[11:8] axi3_priority0_relative_priority: Holds the relative priority of the AXI port 3 for priority 0
commands in weighted round robin arbitration.
[3:0] axi2_priority7_relative_priority: Holds the relative priority of the AXI port 2 for priority 7
commands in weighted round robin arbitration.
MPMC_CTRL_REG_38
Controller configuration register 38
2
1
axi3_priority3_relative_priority
3
RESERVED
4
axi3_priority4_relative_priority
5
RESERVED
6
axi3_priority5_relative_priority
7
RESERVED
8
axi3_priority6_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x098
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 38
[27:24] axi3_priority6_relative_priority: Holds the relative priority of the AXI port 3 for priority 6
commands in weighted round robin arbitration.
[19:16] axi3_priority5_relative_priority: Holds the relative priority of the AXI port 3 for priority 5
commands in weighted round robin arbitration.
[11:8] axi3_priority4_relative_priority: Holds the relative priority of the AXI port 3 for priority 4
commands in weighted round robin arbitration.
[3:0] axi3_priority3_relative_priority: Holds the relative priority of the AXI port 3 for priority 3
commands in weighted round robin arbitration.
MPMC_CTRL_REG_39
Controller configuration register 39
2
1
axi3_priority7_relative_priority
3
RESERVED
4
axi4_priority0_relative_priority
5
RESERVED
6
axi4_priority1_relative_priority
7
RESERVED
8
axi4_priority2_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x09C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 39
[27:24] axi4_priority2_relative_priority: Holds the relative priority of the AXI port 4 for priority 2
commands in weighted round robin arbitration.
[19:16] axi4_priority1_relative_priority: Holds the relative priority of the AXI port 4 for priority 1
commands in weighted round robin arbitration.
[11:8] axi4_priority0_relative_priority: Holds the relative priority of the AXI port 4 for priority 0
commands in weighted round robin arbitration.
[3:0] axi3_priority7_relative_priority: Holds the relative priority of the AXI port 3 for priority 7
commands in weighted round robin arbitration.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_40
Controller configuration register 40
2
1
axi4_priority3_relative_priority
3
RESERVED
4
axi4_priority4_relative_priority
5
RESERVED
6
axi4_priority5_relative_priority
7
RESERVED
8
axi4_priority6_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0A0
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 40
0
[27:24] axi4_priority6_relative_priority: Holds the relative priority of the AXI port 4 for priority 6
commands in weighted round robin arbitration.
[19:16] axi4_priority5_relative_priority: Holds the relative priority of the AXI port 4 for priority 5
commands in weighted round robin arbitration.
[11:8] axi4_priority4_relative_priority: Holds the relative priority of the AXI port 4 for priority 4
commands in weighted round robin arbitration.
[3:0] axi4_priority3_relative_priority: Holds the relative priority of the AXI port 4 for priority 3
commands in weighted round robin arbitration.
MPMC_CTRL_REG_41
Controller configuration register 41
2
1
axi4_priority7_relative_priority
3
RESERVED
4
axi5_priority0_relative_priority
5
RESERVED
6
axi5_priority1_relative_priority
7
RESERVED
8
axi5_priority2_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0A4
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 41
[27:24] axi5_priority2_relative_priority: Holds the relative priority of the AXI port 5 for priority 2
commands in weighted round robin arbitration.
[19:16] axi5_priority1_relative_priority: Holds the relative priority of the AXI port 5 for priority 1
commands in weighted round robin arbitration.
[11:8] axi5_priority0_relative_priority: Holds the relative priority of the AXI port 5 for priority 0
commands in weighted round robin arbitration.
[3:0] axi4_priority7_relative_priority: Holds the relative priority of the AXI port 4 for priority 7
commands in weighted round robin arbitration.
MPMC_CTRL_REG_42
Controller configuration register 42
2
1
axi5_priority3_relative_priority
3
RESERVED
4
axi5_priority4_relative_priority
5
RESERVED
6
axi5_priority5_relative_priority
7
RESERVED
8
axi5_priority6_relative_priority
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0A8
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 42
[27:24] axi5_priority6_relative_priority: Holds the relative priority of the AXI port 5 for priority 6
commands in weighted round robin arbitration.
[19:16] axi5_priority5_relative_priority: Holds the relative priority of the AXI port 5 for priority 5
commands in weighted round robin arbitration.
[11:8] axi5_priority4_relative_priority: Holds the relative priority of the AXI port 5 for priority 4
commands in weighted round robin arbitration.
[3:0] axi5_priority3_relative_priority: Holds the relative priority of the AXI port 5 for priority 3
commands in weighted round robin arbitration.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_43
Controller configuration register 43
2
1
axi5_priority7_relative_priority
3
RESERVED
4
burst_on_fly_bit
5
RESERVED
6
rfu
7
RESERVED
8
dram_class
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0AC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 43
0
[27:24] dram_class: Selects the mode of operation for the Memory Controller.
0100 = DDR2
0110 = DDR3
All other settings reserved.
[19:16] rfu: Reserved for future use: it is mandatory to set this parameter to 0x0.
[11:8] burst_on_fly_bit: Defines the bit of the DRAM address that defines Burst-On-Fly behavior.
The Memory Controller does not support burst-on-fly behavior at this time. However, this
parameter must be set to 1100 for accurate system operation as defined by the JEDEC
specification.
Note: This parameter is only used by the hardware write leveling logic and when operating in
DDR3 mode (the dram_class parameter is set to 0110)
[3:0] axi5_priority7_relative_priority: Holds the relative priority of the AXI port 5 for priority 7
commands in weighted round robin arbitration.
MPMC_CTRL_REG_44
Controller configuration register 44
2
1
initaref
3
RESERVED
4
max_col_reg
5
RESERVED
6
max_row_reg
7
RESERVED
8
port_cmd_error_type
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0B0
Type:
R/W
Reset:
0x000F 0E00
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Description:
RM0089
Controller configuration register 44
[27:24] port_cmd_error_type: Defines the type of error and the access type that caused the port
command error condition. If multiple bits are set to 1, then multiple errors were found. This
parameter is read-only.
Bit [27] = Narrow transfer requested for a requestor Y whose axiY_en_size_lt_width_instr
parameter is clear.
Bit [26] = Reserved.
Bit [25] = Reserved.
Bit [24] = Reserved.
[19:16] max_row_reg: Defines the maximum width of the memory address bus for the memory
controller. This value can be used to set the addr_pins parameter. This parameter is read-only.
addr_pins = max_row_reg - number of row bits in memory device.
[11:8] max_col_reg: Defines the maximum width of column address in the DRAM devices. This value
can be used to set the column_size parameter. This parameter is read-only.
column_size = max_col_reg - number of column bits in memory device.
[3:0] initaref: Defines the number of auto-refresh commands needed by the DRAM devices to
satisfy the initialization sequence.
MPMC_CTRL_REG_45
Controller configuration register 45
2
1
rfu_0
3
RESERVED
4
rfu_1
5
RESERVED
6
tdfi_ctrlupd_min
7
RESERVED
8
tdfi_phy_wrlat
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0B4
Type:
R/W
Reset:
0x0004 0000
Description:
Controller configuration register 45
0
[28:24] tdfi_phy_wrlat: Holds the calculated value of the tphy_wrlat timing parameter and is used to
adjust the dfi_wrdata_en signal timing.
a) If (tdfi_phy_wrlat_base + wrlat_adj) = 2:
tdfi_phy_wrlat = reg_dimm_enable
b)If (tdfi_phy_wrlat_base + wrlat_adj) greater than 2:
tdfi_phy_wrlat =
tdfi_phy_wrlat_base + wrlat_adj + reg_dimm_enable - WRLAT_WIDTH
Note: Values of (tdfi_phy_wrlat_base + wrlat_adj) lower than 2 are not supported. This
parameter is read-only.
[19:16] tdfi_ctrlupd_min: Holds the DFI tctrlupd_min timing parameter. This parameter is read-only.
[11:8] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0x0.
[3:0] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0x0.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_46
Controller configuration register 46
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
twtr
RESERVED
trp_ab
RESERVED
trp
RESERVED
rfu
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0B8
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 46
0
[27:24] twtr: Sets the number of cycles needed to switch from a write to a read operation, as dictated
by the DDR SDRAM specification.
[19:16] trp_ab: Defines the DRAM TRP time for all banks, in cycles.
[11:8] trp: Defines the DRAM pre-charge command time, in cycles.
[3:0] rfu: Reserved for future use: it is mandatory to set this parameter to 0x0.
MPMC_CTRL_REG_47
Controller configuration register 47
2
wrlat
3
RESERVED
4
wrlat_adj
5
RESERVED
6
wrr_param_value_err
7
RESERVED
8
add_odt_clk_difftype_diffcs
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0BC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 47
1
0
[29:24] add_odt_clk_difftype_diffcs: Defines the number of additional clocks of delay to insert
between commands of different types (read to write, write to read) to different chip selects to
meet ODT timing requirements.requirements
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Multi-port DDR controller (MPMC)
RM0089
[19:16] wrr_param_value_err: Shows the weighted round-robin arbitration errors/warnings. This
parameter is read-only.
Bit [19] = The port ordering parameter values for paired ports is not sequential.
Bit [18] = The relative priority values for any of the ports paired through the
weighted_round_robin_weight_sharing parameter are not identical.
Bit [17] = Any of the relative priority parameters have been programmed with a zero value.
Bit [16] = The port ordering parameters do not all contain unique values.
[12:8] wrlat_adj: Adjusts the relative timing between DFI write commands and the dfi_wrdata_en
signal to conform to PHY timing requirements. When this parameter is programmed to 0x0,
dfi_wrdata_en will assert on the same cycle as the dfi_address. This parameter only affects the
DFI.
[4:0] wrlat: Defines the write latency from when the write command is issued to the time the write
data is presented to the DRAM devices, in cycles.
Note: This parameter must be set to 1 when the Memory Controller is used in DDR1 mode.
MPMC_CTRL_REG_48
Controller configuration register 48
4
3
2
caslat_lin
5
RESERVED
6
rfu_0
7
RESERVED
8
rfu_1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0C0
Type:
R/W
Reset:
0x0000 0000
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Description:
Controller configuration register 48
[28:24] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0x00.
[20:16] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0x00.
[5:0] caslat_lin: Sets the CAS latency linear value in 1/2 cycle increments. This sets an internal
adjustment for the delay from when the read command is sent from the memory controller to
when data will be received back. The window of time in which the data is captured is a fixed
length. The caslat_lin parameter adjusts the start of this data capture window. Not all linear
values will be supported for the memory devices being used. Refer to the specification for the
memory devices being used.
00000 - 00001 = Reserved
00010 = 1 cycle
00011 = 1.5 cycles
00100 = 2 cycles
00101 = 2.5 cycles
00110 = 3 cycles
00111 = 3.5 cycles
01000 = 4 cycles
01001 = 4.5 cycles
01010 = 5 cycles
01011 = 5.5 cycles
01100 = 6 cycles
01101 = 6.5 cycles
01110 = 7 cycles
01111 = 7.5 cycles
Additional values of caslat_lin are supported, in half-cycle increments up to 15.5 cycles
MPMC_CTRL_REG_49
Controller configuration register 49
2
rdlat_adj
3
RESERVED
4
tccd
5
RESERVED
6
tckesr
7
RESERVED
8
tdal
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0C4
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 49
[28:24] tdal: Defines the auto pre-charge write recovery time when auto pre-charge is enabled (the ap
parameter is set to 1), in cycles. This is defined internally as tRP (pre-charge time) + auto
pre-charge write recovery time. Not all memories use this parameter. If tDAL is defined in the
memory specification, then program this parameter to the specified value. If the memory does
not specify a tDAL time, then program this parameter to tWR + tRP. DO NOT program this
parameter with a value of 0x0 or the memory controller will not function properly when auto
pre-charge is enabled.
[20:16] tckesr: Defines the minimum number of cycles that CKE must be held low during selfrefresh.
pulse width, in cycles. If the memory specification does not define a tckesr, then the tckesr
parameter should be programmed with the tcke value.
[12:8] tccd: Defines the minimum delay between CAS commands, in cycles. This value is loaded into
a counter when a burst is issued and a new command may be issued when the counter
reaches 0.
[5:0] rdlat_adj: Adjusts the relative timing between DFI read commands and the dfi_rddata_en
signal to conform to PHY timing requirements. When this parameter is programmed to 0x0,
dfi_rddata_en will assert one cycle after the dfi_address. This parameter only affects the DFI.
MPMC_CTRL_REG_50
Controller configuration register 50
2
tdfi_phy_rdlat
3
RESERVED
4
tdfi_rdddata_en
5
RESERVED
6
rfu
7
RESERVED
8
tmrd
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0C8
Type:
R/W
Reset:
0x0000 0000
Description:
1
0
Controller configuration register 50
[28:24] tmrd: Defines the minimum number of cycles required between two mode register write
commands. This is the time required to complete the write operation to the mode register.
[20:16] rfu: Reserved for future use: it is mandatory to set this parameter to 0x00.
[13:8] tdfi_rdddata_en: Holds the calculated value of the trddata_en timing parameter.
a) If (tdfi_rddata_en_base + rdlat_adj) = 2: tdfi_rddata_en = reg_dimm_enable
b) If (tdfi_rddata_en_base + rdlat_adj) greater than 2: tdfi_rddata_en = tdfi_rddata_en_base +
rdlat_adj + reg_dimm_enable - RDLAT_WIDTH
Note: Values of (tdfi_rddata_en_base + rdlat_adj) lower than 2 are not supported.
[5:0] tdfi_phy_rdlat: Holds the DFI tphy_rdlat timing parameter.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_51
Controller configuration register 51
2
twr_int
3
RESERVED
4
age_count
5
RESERVED
6
axi_aligned_strobe_disable
7
RESERVED
8
command_age_count
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0CC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 51
1
0
[29:24] command_age_count: Holds the initial value of the command aging counters associated with
each command in the command queue. When using the placement logic to fill the command
queue, the command aging counters decrement one each time the master aging-rate counter
counts down the number of cycles in the age_count parameter.
[21:16] axi_aligned_strobe_disable: For certain types of AXI transfers, this parameter may be used to
force a standard write transaction instead of a masked write with a read/modify/write sequence.
Each bit of this parameter correlates to a single port on the AXI interface.
Note: When this parameter is set to 1, the AXI strobes will be ignored for the associated port
for these types of transfers. This parameter applies to transfers with the following
characteristics:
-- The transaction is aligned to the user word (in the controller core) at the starting and
ending address.
-- The transaction is exactly one user word in length (128 bits).
0 = Perform this operation as a masked write with a read/modify/write sequence and use
the strobes.
1 = Perform this operation as a standard write operation (not a read/modify/write) and
ignore the strobes.
[13:8] age_count: Holds the initial value of the master aging rate counter. When using the placement
logic to fill the command queue, the command aging counters will be decremented one each
time the master aging-rate counter counts down age_count cycles.
[4:0] twr_int: Defines the DRAM write recovery time, in cycles.
MPMC_CTRL_REG_52
Controller configuration register 52
3
2
out_of_range_type
4
RESERVED
5
tfaw
6
RESERVED
7
trc
8
wldqsen
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R
R/W
R
R
Address:
MPMC_controllerBaseAddress + 0x0D0
Type:
R/W
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RM0089
Reset:
0x0000 0000
Description:
Controller configuration register 52
[29:24] wldqsen: Minimum number of cycles of delay after memory enters write leveling mode (MRS
command issued) before first DQS strobe can be sent.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[23:16] trc: Defines the DRAM period between active commands for the same bank, in cycles.
[13:8] tfaw: Defines the DRAM tFAW parameter, in cycles.
[5:0] out_of_range_type: Holds the type of command that caused an out-of-range interrupt request
to the memory devices. This parameter is read only. For more information on out-of-range
address checking, refer to the Other Memory Controller Features paragraph in RM0078,
Reference manual, SPEAr1340 architecture and functionality.
MPMC_CTRL_REG_53
Controller configuration register 53
2
wlmrd
3
RESERVED
4
rfu
5
RESERVED
6
ecc_c_id
7
RESERVED
8
ecc_c_synd
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0D4
Type:
R/W
Reset:
0x0000 0000
Description:
1
0
Controller configuration register 53
[30:24] ecc_c_synd: Stores the pre-corrected syndrome bits associated with a single-bit correctable
ECC error event. This parameter will only be used when a correctable error occurs and ECC
error reporting is enabled in the ctrl_raw parameter. This parameter is read-only.
[22:16] ecc_c_id: Contains the source ID associated with a single-bit correctable ECC event. This
parameter will only be used when a correctable error occurs and ECC error reporting is
enabled in the ctrl_raw parameter. This parameter is read-only.
[14:8] rfu: Reserved for future use: this parameter is read-only and will always read back as 0x00
[5:0] wlmrd: Defines the delay from when an MRS command is issued to when the first write leveling
strobe is issued. This is a write leveling-specific timing specification.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_54
Controller configuration register 54
ecc_u_id
3
RESERVED
4
ecc_u_synd
5
RESERVED
6
out_of_range_lenght
7
RESERVED
8
out_of_range_source_id
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x0D8
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 54
2
1
0
[30:24] out_of_range_source_id: Holds the Source ID of the command that caused an out-of-range
interrupt request to the memory devices. This parameter is read-only.
For more information on out-of-range address checking, refer to the Other Memory Controller
Features paragraph in RM0078, Reference manual, SPEAr1340 architecture and functionality.
[22:16] out_of_range_lenght: Holds the length of the command that caused an out-of-range interrupt
request to the memory devices. This parameter is read-only.
For more information on out-of-range address checking, refer to the Other Memory Controller
Features paragraph in RM0078, Reference manual, SPEAr1340 architecture and functionality.
[14:8] ecc_u_synd: Stores the syndrome bits associated with a double-bit un-correctable ECC error
event. This parameter will only be used when an un-correctable error occurs and ECC error
reporting is enabled in the ctrl_raw parameter. This parameter is read-only.
[6:0] ecc_u_id: Contains the source ID associated with a double-bit un-correctable ECC event. This
parameter will only be used when an uncorrectable error occurs and ECC error reporting is
enabled in the ctrl_raw parameter. This parameter is read-only.
MPMC_CTRL_REG_55
Controller configuration register 55
4
3
port_cmd_error_id
5
RESERVED
6
port_data_error_id
7
RESERVED
8
rfu
9
dll_rst_adj_dly
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x0DC
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 55
[31:24] dll_rst_adj_dly: Specifies the minimum number of cycles after the master delay value is
programmed before the DLL reset may be asserted.
[23:16] rfu: Reserved for future use: it is mandatory to set this parameter to 0x00
[14:8] port_data_error_id: Holds the source ID of the command that caused a port data error
condition. For AXI ports, the source ID is comprised of the Port ID and the Requestor ID, where
the Requestor ID is the axiY_BID for write response errors, the axiY_RID for read data errors,
or the axiY_WID for write data errors. This parameter is read-only.
[6:0] port_cmd_error_id: Holds the source ID of the command that caused a port command error
condition. For AXI ports, the source ID is comprised of the Port ID and the Requestor ID, where
the Requestor ID is the axiY_AWID for write commands or the axiY_ARID for read commands.
This parameter is read-only.
MPMC_CTRL_REG_56
Controller configuration register 56 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x0E0
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 56 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_57
Controller configuration register 57
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
swlvl_resp_1
swlvl_resp_0
refresh_per_zq
rfu
R
R
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x0E4
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 57
2
1
0
[31:24] swlvl_resp_1: Response for the software leveling process for data slice 1.
[23:16] swlvl_resp_0: Response for the software leveling process for data slice 0.
[15:8] refresh_per_zq: Sets the maximum number of refreshes allowed between automatic ZQCS
commands. Setting this parameter to 0x0 will disable automatic ZQCS commands. When using
the rotate option (the parameter zqcs_rotate is set to 1), this parameter should be programmed
to the total number of cycles desired between ZQCS commands divided by the number of chip
selects in the system.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[7:0] rfu: Reserved for future use: it is mandatory to set this parameter to 0x00
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MPMC_CTRL_REG_58
Controller configuration register 58
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
tdfi_rdlvl_dll
swlvl_resp_4
swlvl_resp_3
swlvl_resp_2
R/W
R
R
R
Address:
MPMC_controllerBaseAddress + 0x0E8
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 58
1
0
[31:24] tdfi_rdlvl_dll: Defines the number of cycles required for the read leveling delay line to update
after a load.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[23:16] swlvl_resp_4: Response for the software leveling process for data slice 4.
[15:8] swlvl_resp_3: Response for the software leveling process for data slice 3.
[7:0] swlvl_resp_2: Response for the software leveling process for data slice 2.
MPMC_CTRL_REG_59
Controller configuration register 59
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
tdfi_wrlvl_en
tdfi_wrlvl_dll
tdfi_rdlvl_resplat
tdfi_rdlvl_en
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x0EC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 59
2
1
0
[31:24] tdfi_wrlvl_en: Defines the minimum number of cycles required after the write leveling enable
signal is asserted until the first write leveling load may be asserted or write strobe may be
asserted.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[23:16] tdfi_wrlvl_dll: Defines the number of cycles required for the write leveling delay line to update
after a load.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:8] tdfi_rdlvl_resplat: Defines the number of cycles after a read command until the response is
valid.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[7:0] tdfi_rdlvl_en: Defines the minimum number of cycles required after the read leveling enable
signal is asserted until the first read leveling load or read command may be asserted.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
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RM0089
MPMC_CTRL_REG_60
Controller configuration register 60
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
trcd_int
tras_min
tmod
tdfi_wrlvl_resplat
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x0F0
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 60
1
0
[31:24] trcd_int: Defines the DRAM RAS to CAS delay, in cycles.
[23:16] tras_min: Defines the DRAM minimum row activate time, in cycles.
[15:8] tmod: Defines the number of cycles of wait time after a mode register write to any nonmode
register write command. For write leveling, this is defined as the number of cycles of wait time
after a MRS command to the ODT enable
[7:0] tdfi_wrlvl_resplat: Defines the number of cycles after a write level strobe until the response is
valid.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_61
Controller configuration register 61
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
axi0_priority_relax
rfu
R
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x0F4
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
2
1
0
Controller configuration register 61
[17:8] axi0_priority_relax: Holds the counter value for AXI port 0 at which the priority relax condition
is triggered in weighted round robin arbitration.
[7:0] rfu: Reserved for future use: it is mandatory to set this parameter to 0x00.
MPMC_CTRL_REG_62
Controller configuration register 62
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
axi2_priority_relax
RESERVED
axi1_priority_relax
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0F8
Type:
R/W
Reset:
0x0000 0000
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Description:
Controller configuration register 62
[25:16] axi2_priority_relax: Holds the counter value for AXI port 2 at which the priority relax condition
is triggered in weighted round robin arbitration.
[9:0] axi1_priority_relax: Holds the counter value for AXI port 1 at which the priority relax condition
is triggered in weighted round robin arbitration.
MPMC_CTRL_REG_63
Controller configuration register 63
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
axi4_priority_relax
RESERVED
axi3_priority_relax
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x0FC
Type:
R/W
Reset:
0x0000 0000
Description:
2
1
0
Controller configuration register 63
[25:16] axi4_priority_relax: Holds the counter value for AXI port 4 at which the priority relax condition
is triggered in weighted round robin arbitration.
[9:0] axi3_priority_relax: Holds the counter value for AXI port 3 at which the priority relax condition
is triggered in weighted round robin arbitration.
MPMC_CTRL_REG_64
Controller configuration register 63
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
tdfi_rdlvl_rr
RESERVED
axi5_priority_relax
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x100
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 63
2
1
0
[25:16] tdfi_rdlvl_rr: Sets the minimum number of cycles that must occur between read commands.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[9:0] axi5_priority_relax: Holds the counter value for AXI port 5 at which the priority relax condition
is triggered in weighted round robin arbitration.
MPMC_CTRL_REG_65
Controller configuration register 65
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
rfu
RESERVED
tdfi_wrlvl_ww
R
R
R
R/W
Address:
MPMC_controllerBaseAddress + 0x104
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 65
[25:16] rfu: Reserved for future use:this parameter is read-only and will always read back as 0x000.
[9:0] tdfi_wrlvl_ww: Sets the minimum number of cycles that must occur between write level
strobes.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_66
Controller configuration register 66
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
RESERVED
zqcs
RESERVED
zqcl
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x108
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 66
4
3
2
1
0
[25:16] zqcs: Specifies the duration of wait time, in cycles, required for the memory devices to
complete a short ZQ calibration command (ZQCS).
Note: If the zqcs_rotate parameter will be used, the user should program this parameter
accordingly. If each memory device must receive a ZQCS command every X cycles, and
there are a total of Y chip selects in the system, then the zqcs parameter should be
programmed to X/Y.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[11:0] zqcl: Specifies the duration of wait time, in cycles, required for the memory devices to complete
a long ZQ calibration command (ZQCL).
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
Note: This parameter must be set to 1/2 of the time set in the zqinit parameter.
MPMC_CTRL_REG_67
Controller configuration register 67
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
RESERVED
tdfi_ctrlupd_max
RESERVED
zqinit
R
R
R
R/W
Address:
MPMC_controllerBaseAddress + 0x10C
Type:
R/W
Reset:
0x0000 0000
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Description:
Controller configuration register 67
[27:16] tdfi_ctrlupd_max: Holds the DFI tctrlupd_max timing parameter. This parameter is read-only.
[11:0] zqinit: Specifies the duration of wait time, in cycles, required for the memory devices to
complete a ZQ command during initialization.
Note: This parameter should be set to the ZQCL time. Internally, the MC will set the time
required for a ZQCL to 1/2 of this setting.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_68
Controller configuration register 68
7
6
tdfi_phyupd_resp
8
RESERVED
9
tdfi_phyupd_type0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
MPMC_controllerBaseAddress + 0x110
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 68
5
4
3
2
1
0
[31:16] tdfi_phyupd_type0: Holds the DFI tphyupd_type0 timing parameter. This parameter is
read-only.
[13:0] tdfi_phyupd_resp: Holds the DFI tphyupd_resp timing parameter. This parameter is read-only.
MPMC_CTRL_REG_69
Controller configuration register 69
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
tdfi_phyupd_type2
tdfi_phyupd_type1
R
R/W
Address:
MPMC_controllerBaseAddress + 0x114
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 69
5
4
3
2
1
0
[31:16] tdfi_phyupd_type2: Holds the DFI tphyupd_type2 timing parameter. This parameter is
read-only.
[15:0] tdfi_phyupd_type1: Holds the DFI tphyupd_type1 timing parameter. This parameter is
read-only.
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RM0089
MPMC_CTRL_REG_70
Controller configuration register 70
7
tdfi_phyupd_type3
8
tref
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R/W
Address:
MPMC_controllerBaseAddress + 0x118
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 70
6
5
4
3
2
1
0
[29:16] tref: Defines the DRAM cycles between refresh commands. This parameter sets the average
interval between refreshes. The actual interval may vary by up to 8 cycles from refresh to
refresh, depending on other activities that are occurring in the controller at the time. Over an
infinite time period, the average interval will be equal to the number of clocks set by this
parameter; however, if the user sets this parameter to be exactly equal to the specification
value tREFi, then local variations might mean that the memory tREF value may be violated by a
very small amount. The amount of this violation would be 8tCK/tREF. For example, for a
400MHz memory and tREF=64ms, the amount of the violation would be 2.5ns/64ms =
0.000004%, but this violation may still be detected by some memory models.We have never
seen a failure in a real system as a result of programming the tref parameter to the exact tREFi
parameter, but if the warning from the memory model is concerning, the user should program
the tref parameter to the value (tREFi/tCK)-8, which will result in slightly lower overall bandwidth
and slightly higher memory power usage.
[15:0] tdfi_phyupd_type3: Holds the DFI tphyupd_type3 timing parameter. This parameter is
read-only.
MPMC_CTRL_REG_71
Controller configuration register 71
mr0_data_0
7
RESERVED
8
mr0_data_1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x11C
Type:
R/W
Reset:
0x0000 0000
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Description:
Controller configuration register 71
[30:16] mr0_data_1: Holds the memory mode register 0 data for chip select 1 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a) For DDR2 memories: This parameter correlates to the memory mode register (MR). The
memory controller does not support interleaving and therefore the A3 bit should be cleared to
0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that
sets the DLL Reset bit during initialization. Also, the memory controller only supports a burst
length of 4 and therefore the bits A2:A0 should be set to 010.
b) For DDR3 memories: This parameter correlates to the memory mode register 0 (MR0). The
memory controller does not support interleaving and therefore the A3 bit should be cleared to
0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that
sets the DLL Reset bit during initialization.
This data will be
programmed into the memory register of the DRAM at initialization or when the write_modereg
parameter is set to 1.
[14:0] mr0_data_0: Holds the memory mode register 0 data for chip select 0 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a) For DDR2 memories: This parameter correlates to the memory mode register (MR). The
memory controller does not support interleaving and therefore the A3 bit should be cleared to
0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that
sets the DLL Reset bit during initialization. Also, the memory controller only supports a burst
length of 4 and therefore the bits A2:A0 should be set to 010.
b) For DDR3 memories: This parameter correlates to the memory mode register 0 (MR0). The
memory controller does not support interleaving and therefore the A3 bit should be cleared to
0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that
sets the DLL Reset bit during initialization.
This data will be
programmed into the memory register of the DRAM at initialization or when the write_modereg
parameter is set to 1.
MPMC_CTRL_REG_72
Controller configuration register 72
mr1_data_0
7
RESERVED
8
mr1_data_1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x120
Type:
R/W
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 72
[30:16] mr1_data_1: Holds the memory mode register 1 data for chip select 1 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a) For DDR2 memories: This parameter correlates to the extended memory mode register 1
(EMR1). The memory controller does not support additive latency and therefore the A5:A3 bits
should be cleared to 000.
b) For DDR3 memories: This parameter correlates to the memory mode register 1 (MR1). The
memory controller does not support additive latency and therefore the A4:A3 bits should be
cleared to 000.
Note: The RTT termination will be set to 40 Ohm at default. The user is required is to change
this setting to meet system specifications.
This data will be programmed into the appropriate memory register of the DRAM at
initialization or when the write_modereg parameter is set to 1
[14:0] mr1_data_0: Holds the memory mode register 1 data for chip select 0 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a) For DDR2 memories: This parameter correlates to the extended memory mode register 1
(EMR1). The memory controller does not support additive latency and therefore the A5:A3 bits
should be cleared to 000.
b) For DDR3 memories: This parameter correlates to the memory mode register 1 (MR1). The
memory controller does not support additive latency and therefore the A4:A3 bits should be
cleared to 000.
Note: The RTT termination will be set to 40 Ohm at default. The user is required is to change
this setting to meet system specifications.
This data will be
programmed into the appropriate memory register of the DRAM at initialization or when
the write_modereg parameter is set to 1
MPMC_CTRL_REG_73
Controller configuration register 73
mr2_data_0
7
RESERVED
8
mr2_data_1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x124
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
Controller configuration register 73
[30:16] mr2_data_1: Holds the memory mode register 2 data for chip select 1 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a) For DDR2 memories: This parameter correlates to the extended memory mode register 2
(EMR2).
b) For DDR3 memories: This parameter correlates to the memory mode register 2 (MR2).
This data will be programmed into the appropriate memory register of the DRAM at initialization
or when the write_modereg parameter is set to 1.
[14:0] mr2_data_0: Holds the memory mode register 2 data for chip select 0 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a) For DDR2 memories: This parameter correlates to the extended memory mode register 2
(EMR2).
b) For DDR3 memories: This parameter correlates to the memory mode register 2 (MR2).
This data will be programmed into the appropriate memory register of the DRAM at initialization
or when the write_modereg parameter is set to 1.
MPMC_CTRL_REG_74
Controller configuration register 74
mr3_data_0
7
RESERVED
8
mr3_data_1
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
Address:
MPMC_controllerBaseAddress + 0x128
Type:
R/W
Reset:
0x0000 0000
Description:
6
5
4
3
2
1
0
Controller configuration register 74
[30:16] mr3_data_1: Holds the memory mode register 3 data for chip select 1 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a)
For DDR2 memories: This parameter correlates to the extended memory mode register 3
(EMR3).
b) For DDR3 memories: This parameter correlates to the memory mode register 3 (MR3).
This data will be programmed into the appropriate memory register of the DRAM at initialization
or when the write_modereg parameter is set to 1.
[14:0] mr3_data_0: Holds the memory mode register 3 data for chip select 0 written during memory
initialization. Consult the memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this memory
controller:
a)
For DDR2 memories: This parameter correlates to the extended memory mode register 3
(EMR3).
b) For DDR3 memories: This parameter correlates to the memory mode register 3 (MR3).
This data will be programmed into the appropriate memory register of the DRAM at initialization
or when the write_modereg parameter is set to 1.
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Multi-port DDR controller (MPMC)
RM0089
MPMC_CTRL_REG_75
Controller configuration register 75
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
axi1_en_size_lt_width_instr
axi0_en_size_lt_width_instr
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x12C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 75
4
3
2
1
0
[31:16] axi1_en_size_lt_width_instr: Allows the port to accept size less than width transactions on
AXI port 1 from requestor Z. Each bit Z corresponds to requestor Z, meaning that if bit [16] is
set, then requestor 0 for AXI port 1 will be able to send size less than width transactions.
Example: if there are 5 requestors on a port and requestors 1, 3 and 4 were able to send size
less than width transactions, then port 1 axi1_en_size_lt_width_instr parameter would be set
to 0x001A.
0 = Requestor Z of port 1 may only issue size equal to width instructions.
1 = Requestor Z of port 1 can issue size equal to width or size less than width instructions.
[15:0] axi0_en_size_lt_width_instr: Allows the port to accept size less than width transactions on
AXI port 0 from requestor Z. Each bit Z corresponds to requestor Z, meaning that if bit [0] is set,
then requestor 0 for AXI port 0 will be able to send size less than width transactions.
Example: if there are 5 requestors on a port and requestors 1, 3 and 4 were able to send size
less than width transactions, then port 0 axi0_en_size_lt_width_instr parameter would be set
to 0x001A.
0 = Requestor Z of port 0 may only issue size equal to width instructions.
1 = Requestor Z of port 0 can issue size equal to width or size less than width instructions.
MPMC_CTRL_REG_76
Controller configuration register 76
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
axi2_en_size_lt_width_instr
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x130
Type:
R/W
Reset:
0x0000 0000
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2
1
0
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 76
[31:16] axi3_en_size_lt_width_instr: Allows the port to accept size less than width transactions on
AXI port 3 from requestor Z. Each bit Z corresponds to requestor Z, meaning that if bit [16] is
set, then requestor 0 for AXI port 3 will be able to send size less than width transactions.
Example: if there are 5 requestors on a port and requestors 1, 3 and 4 were able to send size
less than width transactions, then port 3 axi3_en_size_lt_width_instr parameter would be set
to 0x001A.
0 = Requestor Z of port 3 may only issue size equal to width instructions.
1 = Requestor Z of port 3 can issue size equal to width or size less than width instructions.
[15:0] axi2_en_size_lt_width_instr: Allows the port to accept size less than width transactions on
AXI port 2 from requestor Z. Each bit Z corresponds to requestor Z, meaning that if bit [0] is set,
then requestor 0 for AXI port 2 will be able to send size less than width transactions.
Example: if there are 5 requestors on a port and requestors 1, 3 and 4 were able to send size
less than width transactions, then port 2 axi2_en_size_lt_width_instr parameter would be set
to 0x001A.
0 = Requestor Z of port 2 may only issue size equal to width instructions.
1 = Requestor Z of port 2 can issue size equal to width or size less than width instructions.
MPMC_CTRL_REG_77
Controller configuration register 77
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
axi4_en_size_lt_width_instr
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x134
Type:
R/W
Reset:
0x0000 0000
Description:
9
axi5_en_size_lt_width_instr
4
3
2
1
0
Controller configuration register 77
[31:16] axi5_en_size_lt_width_instr: Allows the port to accept size less than width transactions on
AXI port 5 from requestor Z. Each bit Z corresponds to requestor Z, meaning that if bit [16] is
set, then requestor 0 for AXI port 5 will be able to send size less than width transactions.
Example: if there are 5 requestors on a port and requestors 1, 3 and 4 were able to send size
less than width transactions, then port 5 axi5_en_size_lt_width_instr parameter would be set to
0x001A.
0 = Requestor Z of port 5 may only issue size equal to width instructions.
1 = Requestor Z of port 5 can issue size equal to width or size less than width instructions.
[15:0] axi4_en_size_lt_width_instr: Allows the port to accept size less than width transactions on
AXI port 4 from requestor Z. Each bit Z corresponds to requestor Z, meaning that if bit [0] is set,
then requestor 0 for AXI port 4 will be able to send size less than width transactions.
Example: if there are 5 requestors on a port and requestors 1, 3 and 4 were able to send size
less than width transactions, then port 4 axi4_en_size_lt_width_instr parameter would be set to
0x001A.
0 = Requestor Z of port 4 may only issue size equal to width instructions.
1 = Requestor Z of port 4 can issue size equal to width or size less than width instructions.
MPMC_CTRL_REG_78
Controller configuration register 78
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
9
8
7
dll_rst_delay
rfu
R/W
R/W
6
5
4
3
2
1
0
MPMC_controllerBaseAddress + 0x138
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RM0089
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 78
[31:16] dll_rst_delay: Sets the number of cycles that the reset must be held asserted for the DLL.
[15:0] rfu: Reserved for future use: it is mandatory to set this parameter to 0x0000.
MPMC_CTRL_REG_79
Controller configuration register 79 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R
Address:
MPMC_controllerBaseAddress + 0x13C
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 79 (rfu)
[31:0] rfu: Reserved for future use, this register is read-only and will always read back as 0x00000000
MPMC_CTRL_REG_80
Controller configuration register 80 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R
Address:
MPMC_controllerBaseAddress + 0x140
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 80 (rfu)
[31:0] rfu: Reserved for future use, thisregister is read-only and will always read back as 0x00000000
MPMC_CTRL_REG_81
Controller configuration register 81
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
rdlvl_delay_0
rfu
R/W
R
Address:
MPMC_controllerBaseAddress + 0x144
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 81
6
5
4
3
2
1
0
[31:16] rdlvl_delay_0: Specifies the read leveling delay for data slice 0. This is the number of delay
elements in the delay line at which the read DQS is placed within the DQ data eye.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] rfu: Reserved for future use: this parameter is read-only and will always read back as 0x0000.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_82
Controller configuration register 82
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
rdlvl_delay_2
rdlvl_delay_1
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x148
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 82
5
4
3
2
1
0
[31:16] rdlvl_delay_2: Specifies the read leveling delay for data slice 2. This is the number of delay
elements in the delay line at which the read DQS is placed within the DQ data eye.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] rdlvl_delay_1: Specifies the read leveling delay for data slice 1. This is the number of delay
elements in the delay line at which the read DQS is placed within the DQ data eye.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_83
Controller configuration register 83
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
rdlvl_delay_4
rdlvl_delay_3
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x14C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 83
5
4
3
2
1
0
[31:16] rdlvl_delay_4: Specifies the read leveling delay for data slice 4. This is the number of delay
elements in the delay line at which the read DQS is placed within the DQ data eye.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] rdlvl_delay_3: Specifies the read leveling delay for data slice3. This is the number of delay
elements in the delay line at which the read DQS is placed within the DQ data eye.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_84
Controller configuration register 84 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R
Address:
MPMC_controllerBaseAddress + 0x150
Type:
R
Reset:
0x0000 0000
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Description:
RM0089
Controller configuration register 84 (rfu)
[31:0] rfu: Reserved for future use, this register is read-only and will always read back as 0x00000000
MPMC_CTRL_REG_85
Controller configuration register 85 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R
Address:
MPMC_controllerBaseAddress + 0x154
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 85 (rfu)
[31:0] rfu: Reserved for future use: thisregister is read-only and will always read back as 0x00000000
MPMC_CTRL_REG_86
Controller configuration register 86
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
rdlvl_gate_delay_0
rfu
R/W
R
Address:
MPMC_controllerBaseAddress + 0x158
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 86
6
5
4
3
2
1
0
[31:16] rdlvl_gate_delay_0: Specifies the gate delay for data slice 0. This is the number of delay
elements in the delay line at which the gate will be aligned to the rising edge of DQS for data
slice 0.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] rfu: Reserved for future use:this parameter is read-only and will always read back as 0x0000
MPMC_CTRL_REG_87
Controller configuration register 87
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
rdlvl_gate_delay_1
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x15C
Type:
R/W
Reset:
0x0000 0000
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5
4
3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 87
[31:16] rdlvl_gate_delay_2: Specifies the gate delay for data slice 2. This is the number of delay
elements in the delay line at which the gate will be aligned to the rising edge of DQS for data
slice 2.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] rdlvl_gate_delay_1: Specifies the gate delay for data slice 1. This is the number of delay
elements in the delay line at which the gate will be aligned to the rising edge of DQS for data
slice1.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_88
Controller configuration register 88
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
rdlvl_gate_delay_4
rdlvl_gate_delay_3
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x160
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 88
5
4
3
2
1
0
[31:16] rdlvl_gate_delay_4: Specifies the gate delay for data slice 4. This is the number of delay
elements in the delay line at which the gate will be aligned to the rising edge of DQS for data
slice 4.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] rdlvl_gate_delay_3: Specifies the gate delay for data slice 3. This is the number of delay
elements in the delay line at which the gate will be aligned to the rising edge of DQS for data
slice 3.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_89
Controller configuration register 89 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x164
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 89 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
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MPMC_CTRL_REG_90
RM0089
Controller configuration register 90 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R
Address:
MPMC_controllerBaseAddress + 0x168
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 90 (rfu)
[31:0] rfu: Reserved for future use, this register is read-only and will always read back as 0x00000000
MPMC_CTRL_REG_91
Controller configuration register 91 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R
Address:
MPMC_controllerBaseAddress + 0x16C
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 91 (rfu)
[31:0] rfu: Reserved for future use, this register is read-only and will always read back as 0x00000000
MPMC_CTRL_REG_92
Controller configuration register 92 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x170
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 92 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_93
Controller configuration register 93 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x174
Type:
R/W
Reset:
0x0000 0000
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8
7
6
5
4
3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 93 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_94
Controller configuration register 94 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x178
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 94 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_95
Controller configuration register 95 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x17C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 95 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_96
Controller configuration register 96
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
tdll
tcpd
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x180
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 96
6
5
4
3
2
1
0
[31:16] tdll: Defines the DRAM DLL lock time, in cycles.
[15:0] tcpd: Defines the clock enable to pre-charge delay time for the DRAM devices, in cycles.
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MPMC_CTRL_REG_97
Controller configuration register 97
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
rfu
tpdex
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x184
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 97
6
5
4
3
2
1
0
[31:16] rfu: Reserved for future use: it is mandatory to set this parameter to 0x0000.
[15:0] tpdex: Defines the DRAM power-down exit command period, in cycles. The user should load
this parameter with the txp value from the memory specification. The memory controller will use
this value for power-down exit time when the parameter mr0_data_X [12] bit (Dll Control for
PreCharge) is set to 1 (fast exit).
Note: There are two parameters to specify power-down exit time, tpdex and txpdll. This
parameter, tpdex, is the valid parameter for DDR2 memories. Therefore, when
dram_class is set to
0100, this parameter will be used for power-down exit time.
MPMC_CTRL_REG_98
Controller configuration register 98
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
txpdll
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x188
Type:
R/W
Reset:
0x0000 0000
Description:
9
txsnr
6
5
4
3
2
1
0
Controller configuration register 98
[31:16] txsnr: Defines the DRAM time from a selfrefresh exit to a command that does not require the
memory DLL to be locked. (txs) When operating in DDR3 mode, the user should set this
parameter to the value of the txs parameter in the JEDEC spec.
[15:0] txpdll: Defines the DRAM power-down exit command period, in cycles. The user should load
this parameter with the txpdll value from the memory specification. The memory controller will
use this value for power-down exit time when the parameter mr0_data_X [12] bit (Dll Control for
PreCharge) is cleared to 0 (slow exit).
MPMC_CTRL_REG_99
Controller configuration register 99
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
version
txsr
R
R/W
Address:
MPMC_controllerBaseAddress + 0x18C
Type:
R/W
Reset:
0x2040 0000
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6
5
4
3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 99
[31:16] version: Holds the Memory Controller version number for this controller. This parameter is
read-only.
[15:0] txsr: Defines the DRAM time from a selfrefresh exit to a command that requires the memory
DLL to be locked. When operating in DDR3 mode, the user should set this parameter to the
value of the txsdll parameter in the JEDEC spec.
MPMC_CTRL_REG_100
Controller configuration register 100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
wrlvl_delay_1
wrlvl_delay_0
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x190
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 100
5
4
3
2
1
0
[31:16] wrlvl_delay_1: Specifies the write leveling delay for data slice 1. This is the number of delay
elements in the delay line at which the write DQS rising edge aligns with the rising edge of the
memory clock.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] wrlvl_delay_0: Specifies the write leveling delay for data slice 0. This is the number of delay
elements in the delay line at which the write DQS rising edge aligns with the rising edge of the
memory clock.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_101
Controller configuration register 101
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
wrlvl_delay_3
wrlvl_delay_2
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x194
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 101
5
4
3
2
1
0
[31:16] wrlvl_delay_3: Specifies the write leveling delay for data slice 3. This is the number of delay
elements in the delay line at which the write DQS rising edge aligns with the rising edge of the
memory clock.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
[15:0] wrlvl_delay_2: Specifies the write leveling delay for data slice 2. This is the number of delay
elements in the delay line at which the write DQS rising edge aligns with the rising edge of the
memory clock.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
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Multi-port DDR controller (MPMC)
RM0089
MPMC_CTRL_REG_102
Controller configuration register 102
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
RESERVED
wrlvl_delay_4
R
R/W
Address:
MPMC_controllerBaseAddress + 0x198
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 102
5
4
3
2
1
0
[15:0] wrlvl_delay_4: Specifies the write leveling delay for data slice 4. This is the number of delay
elements in the delay line at which the write DQS rising edge aligns with the rising edge of the
memory clock.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_103
Controller configuration register 103
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
int_ack
R
W
Address:
MPMC_controllerBaseAddress + 0x19C
Type:
W
Reset:
0x0000 0000
Description:
Controller configuration register 103
9
8
7
6
5
4
3
2
1
0
[20:0] int_ack: Controls the clearing of the int_status parameter. If any of the int_ack bits are set to 1,
the corresponding bit in the int_status parameter will be cleared to 0. Any int_ack bits cleared to
0 will not alter the corresponding bit in the int_status parameter. This parameter will always
read back as 0x0.
MPMC_CTRL_REG_104
Controller configuration register 104
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
int_mask
R
R/W
Address:
MPMC_controllerBaseAddress + 0x1A0
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 104
9
8
7
6
5
4
3
2
1
0
[21:0] int_mask: Active-high mask bits that control the value of the memory controller_int signal on
the system interface. Unless the user has suppressed interrupt reporting (by setting the most
significant bit of this parameter to 1), all lower bits of the int_mask parameter will be inverted
and logically ANDed with the corresponding bits of the int_status parameter and the result is
reported on the controller_int signal.
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RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_105
Controller configuration register 105
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
int_status
R
R
Address:
MPMC_controllerBaseAddress + 0x1A4
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 105
9
8
7
6
5
4
3
2
1
0
[21:0] int_status: Shows the status of all possible interrupts generated by the memory controller. The
MSB is the result of a logical OR of all the lower bits. This parameter is read-only.
Note: Backwards compatibility is available for register parameters across configurations.
However, even with this compatibility, the individual bits, their meaning and the size of
the int_status parameter may change.
The int_status bits correspond to these interrupts:
Bit [21] = Logical OR of all lower bits.
Bit [20] = The user-initiated DLL resync has completed.
Bit [19] = A state change has been detected on the dfi_init_complete signal.
Bit [18] = The assertion of the inhibit_dram_cmd parameter has successfully inhibited
the command queue and/or MRR traffic.
Bit [17] = The register interfaceinitiated mode register write has completed and another
mode register
write may be issued.
Bit [16] = The leveling operation has completed.
Bit [15] = A leveling operation has been requested.
Bit [14] = A DFI update error has occurred. Error information can be found in the
update_error_status
parameter.
Bit [13] = A write leveling error has occurred. Error information can be found in the
wrlvl_error_status
parameter.
Bit [12] = A read leveling gate training error has occurred. Error information can be found
in the rdlvl_error_status parameter.
Bit [11] = A read leveling error has occurred. Error information can be found in the
rdlvl_error_status
parameter.
Bit [10] = ODT has been enabled while the MC is programmed for CAS latency 3. This is
an unsupported combination.
Bit [9] = The DRAM initialization has been completed.
Bit [8] = An error occurred on the port data channel.
Bit [7] = An error occurred on the port command channel.
Bit [6] = Multiple uncorrectable ECC events have been detected.
Bit [5] = An uncorrectable ECC event has been detected.
Bit [4] = Multiple correctable ECC events have been detected.
Bit [3] = A correctable ECC event has been detected.
Bit [2] = Multiple accesses outside the defined PHYSICAL memory space have
occurred.
Bit [1] = A memory access outside the defined PHYSICAL memory space has occurred.
Bit [0] = The memory reset is valid on the DFI bus
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_106
RM0089
Controller configuration register 106 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R
Address:
MPMC_controllerBaseAddress + 0x1A8
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 106 (rfu)
[31:0] rfu: Reserved for future use, this register is read-only and will always read back as 0x00000000
MPMC_CTRL_REG_107
Controller configuration register 107: PHY conf reg
8 for data slice 0
6
5
4
3
2
1
0
ddr3_mode
7
RESERVED
8
loopback_control
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1AC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 107: PHY conf reg 8 for data slice 0
[14:8] loopback_control: Data slice 0 loopback control.
Bit [14] = Initiate loopback for data slice.
-- 0 = Stop.
-- 1 = Go.
Bit [13:12] = Data slice loopback duration.
-- 00 = free running.
-- 01 = 1024 clocks.
-- 10 = 8192 clocks.
-- 11 = 64K clocks.
Bit [11] = Data slice loopback clear data error.
Bit [10] = Data slice loopback data type.
-- 0 = LFSR.
-- 1 = Clock pattern.
Bit [9] = Data slice loopback multiplexer use.
-- 0 = Internal mux.
-- 1 = External mux.
Bit [8] = Data slice loopback enable.
[0] ddr3_mode: Data slice 0 DDR3 mode enable.
DDR3 Mode. Enables the generation of the additional DQS pulse required for DDR3 controllers
to serve as the preamble of the write DQS.
-- 0 = No action
-- 1 = Generate Pulse
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RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_108
Controller configuration register 108: PHY conf reg
8 for data slice 1
5
4
3
2
1
0
ddr3_mode
6
RESERVED
7
loopback_control
8
R
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1B0
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Controller configuration register 108: PHY conf reg 8 for data slice 1
[14:8] loopback_control: Data slice 1 loopback control.
Bit [14] = Initiate loopback for data slice.
-- 0 = Stop.
-- 1 = Go.
Bit [13:12] = Data slice loopback duration.
-- 00 = free running.
-- 01 = 1024 clocks.
-- 10 = 8192 clocks.
-- 11 = 64K clocks.
Bit [11] = Data slice loopback clear data error.
Bit [10] = Data slice loopback data type.
-- 0 = LFSR.
-- 1 = Clock pattern.
Bit [9] = Data slice loopback multiplexer use.
-- 0 = Internal mux.
-- 1 = External mux.
Bit [8] = Data slice loopback enable.
[0] ddr3_mode: Data slice 1 DDR3 mode enable.
DDR3 Mode. Enables the generation of the additional DQS pulse required for DDR3 controllers
to serve as the preamble of the write DQS.
-- 0 = No action
-- 1 = Generate Pulse
MPMC_CTRL_REG_109
Controller configuration register 109: PHY conf reg
8 for data slice 2
Address:
6
5
4
3
2
1
0
ddr3_mode
7
RESERVED
8
loopback_control
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/
W
MPMC_controllerBaseAddress + 0x1B4
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Multi-port DDR controller (MPMC)
RM0089
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 109: PHY conf reg 8 for data slice 2
[14:8] loopback_control: Data slice 2 loopback control.
Bit [14] = Initiate loopback for data slice.
-- 0 = Stop.
-- 1 = Go.
Bit [13:12] = Data slice loopback duration.
-- 00 = free running.
-- 01 = 1024 clocks.
-- 10 = 8192 clocks.
-- 11 = 64K clocks.
Bit [11] = Data slice loopback clear data error.
Bit [10] = Data slice loopback data type.
-- 0 = LFSR.
-- 1 = Clock pattern.
Bit [9] = Data slice loopback multiplexer use.
-- 0 = Internal mux.
-- 1 = External mux.
Bit [8] = Data slice loopback enable.
[0] ddr3_mode: Data slice 2 DDR3 mode enable.
DDR3 Mode. Enables the generation of the additional DQS pulse required for DDR3 controllers
to serve as the preamble of the write DQS.
-- 0 = No action
-- 1 = Generate Pulse
MPMC_CTRL_REG_110
Controller configuration register 110: PHY conf reg
8 for data slice 3
5
4
3
2
1
0
ddr3_mode
6
RESERVED
7
loopback_control
8
R
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1B8
Type:
R/W
Reset:
0x0000 0000
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RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 110: PHY conf reg 8 for data slice 3
[14:8] loopback_control: Data slice 3 loopback control.
Bit [14] = Initiate loopback for data slice.
-- 0 = Stop.
-- 1 = Go.
Bit [13:12] = Data slice loopback duration.
-- 00 = free running.
-- 01 = 1024 clocks.
-- 10 = 8192 clocks.
-- 11 = 64K clocks.
Bit [11] = Data slice loopback clear data error.
Bit [10] = Data slice loopback data type.
-- 0 = LFSR.
-- 1 = Clock pattern.
Bit [9] = Data slice loopback multiplexer use.
-- 0 = Internal mux.
-- 1 = External mux.
Bit [8] = Data slice loopback enable.
[0] ddr3_mode: Data slice 3 DDR3 mode enable.
DDR3 Mode. Enables the generation of the additional DQS pulse required for DDR3 controllers
to serve as the preamble of the write DQS.
-- 0 = No action
-- 1 = Generate Pulse
MPMC_CTRL_REG_111
Controller configuration register 111: PHY conf reg
8 for data slice 4
6
5
4
3
2
1
0
ddr3_mode
7
RESERVED
8
loopback_control
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1BC
Type:
R/W
Reset:
0x0000 0000
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Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 111: PHY conf reg 8 for data slice 4
[14:8] loopback_control: Data slice 4 loopback control.
Bit [14] = Initiate loopback for data slice.
-- 0 = Stop.
-- 1 = Go.
Bit [13:12] = Data slice loopback duration.
-- 00 = free running.
-- 01 = 1024 clocks.
-- 10 = 8192 clocks.
-- 11 = 64K clocks.
Bit [11] = Data slice loopback clear data error.
Bit [10] = Data slice loopback data type.
-- 0 = LFSR.
-- 1 = Clock pattern.
Bit [9] = Data slice loopback multiplexer use.
-- 0 = Internal mux.
-- 1 = External mux.
Bit [8] = Data slice loopback enable.
[0] ddr3_mode: Data slice 4 DDR3 mode enable.
DDR3 Mode. Enables the generation of the additional DQS pulse required for DDR3 controllers
to serve as the preamble of the write DQS.
-- 0 = No action
-- 1 = Generate Pulse
MPMC_CTRL_REG_112
Controller configuration register 112
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
tinit
R
R/W
Address:
MPMC_controllerBaseAddress + 0x1C0
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 112
9
8
7
6
5
4
3
2
1
0
[23:0] tinit: Defines the DRAM initialization time, in cycles.
MPMC_CTRL_REG_113
Controller configuration register 113
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
xor_check_bits
R
R/W
Address:
MPMC_controllerBaseAddress + 0x1C4
Type:
R/W
Reset:
0x0000 0000
Description:
9
8
7
6
5
4
3
2
1
0
Controller configuration register 113
[27:0] xor_check_bits: When the fwc parameter is set, the check bits generated by the next write
operation will be XORed with this parameter. The result will be written into memory as the new
check value.
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RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_114
Controller configuration register 114
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
cke_inactive
R/W
Address:
MPMC_controllerBaseAddress + 0x1C8
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 114
[31:0] cke_inactive: Defines the number of cycles after reset before the CKE signal will be active.
Note: This parameter is only used by the hardware write leveling logic and when operating in
DDR3 mode (the dram_class parameter is set to 0110).
MPMC_CTRL_REG_115
Controller configuration register 115: DLL reg 0 for
data slice 0
3
RESERVED
4
dll_ctrl_reg_0_0_10to8
5
dll_ctrl_reg_0_0_11
6
dll_ctrl_reg_0_0_14to12
7
dll_ctrl_reg_0_0_15
8
dll_ctrl_reg_0_0_16
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/W
R/
W
R/W
R
Address:
MPMC_controllerBaseAddress + 0x1CC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 115: DLL reg 0 for data slice 0
2
1
0
[16] dll_ctrl_reg_0_0_16: Active high power down signal for the DLL.
[15] dll_ctrl_reg_0_0_15: Inverts dll_testclk2_out_0. Default is 0.
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Multi-port DDR controller (MPMC)
RM0089
[14:12] dll_ctrl_reg_0_0_14to12: Test control inputs for DLL output dll_tstclk2_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
[11] dll_ctrl_reg_0_0_11: Inverts dll_testclk1_out_0. Default is 0.
[10:8] dll_ctrl_reg_0_0_10to8: Test control inputs for DLL output dll_tstclk1_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
MPMC_CTRL_REG_116
Controller configuration register 116: DLL reg 0 for
data slice 1
dll_ctrl_reg_0_1_10to8
RESERVED
3
dll_ctrl_reg_0_1_11
4
dll_ctrl_reg_0_1_14to12
5
dll_ctrl_reg_0_1_15
6
R/
W
R/
W
R/W
R/
W
R/W
R
MPMC_controllerBaseAddress + 0x1D0
Type:
R/W
Reset:
0x0000 0000
Controller configuration register 116: DLL reg 0 for data slice 1
[16] dll_ctrl_reg_0_1_16: Active high power down signal for the DLL.
[15] dll_ctrl_reg_0_1_15: Inverts dll_testclk2_out_0. Default is 0.
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dll_ctrl_reg_0_1_16
8
R
Address:
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
[14:12] dll_ctrl_reg_0_1_14to12: Test control inputs for DLL output dll_tstclk2_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
[11] dll_ctrl_reg_0_1_11: Inverts dll_testclk1_out_0. Default is 0.
[10:8] dll_ctrl_reg_0_1_10to8: Test control inputs for DLL output dll_tstclk1_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
MPMC_CTRL_REG_117
Controller configuration register 117: DLL reg 0 for
data slice 2
RESERVED
3
dll_ctrl_reg_0_2_10to8
4
dll_ctrl_reg_0_2_11
5
dll_ctrl_reg_0_2_14to12
6
dll_ctrl_reg_0_2_15
7
dll_ctrl_reg_0_2_16
8
R
R/
W
R/
W
R/W
R/
W
R/W
R
Address:
MPMC_controllerBaseAddress + 0x1D4
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
Controller configuration register 117: DLL reg 0 for data slice 2
[16] dll_ctrl_reg_0_2_16: Active high power down signal for the DLL.
[15] dll_ctrl_reg_0_2_15: Inverts dll_testclk2_out_0. Default is 0.
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Multi-port DDR controller (MPMC)
RM0089
[14:12] dll_ctrl_reg_0_2_14to12: Test control inputs for DLL output dll_tstclk2_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
[11] dll_ctrl_reg_0_2_11: Inverts dll_testclk1_out_0. Default is 0.
[10:8] dll_ctrl_reg_0_2_10to8: Test control inputs for DLL output dll_tstclk1_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
MPMC_CTRL_REG_118
Controller configuration register 118: DLL reg 0 for
data slice 3
dll_ctrl_reg_0_3_10to8
RESERVED
3
dll_ctrl_reg_0_3_11
4
dll_ctrl_reg_0_3_14to12
5
dll_ctrl_reg_0_3_15
6
R/
W
R/
W
R/W
R/
W
R/W
R
MPMC_controllerBaseAddress + 0x1D8
Type:
R/W
Reset:
0x0000 0000
Controller configuration register 118: DLL reg 0 for data slice 3
[16] dll_ctrl_reg_0_3_16: Active high power down signal for the DLL.
[15] dll_ctrl_reg_0_3_15: Inverts dll_testclk2_out_0. Default is 0.
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dll_ctrl_reg_0_3_16
8
R
Address:
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
[14:12] dll_ctrl_reg_0_3_14to12: Test control inputs for DLL output dll_tstclk2_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
[11] dll_ctrl_reg_0_3_11: Inverts dll_testclk1_out_0. Default is 0.
[10:8] dll_ctrl_reg_0_3_10to8: Test control inputs for DLL output dll_tstclk1_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
MPMC_CTRL_REG_119
Controller configuration register 119: DLL reg 0 for
data slice 4
RESERVED
3
dll_ctrl_reg_0_4_10to8
4
dll_ctrl_reg_0_4_11
5
dll_ctrl_reg_0_4_14to12
6
dll_ctrl_reg_0_4_15
7
dll_ctrl_reg_0_4_16
8
R
R/
W
R/
W
R/W
R/
W
R/W
R
Address:
MPMC_controllerBaseAddress + 0x1DC
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
Controller configuration register 119: DLL reg 0 for data slice 4
[16] dll_ctrl_reg_0_4_16: Active high power down signal for the DLL.
[15] dll_ctrl_reg_0_4_15: Inverts dll_testclk2_out_0. Default is 0.
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533/1728
Multi-port DDR controller (MPMC)
RM0089
[14:12] dll_ctrl_reg_0_4_14to12: Test control inputs for DLL output dll_tstclk2_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
[11] dll_ctrl_reg_0_4_11: Inverts dll_testclk1_out_0. Default is 0.
[10:8] dll_ctrl_reg_0_4_10to8: Test control inputs for DLL output dll_tstclk1_out_0. Default is 000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
MPMC_CTRL_REG_120
Controller configuration register 120: DLL reg 0 for
addr/ctrl slice
dll_ctrl_reg_2_10to8
RESERVED
3
dll_ctrl_reg_2_11
4
dll_ctrl_reg_2_14to12
5
R/
W
R/
W
R/W
R/
W
R/W
R
MPMC_controllerBaseAddress + 0x1E0
Type:
R/W
Reset:
0x0000 0000
Controller configuration register 120: DLL reg 0 for addr/ctrl slice
[16] dll_ctrl_reg_2_16: Active-high power downsignal for the DLL.
[15] dll_ctrl_reg_2_15: Inverts adr_ctrl_dll_testclk2_out_X. Default is 0.
534/1728
6
dll_ctrl_reg_2_15
7
dll_ctrl_reg_2_16
8
R
Address:
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
[14:12] dll_ctrl_reg_2_14to12: Test control inputs for DLL output adr_ctrl_dll_tstclk2_out_X. Default is
000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
[11] dll_ctrl_reg_2_11: Inverts adr_ctrl_dll_testclk1_out_X. Default is 0.
[10:8] dll_ctrl_reg_2_10to8: Test control inputs for DLL output adr_ctrl_dll_tstclk1_out_X. Default is
000.
-- 000 = CLKOUT [0]
-- 001 = CLKOUT [2]
-- 010 = CLKOUT [4]
-- 011 = CLKOUT [6]
-- 100 = ref_pd
-- 101 = fb_pd
-- 110 = CLKOUT [1]
-- 111 = CLKOUT [3]
MPMC_CTRL_REG_121
Controller configuration register 121
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ecc_c_data
R
Address:
MPMC_controllerBaseAddress + 0x1E4
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 121
[31:0] ecc_c_data: Contains the pre-corrected data associated with a single-bit correctable ECC
event. This parameter will only be used when a correctable error occurs and ECC error
reporting is enabled in the ctrl_raw parameter. This parameter is read-only
MPMC_CTRL_REG_122
Controller configuration register 122
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ecc_u_data
R
Address:
MPMC_controllerBaseAddress + 0x1E8
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 122
[31:0] ecc_u_data: Contains the data associated with a double-bit un-correctable ECC event. This
parameter will only be used when an uncorrectable error occurs and ECC error reporting is
enabled in the ctrl_raw parameter. This parameter is read-only.
Doc ID 018904 Rev 3
535/1728
Multi-port DDR controller (MPMC)
RM0089
MPMC_CTRL_REG_123
Controller configuration register 123 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x1EC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 123 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_124
Controller configuration register 124: PHY conf reg
0 for data slice 0
1
0
manual_reset
2
RESERVED
3
rd_dqs_rise_disable_reg
4
rd_dqs_fall_disable_reg
5
rd_dqs_gate_coarse_reg
6
RESERVED
7
rd_dq_window_size_reg
8
RESERVED
9
wr_dq_coarse_reg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R
R/W
R/W
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1F0
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 124: PHY conf reg 0 for data slice 0
[31:29] wr_dq_coarse_reg: Number of cycles (+1) that the modified dfi_wrdata-based signal will be
delayed before data/mask is captured.
[27:26] rd_dq_window_size_reg: Number of locations from the phy_ctrl_conf reg_2_0 [23:0] or
phy_ctrl_conf reg_3_0 [23:0] settings that are valid.
Note: The 00 setting provides the greatest flexibility but can also produce added latency. This
same setting is used for all DQ bits.
-- 00 = All 8 settings are valid (-1/2 clk to +1/2 clk range).
-- 01 = 6 settings are valid (-3/8 clk to +3/8 clk range).
-- 10 = 4 settings are valid (-1/4 clk to +1/4 clk range).
-- 11 = Reserved.
[22:20] rd_dqs_gate_coarse_reg: Number of cycles (+1) that the modified dfi_rddata_en-based
signal will be delayed to form the coarse gate
[19:14] rd_dqs_fall_disable_reg: Disables the falling edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample.
[13:8] rd_dqs_rise_disable_reg: Disables the rising edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample
[0] manual_reset: 1b0 = No effect
1b1 = Reset the data path logic and cross-coupled NAND gates in the write timing block.
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Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_125
Controller configuration register 125: PHY conf reg
0 for data slice 1
1
0
manual_reset
2
RESERVED
3
rd_dqs_rise_disable_reg
4
rd_dqs_fall_disable_reg
5
rd_dqs_gate_coarse_reg
6
RESERVED
7
rd_dq_window_size_reg
8
RESERVED
9
wr_dq_coarse_reg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R
R/W
R/W
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1F4
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 125: PHY conf reg 0 for data slice 1
[31:29] wr_dq_coarse_reg: Number of cycles (+1) that the modified dfi_wrdata-based signal will be
delayed before data/mask is captured.
[27:26] rd_dq_window_size_reg: Number of locations from the phy_ctrl_conf reg_2_1 [23:0] or
phy_ctrl_conf reg_3_1 [23:0] settings that are valid.
Note: The 00 setting provides the greatest flexibility but can also produce added latency. This
same setting is used for all DQ bits.
-- 00 = All 8 settings are valid (-1/2 clk to +1/2 clk range).
-- 01 = 6 settings are valid (-3/8 clk to +3/8 clk range).
-- 10 = 4 settings are valid (-1/4 clk to +1/4 clk range).
-- 11 = Reserved.
[22:20] rd_dqs_gate_coarse_reg: Number of cycles (+1) that the modified dfi_rddata_en-based
signal will be delayed to form the coarse gate
[19:14] rd_dqs_fall_disable_reg: Disables the falling edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample.
[13:8] rd_dqs_rise_disable_reg: Disables the rising edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample
[0] manual_reset: 1b0 = No effect
1b1 = Reset the data path logic and cross-coupled NAND gates in the write timing block.
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_126
RM0089
Controller configuration register 126: PHY conf reg
0 for data slice 2
1
0
manual_reset
2
RESERVED
3
rd_dqs_rise_disable_reg
4
rd_dqs_fall_disable_reg
5
rd_dqs_gate_coarse_reg
6
RESERVED
7
rd_dq_window_size_reg
8
RESERVED
9
wr_dq_coarse_reg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R
R/W
R/W
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1F8
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 126: PHY conf reg 0 for data slice 2
[31:29] wr_dq_coarse_reg: Number of cycles (+1) that the modified dfi_wrdata-based signal will be
delayed before data/mask is captured.
[27:26] rd_dq_window_size_reg: Number of locations from the phy_ctrl_conf reg_2_2 [23:0] or
phy_ctrl_conf reg_3_2 [23:0] settings that are valid.
Note: The 00 setting provides the greatest flexibility but can also produce added latency. This
same setting is used for all DQ bits.
-- 00 = All 8 settings are valid (-1/2 clk to +1/2 clk range).
-- 01 = 6 settings are valid (-3/8 clk to +3/8 clk range).
-- 10 = 4 settings are valid (-1/4 clk to +1/4 clk range).
-- 11 = Reserved.
[22:20] rd_dqs_gate_coarse_reg: Number of cycles (+1) that the modified dfi_rddata_en-based
signal will be delayed to form the coarse gate
[19:14] rd_dqs_fall_disable_reg: Disables the falling edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample.
[13:8] rd_dqs_rise_disable_reg: Disables the rising edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample
[0] manual_reset: 1b0 = No effect
1b1 = Reset the data path logic and cross-coupled NAND gates in the write timing block.
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Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_127
Controller configuration register 127: PHY conf reg
0 for data slice 3
1
0
manual_reset
2
RESERVED
3
rd_dqs_rise_disable_reg
4
rd_dqs_fall_disable_reg
5
rd_dqs_gate_coarse_reg
6
RESERVED
7
rd_dq_window_size_reg
8
RESERVED
9
wr_dq_coarse_reg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R
R/W
R/W
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x1FC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 127: PHY conf reg 0 for data slice 3
[31:29] wr_dq_coarse_reg: Number of cycles (+1) that the modified dfi_wrdata-based signal will be
delayed before data/mask is captured.
[27:26] rd_dq_window_size_reg: Number of locations from the phy_ctrl_conf reg_2_3 [23:0] or
phy_ctrl_conf reg_3_3 [23:0] settings that are valid.
Note: The 00 setting provides the greatest flexibility but can also produce added latency. This
same setting is used for all DQ bits.
-- 00 = All 8 settings are valid (-1/2 clk to +1/2 clk range).
-- 01 = 6 settings are valid (-3/8 clk to +3/8 clk range).
-- 10 = 4 settings are valid (-1/4 clk to +1/4 clk range).
-- 11 = Reserved.
[22:20] rd_dqs_gate_coarse_reg: Number of cycles (+1) that the modified dfi_rddata_en-based
signal will be delayed to form the coarse gate
[19:14] rd_dqs_fall_disable_reg: Disables the falling edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample.
[13:8] rd_dqs_rise_disable_reg: Disables the rising edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample
[0] manual_reset: 1b0 = No effect
1b1 = Reset the data path logic and cross-coupled NAND gates in the write timing block.
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539/1728
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_128
RM0089
Controller configuration register 128: PHY conf reg
0 for data slice 4
1
0
manual_reset
2
RESERVED
3
rd_dqs_rise_disable_reg
4
rd_dqs_fall_disable_reg
5
rd_dqs_gate_coarse_reg
6
RESERVED
7
rd_dq_window_size_reg
8
RESERVED
9
wr_dq_coarse_reg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/W
R
R/W
R/W
R/W
R
R/
W
Address:
MPMC_controllerBaseAddress + 0x200
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 128: PHY conf reg 0 for data slice 4
[31:29] wr_dq_coarse_reg: Number of cycles (+1) that the modified dfi_wrdata-based signal will be
delayed before data/mask is captured.
[27:26] rd_dq_window_size_reg: Number of locations from the phy_ctrl_conf reg_2_4 [23:0] or
phy_ctrl_conf reg_3_4 [23:0] settings that are valid.
Note: The 00 setting provides the greatest flexibility but can also produce added latency. This
same setting is used for all DQ bits.
-- 00 = All 8 settings are valid (-1/2 clk to +1/2 clk range).
-- 01 = 6 settings are valid (-3/8 clk to +3/8 clk range).
-- 10 = 4 settings are valid (-1/4 clk to +1/4 clk range).
-- 11 = Reserved.
[22:20] rd_dqs_gate_coarse_reg: Number of cycles (+1) that the modified dfi_rddata_en-based
signal will be delayed to form the coarse gate
[19:14] rd_dqs_fall_disable_reg: Disables the falling edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample.
[13:8] rd_dqs_rise_disable_reg: Disables the rising edge pattern match of the corresponding bit in
the DQS 6-bit pattern sample
[0] manual_reset: 1b0 = No effect
1b1 = Reset the data path logic and cross-coupled NAND gates in the write timing block.
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Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
Controller configuration register 129: PHY conf reg
10 for addr/ctrl slice
recal_once_reg
recal_all_reg
ctl_call_offset_reg
loopback_control_start
loopback_duration
loopback_clear_data_error
loopback_control_enable
R/W
R/
W
R/
W
R/W
R/
W
R/W
R/
W
R/
W
6
5
4
3
2
1
ctl_8phase_sel_reg
wrlvl_base_offset_reg
R
7
ctl_source_sel_reg
RESERVED
R/
W
8
ctl_mux_sel_reg
clk_disable_polarity
R
9
clear_fifo_reg
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ctl_sel_override_reg
MPMC_CTRL_REG_129
R/
W
R/
W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x204
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 129: PHY conf reg 10 for addr/ctrl slice
0
[27] clk_disable_polarity: Defines polarity of the dram_clk_disable_conf reg. If set, inverts the
value of the dfi_dram_clk_disable signal as the value of the dram_clk_disable_conf reg
[22:20] wrlvl_base_offset_reg: Specifies the number of phases behind the calibrated clk_ref setting
to set the wrlvl_delay base value of 0.
[19] recal_once_reg: When this bit is set to 1, calibration will occur when the dfi_ctrlupd_req signal
is asserted by the MC. This bit must be cleared and set again before a dfi_ctrlupd_req signal
assertion will trigger another calibration procedure.
[18] recal_all_reg: When this bit is set to 1, calibration will occur on every assertion of the
dfi_ctrlupd_req signal from the MC.
[17:15] ctl_call_offset_reg: Type of adjustment to apply to ctl_8phase_sel_conf reg and
ctl_source_sel_conf reg when ctl_sel_adjust is set.
-- 100 = Subtract 1 from calibrated value.
-- 101 = Subtract 2 from calibrated value.
-- 110 = Add 1 to calibrated value.
-- 111 = Add 2 to calibrated value.
[14] loopback_control_start: Initiate loopback for address/control.
-- 0 = Stop.
-- 1 = Go.
[13:12] loopback_duration: Address/control loopback duration.
-- 00 = free running.
-- 01 = 1024 clocks.
-- 10 = 8192 clocks.
-- 11 = 64K clocks.
[11] loopback_clear_data_error: Address/control loopback/clear data error.
[10] loopback_control_enable: Address/control loopback enable
[9] clear_fifo_reg: When this bit is set to 1, the pointers in the gather FIFO will be reset.
[8] ctl_sel_override_reg: When this bit is set to 1,ctl_8phase_sel_conf reg, ctl_source_sel_conf
reg and ctl_mux_sel_conf reg will override the automatic calibration settings.
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Multi-port DDR controller (MPMC)
RM0089
[7:6] ctl_mux_sel_reg: Selects the clock phase for the flip-flop that sources the input to the output
stage flip-flop.
-- 00 = Selects positive edge of clk.
-- 01 = Selects negative edge of clk.
-- 10 = Selects a cycle-delayed positive edge of clk.
[5:3] ctl_source_sel_reg: Selects 1 of 8 clock phases to drive the second source of data to the
output stage flip-flop.
[2:0] ctl_8phase_sel_reg: Selects 1 of 8 clock phases to drive the output stage flip-flop.
MPMC_CTRL_REG_130
Controller configuration register 130: PHY conf reg
1 for data slice 0
wr_dqs_gate_deassert_fine_reg
wr_dqs_gate_coarse_deassert_reg
wr_dqs_gate_assert_fine_reg
wr_dqs_gate_coarse_assert_reg
1
wr_dqs_oe_coarse_assert_reg
2
wr_dqs_oe_assert_fine_reg
3
wr_dqs_oe_coarse_deassert_reg
4
wr_dqs_oe_deassert_fine_reg
5
wr_dq_oe_coarse_assert_reg
6
wr_dq_oe_assert_fine_reg
7
wr_dq_oe_coarse_deassert_reg
8
wr_dq_oe_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x208
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 130: PHY conf reg 1 for data slice 0
0
[29:28] wr_dq_oe_deassert_fine_reg: Delay of the write DQ/DM output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[27:25] wr_dq_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQ/DM OE.
[24:23] wr_dq_oe_assert_fine_reg: Delay of the write DQ/ DM output enable assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] wr_dq_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarseassertion for the DQ/DM OE.
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Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[19:18] wr_dqs_oe_deassert_fine_reg: Delay of the write DQS output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[17:15] wr_dqs_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS OE.
[14:13] wr_dqs_oe_assert_fine_reg: Delay of the write DQS output enable assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[12:10] wr_dqs_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS OE.
[9:8] wr_dqs_gate_deassert_fine_reg: Delay of the write DQS gate de-assertion from the coarse
adjustment value.
Note: When phy_ctrl_conf reg_0_0 [0] is set, this field contains the base value for a
dfi_wrlvl_delay_0 setting of 0.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
[7:5] wr_dqs_gate_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS gate.
[4:3] wr_dqs_gate_assert_fine_reg: Delay of the write DQS gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
[2:0] wr_dqs_gate_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS gate.
-- 000 = 0 cycles (DDR2) or 1 cycle (DDR3)
-- 001 = 1 cycle
-- 000 = 2 cycles
-- 001 = 3 cycles
-- 100 = 4 cycles
-- 101 = 5 cycles
-- 110 = 6 cycles
-- 111 = 7 cycles
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Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_131
RM0089
Controller configuration register 131: PHY conf reg
1 for data slice 1
wr_dqs_gate_deassert_fine_reg
wr_dqs_gate_coarse_deassert_reg
wr_dqs_gate_assert_fine_reg
wr_dqs_gate_coarse_assert_reg
1
wr_dqs_oe_coarse_assert_reg
2
wr_dqs_oe_assert_fine_reg
3
wr_dqs_oe_coarse_deassert_reg
4
wr_dqs_oe_deassert_fine_reg
5
wr_dq_oe_coarse_assert_reg
6
wr_dq_oe_assert_fine_reg
7
wr_dq_oe_coarse_deassert_reg
8
wr_dq_oe_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x20C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 131: PHY conf reg 1 for data slice 1
0
[29:28] wr_dq_oe_deassert_fine_reg: Delay of the write DQ/DM output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[27:25] wr_dq_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQ/DM OE.
[24:23] wr_dq_oe_assert_fine_reg: Delay of the write DQ/ DM output enable assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] wr_dq_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarseassertion for the DQ/DM OE.
[19:18] wr_dqs_oe_deassert_fine_reg: Delay of the write DQS output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[17:15] wr_dqs_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS OE.
[14:13] wr_dqs_oe_assert_fine_reg: Delay of the write DQS output enable assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
544/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[12:10] wr_dqs_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS OE.
[9:8] wr_dqs_gate_deassert_fine_reg: Delay of the write DQS gate de-assertion from the coarse
adjustment value.
Note: When phy_ctrl_conf reg_0_0 [0] is set, this field contains the base value for a
dfi_wrlvl_delay_0 setting of 0.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
[7:5] wr_dqs_gate_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS gate.
[4:3] wr_dqs_gate_assert_fine_reg: Delay of the write DQS gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
[2:0] wr_dqs_gate_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS gate.
-- 000 = 0 cycles (DDR2) or 1 cycle (DDR3)
-- 001 = 1 cycle
-- 000 = 2 cycles
-- 001 = 3 cycles
-- 100 = 4 cycles
-- 101 = 5 cycles
-- 110 = 6 cycles
-- 111 = 7 cycles
MPMC_CTRL_REG_132
Controller configuration register 132: PHY conf reg
1 for data slice 2
wr_dqs_gate_deassert_fine_reg
wr_dqs_gate_coarse_deassert_reg
wr_dqs_gate_assert_fine_reg
wr_dqs_gate_coarse_assert_reg
1
wr_dqs_oe_coarse_assert_reg
2
wr_dqs_oe_assert_fine_reg
3
wr_dqs_oe_coarse_deassert_reg
4
wr_dqs_oe_deassert_fine_reg
5
wr_dq_oe_coarse_assert_reg
6
wr_dq_oe_assert_fine_reg
7
wr_dq_oe_coarse_deassert_reg
8
wr_dq_oe_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x210
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
0
545/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 132: PHY conf reg 1 for data slice 2
[29:28] wr_dq_oe_deassert_fine_reg: Delay of the write DQ/DM output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[27:25] wr_dq_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQ/DM OE.
[24:23] wr_dq_oe_assert_fine_reg: Delay of the write DQ/ DM output enable assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] wr_dq_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarseassertion for the DQ/DM OE.
[19:18] wr_dqs_oe_deassert_fine_reg: Delay of the write DQS output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[17:15] wr_dqs_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS OE.
[14:13] wr_dqs_oe_assert_fine_reg: Delay of the write DQS output enable assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[12:10] wr_dqs_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS OE.
[9:8] wr_dqs_gate_deassert_fine_reg: Delay of the write DQS gate de-assertion from the coarse
adjustment value.
Note: When phy_ctrl_conf reg_0_0 [0] is set, this field contains the base value for a
dfi_wrlvl_delay_0 setting of 0.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
546/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[7:5] wr_dqs_gate_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS gate.
[4:3] wr_dqs_gate_assert_fine_reg: Delay of the write DQS gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
[2:0] wr_dqs_gate_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS gate.
-- 000 = 0 cycles (DDR2) or 1 cycle (DDR3)
-- 001 = 1 cycle
-- 000 = 2 cycles
-- 001 = 3 cycles
-- 100 = 4 cycles
-- 101 = 5 cycles
-- 110 = 6 cycles
-- 111 = 7 cycles
MPMC_CTRL_REG_133
Controller configuration register 133: PHY conf reg
1 for data slice 3
wr_dqs_gate_deassert_fine_reg
wr_dqs_gate_coarse_deassert_reg
wr_dqs_gate_assert_fine_reg
wr_dqs_gate_coarse_assert_reg
1
wr_dqs_oe_coarse_assert_reg
2
wr_dqs_oe_assert_fine_reg
3
wr_dqs_oe_coarse_deassert_reg
4
wr_dqs_oe_deassert_fine_reg
5
wr_dq_oe_coarse_assert_reg
6
wr_dq_oe_assert_fine_reg
7
wr_dq_oe_coarse_deassert_reg
8
wr_dq_oe_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x214
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
0
547/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 133: PHY conf reg 1 for data slice 3
[29:28] wr_dq_oe_deassert_fine_reg: Delay of the write DQ/DM output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[27:25] wr_dq_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQ/DM OE.
[24:23] wr_dq_oe_assert_fine_reg: Delay of the write DQ/ DM output enable assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] wr_dq_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarseassertion for the DQ/DM OE.
[19:18] wr_dqs_oe_deassert_fine_reg: Delay of the write DQS output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[17:15] wr_dqs_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS OE.
[14:13] wr_dqs_oe_assert_fine_reg: Delay of the write DQS output enable assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[12:10] wr_dqs_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS OE.
[9:8] wr_dqs_gate_deassert_fine_reg: Delay of the write DQS gate de-assertion from the coarse
adjustment value.
Note: When phy_ctrl_conf reg_0_0 [0] is set, this field contains the base value for a
dfi_wrlvl_delay_0 setting of 0.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
548/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[7:5] wr_dqs_gate_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS gate.
[4:3] wr_dqs_gate_assert_fine_reg: Delay of the write DQS gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
[2:0] wr_dqs_gate_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS gate.
-- 000 = 0 cycles (DDR2) or 1 cycle (DDR3)
-- 001 = 1 cycle
-- 000 = 2 cycles
-- 001 = 3 cycles
-- 100 = 4 cycles
-- 101 = 5 cycles
-- 110 = 6 cycles
-- 111 = 7 cycles
MPMC_CTRL_REG_134
Controller configuration register 134: PHY conf reg
1 for data slice 4
wr_dqs_gate_deassert_fine_reg
wr_dqs_gate_coarse_deassert_reg
wr_dqs_gate_assert_fine_reg
wr_dqs_gate_coarse_assert_reg
1
wr_dqs_oe_coarse_assert_reg
2
wr_dqs_oe_assert_fine_reg
3
wr_dqs_oe_coarse_deassert_reg
4
wr_dqs_oe_deassert_fine_reg
5
wr_dq_oe_coarse_assert_reg
6
wr_dq_oe_assert_fine_reg
7
wr_dq_oe_coarse_deassert_reg
8
wr_dq_oe_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x218
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
0
549/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 134: PHY conf reg 1 for data slice 4
[29:28] wr_dq_oe_deassert_fine_reg: Delay of the write DQ/DM output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[27:25] wr_dq_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQ/DM OE.
[24:23] wr_dq_oe_assert_fine_reg: Delay of the write DQ/ DM output enable assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] wr_dq_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarseassertion for the DQ/DM OE.
[19:18] wr_dqs_oe_deassert_fine_reg: Delay of the write DQS output enable de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/4 clk delay.
-- 10 = 1/2 clk delay.
-- 11 = Reserved.
[17:15] wr_dqs_oe_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS OE.
[14:13] wr_dqs_oe_assert_fine_reg: Delay of the write DQS output enable assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[12:10] wr_dqs_oe_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS OE.
[9:8] wr_dqs_gate_deassert_fine_reg: Delay of the write DQS gate de-assertion from the coarse
adjustment value.
Note: When phy_ctrl_conf reg_0_0 [0] is set, this field contains the base value for a
dfi_wrlvl_delay_0 setting of 0.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
550/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[7:5] wr_dqs_gate_coarse_deassert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the DQS gate.
[4:3] wr_dqs_gate_assert_fine_reg: Delay of the write DQS gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved
[2:0] wr_dqs_gate_coarse_assert_reg: Number of cycles that the modified dfi_wrdata_en-based
signal will be delayed to form the coarse assertion for the DQS gate.
-- 000 = 0 cycles (DDR2) or 1 cycle (DDR3)
-- 001 = 1 cycle
-- 000 = 2 cycles
-- 001 = 3 cycles
-- 100 = 4 cycles
-- 101 = 5 cycles
-- 110 = 6 cycles
-- 111 = 7 cycles
MPMC_CTRL_REG_135
Controller configuration register 135: PHY conf reg
2 for data slice 0
rd_dq5_rise_position_offset_reg
rd_dq4_rise_position_offset_reg
rd_dq3_rise_position_offset_reg
rd_dq2_rise_position_offset_reg
rd_dq1_rise_position_offset_reg
rd_dq0_rise_position_offset_reg
1
rd_dq6_rise_position_offset_reg
2
rd_dq7_rise_position_offset_reg
3
rd_dq_rise_pattern_reg_0
4
rd_dq_rise_pattern_reg_1
5
rd_dq_rise_pattern_reg_2
6
rd_dq_rise_pattern_reg_3
7
rd_dq_rise_pattern_reg_4
8
rd_dq_rise_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x21C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 135: PHY conf reg 2 for data slice 0
0
[29] rd_dq_rise_pattern_reg_5: Enable pattern pulse #2 detect for the rising edge of DQS..
[28] rd_dq_rise_pattern_reg_4: Enable pattern pulse #1 detect for the rising edge of DQS
[27] rd_dq_rise_pattern_reg_3: Enable pattern two bit #3 detect for the rising edge of DQS.
[26] rd_dq_rise_pattern_reg_2: Enable pattern two bit #2 detect for the rising edge of DQS.
[25] rd_dq_rise_pattern_reg_1: Enable pattern two bit #1 detect for the rising edge of DQS.
[24] rd_dq_rise_pattern_reg_0: Enable pattern center detect for the rising edge of DQS.
[23:21] rd_dq7_rise_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
Doc ID 018904 Rev 3
551/1728
Multi-port DDR controller (MPMC)
RM0089
[20:18] rd_dq6_rise_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
[17:15] rd_dq5_rise_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
[14:12] rd_dq4_rise_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
[11:9] rd_dq3_rise_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
[8:6] rd_dq2_rise_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
[5:3] rd_dq1_rise_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
[2:0] rd_dq0_rise_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_0 base position for the rising DQS edge.
MPMC_CTRL_REG_136
Controller configuration register 136: PHY conf reg
2 for data slice 1
rd_dq5_rise_position_offset_reg
rd_dq4_rise_position_offset_reg
rd_dq3_rise_position_offset_reg
rd_dq2_rise_position_offset_reg
rd_dq1_rise_position_offset_reg
rd_dq0_rise_position_offset_reg
1
rd_dq6_rise_position_offset_reg
2
rd_dq7_rise_position_offset_reg
3
rd_dq_rise_pattern_reg_0
4
rd_dq_rise_pattern_reg_1
5
rd_dq_rise_pattern_reg_2
6
rd_dq_rise_pattern_reg_3
7
rd_dq_rise_pattern_reg_4
8
rd_dq_rise_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x220
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 136: PHY conf reg 2 for data slice 1
0
[29] rd_dq_rise_pattern_reg_5: Enable pattern pulse #2 detect for the rising edge of DQS..
[28] rd_dq_rise_pattern_reg_4: Enable pattern pulse #1 detect for the rising edge of DQS
[27] rd_dq_rise_pattern_reg_3: Enable pattern two bit #3 detect for the rising edge of DQS.
[26] rd_dq_rise_pattern_reg_2: Enable pattern two bit #2 detect for the rising edge of DQS.
[25] rd_dq_rise_pattern_reg_1: Enable pattern two bit #1 detect for the rising edge of DQS.
[24] rd_dq_rise_pattern_reg_0: Enable pattern center detect for the rising edge of DQS.
[23:21] rd_dq7_rise_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
[20:18] rd_dq6_rise_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
552/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[17:15] rd_dq5_rise_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
[14:12] rd_dq4_rise_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
[11:9] rd_dq3_rise_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
[8:6] rd_dq2_rise_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
[5:3] rd_dq1_rise_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
[2:0] rd_dq0_rise_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_1 base position for the rising DQS edge.
MPMC_CTRL_REG_137
Controller configuration register 137: PHY conf reg
2 for data slice 2
rd_dq5_rise_position_offset_reg
rd_dq4_rise_position_offset_reg
rd_dq3_rise_position_offset_reg
rd_dq2_rise_position_offset_reg
rd_dq1_rise_position_offset_reg
rd_dq0_rise_position_offset_reg
1
rd_dq6_rise_position_offset_reg
2
rd_dq7_rise_position_offset_reg
3
rd_dq_rise_pattern_reg_0
4
rd_dq_rise_pattern_reg_1
5
rd_dq_rise_pattern_reg_2
6
rd_dq_rise_pattern_reg_3
7
rd_dq_rise_pattern_reg_4
8
rd_dq_rise_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x224
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 137: PHY conf reg 2 for data slice 2
0
[29] rd_dq_rise_pattern_reg_5: Enable pattern pulse #2 detect for the rising edge of DQS..
[28] rd_dq_rise_pattern_reg_4: Enable pattern pulse #1 detect for the rising edge of DQS
[27] rd_dq_rise_pattern_reg_3: Enable pattern two bit #3 detect for the rising edge of DQS.
[26] rd_dq_rise_pattern_reg_2: Enable pattern two bit #2 detect for the rising edge of DQS.
[25] rd_dq_rise_pattern_reg_1: Enable pattern two bit #1 detect for the rising edge of DQS.
[24] rd_dq_rise_pattern_reg_0: Enable pattern center detect for the rising edge of DQS.
[23:21] rd_dq7_rise_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
[20:18] rd_dq6_rise_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
[17:15] rd_dq5_rise_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
Doc ID 018904 Rev 3
553/1728
Multi-port DDR controller (MPMC)
RM0089
[14:12] rd_dq4_rise_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
[11:9] rd_dq3_rise_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
[8:6] rd_dq2_rise_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
[5:3] rd_dq1_rise_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
[2:0] rd_dq0_rise_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_2 base position for the rising DQS edge.
MPMC_CTRL_REG_138
Controller configuration register 138: PHY conf reg
2 for data slice 3
rd_dq5_rise_position_offset_reg
rd_dq4_rise_position_offset_reg
rd_dq3_rise_position_offset_reg
rd_dq2_rise_position_offset_reg
rd_dq1_rise_position_offset_reg
rd_dq0_rise_position_offset_reg
1
rd_dq6_rise_position_offset_reg
2
rd_dq7_rise_position_offset_reg
3
rd_dq_rise_pattern_reg_0
4
rd_dq_rise_pattern_reg_1
5
rd_dq_rise_pattern_reg_2
6
rd_dq_rise_pattern_reg_3
7
rd_dq_rise_pattern_reg_4
8
rd_dq_rise_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x228
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 138: PHY conf reg 2 for data slice 3
0
[29] rd_dq_rise_pattern_reg_5: Enable pattern pulse #2 detect for the rising edge of DQS..
[28] rd_dq_rise_pattern_reg_4: Enable pattern pulse #1 detect for the rising edge of DQS
[27] rd_dq_rise_pattern_reg_3: Enable pattern two bit #3 detect for the rising edge of DQS.
[26] rd_dq_rise_pattern_reg_2: Enable pattern two bit #2 detect for the rising edge of DQS.
[25] rd_dq_rise_pattern_reg_1: Enable pattern two bit #1 detect for the rising edge of DQS.
[24] rd_dq_rise_pattern_reg_0: Enable pattern center detect for the rising edge of DQS.
[23:21] rd_dq7_rise_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
[20:18] rd_dq6_rise_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
[17:15] rd_dq5_rise_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
[14:12] rd_dq4_rise_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
554/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[11:9] rd_dq3_rise_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
[8:6] rd_dq2_rise_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
[5:3] rd_dq1_rise_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
[2:0] rd_dq0_rise_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_3 base position for the rising DQS edge.
MPMC_CTRL_REG_139
Controller configuration register 139: PHY conf reg
2 for data slice 4
rd_dq5_rise_position_offset_reg
rd_dq4_rise_position_offset_reg
rd_dq3_rise_position_offset_reg
rd_dq2_rise_position_offset_reg
rd_dq1_rise_position_offset_reg
rd_dq0_rise_position_offset_reg
1
rd_dq6_rise_position_offset_reg
2
rd_dq7_rise_position_offset_reg
3
rd_dq_rise_pattern_reg_0
4
rd_dq_rise_pattern_reg_1
5
rd_dq_rise_pattern_reg_2
6
rd_dq_rise_pattern_reg_3
7
rd_dq_rise_pattern_reg_4
8
rd_dq_rise_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x22C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 139: PHY conf reg 2 for data slice 4
0
[29] rd_dq_rise_pattern_reg_5: Enable pattern pulse #2 detect for the rising edge of DQS..
[28] rd_dq_rise_pattern_reg_4: Enable pattern pulse #1 detect for the rising edge of DQS
[27] rd_dq_rise_pattern_reg_3: Enable pattern two bit #3 detect for the rising edge of DQS.
[26] rd_dq_rise_pattern_reg_2: Enable pattern two bit #2 detect for the rising edge of DQS.
[25] rd_dq_rise_pattern_reg_1: Enable pattern two bit #1 detect for the rising edge of DQS.
[24] rd_dq_rise_pattern_reg_0: Enable pattern center detect for the rising edge of DQS.
[23:21] rd_dq7_rise_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
[20:18] rd_dq6_rise_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
[17:15] rd_dq5_rise_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
[14:12] rd_dq4_rise_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
[11:9] rd_dq3_rise_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
Doc ID 018904 Rev 3
555/1728
Multi-port DDR controller (MPMC)
RM0089
[8:6] rd_dq2_rise_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
[5:3] rd_dq1_rise_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
[2:0] rd_dq0_rise_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_4 base position for the rising DQS edge.
MPMC_CTRL_REG_140
Controller configuration register 140: PHY conf reg
3 for data slice 0
rd_dq5_fall_position_offset_reg
rd_dq4_fall_position_offset_reg
rd_dq3_fall_position_offset_reg
rd_dq2_fall_position_offset_reg
rd_dq1_fall_position_offset_reg
rd_dq0_fall_position_offset_reg
1
rd_dq6_fall_position_offset_reg
2
rd_dq7_fall_position_offset_reg
3
rd_dq_fall_pattern_reg_0
4
rd_dq_fall_pattern_reg_1
5
rd_dq_fall_pattern_reg_2
6
rd_dq_fall_pattern_reg_3
7
rd_dq_fall_pattern_reg_4
8
rd_dq_fall_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x230
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 140: PHY conf reg 3 for data slice 0
0
[29] rd_dq_fall_pattern_reg_5: Enable pattern pulse #2 detect for the falling edge of DQS..
[28] rd_dq_fall_pattern_reg_4: Enable pattern pulse #1 detect for thefalling edge of DQS
[27] rd_dq_fall_pattern_reg_3: Enable pattern two bit #3 detect for the falling edge of DQS.
[26] rd_dq_fall_pattern_reg_2: Enable pattern two bit #2 detect for the falling edge of DQS.
[25] rd_dq_fall_pattern_reg_1: Enable pattern two bit #1 detect for the falling edge of DQS.
[24] rd_dq_fall_pattern_reg_0: Enable pattern center detect for the falling edge of DQS.
[23:21] rd_dq7_fall_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
[20:18] rd_dq6_fall_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
[17:15] rd_dq5_fall_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
[14:12] rd_dq4_fall_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
[11:9] rd_dq3_fall_position_offset_reg: Offsetof the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
556/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[8:6] rd_dq2_fall_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
[5:3] rd_dq1_fall_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
[2:0] rd_dq0_fall_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_0 base position for the falling DQS edge.
MPMC_CTRL_REG_141
Controller configuration register 141: PHY conf reg
3 for data slice 1
rd_dq5_fall_position_offset_reg
rd_dq4_fall_position_offset_reg
rd_dq3_fall_position_offset_reg
rd_dq2_fall_position_offset_reg
rd_dq1_fall_position_offset_reg
rd_dq0_fall_position_offset_reg
1
rd_dq6_fall_position_offset_reg
2
rd_dq7_fall_position_offset_reg
3
rd_dq_fall_pattern_reg_0
4
rd_dq_fall_pattern_reg_1
5
rd_dq_fall_pattern_reg_2
6
rd_dq_fall_pattern_reg_3
7
rd_dq_fall_pattern_reg_4
8
rd_dq_fall_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x234
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 141: PHY conf reg 3 for data slice 1
0
[29] rd_dq_fall_pattern_reg_5: Enable pattern pulse #2 detect for the falling edge of DQS..
[28] rd_dq_fall_pattern_reg_4: Enable pattern pulse #1 detect for thefalling edge of DQS
[27] rd_dq_fall_pattern_reg_3: Enable pattern two bit #3 detect for the falling edge of DQS.
[26] rd_dq_fall_pattern_reg_2: Enable pattern two bit #2 detect for the falling edge of DQS.
[25] rd_dq_fall_pattern_reg_1: Enable pattern two bit #1 detect for the falling edge of DQS.
[24] rd_dq_fall_pattern_reg_0: Enable pattern center detect for the falling edge of DQS.
[23:21] rd_dq7_fall_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_1 base position for the falling DQS edge.
[20:18] rd_dq6_fall_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_ base position for the falling DQS edge.
[17:15] rd_dq5_fall_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_1 base position for the falling DQS edge.
[14:12] rd_dq4_fall_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_1 base position for the falling DQS edge.
[11:9] rd_dq3_fall_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_1 base position for the falling DQS edge.
Doc ID 018904 Rev 3
557/1728
Multi-port DDR controller (MPMC)
RM0089
[8:6] rd_dq2_fall_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_1 base position for the falling DQS edge.
[5:3] rd_dq1_fall_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_1 base position for the falling DQS edge.
[2:0] rd_dq0_fall_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_1 base position for the falling DQS edge.
MPMC_CTRL_REG_142
Controller configuration register 142: PHY conf reg
3 for data slice 2
rd_dq5_fall_position_offset_reg
rd_dq4_fall_position_offset_reg
rd_dq3_fall_position_offset_reg
rd_dq2_fall_position_offset_reg
rd_dq1_fall_position_offset_reg
rd_dq0_fall_position_offset_reg
1
rd_dq6_fall_position_offset_reg
2
rd_dq7_fall_position_offset_reg
3
rd_dq_fall_pattern_reg_0
4
rd_dq_fall_pattern_reg_1
5
rd_dq_fall_pattern_reg_2
6
rd_dq_fall_pattern_reg_3
7
rd_dq_fall_pattern_reg_4
8
rd_dq_fall_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x238
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 142: PHY conf reg 3 for data slice 2
0
[29] rd_dq_fall_pattern_reg_5: Enable pattern pulse #2 detect for the falling edge of DQS..
[28] rd_dq_fall_pattern_reg_4: Enable pattern pulse #1 detect for thefalling edge of DQS
[27] rd_dq_fall_pattern_reg_3: Enable pattern two bit #3 detect for the falling edge of DQS.
[26] rd_dq_fall_pattern_reg_2: Enable pattern two bit #2 detect for the falling edge of DQS.
[25] rd_dq_fall_pattern_reg_1: Enable pattern two bit #1 detect for the falling edge of DQS.
[24] rd_dq_fall_pattern_reg_0: Enable pattern center detect for the falling edge of DQS.
[23:21] rd_dq7_fall_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
[20:18] rd_dq6_fall_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
[17:15] rd_dq5_fall_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
[14:12] rd_dq4_fall_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
[11:9] rd_dq3_fall_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
558/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[8:6] rd_dq2_fall_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
[5:3] rd_dq1_fall_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
[2:0] rd_dq0_fall_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_2 base position for the falling DQS edge.
MPMC_CTRL_REG_143
Controller configuration register 143: PHY conf reg
3 for data slice 3
rd_dq5_fall_position_offset_reg
rd_dq4_fall_position_offset_reg
rd_dq3_fall_position_offset_reg
rd_dq2_fall_position_offset_reg
rd_dq1_fall_position_offset_reg
rd_dq0_fall_position_offset_reg
1
rd_dq6_fall_position_offset_reg
2
rd_dq7_fall_position_offset_reg
3
rd_dq_fall_pattern_reg_0
4
rd_dq_fall_pattern_reg_1
5
rd_dq_fall_pattern_reg_2
6
rd_dq_fall_pattern_reg_3
7
rd_dq_fall_pattern_reg_4
8
rd_dq_fall_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x23C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 143: PHY conf reg 3 for data slice 3
0
[29] rd_dq_fall_pattern_reg_5: Enable pattern pulse #2 detect for the falling edge of DQS..
[28] rd_dq_fall_pattern_reg_4: Enable pattern pulse #1 detect for thefalling edge of DQS
[27] rd_dq_fall_pattern_reg_3: Enable pattern two bit #3 detect for the falling edge of DQS.
[26] rd_dq_fall_pattern_reg_2: Enable pattern two bit #2 detect for the falling edge of DQS.
[25] rd_dq_fall_pattern_reg_1: Enable pattern two bit #1 detect for the falling edge of DQS.
[24] rd_dq_fall_pattern_reg_0: Enable pattern center detect for the falling edge of DQS.
[23:21] rd_dq7_fall_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_3 base position for the falling DQS edge.
[20:18] rd_dq6_fall_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_3 base position for the falling DQS edge.
[17:15] rd_dq5_fall_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_3 base position for the falling DQS edge.
[14:12] rd_dq4_fall_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_3 base position for the falling DQS edge.
[11:9] rd_dq3_fall_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_3 base position for the falling DQS edge.
Doc ID 018904 Rev 3
559/1728
Multi-port DDR controller (MPMC)
RM0089
[8:6] rd_dq2_fall_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_3 base position for the falling DQS edge.
[5:3] rd_dq1_fall_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_3 base position for the falling DQS edge.
[2:0] rd_dq0_fall_position_offset_reg: Beginning of the 4-bit data window (dq0) location relative to
the dfi_rdlvl_delay_3 base position for the falling DQS edge.
MPMC_CTRL_REG_144
Controller configuration register 144: PHY conf reg
3 for data slice 4
rd_dq5_fall_position_offset_reg
rd_dq4_fall_position_offset_reg
rd_dq3_fall_position_offset_reg
rd_dq2_fall_position_offset_reg
rd_dq1_fall_position_offset_reg
rd_dq0_fall_position_offset_reg
1
rd_dq6_fall_position_offset_reg
2
rd_dq7_fall_position_offset_reg
3
rd_dq_fall_pattern_reg_0
4
rd_dq_fall_pattern_reg_1
5
rd_dq_fall_pattern_reg_2
6
rd_dq_fall_pattern_reg_3
7
rd_dq_fall_pattern_reg_4
8
rd_dq_fall_pattern_reg_5
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x240
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 144: PHY conf reg 3 for data slice 4
0
[29] rd_dq_fall_pattern_reg_5: Enable pattern pulse #2 detect for the falling edge of DQS..
[28] rd_dq_fall_pattern_reg_4: Enable pattern pulse #1 detect for thefalling edge of DQS
[27] rd_dq_fall_pattern_reg_3: Enable pattern two bit #3 detect for the falling edge of DQS.
[26] rd_dq_fall_pattern_reg_2: Enable pattern two bit #2 detect for the falling edge of DQS.
[25] rd_dq_fall_pattern_reg_1: Enable pattern two bit #1 detect for the falling edge of DQS.
[24] rd_dq_fall_pattern_reg_0: Enable pattern center detect for the falling edge of DQS.
[23:21] rd_dq7_fall_position_offset_reg: Offset of the 4-bit data window (dq7) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
[20:18] rd_dq6_fall_position_offset_reg: Offset of the 4-bit data window (dq6) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
[17:15] rd_dq5_fall_position_offset_reg: Offset of the 4-bit data window (dq5) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
[14:12] rd_dq4_fall_position_offset_reg: Offset of the 4-bit data window (dq4) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
[11:9] rd_dq3_fall_position_offset_reg: Offset of the 4-bit data window (dq3) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
560/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[8:6] rd_dq2_fall_position_offset_reg: Offset of the 4-bit data window (dq2) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
[5:3] rd_dq1_fall_position_offset_reg: Offset of the 4-bit data window (dq1) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
[2:0] rd_dq0_fall_position_offset_reg: Offset of the 4-bit data window (dq0) location relative to the
dfi_rdlvl_delay_4 base position for the falling DQS edge.
MPMC_CTRL_REG_145
Controller configuration register 145: PHY conf reg
4 for data slice 0
wr_dq0_a_timing_reg
1
wr_dq1_a_timing_reg
2
wr_dq2_a_timing_reg
3
wr_dq3_a_timing_reg
4
wr_dq4_a_timing_reg
5
wr_dq5_a_timing_reg
6
wr_dq6_a_timing_reg
7
wr_dq7_a_timing_reg
8
wr_dm_a_timing_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x244
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 145: PHY conf reg 4 for data slice 0
0
[26:24] wr_dm_a_timing_reg: Identifies the clock phase generating DM prior to the rising edge of the
DQS clock phase.
[23:21] wr_dq7_a_timing_reg: Identifies the clock phase generating DQ7 prior to the rising edge of
the DQS clock phase.
[20:18] wr_dq6_a_timing_reg: Identifies the clock phase generating DQ6 prior to the rising edge of
the DQS clock phase.
[17:15] wr_dq5_a_timing_reg: Identifies the clock phase generating DQ5 prior to the rising edge of
the DQS clock phase.
[14:12] wr_dq4_a_timing_reg: Identifies the clock phase generating DQ4 prior to the rising edge of
the DQS clock phase.
[11:9] wr_dq3_a_timing_reg: Identifies the clock phase generating DQ3 prior to the rising edge of
the DQS clock phase.
[8:6] wr_dq2_a_timing_reg: Identifies the clock phase generating DQ2 prior to the rising edge of
the DQS clock phase.
[5:3] wr_dq1_a_timing_reg: Identifies the clock phase generating DQ1 prior to the rising edge of
the DQS clock phase.
[2:0] wr_dq0_a_timing_reg: Identifies the clock phase generating DQ0 prior to the rising edge of
the DQS clock phase.
Doc ID 018904 Rev 3
561/1728
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_146
RM0089
Controller configuration register 146: PHY conf reg
4 for data slice 1
wr_dq0_a_timing_reg
1
wr_dq1_a_timing_reg
2
wr_dq2_a_timing_reg
3
wr_dq3_a_timing_reg
4
wr_dq4_a_timing_reg
5
wr_dq5_a_timing_reg
6
wr_dq6_a_timing_reg
7
wr_dq7_a_timing_reg
8
wr_dm_a_timing_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x248
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 146: PHY conf reg 4 for data slice 1
0
[26:24] wr_dm_a_timing_reg: Identifies the clock phase generating DM prior to the rising edge of the
DQS clock phase
[23:21] wr_dq7_a_timing_reg: Identifies the clock phase generating DQ7 prior to the rising edge of
the DQS clock phase.
[20:18] wr_dq6_a_timing_reg: Identifies the clock phase generating DQ6 prior to the rising edge of
the DQS clock phase.
[17:15] wr_dq5_a_timing_reg: Identifies the clock phase generating DQ5 prior to the rising edge of
the DQS clock phase.
[14:12] wr_dq4_a_timing_reg: Identifies the clock phase generating DQ4 prior to the rising edge of
the DQS clock phase.
[11:9] wr_dq3_a_timing_reg: Identifies the clock phase generating DQ3 prior to the rising edge of
the DQS clock phase.
[8:6] wr_dq2_a_timing_reg: Identifies the clock phase generating DQ2 prior to the rising edge of
the DQS clock phase.
[5:3] wr_dq1_a_timing_reg: Identifies the clock phase generating DQ1 prior to the rising edge of
the DQS clock phase.
[2:0] wr_dq0_a_timing_reg: Identifies the clock phase generating DQ0 prior to the rising edge of
the DQS clock phase.
MPMC_CTRL_REG_147
Controller configuration register 147: PHY conf reg
4 for data slice 2
wr_dq0_a_timing_reg
1
wr_dq1_a_timing_reg
2
wr_dq2_a_timing_reg
3
wr_dq3_a_timing_reg
4
wr_dq4_a_timing_reg
5
wr_dq5_a_timing_reg
6
wr_dq6_a_timing_reg
7
wr_dq7_a_timing_reg
8
wr_dm_a_timing_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
562/1728
MPMC_controllerBaseAddress + 0x24C
Doc ID 018904 Rev 3
0
RM0089
Multi-port DDR controller (MPMC)
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 147: PHY conf reg 4 for data slice 2
[26:24] wr_dm_a_timing_reg: Identifies the clock phase generating DM prior to the rising edge of the
DQS clock phase.
[23:21] wr_dq7_a_timing_reg: Identifies the clock phase generating DQ7 prior to the rising edge of
the DQS clock phase.
[20:18] wr_dq6_a_timing_reg: Identifies the clock phase generating DQ6 prior to the rising edge of
the DQS clock phase.
[17:15] wr_dq5_a_timing_reg: Identifies the clock phase generating DQ5 prior to the rising edge of
the DQS clock phase.
[14:12] wr_dq4_a_timing_reg: Identifies the clock phase generating DQ4 prior to the rising edge of
the DQS clock phase.
[11:9] wr_dq3_a_timing_reg: Identifies the clock phase generating DQ3 prior to the rising edge of
the DQS clock phase.
[8:6] wr_dq2_a_timing_reg: Identifies the clock phase generating DQ2 prior to the rising edge of
the DQS clock phase.
[5:3] wr_dq1_a_timing_reg: Identifies the clock phase generating DQ1 prior to the rising edge of
the DQS clock phase.
[2:0] wr_dq0_a_timing_reg: Identifies the clock phase generating DQ0 prior to the rising edge of
the DQS clock phase.
MPMC_CTRL_REG_148
Controller configuration register 148: PHY conf reg
4 for data slice 3
wr_dq0_a_timing_reg
1
wr_dq1_a_timing_reg
2
wr_dq2_a_timing_reg
3
wr_dq3_a_timing_reg
4
wr_dq4_a_timing_reg
5
wr_dq5_a_timing_reg
6
wr_dq6_a_timing_reg
7
wr_dq7_a_timing_reg
8
wr_dm_a_timing_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x250
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 148: PHY conf reg 4 for data slice 3
0
[26:24] wr_dm_a_timing_reg: Identifies the clock phase generating DM prior to the rising edge of the
DQS clock phase.
[23:21] wr_dq7_a_timing_reg: Identifies the clock phase generating DQ7 prior to the rising edge of
the DQS clock phase.
[20:18] wr_dq6_a_timing_reg: Identifies the clock phase generating DQ6 prior to the rising edge of
the DQS clock phase.
Doc ID 018904 Rev 3
563/1728
Multi-port DDR controller (MPMC)
RM0089
[17:15] wr_dq5_a_timing_reg: Identifies the clock phase generating DQ5 prior to the rising edge of
the DQS clock phase.
[14:12] wr_dq4_a_timing_reg: Identifies the clock phase generating DQ4 prior to the rising edge of
the DQS clock phase.
[11:9] wr_dq3_a_timing_reg: Identifies the clock phase generating DQ3 prior to the rising edge of
the DQS clock phase.
[8:6] wr_dq2_a_timing_reg: Identifies the clock phase generating DQ2 prior to the rising edge of
the DQS clock phase.
[5:3] wr_dq1_a_timing_reg: Identifies the clock phase generating DQ1 prior to the rising edge of
the DQS clock phase.
[2:0] wr_dq0_a_timing_reg: Identifies the clock phase generating DQ0 prior to the rising edge of
the DQS clock phase.
MPMC_CTRL_REG_149
Controller configuration register 149: PHY conf reg
4 for data slice 4
wr_dq0_a_timing_reg
1
wr_dq1_a_timing_reg
2
wr_dq2_a_timing_reg
3
wr_dq3_a_timing_reg
4
wr_dq4_a_timing_reg
5
wr_dq5_a_timing_reg
6
wr_dq6_a_timing_reg
7
wr_dq7_a_timing_reg
8
wr_dm_a_timing_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x254
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 149: PHY conf reg 4 for data slice 4
0
[26:24] wr_dm_a_timing_reg: Identifies the clock phase generating DM prior to the rising edge of the
DQS clock phase.
[23:21] wr_dq7_a_timing_reg: Identifies the clock phase generating DQ7 prior to the rising edge of
the DQS clock phase.
[20:18] wr_dq6_a_timing_reg: Identifies the clock phase generating DQ6 prior to the rising edge of
the DQS clock phase.
[17:15] wr_dq5_a_timing_reg: Identifies the clock phase generating DQ5 prior to the rising edge of
the DQS clock phase.
[14:12] wr_dq4_a_timing_reg: Identifies the clock phase generating DQ4 prior to the rising edge of
the DQS clock phase.
[11:9] wr_dq3_a_timing_reg: Identifies the clock phase generating DQ3 prior to the rising edge of
the DQS clock phase.
564/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[8:6] wr_dq2_a_timing_reg: Identifies the clock phase generating DQ2 prior to the rising edge of
the DQS clock phase.
[5:3] wr_dq1_a_timing_reg: Identifies the clock phase generating DQ1 prior to the rising edge of
the DQS clock phase.
[2:0] wr_dq0_a_timing_reg: Identifies the clock phase generating DQ0 prior to the rising edge of
the DQS clock phase.
MPMC_CTRL_REG_150
Controller configuration register 150: PHY conf reg
5 for data slice 0
5
4
3
2
1
wr_dq_dqs_gate_coarse_assert_reg
6
wr_dq_dqs_gate_assert_fine_reg
7
wr_dq_dqs_gate_coarse_deassert_reg
8
wr_dq_dqs_gate_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x258
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 150: PHY conf reg 5 for data slice 0
0
[9:8] wr_dq_dqs_gate_deassert_fine_reg: Delay of the write clock gate de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] wr_dq_dqs_gate_coarse_deassert_reg: Number of cycles (+1) tha tthe modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the data clock
gate.
[4:3] wr_dq_dqs_gate_assert_fine_reg: Delay of the write clock gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] wr_dq_dqs_gate_coarse_assert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse assertion for the data clock gate.
Doc ID 018904 Rev 3
565/1728
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_151
RM0089
Controller configuration register 151: PHY conf reg
5 for data slice 1
5
4
3
2
1
wr_dq_dqs_gate_coarse_assert_reg
6
wr_dq_dqs_gate_assert_fine_reg
7
wr_dq_dqs_gate_coarse_deassert_reg
8
wr_dq_dqs_gate_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x25C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 151: PHY conf reg 5 for data slice 1
0
[9:8] wr_dq_dqs_gate_deassert_fine_reg: Delay of the write clock gate de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] wr_dq_dqs_gate_coarse_deassert_reg: Number of cycles (+1) tha tthe modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the data clock
gate.
[4:3] wr_dq_dqs_gate_assert_fine_reg: Delay of the write clock gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] wr_dq_dqs_gate_coarse_assert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse assertion for the data clock gate.
566/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_152
Controller configuration register 152: PHY conf reg
5 for data slice 2
5
4
3
2
1
wr_dq_dqs_gate_coarse_assert_reg
6
wr_dq_dqs_gate_assert_fine_reg
7
wr_dq_dqs_gate_coarse_deassert_reg
8
wr_dq_dqs_gate_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x260
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 152: PHY conf reg 5 for data slice 2
0
[9:8] wr_dq_dqs_gate_deassert_fine_reg: Delay of the write clock gate de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] wr_dq_dqs_gate_coarse_deassert_reg: Number of cycles (+1) tha tthe modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the data clock
gate.
[4:3] wr_dq_dqs_gate_assert_fine_reg: Delay of the write clock gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] wr_dq_dqs_gate_coarse_assert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse assertion for the data clock gate.
Doc ID 018904 Rev 3
567/1728
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_153
RM0089
Controller configuration register 153: PHY conf reg
5 for data slice 3
5
4
3
2
1
wr_dq_dqs_gate_coarse_assert_reg
6
wr_dq_dqs_gate_assert_fine_reg
7
wr_dq_dqs_gate_coarse_deassert_reg
8
wr_dq_dqs_gate_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x264
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 153: PHY conf reg 5 for data slice 3
0
[9:8] wr_dq_dqs_gate_deassert_fine_reg: Delay of the write clock gate de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] wr_dq_dqs_gate_coarse_deassert_reg: Number of cycles (+1) tha tthe modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the data clock
gate.
[4:3] wr_dq_dqs_gate_assert_fine_reg: Delay of the write clock gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] wr_dq_dqs_gate_coarse_assert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse assertion for the data clock gate.
568/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_154
Controller configuration register 154: PHY conf reg
5 for data slice 4
5
4
3
2
1
wr_dq_dqs_gate_coarse_assert_reg
6
wr_dq_dqs_gate_assert_fine_reg
7
wr_dq_dqs_gate_coarse_deassert_reg
8
wr_dq_dqs_gate_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x268
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 154: PHY conf reg 5 for data slice 4
0
[9:8] wr_dq_dqs_gate_deassert_fine_reg: Delay of the write clock gate de-assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] wr_dq_dqs_gate_coarse_deassert_reg: Number of cycles (+1) tha tthe modified
dfi_wrdata_en-based signal will be delayed to form the coarse de-assertion for the data clock
gate.
[4:3] wr_dq_dqs_gate_assert_fine_reg: Delay of the write clock gate assertion from the coarse
adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] wr_dq_dqs_gate_coarse_assert_reg: Number of cycles (+1) that the modified
dfi_wrdata_en-based signal will be delayed to form the coarse assertion for the data clock gate.
Doc ID 018904 Rev 3
569/1728
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_155
RM0089
Controller configuration register 155: PHY conf reg
6 for data slice 0
tsel_dqs_rd_deassert_fine_reg
tsel_dqs_rd_coarse_deassert_reg
tsel_dqs_rd_assert_fine_reg
tsel_dqs_rd_coarse_assert_reg
1
tsel_dqs_wr_coarse_assert_reg
2
tsel_dqs_wr_assert_fine_reg
3
tsel_dqs_wr_coarse_deassert_reg
4
tsel_dqs_wr_deassert_fine_reg
5
tsel_dq_rd_coarse_assert_reg
6
tsel_dq_rd_assert_fine_reg
7
tsel_dq_rd_coarse_deassert_reg
8
tsel_dq_rd_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x26C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 155: PHY conf reg 6 for data slice 0
0
[29:28] tsel_dq_rd_deassert_fine_reg: Delay of the DQ/DM read termination select de-assertion
from the coarse adjustment value..
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[27:25] tsel_dq_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read de-assertion.
[24:23] tsel_dq_rd_assert_fine_reg: Delay of the DQ/DM read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] tsel_dq_rd_coarse_assert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read assertion.
[19:18] tsel_dqs_wr_deassert_fine_reg: Delay of the DQS write termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[17:15] tsel_dqs_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQS write de-assertion.
[14:13] tsel_dqs_wr_assert_fine_reg: Delay of the DQS write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
570/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[12:10] tsel_dqs_wr_coarse_assert_reg: Number of cycles that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQS write assertion.
[9:8] tsel_dqs_rd_deassert_fine_reg: Delay of the DQS read termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] tsel_dqs_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will
be delayed to form the coarse select for DQS read de-assertion.
[4:3] tsel_dqs_rd_assert_fine_reg: Delay of the DQS read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] tsel_dqs_rd_coarse_assert_reg: Number of cycles that the dfi_rddata_en signal will be
delayed to form the coarse select for DQS read assertion.
MPMC_CTRL_REG_156
Controller configuration register 156: PHY conf reg
6 for data slice 1
tsel_dqs_rd_deassert_fine_reg
tsel_dqs_rd_coarse_deassert_reg
tsel_dqs_rd_assert_fine_reg
tsel_dqs_rd_coarse_assert_reg
1
tsel_dqs_wr_coarse_assert_reg
2
tsel_dqs_wr_assert_fine_reg
3
tsel_dqs_wr_coarse_deassert_reg
4
tsel_dqs_wr_deassert_fine_reg
5
tsel_dq_rd_coarse_assert_reg
6
tsel_dq_rd_assert_fine_reg
7
tsel_dq_rd_coarse_deassert_reg
8
tsel_dq_rd_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x270
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
0
571/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 156: PHY conf reg 6 for data slice 1
[29:28] tsel_dq_rd_deassert_fine_reg: Delay of the DQ/DM read termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[27:25] tsel_dq_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read de-assertion.
[24:23] tsel_dq_rd_assert_fine_reg: Delay of the DQ/DM read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] tsel_dq_rd_coarse_assert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read assertion.
[19:18] tsel_dqs_wr_deassert_fine_reg: Delay of the DQS write termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[17:15] tsel_dqs_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQS write de-assertion.
[14:13] tsel_dqs_wr_assert_fine_reg: Delay of the DQS write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[12:10] tsel_dqs_wr_coarse_assert_reg: Number of cycles that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQS write assertion.
[9:8] tsel_dqs_rd_deassert_fine_reg: Delay of the DQS read termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] tsel_dqs_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will
be delayed to form the coarse select for DQS read de-assertion.
[4:3] tsel_dqs_rd_assert_fine_reg: Delay of the DQS read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] tsel_dqs_rd_coarse_assert_reg: Number of cycles that the dfi_rddata_en signal will be
delayed to form the coarse select for DQS read assertion.
572/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_157
Controller configuration register 157: PHY conf reg
6 for data slice 2
tsel_dqs_rd_deassert_fine_reg
tsel_dqs_rd_coarse_deassert_reg
tsel_dqs_rd_assert_fine_reg
tsel_dqs_rd_coarse_assert_reg
1
tsel_dqs_wr_coarse_assert_reg
2
tsel_dqs_wr_assert_fine_reg
3
tsel_dqs_wr_coarse_deassert_reg
4
tsel_dqs_wr_deassert_fine_reg
5
tsel_dq_rd_coarse_assert_reg
6
tsel_dq_rd_assert_fine_reg
7
tsel_dq_rd_coarse_deassert_reg
8
tsel_dq_rd_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x274
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 157: PHY conf reg 6 for data slice 2
0
[29:28] tsel_dq_rd_deassert_fine_reg: Delay of the DQ/DM read termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[27:25] tsel_dq_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read de-assertion.
[24:23] tsel_dq_rd_assert_fine_reg: Delay of the DQ/DM read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] tsel_dq_rd_coarse_assert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read assertion.
[19:18] tsel_dqs_wr_deassert_fine_reg: Delay of the DQS write termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[17:15] tsel_dqs_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQS write de-assertion.
[14:13] tsel_dqs_wr_assert_fine_reg: Delay of the DQS write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
Doc ID 018904 Rev 3
573/1728
Multi-port DDR controller (MPMC)
RM0089
[12:10] tsel_dqs_wr_coarse_assert_reg: Number of cycles that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQS write assertion.
[9:8] tsel_dqs_rd_deassert_fine_reg: Delay of the DQS read termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 21 = Reserved.
[7:5] tsel_dqs_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will
be delayed to form the coarse select for DQS read de-assertion.
[4:3] tsel_dqs_rd_assert_fine_reg: Delay of the DQS read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] tsel_dqs_rd_coarse_assert_reg: Number of cycles that the dfi_rddata_en signal will be
delayed to form the coarse select for DQS read assertion.
MPMC_CTRL_REG_158
Controller configuration register 158: PHY conf reg
6 for data slice 3
tsel_dqs_rd_deassert_fine_reg
tsel_dqs_rd_coarse_deassert_reg
tsel_dqs_rd_assert_fine_reg
tsel_dqs_rd_coarse_assert_reg
1
tsel_dqs_wr_coarse_assert_reg
2
tsel_dqs_wr_assert_fine_reg
3
tsel_dqs_wr_coarse_deassert_reg
4
tsel_dqs_wr_deassert_fine_reg
5
tsel_dq_rd_coarse_assert_reg
6
tsel_dq_rd_assert_fine_reg
7
tsel_dq_rd_coarse_deassert_reg
8
tsel_dq_rd_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x278
Type:
R/W
Reset:
0x0000 0000
574/1728
Doc ID 018904 Rev 3
0
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 158: PHY conf reg 6 for data slice 3
[29:28] tsel_dq_rd_deassert_fine_reg: Delay of the DQ/DM read termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[27:25] tsel_dq_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read de-assertion.
[24:23] tsel_dq_rd_assert_fine_reg: Delay of the DQ/DM read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] tsel_dq_rd_coarse_assert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read assertion.
[19:18] tsel_dqs_wr_deassert_fine_reg: Delay of the DQS write termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[17:15] tsel_dqs_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQS write de-assertion.
[14:13] tsel_dqs_wr_assert_fine_reg: Delay of the DQS write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[12:10] tsel_dqs_wr_coarse_assert_reg: Number of cycles that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQS write assertion.
[9:8] tsel_dqs_rd_deassert_fine_reg: Delay of the DQS read termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] tsel_dqs_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will
be delayed to form the coarse select for DQS read de-assertion.
[4:3] tsel_dqs_rd_assert_fine_reg: Delay of the DQS read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] tsel_dqs_rd_coarse_assert_reg: Number of cycles that the dfi_rddata_en signal will be
delayed to form the coarse select for DQS read assertion.
Doc ID 018904 Rev 3
575/1728
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_159
RM0089
Controller configuration register 159: PHY conf reg
6 for data slice 4
tsel_dqs_rd_deassert_fine_reg
tsel_dqs_rd_coarse_deassert_reg
tsel_dqs_rd_assert_fine_reg
tsel_dqs_rd_coarse_assert_reg
1
tsel_dqs_wr_coarse_assert_reg
2
tsel_dqs_wr_assert_fine_reg
3
tsel_dqs_wr_coarse_deassert_reg
4
tsel_dqs_wr_deassert_fine_reg
5
tsel_dq_rd_coarse_assert_reg
6
tsel_dq_rd_assert_fine_reg
7
tsel_dq_rd_coarse_deassert_reg
8
tsel_dq_rd_deassert_fine_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x27C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 159: PHY conf reg 6 for data slice 4
0
[29:28] tsel_dq_rd_deassert_fine_reg: Delay of the DQ/DM read termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[27:25] tsel_dq_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read de-assertion.
[24:23] tsel_dq_rd_assert_fine_reg: Delay of the DQ/DM read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[22:20] tsel_dq_rd_coarse_assert_reg: Number of cycles (+1) that the dfi_rddata_en signal will be
delayed to form the coarse select for DQ/DM read assertion.
[19:18] tsel_dqs_wr_deassert_fine_reg: Delay of the DQS write termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[17:15] tsel_dqs_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQS write de-assertion.
[14:13] tsel_dqs_wr_assert_fine_reg: Delay of the DQS write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
576/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[12:10] tsel_dqs_wr_coarse_assert_reg: Number of cycles that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQS write assertion.
[9:8] tsel_dqs_rd_deassert_fine_reg: Delay of the DQS read termination select de-assertion from
the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[7:5] tsel_dqs_rd_coarse_deassert_reg: Number of cycles (+1) that the dfi_rddata_en signal will
be delayed to form the coarse select for DQS read de-assertion.
[4:3] tsel_dqs_rd_assert_fine_reg: Delay of the DQS read termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[2:0] tsel_dqs_rd_coarse_assert_reg: Number of cycles that the dfi_rddata_en signal will be
delayed to form the coarse select for DQS read assertion.
MPMC_CTRL_REG_160
Controller configuration register 160: PHY conf reg
7 for data slice 0
Address:
MPMC_controllerBaseAddress + 0x280
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
1
0
dqs_tsel_enable_reg_read
R/W
2
dqs_tsel_enable_reg_write
dq_tsel_mux_reg_read
R/W
3
dqs_tsel_enable_reg_idle
dq_tsel_mux_reg_write
R/W
4
dqs_tsel_mux_reg_read
dq_tsel_mux_reg_idle
R/W
5
dqs_tsel_mux_reg_write
tsel_dq_wr_coarse_assert_reg
R/W
6
dqs_tsel_mux_reg_idle
tsel_dq_wr_assert_fine_reg
R/W
7
dq_tsel_enable_reg_read
tsel_dq_wr_coarse_deassert_reg
R/W
8
dq_tsel_enable_reg_idle
tsel_dq_wr_deassert_fine_reg
R
9
dq_tsel_enable_reg_write
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/
W
R/
W
R/
W
577/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 160: PHY conf reg 7 for data slice 0
[27:26] tsel_dq_wr_deassert_fine_reg: Delay of the DQ/DM write termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[25:23] tsel_dq_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQ/DM write de-assertion.
[22:21] tsel_dq_wr_assert_fine_reg: Delay of the DQ/DM write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[20:18] tsel_dq_wr_coarse_assert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQ/DM write assertion.
[17:16] dq_tsel_mux_reg_idle: External DQ/DM termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[15:14] dq_tsel_mux_reg_write: External DQ/DM termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[13:12] dq_tsel_mux_reg_read: External DQ/DM termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[11] dq_tsel_enable_reg_idle: Enables the DQ/DM termination select on an idle cycle.
[10] dq_tsel_enable_reg_write: Enables the DQ/DM termination select on a write cycle.
[9] dq_tsel_enable_reg_read: Enables the DQ/DM termination select on a read cycle.
[8:7] dqs_tsel_mux_reg_idle: External DQS termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[6:5] dqs_tsel_mux_reg_write: External DQS termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
578/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
[4:3] dqs_tsel_mux_reg_read: External DQS termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[2] dqs_tsel_enable_reg_idle: Enables the DQS termination select on a idle cycle.
[1] dqs_tsel_enable_reg_write: Enables the DQS termination select on a write cycle.
[0] dqs_tsel_enable_reg_read: Enables the DQS termination select on a read cycle.
MPMC_CTRL_REG_161
Controller configuration register 161: PHY conf reg
7 for data slice 1
Address:
MPMC_controllerBaseAddress + 0x284
Type:
R/W
Reset:
0x0000 0000
Description:
1
0
dqs_tsel_enable_reg_read
R/W
2
dqs_tsel_enable_reg_write
dq_tsel_mux_reg_read
R/W
3
dqs_tsel_enable_reg_idle
dq_tsel_mux_reg_write
R/W
4
dqs_tsel_mux_reg_read
dq_tsel_mux_reg_idle
R/W
5
dqs_tsel_mux_reg_write
tsel_dq_wr_coarse_assert_reg
R/W
6
dqs_tsel_mux_reg_idle
tsel_dq_wr_assert_fine_reg
R/W
7
dq_tsel_enable_reg_read
tsel_dq_wr_coarse_deassert_reg
R/W
8
dq_tsel_enable_reg_idle
tsel_dq_wr_deassert_fine_reg
R
9
dq_tsel_enable_reg_write
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/
W
R/
W
R/
W
Controller configuration register 161: PHY conf reg 7 for data slice 1
[27:26] tsel_dq_wr_deassert_fine_reg: Delay of the DQ/DM write termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[25:23] tsel_dq_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQ/DM write de-assertion.
[22:21] tsel_dq_wr_assert_fine_reg: Delay of the DQ/DM write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[20:18] tsel_dq_wr_coarse_assert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQ/DM write assertion.
Doc ID 018904 Rev 3
579/1728
Multi-port DDR controller (MPMC)
RM0089
[17:16] dq_tsel_mux_reg_idle: External DQ/DM termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[15:14] dq_tsel_mux_reg_write: External DQ/DM termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[13:12] dq_tsel_mux_reg_read: External DQ/DM termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[11] dq_tsel_enable_reg_idle: Enables the DQ/DM termination select on an idle cycle.
[10] dq_tsel_enable_reg_write: Enables the DQ/DM termination select on a write cycle.
[9] dq_tsel_enable_reg_read: Enables the DQ/DM termination select on a read cycle.
[8:7] dqs_tsel_mux_reg_idle: External DQS termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[6:5] dqs_tsel_mux_reg_write: External DQS termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[4:3] dqs_tsel_mux_reg_read: External DQS termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[2] dqs_tsel_enable_reg_idle: Enables the DQS termination select on a idle cycle.
[1] dqs_tsel_enable_reg_write: Enables the DQS termination select on a write cycle.
[0] dqs_tsel_enable_reg_read: Enables the DQS termination select on a read cycle.
580/1728
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_162
Controller configuration register 162: PHY conf reg
7 for data slice 2
1
0
dqs_tsel_enable_reg_read
R/W
2
dqs_tsel_enable_reg_write
dq_tsel_mux_reg_read
R/W
3
dqs_tsel_enable_reg_idle
dq_tsel_mux_reg_write
R/W
4
dqs_tsel_mux_reg_read
dq_tsel_mux_reg_idle
R/W
5
dqs_tsel_mux_reg_write
tsel_dq_wr_coarse_assert_reg
R/W
6
dqs_tsel_mux_reg_idle
tsel_dq_wr_assert_fine_reg
R/W
7
dq_tsel_enable_reg_read
tsel_dq_wr_coarse_deassert_reg
R/W
8
dq_tsel_enable_reg_idle
tsel_dq_wr_deassert_fine_reg
R
9
dq_tsel_enable_reg_write
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/
W
R/
W
R/
W
Address:
MPMC_controllerBaseAddress + 0x288
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 162: PHY conf reg 7 for data slice 2
[27:26] tsel_dq_wr_deassert_fine_reg: Delay of the DQ/DM write termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[25:23] tsel_dq_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQ/DM write de-assertion.
[22:21] tsel_dq_wr_assert_fine_reg: Delay of the DQ/DM write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[20:18] tsel_dq_wr_coarse_assert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQ/DM write assertion.
[17:16] dq_tsel_mux_reg_idle: External DQ/DM termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[15:14] dq_tsel_mux_reg_write: External DQ/DM termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
Doc ID 018904 Rev 3
581/1728
Multi-port DDR controller (MPMC)
RM0089
[13:12] dq_tsel_mux_reg_read: External DQ/DM termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[11] dq_tsel_enable_reg_idle: Enables the DQ/DM termination select on an idle cycle.
[10] dq_tsel_enable_reg_write: Enables the DQ/DM termination select on a write cycle.
[9] dq_tsel_enable_reg_read: Enables the DQ/DM termination select on a read cycle.
[8:7] dqs_tsel_mux_reg_idle: External DQS termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[6:5] dqs_tsel_mux_reg_write: External DQS termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[4:3] dqs_tsel_mux_reg_read: External DQS termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[2] dqs_tsel_enable_reg_idle: Enables the DQS termination select on a idle cycle.
[1] dqs_tsel_enable_reg_write: Enables the DQS termination select on a write cycle.
[0] dqs_tsel_enable_reg_read: Enables the DQS termination select on a read cycle.
MPMC_CTRL_REG_163
Controller configuration register 163: PHY conf reg
7 for data slice 3
Address:
MPMC_controllerBaseAddress + 0x28C
Type:
R/W
582/1728
Doc ID 018904 Rev 3
1
0
dqs_tsel_enable_reg_read
R/W
2
dqs_tsel_enable_reg_write
dq_tsel_mux_reg_read
R/W
3
dqs_tsel_enable_reg_idle
dq_tsel_mux_reg_write
R/W
4
dqs_tsel_mux_reg_read
dq_tsel_mux_reg_idle
R/W
5
dqs_tsel_mux_reg_write
tsel_dq_wr_coarse_assert_reg
R/W
6
dqs_tsel_mux_reg_idle
tsel_dq_wr_assert_fine_reg
R/W
7
dq_tsel_enable_reg_read
tsel_dq_wr_coarse_deassert_reg
R/W
8
dq_tsel_enable_reg_idle
tsel_dq_wr_deassert_fine_reg
R
9
dq_tsel_enable_reg_write
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/
W
R/
W
R/
W
RM0089
Multi-port DDR controller (MPMC)
Reset:
0x0000 0000
Description:
Controller configuration register 163: PHY conf reg 7 for data slice 3
[27:26] tsel_dq_wr_deassert_fine_reg: Delay of the DQ/DM write termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[25:23] tsel_dq_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQ/DM write de-assertion.
[22:21] tsel_dq_wr_assert_fine_reg: Delay of the DQ/DM write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[20:18] tsel_dq_wr_coarse_assert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQ/DM write assertion.
[17:16] dq_tsel_mux_reg_idle: External DQ/DM termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[15:14] dq_tsel_mux_reg_write: External DQ/DM termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[13:12] dq_tsel_mux_reg_read: External DQ/DM termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[11] dq_tsel_enable_reg_idle: Enables the DQ/DM termination select on an idle cycle.
[10] dq_tsel_enable_reg_write: Enables the DQ/DM termination select on a write cycle.
[9] dq_tsel_enable_reg_read: Enables the DQ/DM termination select on a read cycle.
[8:7] dqs_tsel_mux_reg_idle: External DQS termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
Doc ID 018904 Rev 3
583/1728
Multi-port DDR controller (MPMC)
RM0089
[6:5] dqs_tsel_mux_reg_write: External DQS termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[4:3] dqs_tsel_mux_reg_read: External DQS termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[2] dqs_tsel_enable_reg_idle: Enables the DQS termination select on a idle cycle.
[1] dqs_tsel_enable_reg_write: Enables the DQS termination select on a write cycle.
[0] dqs_tsel_enable_reg_read: Enables the DQS termination select on a read cycle.
MPMC_CTRL_REG_164
Controller configuration register 164: PHY conf reg
7 for data slice 4
Address:
MPMC_controllerBaseAddress + 0x290
Type:
R/W
Reset:
0x0000 0000
584/1728
Doc ID 018904 Rev 3
1
0
dqs_tsel_enable_reg_read
R/W
2
dqs_tsel_enable_reg_write
dq_tsel_mux_reg_read
R/W
3
dqs_tsel_enable_reg_idle
dq_tsel_mux_reg_write
R/W
4
dqs_tsel_mux_reg_read
dq_tsel_mux_reg_idle
R/W
5
dqs_tsel_mux_reg_write
tsel_dq_wr_coarse_assert_reg
R/W
6
dqs_tsel_mux_reg_idle
tsel_dq_wr_assert_fine_reg
R/W
7
dq_tsel_enable_reg_read
tsel_dq_wr_coarse_deassert_reg
R/W
8
dq_tsel_enable_reg_idle
tsel_dq_wr_deassert_fine_reg
R
9
dq_tsel_enable_reg_write
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/W
R/W
R/W
R/
W
R/
W
R/
W
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 164: PHY conf reg 7 for data slice 4
[27:26] tsel_dq_wr_deassert_fine_reg: Delay of the DQ/DM write termination select de-assertion
from the coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[25:23] tsel_dq_wr_coarse_deassert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will
be delayed to form the coarse select for DQ/DM write de-assertion.
[22:21] tsel_dq_wr_assert_fine_reg: Delay of the DQ/DM write termination select assertion from the
coarse adjustment value.
-- 00 = 0 clk delay.
-- 01 = 1/2 clk delay.
-- 10 = 1 clk delay.
-- 11 = Reserved.
[20:18] tsel_dq_wr_coarse_assert_reg: Number of cycles (+1) that the dfi_wrdata_en signal will be
delayed to form the coarse select for DQ/DM write assertion.
[17:16] dq_tsel_mux_reg_idle: External DQ/DM termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[15:14] dq_tsel_mux_reg_write: External DQ/DM termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[13:12] dq_tsel_mux_reg_read: External DQ/DM termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[11] dq_tsel_enable_reg_idle: Enables the DQ/DM termination select on an idle cycle.
[10] dq_tsel_enable_reg_write: Enables the DQ/DM termination select on a write cycle.
[9] dq_tsel_enable_reg_read: Enables the DQ/DM termination select on a read cycle.
[8:7] dqs_tsel_mux_reg_idle: External DQS termination mux control for idle cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[6:5] dqs_tsel_mux_reg_write: External DQS termination mux control for write cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
Doc ID 018904 Rev 3
585/1728
Multi-port DDR controller (MPMC)
RM0089
[4:3] dqs_tsel_mux_reg_read: External DQS termination mux control for read cycles.
DDR3
DDR2
-- 00
ODT disabled
-- 01
120 Ohm 150 Ohm
-- 10
120 Ohm 150 Ohm
-- 11
60 Ohm 75 Ohm
[2] dqs_tsel_enable_reg_idle: Enables the DQS termination select on a idle cycle.
[1] dqs_tsel_enable_reg_write: Enables the DQS termination select on a write cycle.
[0] dqs_tsel_enable_reg_read: Enables the DQS termination select on a read cycle.
MPMC_CTRL_REG_165
Controller configuration register 165: PHY conf reg
9 for data slice 0
2
1
0
slice_cal_override_reg
3
R
R/W
R/W
R/W
R/W
R/
W
R/
W
Address:
MPMC_controllerBaseAddress + 0x294
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 165: PHY conf reg 9 for data slice 0
[13:11] ph_clk_match_override_reg: phy_clk_match override value.
[10:8] src_clk_match_override_reg: src_clk_match override value.
[7:5] dq_clk_match_override_reg: dq_clk_match override value.
[4:2] dqs_clk_match_override_reg: dqs_clk_match override value.
[1] dqs_capture_phase_override_reg: dqs_capture_phase override value.
[0] slice_cal_override_reg: Enables override of all calibration settings.
586/1728
4
dqs_capture_phase_override_reg
5
dqs_clk_match_override_reg
6
dq_clk_match_override_reg
7
src_clk_match_override_reg
8
ph_clk_match_override_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_166
Controller configuration register 166: PHY conf reg
9 for data slice 1
2
1
0
slice_cal_override_reg
3
dqs_capture_phase_override_reg
4
dqs_clk_match_override_reg
5
dq_clk_match_override_reg
6
src_clk_match_override_reg
7
ph_clk_match_override_reg
8
R
R/W
R/W
R/W
R/W
R/
W
R/
W
Address:
MPMC_controllerBaseAddress + 0x298
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Controller configuration register 166: PHY conf reg 9 for data slice 1
[13:11] ph_clk_match_override_reg: phy_clk_match override value.
[10:8] src_clk_match_override_reg: src_clk_match override value.
[7:5] dq_clk_match_override_reg: dq_clk_match override value.
[4:2] dqs_clk_match_override_reg: dqs_clk_match override value.
[1] dqs_capture_phase_override_reg: dqs_capture_phase override value.
[0] slice_cal_override_reg: Enables override of all calibration settings.
MPMC_CTRL_REG_167
Controller configuration register 167: PHY conf reg
9 for data slice 2
3
2
1
0
slice_cal_override_reg
4
dqs_capture_phase_override_reg
5
dqs_clk_match_override_reg
6
dq_clk_match_override_reg
7
src_clk_match_override_reg
8
ph_clk_match_override_reg
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/W
R/
W
R/
W
Address:
MPMC_controllerBaseAddress + 0x29C
Type:
R/W
Reset:
0x0000 0000
Doc ID 018904 Rev 3
587/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 167: PHY conf reg 9 for data slice 2
[13:11] ph_clk_match_override_reg: phy_clk_match override value.
[10:8] src_clk_match_override_reg: src_clk_match override value.
[7:5] dq_clk_match_override_reg: dq_clk_match override value.
[4:2] dqs_clk_match_override_reg: dqs_clk_match override value.
[1] dqs_capture_phase_override_reg: dqs_capture_phase override value.
[0] slice_cal_override_reg: Enables override of all calibration settings.
MPMC_CTRL_REG_168
Controller configuration register 168: PHY conf reg
9 for data slice 3
1
0
slice_cal_override_reg
2
dqs_capture_phase_override_reg
3
dqs_clk_match_override_reg
4
R/W
R/W
R/W
R/W
R/
W
R/
W
MPMC_controllerBaseAddress + 0x2A0
Type:
R/W
Reset:
0x0000 0000
Controller configuration register 168: PHY conf reg 9 for data slice 3
[13:11] ph_clk_match_override_reg: phy_clk_match override value.
[10:8] src_clk_match_override_reg: src_clk_match override value.
[7:5] dq_clk_match_override_reg: dq_clk_match override value.
[4:2] dqs_clk_match_override_reg: dqs_clk_match override value.
[1] dqs_capture_phase_override_reg: dqs_capture_phase override value.
[0] slice_cal_override_reg: Enables override of all calibration settings.
588/1728
5
dq_clk_match_override_reg
6
src_clk_match_override_reg
7
ph_clk_match_override_reg
8
R
Address:
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_169
Controller configuration register 169: PHY conf reg
9 for data slice 4
2
1
0
slice_cal_override_reg
3
dqs_capture_phase_override_reg
4
dqs_clk_match_override_reg
5
dq_clk_match_override_reg
6
src_clk_match_override_reg
7
ph_clk_match_override_reg
8
R
R/W
R/W
R/W
R/W
R/
W
R/
W
Address:
MPMC_controllerBaseAddress + 0x2A4
Type:
R/W
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Controller configuration register 169: PHY conf reg 9 for data slice 4
[13:11] ph_clk_match_override_reg: phy_clk_match override value.
[10:8] src_clk_match_override_reg: src_clk_match override value.
[7:5] dq_clk_match_override_reg: dq_clk_match override value.
[4:2] dqs_clk_match_override_reg: dqs_clk_match override value.
[1] dqs_capture_phase_override_reg: dqs_capture_phase override value.
[0] slice_cal_override_reg: Enables override of all calibration settings.
MPMC_CTRL_REG_170
Controller configuration register 170: PHY obs reg
0 for data slice 0
4
3
lpbk_err_data
5
lpbk_act_data
6
lpbk_err_byte
R
7
lpbk_data_error
RESERVED
R
8
ctrl_lpbk_done
dqs_byte_patt_mux_data1
R
9
lpbk_data_syncd_n
dqs_capture_phase
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2A8
Type:
R
Reset:
0x0000 0000
Doc ID 018904 Rev 3
2
1
0
589/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 170: PHY obs reg 0 for data slice 0
[31] dqs_capture_phase: Contains information on DLL clocks to clk_phy crossings.
[30:23] dqs_byte_patt_mux_data1: Contains data output path delay informaiton.
[19] ctrl_lpbk_done: Loopback data slice process complete indicator.
[18] lpbk_data_syncd_n: Loopback data is not synchronized.
[17] lpbk_data_error: Loopback data slice error indicator.
[16] lpbk_err_byte: Loopback data slice failing byte indicator.
-- 0 = Lower byte.
-- 1 = Upper byte.
[15:8] lpbk_act_data: Expected loopback data.
[7:0] lpbk_err_data: Actual loopback data.
MPMC_CTRL_REG_171
Controller configuration register 171: PHY obs reg
0 for data slice 1
4
3
lpbk_err_data
5
lpbk_act_data
6
lpbk_err_byte
R
7
lpbk_data_error
RESERVED
R
8
ctrl_lpbk_done
dqs_byte_patt_mux_data1
R
9
lpbk_data_syncd_n
dqs_capture_phase
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2AC
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 171: PHY obs reg 0 for data slice 1
[31] dqs_capture_phase: Contains information on DLL clocks to clk_phy crossings.
[30:23] dqs_byte_patt_mux_data1: Contains data output path delay informaiton.
[19] ctrl_lpbk_done: Loopback data slice process complete indicator.
[18] lpbk_data_syncd_n: Loopback data is not synchronized.
[17] lpbk_data_error: Loopback data slice error indicator.
[16] lpbk_err_byte: Loopback data slice failing byte indicator.
-- 0 = Lower byte.
-- 1 = Upper byte.
[15:8] lpbk_act_data: Expected loopback data.
[7:0] lpbk_err_data: Actual loopback data.
590/1728
Doc ID 018904 Rev 3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_172
Controller configuration register 172: PHY obs reg
0 for data slice 2
4
3
lpbk_err_data
5
lpbk_act_data
6
lpbk_err_byte
R
7
lpbk_data_error
RESERVED
R
8
ctrl_lpbk_done
dqs_byte_patt_mux_data1
R
9
lpbk_data_syncd_n
dqs_capture_phase
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2B0
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 172: PHY obs reg 0 for data slice 2
2
1
0
[31] dqs_capture_phase: Contains information on DLL clocks to clk_phy crossings.
[30:23] dqs_byte_patt_mux_data1: Contains data output path delay informaiton.
[19] ctrl_lpbk_done: Loopback data slice process complete indicator.
[18] lpbk_data_syncd_n: Loopback data is not synchronized.
[17] lpbk_data_error: Loopback data slice error indicator.
[16] lpbk_err_byte: Loopback data slice failing byte indicator.
-- 0 = Lower byte.
-- 1 = Upper byte.
[15:8] lpbk_act_data: Expected loopback data.
[7:0] lpbk_err_data: Actual loopback data.
MPMC_CTRL_REG_173
Controller configuration register 173: PHY obs reg
0 for data slice 3
4
3
lpbk_err_data
5
lpbk_act_data
6
lpbk_err_byte
R
7
lpbk_data_error
RESERVED
R
8
ctrl_lpbk_done
dqs_byte_patt_mux_data1
R
9
lpbk_data_syncd_n
dqs_capture_phase
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2B4
Type:
R
Reset:
0x0000 0000
Doc ID 018904 Rev 3
2
1
0
591/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 173: PHY obs reg 0 for data slice 3
[31] dqs_capture_phase: Contains information on DLL clocks to clk_phy crossings.
[30:23] dqs_byte_patt_mux_data1: Contains data output path delay informaiton.
[19] ctrl_lpbk_done: Loopback data slice process complete indicator.
[18] lpbk_data_syncd_n: Loopback data is not synchronized.
[17] lpbk_data_error: Loopback data slice error indicator.
[16] lpbk_err_byte: Loopback data slice failing byte indicator.
-- 0 = Lower byte.
-- 1 = Upper byte.
[15:8] lpbk_act_data: Expected loopback data.
[7:0] lpbk_err_data: Actual loopback data.
MPMC_CTRL_REG_174
Controller configuration register 174: PHY obs reg
0 for data slice 4
4
3
lpbk_err_data
5
lpbk_act_data
6
lpbk_err_byte
R
7
lpbk_data_error
RESERVED
R
8
ctrl_lpbk_done
dqs_byte_patt_mux_data1
R
9
lpbk_data_syncd_n
dqs_capture_phase
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2B8
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 174: PHY obs reg 0 for data slice 4
[31] dqs_capture_phase: Contains information on DLL clocks to clk_phy crossings.
[30:23] dqs_byte_patt_mux_data1: Contains data output path delay informaiton.
[19] ctrl_lpbk_done: Loopback data slice process complete indicator.
[18] lpbk_data_syncd_n: Loopback data is not synchronized.
[17] lpbk_data_error: Loopback data slice error indicator.
[16] lpbk_err_byte: Loopback data slice failing byte indicator.
-- 0 = Lower byte.
-- 1 = Upper byte.
[15:8] lpbk_act_data: Expected loopback data.
[7:0] lpbk_err_data: Actual loopback data.
592/1728
Doc ID 018904 Rev 3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_175
Controller configuration register 175: PHY obs reg
1 for data slice 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
dqs_byte_patt_mux_src
dqs_byte_patt_mux_data
dqs_byte_patt_mux_dqs
dqs_byte_patt_clk
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2BC
Type:
R
Reset:
0x0000 0000
Description:
1
0
Controller configuration register 175: PHY obs reg 1 for data slice 0
[31:24] dqs_byte_patt_mux_src: Contains path delay information for clk0/4_source_X selection.
[23:16] dqs_byte_patt_mux_data: Contains data path output delay information.
[15:8] dqs_byte_patt_mux_dqs: Contains DQS output path delay information.
[7:0] dqs_byte_patt_clk: Contains relationship information between DLL clocks and clk_phy.
MPMC_CTRL_REG_176
Controller configuration register 176: PHY obs reg
1 for data slice 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
dqs_byte_patt_mux_src
dqs_byte_patt_mux_data
dqs_byte_patt_mux_dqs
dqs_byte_patt_clk
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2C0
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 176: PHY obs reg 1 for data slice 1
1
0
[31:24] dqs_byte_patt_mux_src: Contains path delay information for clk0/4_source_X selection.
[23:16] dqs_byte_patt_mux_data: Contains data path output delay information.
[15:8] dqs_byte_patt_mux_dqs: Contains DQS output path delay information.
[7:0] dqs_byte_patt_clk: Contains relationship information between DLL clocks and clk_phy.
MPMC_CTRL_REG_177
Controller configuration register 177: PHY obs reg
1 for data slice 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
dqs_byte_patt_mux_src
dqs_byte_patt_mux_data
dqs_byte_patt_mux_dqs
dqs_byte_patt_clk
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2C4
Type:
R
Reset:
0x0000 0000
Doc ID 018904 Rev 3
1
0
593/1728
Multi-port DDR controller (MPMC)
Description:
RM0089
Controller configuration register 177: PHY obs reg 1 for data slice 2
[31:24] dqs_byte_patt_mux_src: Contains path delay information for clk0/4_source_X selection.
[23:16] dqs_byte_patt_mux_data: Contains data path output delay information.
[15:8] dqs_byte_patt_mux_dqs: Contains DQS output path delay information.
[7:0] dqs_byte_patt_clk: Contains relationship information between DLL clocks and clk_phy.
MPMC_CTRL_REG_178
Controller configuration register 178: PHY obs reg
1 for data slice 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
dqs_byte_patt_mux_src
dqs_byte_patt_mux_data
dqs_byte_patt_mux_dqs
dqs_byte_patt_clk
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2C8
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 178: PHY obs reg 1 for data slice 3
1
0
[31:24] dqs_byte_patt_mux_src: Contains path delay information for clk0/4_source_X selection.
[23:16] dqs_byte_patt_mux_data: Contains data path output delay information.
[15:8] dqs_byte_patt_mux_dqs: Contains DQS output path delay information.
[7:0] dqs_byte_patt_clk: Contains relationship information between DLL clocks and clk_phy.
MPMC_CTRL_REG_179
Controller configuration register 179: PHY obs reg
1 for data slice 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
dqs_byte_patt_mux_src
dqs_byte_patt_mux_data
dqs_byte_patt_mux_dqs
dqs_byte_patt_clk
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2CC
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 179: PHY obs reg 1 for data slice 4
1
[31:24] dqs_byte_patt_mux_src: Contains path delay information for clk0/4_source_X selection.
[23:16] dqs_byte_patt_mux_data: Contains data path output delay information.
[15:8] dqs_byte_patt_mux_dqs: Contains DQS output path delay information.
[7:0] dqs_byte_patt_clk: Contains relationship information between DLL clocks and clk_phy.
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RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_180
Controller configuration register 180: PHY addr/ctrl
loopback reg
3
lpbk_err_data
4
lpbk_act_data
5
lpbk_err_byte
6
lpbk_data_error
7
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2D0
Type:
R
Reset:
0x0000 0000
Description:
8
ctrl_lpbk_done
R
9
lpbk_data_syncd_n
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
Controller configuration register 180: PHY addr/ctrl loopback reg
[19] ctrl_lpbk_done: Loopback address/control process complete indicator.
[18] lpbk_data_syncd_n: Loopback address/control data is not synchronized.
[17] lpbk_data_error: Loopback address/control error indicator.
[16] lpbk_err_byte: Loopback address/control failing byte indicator.
-- 0 = Lower byte.
-- 1 = Upper byte.
[15:8] lpbk_act_data: Expected loopback data for the address/control loopback test.
[7:0] lpbk_err_data: Actual loopback data for the address/control loopback test.
MPMC_CTRL_REG_181
Controller configuration register 181: PHY addr/ctrl
calibration reg
4
3
cal_clk_byte_patt
5
cal_clk_ref_byte_patt
6
ctl_mux_byte_patt
7
ctl_source_sel_cal
8
ctl_8phase_sel_cal
9
ctl_clk_phase_sel_cal
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
Address:
MPMC_controllerBaseAddress + 0x2D4
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 181: PHY addr/ctrl calibration reg
2
1
0
[31:30] ctl_clk_phase_sel_cal: Reports the mux select value for the source of output driving flop.
[29:27] ctl_8phase_sel_cal: Reports the mux select value for ctl_8phase_clk_X generation.
[26:24] ctl_source_sel_cal: Reports the mux select value for pre_ctl_8phase_clk_X generation.
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RM0089
[23:16] ctl_mux_byte_patt: Contains path delay information for pre_ctl/ctl_8phase_clk_X selection.
[15:8] cal_clk_ref_byte_patt: Contains relationship information between DLL clocks and mem_clk.
[7:0] cal_clk_byte_patt: Contains relationship information between DLL clocks and clk_phy.
MPMC_CTRL_REG_182
Controller configuration register 182(rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x2D8
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 182(rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_183
Controller configuration register 183 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x2DC
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 183 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_184
Controller configuration register 184 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x2E0
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 184 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
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1
0
RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_185
Controller configuration register 185 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x2E4
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 185 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_186
Controller configuration register 186
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
trst_pwron
R/W
Address:
MPMC_controllerBaseAddress + 0x2E8
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 186
[31:0] trst_pwron: Defines the number of cycles that memory will be held in reset during the
power-on initialization sequence.
MPMC_CTRL_REG_187
Controller configuration register 187
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ecc_c_addr_reg_31to0
R
Address:
MPMC_controllerBaseAddress + 0x2EC
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 187
[31:0] ecc_c_addr_reg_31to0: Holds the address (lower 32 bits) of the read data that caused a
single-bit correctable ECC event. The memory controller will pad this parameter with zeros for
any address bits not used by the memory controller. This parameter will only be used when a
correctable error occurs and ECC error reporting is enabled in the ctrl_raw parameter. This
parameter is read-only.
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RM0089
MPMC_CTRL_REG_188
Controller configuration register 188
8
7
6
5
4
3
2
1
ecc_c_addr_reg_34to32
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
Address:
MPMC_controllerBaseAddress + 0x2F0
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 188
0
[2:0] ecc_c_addr_reg_34to32: Holds the address (upper 3 bits) of the read data that caused a
single-bit correctable ECC event. The memory controller will pad this parameter with zeros for
any address bits not used by the memory controller. This parameter will only be used when a
correctable error occurs and ECC error reporting is enabled in the ctrl_raw parameter. This
parameter is read-only.
MPMC_CTRL_REG_189
Controller configuration register 189
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ecc_u_addr_31to0
R
Address:
MPMC_controllerBaseAddress + 0x2F4
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 189
[31:0] ecc_u_addr_31to0: Holds the address (lower 32 bits) of the read data that caused a double-bit
un-correctable ECC event. The memory controller will pad this parameter with zeros for any
address bits not used by the memory controller. This parameter will only be used when an
uncorrectable error occurs and ECC error reporting is enabled in the ctrl_raw parameter. This
parameter is read-only.
MPMC_CTRL_REG_190
Controller configuration register 190
Address:
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8
7
6
5
4
3
2
1
ecc_u_addr_34to32
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
MPMC_controllerBaseAddress + 0x2F8
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RM0089
Multi-port DDR controller (MPMC)
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 190
[2:0] ecc_u_addr_34to32: Holds the address (upper 3 bits) of the read data that caused a
double-bit un-correctable ECC event. The memory controller will pad this parameter with zeros
for any address bits not used by the memory controller. This parameter will only be used when
an uncorrectable error occurs and ECC error reporting is enabled in the ctrl_raw parameter.
This parameter is read-only.
MPMC_CTRL_REG_191
Controller configuration register 191
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
out_of_range_addr_31to0
R
Address:
MPMC_controllerBaseAddress + 0x2FC
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 191
[31:0] out_of_range_addr_31to0: Holds the address of the command that caused an out-of-range
interrupt request to the memory devices. This parameter is read-only.
For more information on out-of-range address checking, refer to the Other Memory Controller
Features paragraph in RM0078, Reference manual, SPEAr1340 architecture and functionality.
MPMC_CTRL_REG_192
Controller configuration register 192
7
6
5
4
3
2
1
out_of_range_addr_34to32
8
R
R
Address:
MPMC_controllerBaseAddress + 0x300
Type:
R
Reset:
0x0000 0000
Description:
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
Controller configuration register 192
[2:0] out_of_range_addr_34to32: Holds the address (upper 3 bits) of the command that caused an
out-of-range interrupt request to the memory devices. This parameter is read-only.
For more information on out-of-range address checking, refer to the Other Memory Controller
Features paragraph in RM0078, Reference manual, SPEAr1340 architecture and functionality.
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RM0089
MPMC_CTRL_REG_193
Controller configuration register 193
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
port_cmd_error_addr_31to0
R
Address:
MPMC_controllerBaseAddress + 0x304
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 193
[31:0] port_cmd_error_addr_31to0: Holds the address (lower 32 bits) of the command that caused
a port command error condition. This parameter is read-only.
MPMC_CTRL_REG_194
Controller configuration register 194
8
7
6
5
4
3
2
1
port_cmd_error_addr_34to32
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
Address:
MPMC_controllerBaseAddress + 0x308
Type:
R
Reset:
0x0000 0000
Description:
Controller configuration register 194
0
[2:0] port_cmd_error_addr_34to32: Holds the address (upper 3 bits) of the command that caused
a port command error condition. This parameter is read-only.
MPMC_CTRL_REG_195
Controller configuration register 195 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x30C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 195 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
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RM0089
Multi-port DDR controller (MPMC)
MPMC_CTRL_REG_196
Controller configuration register 196 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x310
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 196 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_197
Controller configuration register 197 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x314
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 197 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_198
Controller configuration register 198
3
rfu_0
4
RESERVED
5
cke_status
6
RESERVED
7
rfu_1
8
RESERVED
9
tdfi_rdlvl_load
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R
R/
W
R
R
R
R/W
Address:
MPMC_controllerBaseAddress + 0x318
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 198
2
1
0
[31:24] tdfi_rdlvl_load: Defines the minimum number of cycles required after the read leveling delays
are loaded until the first read leveling load may be asserted.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
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RM0089
[16] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0x0
[8] cke_status: Provides the value of the cke_status signal in a parameter. This parameter is
readonly.
Note: the cke_status signal is also connected to the MISCELLANEOUS register
MPMC_CTR_STS[13] (register offset 0x334)
[6:0] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0x00
MPMC_CTRL_REG_199
Controller configuration register 199
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
rfu
tdfi_wrlvl_load
R
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x31C
Type:
R/W
Reset:
0x0000 0000
Description:
1
0
Controller configuration register 199
[23:8] rfu: Reserved for future use: it is mandatory to set this parameter to 0x0000
[7:0] tdfi_wrlvl_load: Defines the minimum number of cycles required after the write leveling delays
are loaded until the first write leveling load may be asserted.
Note: This parameter is only relevant when operating in DDR3 mode (the dram_class
parameter is set to 0110).
MPMC_CTRL_REG_200
Controller configuration register 200 (rfu)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfu
R/W
Address:
MPMC_controllerBaseAddress + 0x320
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 200 (rfu)
[31:0] rfu: Reserved for future use, it is mandatory to set this parameter to 0x00000000
MPMC_CTRL_REG_201
Controller configuration register 201
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
tras_max
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x324
Type:
R/W
Reset:
0x0000 0000
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Doc ID 018904 Rev 3
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5
4
3
2
1
0
RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 201
[31:17] rfu: Reserved for future use: it is mandatory to set this parameter to 0x0000
[16:0] tras_max: DRAM TRAS_MAX parameter in cycles
MPMC_CTRL_REG_202
Controller configuration register 202
6
5
4
trfc
7
rfu_0
8
srefresh_exit_no_refresh
9
rfu_1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/
W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x328
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 202
3
2
1
0
[31:17] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0x0000
[16] srefresh_exit_no_refresh: Disables the automatic refresh request associated with SREF exit
[15:10] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0x00
[9:0] trfc: DRAM TRFC parameter in cycles
MPMC_CTRL_REG_203
Controller configuration register 203
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rfu
write_modereg
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x32C
Type:
R/W
Reset:
0x0000 0000
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6
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Description:
RM0089
Controller configuration register 203
[31:26] rfu: Reserved for future use: it is mandatory to set this parameter to 0x00
[25:0] write_modereg: Issues mode register write(s) to the specified mode register(s) and
chipselect(s) to the memory devices. When thewrite has been completed, the mode register
write bit (bit 17) will be set in the int_status parameter. Any errors will be reported in the
mrw_status parameter.
This parameter will be reset to 0x0 on the controller clock after it is changed and can not be
reprogrammed until the interrupt occurs.
Bit [25] = Trigger the MRW sequence.
Bit [24] = Write all chip selects. If set, bits [15:8] will be ignored. Bits [23:16] specify which mode
registers to write.
Bits [23:16] = Mode register write type. Only one of these bits should be set at a time. If no bits
are set, an error will be flagged in the mrw_status parameter.Bit [24] defines the chip selects.
-- Bit [23] = Write a single MRz. The mode register
specified in bits [7:0] will be written
with the data in the associated mrsingle_data_X parameter(s). The associated mrZ_data_X, if
one exists, will NOT be referenced or updated with this command.
-- Bit [17] = Write MR0, MR1, MR2,MR3
-- Bit [16] = Write MR0, MR1, MR2,MR3
-- All other bits reserved
Bits [15:8] = Chip select number to be written. This field is only valid when bit [24] is cleared to
1b0 (write one MR).
Bits [7:0] = Mode register number to be written. This field is only valid when bit [23] is set to 1b1
(write one MR).
MPMC_CTRL_REG_204
Controller configuration register 204
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
rfu
mrsingle_data_0
mrw_status
R/W
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x330
Type:
R/W
Reset:
0x0000 0000
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RM0089
Multi-port DDR controller (MPMC)
Description:
Controller configuration register 204
[31:23] rfu: Reserved for future use: it is mandatory to set this parameter to 0x000
[22:8] mrsingle_data_0: Holds the data to be programmed into a single memory mode register for
chip select 0. This parameter is used when the write_modereg parameter bit [23] is set to 1.
The write_modereg parameter will specify which mode register and which chip selects (one or
all) are to be programmed. The user is expected to define mode register write data accurately. If
the mode register number specified in write_modereg bits [7:0] is not a valid setting for the
memory system, the memory controller may exhibit unpredictable behavior.
[7:0] mrw_status: Provides status of the write mode register
request issued through the assertion of
write_modereg. This parameter is readonly
and is valid when the mode register
write bit (bit 17) is set in the int_status
parameter.
Bits [7:3] = Reserved
Bit [2] = Reserved
Bit [1] = Reserved
Bit [0] = write_modereg programming error. This bit will be set if no mode register write type is
specified (write_modereg bits [23:16]) but the mode register write was triggered
(write_modereg bit [25] = 1b1).
MPMC_CTRL_REG_205
Controller configuration register 205
inhibit_dram_cmd
rfu_0
mrsingle_data_1
7
rfu_1
8
add_odt_clk_r2w_samecs
9
rfu_2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/
W
R/
W
R/W
Address:
MPMC_controllerBaseAddress + 0x334
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 205
6
5
4
3
2
1
0
[31:28] rfu_2: Reserved for future use: it is mandatory to set this parameter to 0x0
[27:24] add_odt_clk_r2w_samecs: Additional delay to insert between RD and WR transaction types
to the same chip select to meet ODT timing requirements.
[23:17] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0x00
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RM0089
[16] inhibit_dram_cmd: Inhibits certain types of commands from being executed from the
command queue. Even when set to non-zero value, commands may still be accepted into the
memory controller and the memory controller core command queue, but they will not be
executed.
1b0 = Enable any command in the command to execute.
1b1 = Inhibit read/write traffic and associated bank commands in the command queue from
being executed.
[15] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0
[14:0] mrsingle_data_1: Holds the data to be programmed into a single memory mode register for
chip select 1. This parameter is used when the write_modereg parameter bit [23] is set to 1.
The write_modereg parameter will specify which mode register and which chip selects (one or
all) are to be programmed. The user is expected to define mode register write data accurately. If
the mode register number specified in write_modereg bits [7:0] is not a valid setting for the
memory system, the memory controller may exhibit unpredictable behavior.
MPMC_CTRL_REG_206
Controller configuration register 206
4
3
2
1
add_odt_clk_w2r_samecs
5
rfu_0
6
mem_rst_valid
7
rfu_1
8
update_error_staus
9
rfu_2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R
R/W
R/W
Address:
MPMC_controllerBaseAddress + 0x338
Type:
R/W
Reset:
0x0000 0000
Description:
0
Controller configuration register 206
[31:23] rfu_2: Reserved for future use: it is mandatory to set this parameter to 0x000
[22:16] update_error_staus: Reports on errors in the PHY update process. This parameter will be
valid when the DFI update error bit (bit 14) in the int_status parameter is set. If multiple errors
occur, only the last error will be reported in this parameter. This parameter is read-only. Each bit
represents a violation of the timing defined in the associated parameter:
Bit [6] = tdfi_phyupd_resp
Bit [5] = tdfi_phyupd_type3
Bit [4] = tdfi_phyupd_type2
Bit [3] = tdfi_phyupd_type1
Bit [2] = tdfi_phyupd_type0
Bit [1] = tdfi_ctrlupd_max
Bit [0] = tdfi_ctrlupd_interval
[15:9] rfu_1: Reserved for future use: it is mandatory to set this parameter to 0x00
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RM0089
Multi-port DDR controller (MPMC)
[8] mem_rst_valid: Provides the value of the mem_rst_valid signal in a parameter. When memory
is in self-refresh, this signal is used to indicate that a full memory initialization is not required. It
also indicates that the system is driving the memory reset and cke signals. The assertion of the
mem_rst_valid signal indicates that the MC is able to regain control of the memory reset and
cke signals and that the memory reset signal on the DFI bus if valid and stable. Once the
mem_rst_valid signal is asserted and the timing in the tdfi_ctrl_delay parameter has been met,
the system may release control of these signals.Typically this bit is cleared to 1b0, and is
generally only used when the controller is powering up and the pwrup_srefresh_exit parameter
is set to 1.
This parameter is read-only
[7:4] rfu_0: Reserved for future use: it is mandatory to set this parameter to 0x0
[3:0] add_odt_clk_w2r_samecs: Additional delay to insert between WR and RD transaction types
to the same chip select to meet ODT
timing requirements.
MPMC_CTRL_REG_207
Controller configuration register 207
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
tdfi_ctrlupd_interval
R/W
Address:
MPMC_controllerBaseAddress + 0x33C
Type:
R/W
Reset:
0x0000 0000
Description:
Controller configuration register 207
[31:0] tdfi_ctrlupd_interval: Holds the DFI tctrlupd_interval timing parameter, the maximum number
of DFI clocks that the MC may wait between assertions of the dfi_ctrlupd_req signal.If this
timing is violated, the memory controller will set the DFI update error bit (bit 14) in the int_status
parameter and report the error type in the update_error_status parameter in bit [0].
Clearing this parameter to 0x0 disables the timer (providing the memory controller an unlimited
number of DFI clocks between controller-initiated update requests) and disables the interrupt
and error reporting.
All DFI timing parameters must be programmed relative to the DFI clock.
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Static memory controller (FSMC)
RM0089
16
Static memory controller (FSMC)
16.1
Register summary
Table 87.
FSMC_CONFIG register list
Offset
Register name
Description
Page
0x0
GenMemCtrl0
Control bank 0
on page 610
0x4
GenMemCtrl_tim0
Read/write, read only timings 0
on page 611
0x8
GenMemCtrl1
Control bank 1
on page 612
0xC
GenMemCtrl_tim1
Read/write, read only timings 1
on page 613
0x40
GenMemCtrl_PC0
Control bank 0
on page 614
0x44
GenMemCtrl_Status0
Interrupts and FIFO status bank 0
on page 615
0x48
GenMemCtrl_Comm0
Timings for PCcard common mode and NAND bank 0
on page 616
0x4C
GenMemCtrl_Attrib0
Timings for PCcard attribute mode and wait mode NAND
bank 0
on page 616
0x50
GenMemCtrl_IO_ATA0
Timings for PCcard I/O mode and ATA bank 0
on page 617
0x54
GenMemCtrl_ECCr0
ECC (Error Correcting Code) for NAND bank 0
on page 618
0x58
GenMemCtrl_ECC2r0
ECC (Error Correcting Code) for NAND bank 0
on page 618
0x5C
GenMemCtrl_ECC3r0
ECC (Error Correcting Code) for NAND bank 0
on page 618
0x60
GenMemCtrl_PC1
Control bank 1
on page 619
0x64
GenMemCtrl_Status1
Interrupts and FIFO status bank 1
on page 620
0x68
GenMemCtrl_Comm1
Timings for PCcard common mode and NAND bank 1
on page 621
0x6C
GenMemCtrl_Attrib1
Timings for PCcard attribute mode and wait mode NAND
bank 1
on page 622
0x70
GenMemCtrl_IO_ATA1
Timings for PCcard I/O mode and ATA bank 1
on page 622
0x74
GenMemCtrl_ECCr1
ECC (Error Correcting Code) for NAND bank 1
on page 623
0x78
GenMemCtrl_ECC2r1
ECC (Error Correcting Code) for NAND bank 1
on page 623
0x7C
GenMemCtrl_ECC3r1
ECC (Error Correcting Code) for NAND bank 1
on page 624
0xC0
GenMemCtrl_TSTCR
Test control register
on page 624
0xC4
GenMemCtrl_ITIP_1
Integration test input register 1
on page 624
0xC8
GenMemCtrl_ITIP_2
Integration test input register 2
on page 625
0xCC
GenMemCtrl_ITOP_1
Integration test output register 1
on page 625
0xD0
GenMemCtrl_ITOP_2
Integration test output register 2
on page 625
0xD4
GenMemCtrl_ITOP_3
Integration test output register 3
on page 626
0xD8
GenMemCtrl_ITOP_4
Integration test output register 4
on page 626
0x104
Ctrl_tim_write_mod0
Write only timings bank 0
on page 627
0x10C
Ctrl_tim_write_mod1
Write only timings bank 1
on page 627
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Doc ID 018904 Rev 3
RM0089
Table 87.
Offset
Static memory controller (FSMC)
FSMC_CONFIG register list (continued)
Register name
Description
Page
0xFE0
GenMemCtrl_PeriphID0 Peripheral identification register 0
on page 628
0xFE4
GenMemCtrl_PeriphID1 Peripheral identification register 1
on page 628
0xFE8
GenMemCtrl_PeriphID2 Peripheral identification register 2
on page 629
0xFEC
GenMemCtrl_PeriphID3 Peripheral identification register 3
on page 629
0xFF0
GenMemCtrl_PcellID0
IPCell identification register [7:0]
on page 629
0xFF4
GenMemCtrl_PcellID1
IPCell identification register [15:8]
on page 630
0xFF8
GenMemCtrl_PcellID2
IPCell identification register [23:16]
on page 630
0xFFC
GenMemCtrl_PcellID3
IPCell identification register [31:24]
on page 630
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Static memory controller (FSMC)
16.2
RM0089
Register descriptions
GenMemCtrl0
Control bank 0
Address:
FSMC_CONFIGBaseAddress + 0x0
Type:
R/W
Reset:
0x30CB
Description:
0
Muxed
1
BankEnable
2
MemoryType
3
DeviceWidth
4
RstPowerDwnN
5
Wprot
R/
W
6
RESERVED
WaitAsynch
R
7
If_we
RESERVED
R/
W
8
ExtendMode
OEN_delay
R
9
ForceBusTurn
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R
R/
W
R/
W
R/W
R/W
R/
W
R/
W
Control bank 0
[20] OEN_delay: Valid when reading asynchronous memories in Mode D and Muxed.
0: FSMC_REn is deasserted when FSMC_CExn is deasserted (default)
1: FSMC_REn is deasserted 1 HCLK cycle before deassertion of FSMC_CExn
[15] WaitAsynch: When high means that the memory can issue a wait also when accessed with
asynchronous protocol. In such case FSMC takes into account the value and waits until it is deasserted before closing the access.
[14] ExtendMode: When high enables the Ctrl_tim_write_mod0 register, so to allow different
timings for read and write.
[13] ForceBusTurn: When set to high, the FSMC enters in bus turn around after DATA_ST phase.
See “Bus turn around“ section in RM0078, Reference manual, SPEAr1340 architecture and
functionality.
[12] If_we: Interface write enable. Enables write in NOR flash / SRAM.
0: Write disabled
1: Write enabled (default)
[7] Wprot: Wprot signal to flash memory, this is connected directly to the input pin of the flash
memory, valid only with flash memories.
Default value: 1
[6] RstPowerDwnN: Reset / power down signal to flash memory, this is connected directly to the
input pin of the flash memory, valid only with flash memories.
Default value: 1
[5:4] DeviceWidth: Device width, memory data size, valid for all type of memories.
00: 8 bits (default)
01: 16 bits
10: Unsupported
11: Unsupported
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Static memory controller (FSMC)
[3:2] MemoryType: Indicates the type of the memory.
00: SRAM, ROM
01: Cellular RAM (asynchronous mode only)
10: NOR/OneNand flash (default)
11: Reserved
[1] Muxed: Muxed memory uses the data bus to get the address.
0: Non muxed
1: Muxed (default)
[0] BankEnable: Enables the bank.
0: Disabled
1: Enabled (default)
Accessing a disabled bank causes a HRESP=ERROR on AHB.
GenMemCtrl_tim0
Read/write, read only timings 0
3
2
1
Addr_ST
4
Hold_addr
5
Data_ST
6
BusTurn
7
RESERVED
8
AccessMode
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x4
Type:
R/W
Reset:
0xFFFFFFF
Description:
Read/write, read only timings 0
0
[29:28] AccessMode: Specifies the asynchronous access modes.
These bits are taken into account only when ExtendMode field of GenMemCtrl0 is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
For description of A, B, C and D see the “Asynchronous operating modes“ section in RM0078,
Reference manual, SPEAr1340 architecture and functionality.
[19:16] BusTurn: Bus turn around duration (HCLK cycles + 1), used as specified in “Bus turn around“
section in RM0078, Reference manual, SPEAr1340 architecture and functionality.
[15:8] Data_ST: Duration of Data_ST phase, valid for all memory types.
(HCLK cycles + 3) for read
(HCLK cycles + 1) for write
Minimum value of Data_ST is 0 for read and 1 for write.
If extended mode is set it is possible to differentiate read and write values, otherwise only one
value must be set, and it must be the higher.
[7:4] Hold_addr: Duration of Hold_addr phase (HCLK cycles + 1), only used in muxed memories.
0x0: Do not use
0x1: 2 HCLK cycles
...
0xF: 16 HCLK cycles
Minimum value is 1.
[3:0] Addr_ST: Duration of address state phase (HCLK cycles + 1), used in NOR flash and cellular
RAM (asynchronous mode only) memory access.
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Static memory controller (FSMC)
RM0089
GenMemCtrl1
Control bank 1
Address:
FSMC_CONFIGBaseAddress + 0x8
Type:
R/W
Reset:
0x30C2
Description:
Control bank 1
0
Muxed
1
BankEnable
2
MemoryType
3
DeviceWidth
4
RstPowerDwnN
5
Wprot
R/
W
6
RESERVED
WaitAsynch
R
7
If_we
RESERVED
R/
W
8
ExtendMode
OEN_delay
R
9
ForceBusTurn
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R
R/
W
R/
W
R/W
R/W
R/
W
R/
W
[20] OEN_delay: Valid when reading asynchronous memories in Mode D and Muxed.
0: FSMC_REn is deasserted when FSMC_CExn is deasserted (default)
1: FSMC_REn is deasserted 1 HCLK cycle before deassertion of FSMC_CExn
[15] WaitAsynch: When high means that the memory can issue a wait also when accessed with
asynchronous protocol. In such case FSMC takes into account the value and waits until it is deasserted before closing the access.
[14] ExtendMode: When high enables the Ctrl_tim_write_mod1 register, so to allow different
timings for read and write.
[13] ForceBusTurn: When set to high, the FSMC enters in bus turn around after DATA_ST phase.
See “Bus turn around“ section in RM0078, Reference manual, SPEAr1340 architecture and
functionality.
[12] If_we: Interface write enable. Enables write in NOR flash / SRAM.
0: Write disabled
1: Write enabled (default)
[7] Wprot: Wprot signal to flash memory, this is connected directly to the input pin of the flash
memory, valid only with flash memories.
Default value: 1
[6] RstPowerDwnN: Reset / power down signal to flash memory, this is connected directly to the
input pin of the flash memory, valid only with flash memories.
Default value: 1
[5:4] DeviceWidth: Device width, memory data size, valid for all type of memories.
00: 8 bits (default)
01: 16 bits
10: Unsupported
11: Unsupported
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Static memory controller (FSMC)
[3:2] MemoryType: Indicates the type of the memory.
00: SRAM, ROM (default)
01: Cellular RAM (asynchronous mode only)
10: NOR/OneNand flash
11: Reserved
[1] Muxed: Muxed memory uses the data bus to get the address.
0: Non muxed
1: Muxed (default)
[0] BankEnable: Enables the bank.
0: Disabled (default)
1: Enabled
Accessing a disabled bank causes a HRESP=ERROR on AHB.
GenMemCtrl_tim1
Read/write, read only timings 1
3
2
1
Addr_ST
4
Hold_addr
5
Data_ST
6
BusTurn
7
RESERVED
8
AccessMode
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0xC
Type:
R/W
Reset:
0xFFFFFFF
Description:
Read/write, read only timings 1
0
[29:28] AccessMode: Specifies the asynchronous access modes.
These bits are taken into account only when ExtendMode field of GenMemCtrl1 is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
For description of A, B, C and D see the “Asynchronous operating modes“ section in RM0078,
Reference manual, SPEAr1340 architecture and functionality.
[19:16] BusTurn: Bus turn around duration (HCLK cycles + 1), used as specified in “Bus turn around“
section in RM0078, Reference manual, SPEAr1340 architecture and functionality.
[15:8] Data_ST: Duration of Data_ST phase, valid for all memory types.
(HCLK cycles + 3) for read
(HCLK cycles + 1) for write
Minimum value of Data_ST is 0 for read and 1 for write.
If extended mode is set it is possible to differentiate read and write values, otherwise only one
value must be set, and it must be the higher.
[7:4] Hold_addr: Duration of Hold_addr phase (HCLK cycles + 1), only used in muxed memories.
0x0: Do not use
0x1: 2 HCLK cycles
...
0xF: 16 HCLK cycles
Minimum value is 1.
[3:0] Addr_ST: Duration of address state phase (HCLK cycles + 1), used in NOR flash and cellular
RAM (asynchronous mode only) memory access.
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Static memory controller (FSMC)
RM0089
GenMemCtrl_PC0
Control bank 0
Wait_on
Reset
R
R/W
R/W
R/W
R/
W
R/
W
R/
W
R/W
R/
W
R/
W
R/
W
R/
W
Address:
FSMC_CONFIGBaseAddress + 0x40
Type:
R/W
Reset:
0x8
Description:
Control bank 0
[19:17] EccPageSize: NAND flash, extended ECC only: the page size for the extended ECC block.
000: 256 byte
001: 512 byte
010: 1024 byte
011: 2048 byte
100: 4096 byte
101: 8192 byte
[16:13] Tar: NAND flash: ALE to RE delay.
Time from ALE low to RE low.
The total time is: Tar = Tclk * (tar + 1).
Min value for tar is 0.
[12:9] Tclr: NAND flash: CLE to RE delay.
Time from CLE low to RE low.
The total time is: Tclr = Tclk * (tclr + 1).
Min value for tclr is 0.
[8] Addrmux: PCcard: muxed address.
Output address pcad[24:16] comes from pcad[8:0] instead of pcad[24:16].
0: Inactive (default)
1: Active
[7] Eccplen: ECC page length.
Defines the page length of the NAND flash memory device, for configuring the ECC
computation logic.
0: 512 bytes
1: 256 bytes
[6] Eccen: ECC computation logic enable.
0: ECC logic disabled and reset
1: ECC logic enabled
[5:4] DeviceWidth: Device width, memory data size, valid for all type of memories.
00: 8 bits (default)
01: 16 bits
10: Unsupported
11: Unsupported
[3] DeviceType: Indicates the type of the memory.
0: PCCard
1: NAND flash
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0
Enable
1
DeviceType
2
DeviceWidth
3
Eccen
4
Eccplen
5
Addrmux
6
Tclr
7
Tar
8
EccPageSize
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 018904 Rev 3
RM0089
Static memory controller (FSMC)
[2] Enable: Enables device.
0: Disabled
1: Enabled
[1] Wait_on: Activates the wait sensitivity.
0: Inactive
1: Active
[0] Reset: Software reset for PCcard #1.
0: Inactive
1: Active
Interrupts and FIFO status bank 0
R
Address:
FSMC_CONFIGBaseAddress + 0x44
Type:
R/W
Reset:
0x0
Description:
Interrupts and FIFO status bank 0
R
R/
W
2
1
0
InterruptLevel1
R
3
InterruptRisingEdge
R
4
InterruptFallingEdge
ECCType
R
5
EnableLevel
ErrorsFound
R
6
EnableRisingEdge
CodeType
R
7
FIFOEmpty
CodeReady
8
Byte13_BCH8
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EnableFallingEdge
GenMemCtrl_Status0
R/
W
R/
W
R/
W
R/
W
R/
W
[24:16] Byte13_BCH8: BCH 8 error requires 13 bytes to provide ECC code and error position.
The 3 GenMemCtrl_ECCr registers contain 12 bytes in all, the 13th is here.
[15] CodeReady: When high, ECC code or error position and errors found are ready (BCH only).
[14] CodeType: 0: ECC code fields contain error position
1: ECC code fields contain ECC code
[13:10] ErrorsFound: Returns the number of errors found in BCH search, valid only with BCH
decoders.
See “ECC calculation“ section in RM0078, Reference manual, SPEAr1340 architecture and
functionality.
[9:7] ECCType: Reports which ECC block is instantied, useful to detect the implemented hardware.
000: No ECC
001: Hamming standard
010: Hamming extended
011: BCH 4 error correction
100: BCH 8 error correction
[6] FIFOEmpty: Read only bit that provides the status of the FIFO.
0: FIFO not empty
1: FIFO empty
[5] EnableFallingEdge: Enables interrupt falling edge detection
[4] EnableLevel: Enables interrupt level detection
[3] EnableRisingEdge: Enables interrupt rising edge detection
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Static memory controller (FSMC)
RM0089
[2] InterruptFallingEdge: Interrupt falling edge status
[1] InterruptLevel1: Interrupt ‘level 1‘ status
[0] InterruptRisingEdge: Interrupt rising edge status
GenMemCtrl_Comm0
Timings for PCcard common mode and NAND bank
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
Thiz
Thold
Twait
Tset
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x48
Type:
R/W
Reset:
0xFCFC FCFC
Description:
Timings for PCcard common mode and NAND bank 0
2
1
0
[31:24] Thiz: Write cycle only.
Time from CE low to data bus driven.
In this field there is the preset for the counter.
The total time is: thiz = Tclk * Thiz.
Min value for Thiz is 0.
[23:16] Thold: Read and write cycle.
Time from enable off (RE/WE) and end of cycle (CE goes high).
In this field there is the preset for the counter.
The total time is: thold = Tclk * Thold.
Remember: T period = tset + twait + thold.
Min value for Thold is 1.
[15:8] Twait: Read and write cycle.
Time from enable on to enable off for all signals: RE/WE.
In this field there is the preset for the counter.
The total time is twait = Tclk * (Twait + 1).
Min value for Twait is 1.
[7:0] Tset: Read and write cycle.
Time from CE low to RE/WE low.
In this field there is the preset for the counter.
The total time is: tset = Tclk * (Tset + 1).
Min value for Tset is 0.
GenMemCtrl_Attrib0
Timings for PCcard attribute mode and wait mode
NAND bank 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
Thold
Twait
Tset
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x4C
Type:
R/W
Reset:
0xFCFC FCFC
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Thiz
Doc ID 018904 Rev 3
2
1
0
RM0089
Static memory controller (FSMC)
Description:
Timings for PCcard attribute mode and wait mode NAND bank 0
[31:24] Thiz: Write cycle only.
Time from CE low to data bus driven.
In this field there is the preset for the counter.
The total time is: thiz = Tclk * Thiz.
Min value for Thiz is 0.
[23:16] Thold: Read and write cycle.
Time from enable off (RE/WE) and end of cycle (CE goes high).
In this field there is the preset for the counter.
The total time is: thold = Tclk * Thold.
Remember: T period = tset + twait + thold.
Min value for Thold is 1.
[15:8] Twait: Read and write cycle.
Time from enable on to enable off for all signals: RE/WE.
In this field there is the preset for the counter.
The total time is twait = Tclk * (Twait + 1).
Min value for Twait is 1.
[7:0] Tset: Read and write cycle.
Time from CE low to RE/WE low.
In this field there is the preset for the counter.
The total time is: tset = Tclk * (Tset + 1).
Min value for Tset is 0.
GenMemCtrl_IO_ATA0
Timings for PCcard I/O mode and ATA bank 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
Thiz
Thold
Twait
Tset
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x50
Type:
R/W
Reset:
0xFCFC FCFC
Description:
Timings for PCcard I/O mode and ATA bank 0
2
1
0
[31:24] Thiz: Write cycle only.
Time from CE low to data bus driven.
In this field there is the preset for the counter.
The total time is: thiz = Tclk * Thiz.
Min value for Thiz is 0.
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Static memory controller (FSMC)
RM0089
[23:16] Thold: Read and write cycle.
Time from enable off (RE/WE) and end of cycle (CE goes high).
In this field there is the preset for the counter.
The total time is: thold = Tclk * Thold.
Remember: T period = tset + twait + thold.
Min value for Thold is 1.
[15:8] Twait: Read and write cycle.
Time from enable on to enable off for all signals: RE/WE.
In this field there is the preset for the counter.
The total time is twait = Tclk * (Twait + 1).
Min value for Twait is 1.
[7:0] Tset: Read and write cycle.
Time from CE low to RE/WE low.
In this field there is the preset for the counter.
The total time is: tset = Tclk * (Tset + 1).
Min value for Tset is 0.
GenMemCtrl_ECCr0
ECC (Error Correcting Code) for NAND bank 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ECC[31:0]
R
Address:
FSMC_CONFIGBaseAddress + 0x54
Type:
R
Reset:
0x0
Description:
ECC (Error Correcting Code) for NAND bank 0
[31:0] ECC[31:0]: First 32 bits of ECC.
GenMemCtrl_ECC2r0
ECC (Error Correcting Code) for NAND bank 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ECC[63:32]
R
Address:
FSMC_CONFIGBaseAddress + 0x58
Type:
R
Reset:
0x0
Description:
ECC (Error Correcting Code) for NAND bank 0
[31:0] ECC[63:32]: Second 32 bits of ECC.
GenMemCtrl_ECC3r0
ECC (Error Correcting Code) for NAND bank 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ECC[95:64]
R
Address:
618/1728
FSMC_CONFIGBaseAddress + 0x5C
Doc ID 018904 Rev 3
9
8
7
6
5
4
3
2
1
0
RM0089
Static memory controller (FSMC)
Type:
R
Reset:
0x0
Description:
ECC (Error Correcting Code) for NAND bank 0
[31:0] ECC[95:64]: Third 32 bits of ECC.
GenMemCtrl_PC1
Control bank 1
Wait_on
Reset
0
Enable
1
DeviceType
2
DeviceWidth
3
Eccen
4
Eccplen
5
Addrmux
6
Tclr
7
Tar
8
EccPageSize
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/W
R/W
R/
W
R/
W
R/
W
R/W
R/
W
R/
W
R/
W
R/
W
Address:
FSMC_CONFIGBaseAddress + 0x60
Type:
R/W
Reset:
0x8
Description:
Control bank 1
[19:17] EccPageSize: NAND flash, extended ECC only: the page size for the extended ECC block.
000: 256 byte
001: 512 byte
010: 1024 byte
011: 2048 byte
100: 4096 byte
101: 8192 byte
[16:13] Tar: NAND flash: ALE to RE delay.
Time from ALE low to RE low.
The total time is: Tar = Tclk * (tar + 1).
Min value for tar is 0.
[12:9] Tclr: NAND flash: CLE to RE delay.
Time from CLE low to RE low.
The total time is: Tclr = Tclk * (tclr + 1).
Min value for tclr is 0.
[8] Addrmux: PCcard: muxed address.
Output address pcad[24:16] comes from pcad[8:0] instead of pcad[24:16].
0: Inactive (default)
1: Active
[7] Eccplen: ECC page length.
Defines the page length of the NAND flash memory device, for configuring the ECC
computation logic.
0: 512 bytes
1: 256 bytes
[6] Eccen: ECC computation logic enable.
0: ECC logic disabled and reset
1: ECC logic enabled
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Static memory controller (FSMC)
RM0089
[5:4] DeviceWidth: Device width, memory data size, valid for all type of memories.
00: 8 bits (default)
01: 16 bits
10: Unsupported
11: Unsupported
[3] DeviceType: Indicates the type of the memory.
0: PCCard
1: NAND flash
[2] Enable: Enables device.
0: Disabled
1: Enabled
[1] Wait_on: Activates the wait sensitivity.
0: Inactive
1: Active
[0] Reset: Software reset for PCcard #2.
0: Inactive
1: Active
Interrupts and FIFO status bank 1
R
Address:
FSMC_CONFIGBaseAddress + 0x64
Type:
R/W
Reset:
0x0
Description:
Interrupts and FIFO status bank 1
R
R/
W
2
1
0
InterruptLevel1
R
3
InterruptRisingEdge
R
4
InterruptFallingEdge
ECCType
R
5
EnableLevel
ErrorsFound
R
6
EnableRisingEdge
CodeType
R
7
FIFOEmpty
CodeReady
8
Byte13_BCH8
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EnableFallingEdge
GenMemCtrl_Status1
R/
W
R/
W
R/
W
R/
W
R/
W
[24:16] Byte13_BCH8: BCH 8 error requires 13 bytes to provide ECC code and error position.
The 3 GenMemCtrl_ECCr registers contain 12 bytes in all, the 13th is here.
[15] CodeReady: When high, ECC code or error position and errors found are ready (BCH only).
[14] CodeType: 0: ECC code fields contain error position
1: ECC code fields contain ECC code
[13:10] ErrorsFound: Returns the number of errors found in BCH search, valid only with BCH
decoders.
See “ECC calculation“ section in RM0078, Reference manual, SPEAr1340 architecture and
functionality.
[9:7] ECCType: Reports which ECC block is instantied, useful to detect the implemented hardware.
000: No ECC
001: Hamming standard
010: Hamming extended
011: BCH 4 error correction
100: BCH 8 error correction
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Doc ID 018904 Rev 3
RM0089
Static memory controller (FSMC)
[6] FIFOEmpty: Read only bit that provides the status of the FIFO.
0: FIFO not empty
1: FIFO empty
[5] EnableFallingEdge: Enables interrupt falling edge detection
[4] EnableLevel: Enables interrupt level detection
[3] EnableRisingEdge: Enables interrupt rising edge detection
[2] InterruptFallingEdge: Interrupt falling edge status
[1] InterruptLevel1: Interrupt ‘level 1‘ status
[0] InterruptRisingEdge: Interrupt rising edge status
GenMemCtrl_Comm1
Timings for PCcard common mode and NAND bank
1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
Thiz
Thold
Twait
Tset
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x68
Type:
R/W
Reset:
0xFCFC FCFC
Description:
Timings for PCcard common mode and NAND bank 1
2
1
0
[31:24] Thiz: Write cycle only.
Time from CE low to data bus driven.
In this field there is the preset for the counter.
The total time is: thiz = Tclk * Thiz.
Min value for Thiz is 0.
[23:16] Thold: Read and write cycle.
Time from enable off (RE/WE) and end of cycle (CE goes high).
In this field there is the preset for the counter.
The total time is: thold = Tclk * Thold.
Remember: T period = tset + twait + thold.
Min value for Thold is 1.
[15:8] Twait: Read and write cycle.
Time from enable on to enable off for all signals: RE/WE.
In this field there is the preset for the counter.
The total time is twait = Tclk * (Twait + 1).
Min value for Twait is 1.
[7:0] Tset: Read and write cycle.
Time from CE low to RE/WE low.
In this field there is the preset for the counter.
The total time is: tset = Tclk * (Tset + 1).
Min value for Tset is 0.
Doc ID 018904 Rev 3
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Static memory controller (FSMC)
GenMemCtrl_Attrib1
RM0089
Timings for PCcard attribute mode and wait mode
NAND bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
Thiz
Thold
Twait
Tset
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x6C
Type:
R/W
Reset:
0xFCFC FCFC
Description:
2
1
0
Timings for PCcard attribute mode and wait mode NAND bank 1
[31:24] Thiz: Write cycle only.
Time from CE low to data bus driven.
In this field there is the preset for the counter.
The total time is: thiz = Tclk * Thiz.
Min value for Thiz is 0.
[23:16] Thold: Read and write cycle.
Time from enable off (RE/WE) and end of cycle (CE goes high).
In this field there is the preset for the counter.
The total time is: thold = Tclk * Thold.
Remember: T period = tset + twait + thold.
Min value for Thold is 1.
[15:8] Twait: Read and write cycle.
Time from enable on to enable off for all signals: RE/WE.
In this field there is the preset for the counter.
The total time is twait = Tclk * (Twait + 1).
Min value for Twait is 1.
[7:0] Tset: Read and write cycle.
Time from CE low to RE/WE low.
In this field there is the preset for the counter.
The total time is: tset = Tclk * (Tset + 1).
Min value for Tset is 0.
GenMemCtrl_IO_ATA1
Timings for PCcard I/O mode and ATA bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
Thold
Twait
Tset
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x70
Type:
R/W
Reset:
0xFCFC FCFC
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Thiz
Doc ID 018904 Rev 3
2
1
0
RM0089
Static memory controller (FSMC)
Description:
Timings for PCcard I/O mode and ATA bank 1
[31:24] Thiz: Write cycle only.
Time from CE low to data bus driven.
In this field there is the preset for the counter.
The total time is: thiz = Tclk * Thiz.
Min value for Thiz is 0.
[23:16] Thold: Read and write cycle.
Time from enable off (RE/WE) and end of cycle (CE goes high).
In this field there is the preset for the counter.
The total time is: thold = Tclk * Thold.
Remember: T period = tset + twait + thold.
Min value for Thold is 1.
[15:8] Twait: Read and write cycle.
Time from enable on to enable off for all signals: RE/WE.
In this field there is the preset for the counter.
The total time is twait = Tclk * (Twait + 1).
Min value for Twait is 1.
[7:0] Tset: Read and write cycle.
Time from CE low to RE/WE low.
In this field there is the preset for the counter.
The total time is: tset = Tclk * (Tset + 1).
Min value for Tset is 0.
GenMemCtrl_ECCr1
ECC (Error Correcting Code) for NAND bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ECC[31:0]
R
Address:
FSMC_CONFIGBaseAddress + 0x74
Type:
R
Reset:
0x0
Description:
ECC (Error Correcting Code) for NAND bank 1
[31:0] ECC[31:0]: First 32 bits of ECC.
GenMemCtrl_ECC2r1
ECC (Error Correcting Code) for NAND bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ECC[63:32]
R
Address:
FSMC_CONFIGBaseAddress + 0x78
Type:
R
Reset:
0x0
Description:
ECC (Error Correcting Code) for NAND bank 1
[31:0] ECC[63:32]: Second 32 bits of ECC.
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Static memory controller (FSMC)
GenMemCtrl_ECC3r1
RM0089
ECC (Error Correcting Code) for NAND bank 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ECC[95:64]
R
Address:
FSMC_CONFIGBaseAddress + 0x7C
Type:
R
Reset:
0x0
Description:
ECC (Error Correcting Code) for NAND bank 1
[31:0] ECC[95:64]: Third 32 bits of ECC.
GenMemCtrl_TSTCR
Test control register
8
7
6
5
4
3
2
1
0
ITEN
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
Address:
FSMC_CONFIGBaseAddress + 0xC0
Type:
R/W
Reset:
0x0
Description:
Test control register
[0] ITEN: 0: Normal operation functional mode.
1: Integration test mode.
GenMemCtrl_ITIP_1
Integration test input register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
pcdai
R
R
Address:
FSMC_CONFIGBaseAddress + 0xC4
Type:
R
Reset:
0x0
Description:
Integration test input register 1
[15:0] pcdai: Input data bus.
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9
RESERVED
Doc ID 018904 Rev 3
6
5
4
3
2
1
0
RM0089
Static memory controller (FSMC)
GenMemCtrl_ITIP_2
Integration test input register 2
3
2
1
0
pcwaitn
4
RESERVED
5
pc1_intrq
6
pc2_intrq
7
RESERVED
8
ExtDevWidth
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
Address:
FSMC_CONFIGBaseAddress + 0xC8
Type:
R
Reset:
0x0
Description:
Integration test input register 2
[12:11] ExtDevWidth: Specifies the default device data width.
[3] pc2_intrq: Interrupt input #2 from NAND.
[2] pc1_intrq: Interrupt input #1 from NAND.
[1] pcwaitn: Wait input from NAND.
GenMemCtrl_ITOP_1
Integration test output register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
RESERVED
pcdao
R
R/W
Address:
FSMC_CONFIGBaseAddress + 0xCC
Type:
R/W
Reset:
0x0
Description:
Integration test output register 1
6
5
4
3
2
1
0
[15:0] pcdao: Output data bus.
GenMemCtrl_ITOP_2
Integration test output register 2
pcwen
pcoen
RESERVED
pc2_int
pc1_int
pcad
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R
R/
W
R/
W
R/W
Address:
FSMC_CONFIGBaseAddress + 0xD0
Type:
R/W
Reset:
0x0
Doc ID 018904 Rev 3
9
8
7
6
5
4
3
2
1
0
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Static memory controller (FSMC)
Description:
RM0089
Integration test output register 2
[31] pcwen: Write enable, active low.
[30] pcoen: Output enable, active low.
[27] pc2_int: Interrupt #2 to ARM.
[26] pc1_int: Interrupt #1 to ARM.
[25:0] pcad: Address bus.
GenMemCtrl_ITOP_3
Integration test output register 3
Ebar
0
Wprot
1
pcdir
2
pcce1n
3
RESERVED
4
Lbar
5
RESERVED
6
BLN
7
RESERVED
8
pcsel
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/
W
R
R/
W
R
R/
W
R/
W
R/W
R/
W
Address:
FSMC_CONFIGBaseAddress + 0xD4
Type:
R/W
Reset:
0x0
Description:
Integration test output register 3
[19:16] pcsel: Chip select for NAND.
[13] BLN: Byte lane.
[10] Lbar: Address valid.
[6] pcce1n: Primary chip select.
[5] pcdir: Direction of the data bus.
0: Out
1: In
[7:4] Wprot: Write protection for NOR.
[3:0] Ebar: Chip select for NOR/SRAM.
GenMemCtrl_ITOP_4
Integration test output register 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
2
1
RstPwndn
Wprot
Ebar
R
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0xD8
Type:
R/W
Reset:
0x0
Description:
Integration test output register 4
[11:8] RstPwndn: Reset / power down for NOR.
[7:4] Wprot: Write protection for NOR.
[3:0] Ebar: Chip selects for NOR/SRAM.
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RESERVED
Doc ID 018904 Rev 3
0
RM0089
Static memory controller (FSMC)
Ctrl_tim_write_mod0
Write only timings bank 0
3
2
1
Addr_ST
4
Hold_addr
5
Data_ST
6
BusTurn
7
RESERVED
8
AccessMode
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x104
Type:
R/W
Reset:
0xFFFFFFF
Description:
Write only timings bank 0
0
[29:28] AccessMode: Specifies the asynchronous access modes.
These bits are taken into account only when ExtendMode field of GenMemCtrl0 is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
For description of A, B, C and D see the “Asynchronous operating modes“ section in RM0078,
Reference manual, SPEAr1340 architecture and functionality.
[19:16] BusTurn: Bus turn around duration (HCLK cycles + 1), used as specified in “Bus turn around“
section in RM0078, Reference manual, SPEAr1340 architecture and functionality.
[15:8] Data_ST: Duration of Data_ST phase, valid for all memory types.
(HCLK cycles + 3) for read
(HCLK cycles + 1) for write
Minimum value of Data_ST is 0 for read and 1 for write.
If extended mode is set it is possible to differentiate read and write values, otherwise only one
value must be set, and it must be the higher.
[7:4] Hold_addr: Duration of Hold_addr phase (HCLK cycles + 1), only used in muxed memories.
0x0: Do not use
0x1: 2 HCLK cycles
...
0xF: 16 HCLK cycles
Minimum value is 1.
[3:0] Addr_ST: Duration of address state phase (HCLK cycles + 1), used in NOR flash and cellular
RAM (asynchronous mode only) memory access.
Ctrl_tim_write_mod1
Write only timings bank 1
3
2
1
Addr_ST
4
Hold_addr
5
Data_ST
6
BusTurn
7
RESERVED
8
AccessMode
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R
R/W
R/W
R/W
R/W
Address:
FSMC_CONFIGBaseAddress + 0x10C
Type:
R/W
Reset:
0xFFFFFFF
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Static memory controller (FSMC)
Description:
RM0089
Write only timings bank 1
[29:28] AccessMode: Specifies the asynchronous access modes.
These bits are taken into account only when ExtendMode field of GenMemCtrl1 is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
For description of A, B, C and D see the “Asynchronous operating modes“ section in RM0078,
Reference manual, SPEAr1340 architecture and functionality.
[19:16] BusTurn: Bus turn around duration (HCLK cycles + 1), used as specified in “Bus turn around“
section in RM0078, Reference manual, SPEAr1340 architecture and functionality.
[15:8] Data_ST: Duration of Data_ST phase, valid for all memory types.
(HCLK cycles + 3) for read
(HCLK cycles + 1) for write
Minimum value of Data_ST is 0 for read and 1 for write.
If extended mode is set it is possible to differentiate read and write values, otherwise only one
value must be set, and it must be the higher.
[7:4] Hold_addr: Duration of Hold_addr phase (HCLK cycles + 1), only used in muxed memories.
0x0: Do not use
0x1: 2 HCLK cycles
...
0xF: 16 HCLK cycles
Minimum value is 1.
[3:0] Addr_ST: Duration of address state phase (HCLK cycles + 1), used in NOR flash and cellular
RAM (asynchronous mode only) memory access.
GenMemCtrl_PeriphID0
Peripheral identification register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
PartNumber0
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFE0
Type:
R
Reset:
0x90
Description:
Peripheral identification register 0.
1
0
[7:0] PartNumber0: Part number 0
GenMemCtrl_PeriphID1
Peripheral identification register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
2
1
0
Designer0
PartNumber1
R
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFE4
Type:
R
Reset:
0x0
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RESERVED
Doc ID 018904 Rev 3
RM0089
Description:
Static memory controller (FSMC)
Peripheral identification register 1.
[7:4] Designer0: Designer 0
[3:0] PartNumber1: Part number 1
GenMemCtrl_PeriphID2
Peripheral identification register 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RESERVED
Revision
Designer1
R
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFE8
Type:
R
Reset:
0x88
Description:
Peripheral identification register 2.
0
[7:4] Revision: Revision
[3:0] Designer1: Designer 1
GenMemCtrl_PeriphID3
Peripheral identification register 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
RESERVED
Configuration
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFEC
Type:
R
Reset:
0x0
Description:
Peripheral identification register 3.
1
0
[7:0] Configuration: Configuration
GenMemCtrl_PcellID0
IPCell identification register [7:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
PcellID0
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFF0
Type:
R
Reset:
0xD
Description:
IPCell identification register [7:0].
2
1
0
[7:0] PcellID0: 1st byte of IPCell identification register.
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Static memory controller (FSMC)
RM0089
GenMemCtrl_PcellID1
IPCell identification register [15:8]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
RESERVED
PcellID1
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFF4
Type:
R
Reset:
0xF0
Description:
IPCell identification register [15:8].
2
1
0
[7:0] PcellID1: 2nd byte of IPCell identification register.
GenMemCtrl_PcellID2
IPCell identification register [23:16]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
PcellID2
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFF8
Type:
R
Reset:
0x7
Description:
9
RESERVED
2
1
0
IPCell identification register [23:16].
[7:0] PcellID2: 3rd byte of IPCell identification register.
GenMemCtrl_PcellID3
IPCell identification register [31:24]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
RESERVED
PcellID3
R
R
Address:
FSMC_CONFIGBaseAddress + 0xFFC
Type:
R
Reset:
0x21
Description:
IPCell identification register [31:24].
[7:0] PcellID3: 4th byte of IPCell identification register.
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2
1
0
RM0089
Serial NOR Flash controller (SMI)
17
Serial NOR Flash controller (SMI)
17.1
Register summary
Table 88.
SMI register list
Offset
Register name
Description
Page
0x00
CR1
SMI Control Register 1
on page 632
0x04
CR2
SMI Control Register 2
on page 633
0x08
SR
SMI Status Register
on page 635
0x0C
TR
SMI Transmit Register
on page 636
0x10
RR
SMI Receive Register
on page 637
Doc ID 018904 Rev 3
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Serial NOR Flash controller (SMI)
17.2
RM0089
Register descriptions
CR1
SMI Control Register 1
1
BE
2
TCS
3
PRESC
4
FAST
5
HOLD
6
ADD_LENGTH
7
SW
8
WBM
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/
W
R/
W
R/W
R/W
R/
W
R/W
R/W
R/W
Address:
SMIBaseAddress + 0x00
Type:
R/W
Reset:
0x0000 0250
Description:
SMI Control Register 1
0
[29] WBM: Write Burst Mode
0: When a AHB write request to external memory occurs, chip select is released at the end of
the AHB request and page programming cycle starts.
1: After the AHB write request, the external memory chip select remains active, until this bit is
reset. Then the page programming cycle starts.
[28] SW: Software Mode
0: Hardware mode: External memory is accessible with AHB transfers, transmit and receive
registers are not accessible.
1: Software mode : Transmit and receive registers are accessible. AHB read or write transfers
to external memory is not allowed
[27:24] ADD_LENGTH: ADD_LENGTH[3:0] are Address Length for CS[3:0] Bank
0: The address following the instruction opcode is 3 bytes long
1: The address following the instruction opcode is 2 bytes long (for EEPROM compatibility)
[23:16] HOLD: Clock Hold Period Selection
When programmed, this register stops the clock between each byte, while CS remains active
(hold).
0x00: smi_clk_o is sent continuously
0x01: 1 smi_clk_o period of hold between each byte
...
0xFF: 255 smi_clk_o periods of hold between each byte
[15] FAST: Fast Read Mode Selection
0: Normal read: opcode 0x03 + address + reception
1: Fast read: opcode 0x0B + address + dummy byte + reception
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Serial NOR Flash controller (SMI)
[14:8] PRESC: Prescaler value
0x00: fAHB divided by 1
0x01: fAHB divided by 1
..
0x7F: fAHB divided by 127
Note: The frequency is changed after the completion of the current transfer.
[7:4] TCS: Deselect Time
When CS is deselected, it remains deselected for at least (DESELECT_TIME + 1) smi_clk_o
periods. The reset value (0x5) corresponds to smi_clk_o frequency limited to 20MHz at reset.
So Tcs = 6*50ns = 300 ns.
Note: FAST and TCS have to be written at the same time as PRESC. They are all taken into
account after the completion of the current transfer.
Any check of the consistency between these three values has to be done by software.
[3:0] BE: Bank Enable Bits
0 : Bank disabled
1 : Bank enabled
Note:
- At reset, if External Memory Boot mode is selected by the microcontrollers M0 and M1
pins, all banks are disabled except Bank 0.
- If the AHB make a request on a disabled bank, an ERROR response is sent on
HRESP.
- WEN, RSR and SEND commands are not sent if the bank selected by BS is disable,
without any error message.
CR2
SMI Control Register 2
TRA_LENGTH
1
RESERVED
2
REC_LENGTH
3
SEND
4
TFIE
5
WCIE
6
RSR
7
WEN
8
BS
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R/W
R/
W
R/
W
R/
W
R/
W
R/
W
R/W
R
R/W
Address:
SMIBaseAddress + 0x04
Type:
R/W
Reset:
0x0000 0000
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Serial NOR Flash controller (SMI)
Description:
RM0089
SMI Control Register 2
[13:12] BS: Bank Select
Selects the Bank to be accessed. Only one bank can be accessed at a time. This value is
latched at the beginning of the transfer.
0b00: Bank 0
0b01: Bank 1
0b10: Bank 2
0b11: Bank 3
[11] WEN: Write Enable Command (RS bit: Read/Set bit i.e. software can read as well as set this
bit, writing 0 has no effect)
0: No effect
1: Sends a Write Enable command to the selected memory bank (selected by BS bits). Then a
write command can be sent to the memory.
Note: This bit is cleared by hardware when the Write Enable command has been sent. This bit
must not be used in order to send a write or an erase through SW mode
[10] RSR: Read Status Register Command (RS bit: Read/Set bit i.e. software can read as well as
set this bit, writing 0 has no effect)
0: No effect
1: Send the READ STATUS REGISTER command to the selected bank (selected by BS[1:0]
bits) and load the result in STATUS_REGISTER[7:0]
Note: This bit is cleared by hardware when the Read Status command has been completed.
[9] WCIE: Write Complete Interrupt Enable
0: Interrupt disabled
1: Generate an interrupt request when WRITE COMPLETE flag is set.
[8] TFIE: Transfer Finished Interrupt Enable
0: Interrupt disabled
1: Generate an interrupt request when TRANSFER FINISHED flag is set
[7] SEND: Send Command (RS bit: Read/Set bit i.e. software can read as well as set this bit,
writing 0 has no effect)
0: No effect
1: Start a transfer in the format defined by TRANSMISSION_LENGTH[2:0] +
RECEPTION_LENGTH[2:0].
Note: This bit is cleared by hardware only and can be set by software only if the SW bit in the
SMI_CR1 register is set.
[6:4] REC_LENGTH: Reception Length
This value must be written by software to define the number of bytes to be received from
external memory. This value is latched at the beginning of the software transfer.
0b000: 0 bytes
0b001: 1 byte
0b010: 2 bytes
0b011: 3 bytes
0b1xx: 4 bytes
[2:0] TRA_LENGTH: Transmission Length
This value must be written by software to define the number of bytes to be transmitted to
external memory. This value is latched at the beginning of the software transfer.
0b000: 0 bytes
0b001: 1 byte
0b010: 2 bytes
0b011: 3 bytes
0b1xx : 4 bytes
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Serial NOR Flash controller (SMI)
SR
SMI Status Register
3
STATUS_REGISTER
4
TFF
5
WCF
6
ERF1
7
ERF2
8
WM
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R/
W
R/
W
R/
W
R/
W
R
Address:
SMIBaseAddress + 0x08
Type:
R/W
Reset:
0x0000 0000
Description:
SMI Status Register
2
1
0
[13:12] WM: Write Mode for CS[1:0] banks
0: Bank x not in Write Mode (Write request to this bank is finished).
1: Bank x in Write Mode (SMI_CR1 WEN bit has been sent to this bank).
Note: This bit is not cleared by the instructions sent in SW mode.
[11] ERF2: Error Flag 2: Forbidden Write Request (RC0 bit: Read/Clear bit i.e. software can read as
well as clear this bit by writing 0, writing 1 has no effect)
0: No error
1: Write request while corresponding write_mode bit is reset, or when size is changed or
address is not incremented. An ERROR response is sent on AHB HRESP bus.
[10] ERF1: Error Flag 1: Forbidden Access (RC0 bit: Read/Clear bit i.e. software can read as well as
clear this bit by writing 0, writing 1 has no effect)
0: No error
1: Read or write access requested on disabled bank, or while SW bit is set, or Read request
while WBM is set. An ERROR response is sent on AHB HRESP bus.
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Serial NOR Flash controller (SMI)
RM0089
[9] WCF: Write Complete Flag (RC0 bit: Read/Clear bit i.e. software can read as well as clear this
bit by writing 0, writing 1 has no effect)
0: No Write Complete event
1: Write Complete.
After a write instruction, a Read Status Register command is performed by hardware, this flag
is set when the WIP bit of the SMI_SR Status Register is reset (meaning the end of
programming). The WIP bit of the memory device Status Register (STATUS_REGISTER[0])
has to be bit 0.
Note: WCF is not set during a Boot phase or by the instructions sent in SW mode.
[8] TFF: Transfer Finished Flag (RC0 bit: Read/Clear bit i.e. software can read as well as clear this
bit by writing 0, writing 1 has no effect)
0: No Transfer Finished event
1: The software transfer defined by TRANSMISSION-LENGTH + RECEPTION_LENGTH has
completed, or the SMI_CR2 register RSR or WEN commands are finished.
[7:0] STATUS_REGISTER: Memory Device Status Register
These bits are used to store a copy of the external memory status register. This register is
updated in 2 ways:
- When the SMI_CR2 RSR bit is set, STATUS_REGISTER [7:0] is updated after the RSR
sequence.
- After a write request to a memory bank, STATUS_REGISTER [7:0] is updated until the write
cycle is finished (Bit 0 of SMI_SR is cleared).
These is the meaning of various bit of STATUS_REGISTER:
[0]: WIP : The Write In Progress (WIP) bit indicates whether the memory is busy with a Write
Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset
to 0 no such cycle is in progress.
[1]: WEL : The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable
Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write
Enable Latch is reset and no Write Status Register, Program or Erase instruction of external
memory is accepted.
[2]: BP0
[3]: BP1
[4]: BP2
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. When one or more of the Block
Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area becomes protected against
Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0)
bits can be written provided that the Hardware Protected mode has not been set. The Bulk
Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.
[5]: Reserved
[6]: Reserved
[7]: SRWD : The Status Register Write Disable (SRWD) bit is operated in conjunction with the
Write Protect signal. The Status Register Write Disable (SRWD) bit and Write Protect signal
allow the device to be put in the Hardware Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect signal is driven Low). In this mode, the nonvolatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
TR
SMI Transmit Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
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9
8
7
6
5
4
3
Byte3
Byte2
Byte1
Byte0
R/W
R/W
R/W
R/W
SMIBaseAddress + 0x0C
Doc ID 018904 Rev 3
2
1
0
RM0089
Serial NOR Flash controller (SMI)
Type:
R/W
Reset:
0x0000 0000
Description:
SMI Transmit Register
[31:0] Byte[3:0]: Transmitted bytes
This register is a barrel shifter. TR[7:0] is sent first and then 8 bits are shifted.
Note:
- This register can be written only in software mode when SW=1 and SEND=0.
- SMI_TR is also used in hardware mode. If the SMI is put in hardware mode the value is
not kept.
RR
SMI Receive Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
Byte3
Byte2
Byte1
Byte0
R
R
R
R
Address:
SMIBaseAddress + 0x10
Type:
R
Reset:
0x0000 0000
Description:
SMI Receive Register
2
1
0
[31:0] Byte[3:0]: Received bytes
1st received byte is placed in RR[7:0], then in RR[14:8], then in RR[23:16], then in RR[31:24].
Note:
- In software mode, this register must be read after the TFF bit is set (otherwise the
value is not valid).
- SMI_RR is also used in hardware mode. If the SMI is put inhardware mode the value is
not kept.
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Memory card interface (MCIF)
18
18.1
RM0089
Memory card interface (MCIF)
●
Section 18.1: SD Host controller registers on page 638
●
Section 18.2: CF Host controller registers on page 675
●
Section 18.3: xD Host controller registers on page 687
●
Section 18.4: CFxD Global Interrupt registers on page 702
SD Host controller registers
Table 89.
Determining the transfer type
Multi /Single
block select
Block count enable
0
Don’t care
Don’t care
Single transfer
1
0
Don’t care
Infinite transfer
1
1
Not zero
Multiple transfer
1
1
Zero
Stop multiple transfer
Table 90.
Block count
Relation between parameters and response type name
Name of response
type
Response type
Index check enable
CRC check enable
00
0
0
No response
01
0
1
R2
10
0
0
R3, R4
10
1
1
R1, R6, R5, R7
11
1
1
R1b, R5b
Table 91.
Response type bits
Type of response
Meaning of response
Response field Response register
R[39:8](1)
REP[31:0](2)
R1b (Auto CMD12 response) Card status for Auto CMD12
R[127:8](1)
REP[127:96](2)
R2 (CID,CSD register)
CID or CSD reg. incl.
R[39:8](1)
REP[119:0](2)
R3 (OCR register)
OCR register for memory
R[39:8](1)
REP[31:0](2)
R4 (OCR register)
OCR register for I/O etc.
R[39:8](1)
REP[31:0](2)
R1,R1b (Normal response)
Card status
1. R[] refers to a bit range within the response data as transmitted on the SD Bus.
2. REP[] refers to a bit range within the Response register.
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Doc ID 018904 Rev 3
RM0089
Memory card interface (MCIF)
Table 92.
Relation between transfer complete and data timeout error
Transfer complete
Data timeout error
0
0
Interrupted by another factor
1
1
Timeout occurs during transfer
1
Don’t care
Table 93.
Meaning of the status
Data transfer complete
Relation between command complete and command timeout error
Command complete
Command timeout error
0
0
Interrupted by another factor
Don’t care
1
Response not received within 64
SDCLK cycles
1
0
Data transfer complete
Table 94.
Meaning of the status
Relation between command CRC error and command timeout error
Command CRC error
Command timeout error
0
0
No error
0
1
Response timeout error
1
0
Response CRC error
1
1
CMD line conflict
Table 95.
Kind of error
Relation between Auto CMD12 CRC error and Auto CMD12 timeout error
Auto CMD12 CRC error
Auto CMD12 timeout error
0
0
No error
0
1
Response timeout error
1
0
Response CRC error
1
1
CMD line conflict
Table 96.
Kinds of error
Maximum current value definition
Register value
Current value
0
Get information via another method
1
4 mA
2
8 mA
3
12 mA
……
……..
255
1020 mA
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Memory card interface (MCIF)
RM0089
18.1.1
SD Host controller register summary
Table 97.
SD Host controller register list
Offset
Register name
Description
Page
0x000
REG_00
SDMA System Address
on page 641
0x004
REG_01
Block Size
on page 641
0x006
REG_02
Block Count
on page 642
0x008
REG_03
Argument
on page 643
0x00C
REG_04
Transfer Mode
on page 643
0x00E
REG_05
Command
on page 644
0x010
REG_06
Response [128:0]
on page 646
0x020
REG_07
Buffer Data Port
on page 646
0x024
REG_08
Present State
on page 646
0x028
REG_09
Host Control
on page 649
0x029
REG_10
Power Control
on page 650
0x02A
REG_11
Block Gap Control
on page 651
0x02B
REG_12
Wakeup Control
on page 652
0x02C
REG_13
Clock Control
on page 653
0x02E
REG_14
Timeout Control
on page 654
0x02F
REG_15
Software reset
on page 655
0x030
REG_16
Normal Interrupt Status
on page 656
0x032
REG_17
Error Interrupt status
on page 659
0x034
REG_18
Normal Interrupt Status Enable
on page 661
0x036
REG_19
Error Interrupt Status enable
on page 662
0x038
REG_20
Normal Interrupt Signal Enable
on page 663
0x03A
REG_21
Error Interrupt Signal Enable
on page 664
0x03C
REG_22
AutoCMD12 error Status
on page 665
0x040
REG_23
Capabilities
on page 666
0x048
REG_24
Maximum Current Capabilities
on page 668
0x050
REG_25
Force Event for AutoCmd12 Error Status
on page 669
0x052
REG_26
Force event for Error Int Status
on page 670
0x054
REG_27
ADMA error status register
on page 671
0x058
REG_28
ADMA System address
on page 672
0x060
REG_29
Boot Timeout control register
on page 672
0x064
REG_30
Debug selection
on page 673
0x065
REG_31
Incr Burst control
on page 673
0x0F0
REG_32
SPI int support
on page 673
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RM0089
Memory card interface (MCIF)
Table 97.
SD Host controller register list (continued)
Offset
Register name
Description
Page
0x0FC
REG_33
Slot interrupt status
on page 674
0x0FE
REG_34
Host controller version
on page 674
18.1.2
SD Host controller register descriptions
REG_00
SDMA System Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SDMA_System_Address
R/W
Address:
SDControllerBaseAddress + 0x000
Type:
R/W
Reset:
0x0
Description:
SDMA System Address
[31:0] SDMA_System_Address: Contains the system memory address for a DMA transfer (lower 16
bits). This register contains the system memory address for a DMA transfer. When the Host
Controller (HC) stops a DMA transfer, this register shall point to the system address of the next
contiguous data position. It can be accessed only if no transaction is executing (i.e after a
transaction has stopped). Read operations during transfer return an invalid value. The Host
Driver (HD) shall initialize this register before starting a DMA transaction. After DMA has
stopped, the next system address of the next contiguous data position can be read from this
register. The DMA transfer waits at every boundary specified by the Host DMA Buffer Size in
the Block Size register. The Host Controller generates DMA Interrupt to request to update this
register. The HD sets the next system address of the next data position to this register. When
most upper byte of this register (003h) is written, the HC restart the DMA transfer. When
restarting DMA by the resume command or by setting Continue Request in the Block Gap
Control register, the HC shall start at the next contiguous address stored here in the System
Address register.
REG_01
12
11
10
9
8
7
6
5
Transfer_Block_Size
13
Host_SDMA_Buffer_Size
14
Transfer_Block_Size_12th_bit
15
Block Size
R/W
R/W
R/W
Address:
SDControllerBaseAddress + 0x004
Type:
R/W
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2
1
0
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Memory card interface (MCIF)
Reset:
0x0
Description:
Block Size
RM0089
[15] Transfer_Block_Size_12th_bit: Transfer Block Size 12th bit. This bit is added to support 4kb
data block transfer
[14:12] Host_SDMA_Buffer_Size: To perform long DMA transfer, System Address register shall be
updated at every system boundary during DMA transfer. These bits specify the size of
contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary
specified by these fields and the HC generates the DMA Interrupt to request the HD to update
the System Address register.These bits shall support when the DMA Support in the Capabilities
register is set to 1 and this function is active when the DMA Enable in the Transfer Mode
register is set to 1.
000 - 4KB(Detects A11 Carry out)
001 - 8KB(Detects A12 Carry out)
010 - 16KB(Detects A13 Carry out)
011 - 32KB(Detects A14 Carry out)
100 - 64KB(Detects A15 Carry out)
101 -128KB(Detects A16 Carry out)
110 - 256KB(Detects A17 Carry out)
111 - 512KB(Detects A18 Carry out)
[11:0] Transfer_Block_Size: This register specifies the block size for block data transfers for CMD17,
CMD18, CMD24, CMD25, and CMD53. It can be accessed only if no transaction is executing
(i.e after a transaction has stopped). Read operations during transfer return an invalid value
and write operations shall be ignored.
0x0000 - No Data Transfer
0x0001 - 1 Byte
0x0002 - 2 Bytes
0x0003 - 3 Bytes
0x0004 - 4 Bytes
--- --0x01FF - 511 Bytes
0x0200 - 512 Bytes
--- --0x0800 - 2048 Bytes
REG_02
15
14
Block Count
13
12
11
10
9
8
7
6
Block_Count_for_Current_Transfer
R/W
Address:
SDControllerBaseAddress + 0x006
Type:
R/W
Reset:
0x0
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5
4
3
2
1
0
RM0089
Memory card interface (MCIF)
Description:
Block Count
[15:0] Block_Count_for_Current_Transfer: This register is enabled when Block Count Enable in the
Transfer Mode register is set to 1 and is valid only for multiple block transfers. The HC
decrements the block count after each block transfer and stops when the count reaches zero. It
can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read
operations during transfer return an invalid value and write operations shall be ignored. When
saving transfer context as a result of Suspend command, the number of blocks yet to be
transferred can be determined by reading this register. When restoring transfer context prior to
issuing a Resume command, the HD shall restore the previously save block count.
0x0000 - Stop Count
0x0001 - 1 block
0x0002 - 2 blocks
--- --0xFFFF - 65535 blocks
For determination of data type refer to the Table 89: Determining the transfer type
REG_03
Argument
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Command_Argument
R/W
Address:
SDControllerBaseAddress + 0x008
Type:
R/W
Reset:
0x0
Description:
Argument
[31:0] Command_Argument: The SD Command Argument is specified as bit39-8 of Command
Format.
REG_04
5
4
3
2
1
0
DMA_Enable
6
Block_Count_Enable
7
Auto_CMD12_Enable
8
RESERVED
9
Data_Transfer_direction_select
10
Multi_Single_Block_Select
11
RESERVED
12
SPI_MODE
13
BOOT_EN
14
RESERVED
15
Transfer Mode
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R/W
Address:
SDControllerBaseAddress + 0x00C
Type:
R/W
Reset:
0x0
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Memory card interface (MCIF)
Description:
RM0089
Transfer Mode
[8] BOOT_EN: To start boot operation for MMC4.3
1 - To start boot mode
0 - Stop the boot read
[7] SPI_MODE: SPI mode enable bit.
1 - SPI mode
0 - SD mode
[5] Multi_Single_Block_Select: This bit enables multiple block DAT line data transfers.
0 - Single Block
1 - Multiple Block
For determination of data type refers to the Table 89: Determining the transfer type
[4] Data_Transfer_direction_select: This bit defines the direction of DAT line data transfers.
0 - Write (Host to Card)
1 - Read (Card to Host)
[2] Auto_CMD12_Enable: Multiple block transfers for memory require CMD12 to stop the
transaction.When this bit is set to 1, the HC shall issue CMD12 automatically when last block
transfer is completed. The HD shall not set this bit to issue commands that do not require
CMD12 to stop data transfer.
0 - Disable
1 - Enable
[1] Block_Count_Enable: This bit is used to enable the Block count register, which is only relevant
for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is
useful in executing an infinite transfer.
0 - Disable
1 - Enable
For determination of data type refer to the Table 89: Determining the transfer type
[0] DMA_Enable: DMA can be enabled only if DMA Support bit in the Capabilities register is set. If
this bit is set to 1, a DMA operation shall begin when the HD writes to the upper byte of
Command register (0x00F).
0 - Disable
1 - Enable
REG_05
7
6
5
4
3
2
1
0
Response_Type_Select
8
RESERVED
9
Command_CRC_Check_Enable
10
Commad_index_Check_Enable
11
Data_Present_Select
12
Command_Type
13
Command_Index
14
RESERVED
15
Command
R
R/W
R/W
R/W
R/W
R/W
R
R/W
Address:
SDControllerBaseAddress + 0x00E
Type:
R/W
Reset:
0x0
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RM0089
Memory card interface (MCIF)
Description:
Command
[13:8] Command_Index: This bit shall be set to the command number (CMD0-63, ACMD0-63).
[7:6] Command_Type: There are three types of special commands. Suspend, Resume and Abort.
These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend
command succeeds, the HC shall assume the SD Bus has been released and that it is possible
to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read
transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in
4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD
shall restart the transfer by setting Continue Request in the Block Gap Control Register.
Resume Command The HD re-starts the data transfer by restoring the registers in the range of
0x000-0x00D. The HC shall check for busy before starting write transfers. Abort Command If
this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this
command is set when executing a write transfer, the HC shall stop driving the DAT line. After
issuing the Abort command, the HD should issue a software reset
00 - Normal
01 - Suspend
10 - Resume
11 - Abort
[5] Data_Present_Select: This bit is set to 1 to indicate that data is present and shall be
transferred using the DAT line. If is set to 0 for the following:
1. Commands using only CMD line (ex. CMD52)
2. Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b ex.
CMD38)
3. Resume Command
0 - No Data Present
1 - Data Present
[4] Commad_index_Check_Enable: If this bit is set to 1, the HC shall check the index field in the
response to see if it has the same value as the command index. If it is not, it is reported as a
Command Index Error. If this bit is set to 0, the Index field is not checked.
0 - Disable
1 - Enable
For relation between parameters an the name of response type refer to Table 90: Relation
between parameters and response type name
[3] Command_CRC_Check_Enable: If this bit is set to 1, the HC shall check the CRC field in the
response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0,
the CRC field is not checked.
0 - Disable
1 - Enable
For relation between parameters an the name of response type refer to Table 90: Relation
between parameters and response type name
[1:0] Response_Type_Select: Response Type Select
00 - No Response
01 - Response length 136
10 - Response length 48
11 - Response length 48 check
Busy after response
For relation between parameters an the name of response type refer to Table 90: Relation
between parameters and response type name
Doc ID 018904 Rev 3
645/1728
Memory card interface (MCIF)
RM0089
REG_06
Response [128:0]
128
...
0
Command_Response_128_0
R
Address:
SDControllerBaseAddress + 0x010
Type:
R
Reset:
0x0
Description:
Response [128:0]
[127:0] Command_Response_128_0: Table 91: Response type bits describes the mapping of
command responses from the SD Bus to this register for each response type. In the table, R[]
refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit
range within the Response register.
REG_07
Buffer Data Port
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Buffer_Data
R/W
Address:
SDControllerBaseAddress + 0x020
Type:
R/W
Reset:
0x0
Description:
Buffer Data Port
[31:0] Buffer_Data: The Host Controller Buffer can be accessed through this 32-bit Data Port
Register.
REG_08
Present State
Buffer_Write_Enable
Read_Transfer_Active
Write_transfer_active
RESERVED
Dat_line_active
Command_inhibit_DAT
Command_Inhibit_CMD
0
Buffer_Read_Enable
1
RESERVED
2
Card_Inserted
3
Card_State_stable
4
Card_detect_pin_level
5
Write_Protect_Switch_pin_level
6
DAT_3_0_line_signal_level
7
CMD_line_signal_level
8
DAT_7_4_line_signal_level
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Address:
SDControllerBaseAddress + 0x024
Type:
R
Reset:
0x1FF0 0000
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Doc ID 018904 Rev 3
RM0089
Memory card interface (MCIF)
Description:
Present State
[28:25] DAT_7_4_line_signal_level: This status is used to check DAT line level to recover from errors,
and for debugging.
D12 - DAT[7]
D11 - DAT[6]
D10 - DAT[5]
D09 - DAT[4]
[24] CMD_line_signal_level: This status is used to check CMD line level to recover from errors,
and for debugging.
[23:20] DAT_3_0_line_signal_level: This status is used to check DAT line level to recover from errors,
and for debugging. This is especially useful in detecting the busy signal level from DAT[0].
D07 - DAT[3]
D06 - DAT[2]
D05 - DAT[1]
D04 - DAT[0]
[19] Write_Protect_Switch_pin_level: The Write Protect Switch is supported for memory and
combo cards.
This bit reflects the SDWP# pin.
0 - Write protected (SDWP# = 1)
1 - Write enabled (SDWP# = 0)
[18] Card_detect_pin_level: This bit reflects the inverse value of the SDCD# pin.
0 - No Card present (SDCD# = 1)
1 - Card present (SDCD# = 0)
[17] Card_State_stable: This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable.
If this bit is set to 1, it means the Card Detect Pin Level is stable. The Software Reset For All in
the Software Reset Register shall not affect this bit.
0 - Reset of Debouncing
1 - No Card or Inserted
[16] Card_Inserted: This bit indicates whether a card has been inserted. Changing from 0 to 1
generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1
to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software
Reset For All in the Software Reset register shall not affect this bit. If a Card is removed while
its power is on
and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and
SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the
Software Reset For All in Software register. The card detect is active regardless of the SD Bus
Power.
0 - Reset or Debouncing or No Card
1 - Card Inserted
[11] Buffer_Read_Enable: This status is used for non-DMA read transfers. This read only flag
indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists
in the buffer.
A change of this bit from 1 to 0 occurs when all the block data is readfrom the buffer. A change
of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the
Buffer Read Ready Interrupt.
0 - Read Disable
1 - Read Enable.
Doc ID 018904 Rev 3
647/1728
Memory card interface (MCIF)
RM0089
[10] Buffer_Write_Enable: This status is used for non-DMA write transfers.This read only flag
indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A
change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of
this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the
Buffer Write Ready Interrupt.
0 - Write Disable
1 - Write Enable.
[9] Read_Transfer_Active: This status is used for detecting completion of a read transfer.
This bit is set to 1 for either of the following conditions:
1. After the end bit of the read command
2. When writing a 1 to continue Request in the Block Gap Control register to restart a read
transfer
This bit is cleared to 0 for either of the following conditions:
1. When the last data block as specified by block length is transferred to the system.
2. When all valid data blocks have been transferred to the system and no current block transfers
are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete
interrupt is generated when this bit changes to 0.
1 - Transferring data
0 - No valid data
[8] Write_transfer_active: This status indicates a write transfer is active. If this bit is 0, it means
no valid write data exists in the HC. This bit is set in either of the following cases:
1. After the end bit of the write command.
2. When writing a 1 to Continue Request in the Block Gap Control register to restart a write
transfer.
This bit is cleared in either of the following cases:
1. After getting the CRC status of the last data block as specified by the transfer count (Single
or Multiple)
2. After getting a CRC status of any block where data transmission is about to be stopped by a
Stop At Block Gap Request.
During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to
0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in
determining when to issue commands during write busy.
1 - transferring data
0 - No valid data
648/1728
Doc ID 018904 Rev 3
RM0089
Memory card interface (MCIF)
[2] Dat_line_active: This bit indicates whether one of the DAT line on SD bus is in use.
1 - DAT line active
0 - DAT line inactive
[1] Command_inhibit_DAT: This status bit is generated if either the DAT Line Active or the Read
transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command.
Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type).
Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status
register.
Note: The SD Host Driver can save registers in the range of 0x000-0x00D for a suspend
transaction after this bit has changed from 1 to 0.
1 - cannot issue command which uses the DAT line
0 - Can issue command which uses the DAT line
[0] Command_Inhibit_CMD: If this bit is 0, it indicates the CMD line is not in use and the HC can
issue a SD command using the CMD line. This bit is set immediately after the Command
register (00Fh) is written. This bit is cleared when the command response is received.
Even if the Command Inhibit (DAT) is set to 1,
Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
generates a Command complete interrupt in the Normal Interrupt Status register. If the HC
cannot issue the command because of a command conflict error or because of Command Not
Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set.
Status issuing Auto CMD12 is not read from this bit.
REG_09
0
Led_control
1
Data_transfer_width_SD1_or_SD4
2
High_speed_enable
3
DMA_select
4
SD8_bit_mode
5
Card_detect_test_level
6
Card_detect_signal_detection
7
Host Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
SDControllerBaseAddress + 0x028
Type:
R/W
Reset:
0x0
Doc ID 018904 Rev 3
649/1728
Memory card interface (MCIF)
Description:
RM0089
Host Control
[7] Card_detect_signal_detection: This bit selects source for card detection.
1- The card detect test level is selected
0 -SDCD# is selected (for normal use)
[6] Card_detect_test_level: This bit is enabled while the Card Detect Signal Selection is set to 1
and it indicates card inserted or not.
1 - Card Inserted
0 - No Card
[5] SD8_bit_mode: This bit selects the data width of the HC. The HD shall select it to match the
data width of the SD card.
1 - 8 bit mode is selected
0 - 8 bit mode is not selected
[4:3] DMA_select: One of supported DMA modes can be selected. The host driver shall check
support of DMA modes by referring the Capabilities register.
00 - SDMA is selected
01 - 32-bit Address ADMA1 is selected
10 -32-bit Address ADMA2 is selected
11 - 64-bit Address ADMA2 is selected
[2] High_speed_enable: This bit is optional. Before setting this bit, the HD shall check the High
Speed Support in the capabilities register. If this bit is set to 0 (default), the HC outputs CMD
line and DAT lines at the falling edge of the SD clock (up to 25 MHz/20MHz for MMC). If this bit
is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50
MHz for SD/52MHz for MMC)
1 - High Speed Mode
0 - Normal Speed Mode
[1] Data_transfer_width_SD1_or_SD4: This bit selects the data width of the HC. The HD shall
select it to match the data width of the SD card.
1 - 4 bit mode
0 - 1 bit mode
[0] Led_control: This bit is used to caution the user not to remove the card while the SD card is
being accessed. If the software is going to issue multiple SD commands, this bit can be set
during all transactions. It is not necessary to change for each transaction.
1 - LED on
0 - LED off
REG_10
4
2
1
0
R
R/W
R/W
Address:
SDControllerBaseAddres