Si5040 10 Gbps XFP Transceiver Description Summary of Key Features - Continuous operation from 9.95 to 11.4 Gbps - Transmit jitter attenuation with selectable loop The Si5040 is a high performance, protocol agnostic 10 Gbps XFP transceiver featuring integrated jitter attenuating capability based on Silicon Laboratories’ proven DSPLL technology. The device is designed to perform reshaping, re-amplifying, and retiming of the bi-directional 10 Gbps serial data by integrating two independent Clock and Data Recoveries (CDRs), two DSPLL-based Clock Multiplier Units (CMUs), and data re-timers in both transmit and receive directions. The DSPLL-based CMU and the data re-timer in the transmit direction eliminate the need for external jitter clean up circuitry to achieve compliance with telecom and datacom jitter specifications. The same DSPLL technology minimizes jitter in the receive path ensuring error free operation with ASICs or FPGAs connected via the XFI interface. The Si5040 provides three receive signal quality monitors including analog loss-of-signal (LOS) detection, consecutive identical digit (CID) detection, and a proprietary digital measure of receive eye opening. Comprehensive diagnostics are also supported via two loop back modes as well as pattern generation and check capability on both the receive and transmit data paths. The Si5040 provides industry leading jitter performance for all telecom and datacom protocols between 9.9 and 11.4 Gbps, including OC-192/STM-64, 10 GbE, 10 G Fiber Channel, and their associated forward error correction (FEC) data rates: bandwidths from 200 Hz to 1.2 MHz - SONET jitter generation 2.5 mUI RMS - SONET jitter tolerance > 0.55UIpp (0.15UIpp spec) - Integrated limiting amplifier with high input sensitivity: 5 mV ppd Typ - Auto-slice adjustment (programmable adjust optional) - Programmable sample phase adjust - Three signal quality monitors: loss-of-signal (LOS) - Applications - XFP Optical Module - Line card and Backplane - Regenerate 10 Gbps electrical signal for longer - OC192/STM64: 9.95 Gbps 10 Gbps Ethernet LAN PHY: 10.3125 Gbps 10 Gbps Fibre Channel: 10.51875 Gbps G.709 OTU2: 10.709 Gbps 10 Gbps Ethernet + FEC: 11.0957 Gbps 10 Gbps Fibre Channel + FEC: 11.3176 Gbps To address XFP module space and power constraints, the Si5040 comes in a 5 x 5 mm LGA package and only consumes 575 mW typ. Optical Line Side RX_LOS detector, consecutive identical digit (CID) detector, and a receive eye opening monitor PRBS or user-defined pattern generation and checking in both TX and RX directions Operation over wide power supply variation (–10% to +5%) Industrial temperature operation (–40 to +85 °C) Adjustable output swing Low power: 575 mW (typ) Small size: 5 x 5 mm LGA Serial microcontroller interface reach of the PCB trace - Added jitter attenuation with jitter transfer compliance - Added jitter tolerance - CWDM - Complete regeneration of the 10 Gbps signal in O/E/O applications - Optical Test Equipment - 10 Gbps Standalone Clock and Data Recovery - 10 Gbps Standalone Optical Transmitter RX_LOL XFI System Side Phase Adjust RXDIN LA RX Pattern Check CDR RX Pattern Gen FIFO & ReTimer D Clk CML Slice Adjust Alarms DSPLL® Jitter Attenuator XFI Loopback Optional Crystal Line Loopback Serial Port DSPLL® Jitter Attenuator TXDOUT FIFO & ReTimer CML TX Pattern Gen Networking Products RD Interrupt µController Interface (I2C or 3-wire) RefCLK (optional) D Clk CDR Equalizer TD TX Pattern Check Copyright © 2006 by Silicon Laboratories 1.5.2006 Si5040 10 Gbps XFP Transceiver Selected Electrical Specifications Parameter Symbol Min Typ Max TA –40 25 85 VDD 1.62 1.80 1.89 V VDDIO 1.62 — 3.63 V — 575 — mW 9.90 9.95 11.4 Gbps 8 — 1000 mV Analog LOS Range 10 — 400 mVPPD Analog LOS Accuracy 1 — — Consecutive Identical Digit Detection (CID) Range 0.5 — 100 uS Consecutive Identical Digit Detection (CID) Accuracy 0.5 — — uS F = 2.0 KHz 1.5 3.0 — UIPP F = 20 KHz 1.5 3.0 — UIPP F = 400 KHz 1.5 3.0 — UIPP F = 4 MHz 0.4 — — UIPP F = 400 MHz 0.55 — — UIPP Ambient Temperature Supply Voltage LVTTL I/O Supply Voltage Power Dissipation PD Test Condition VDD = 1.89 V VDDIO = 3.3 V Data Rate Unit o C RXDIN Differential Input Swing VID Jitter Tolerance (OC-192 at BER = 1E-12) JTOL(PP) At BER = 1E-12 TXDOUT Random RMS Jitter Generation Total Peak-to-Peak Jitter Generation Jitter Transfer Bandwidth (Programmable) Input Reference Clock Frequency JGEN(RMS) With PRBS31 at 50 kHz–80 MHz — 2.5 — mUIRMS JGEN(PP) With PRBS31 at 50 kHz–80 MHz — 20 — mUIPP 200 — 1.2 M Hz 622 or 155 — 712.5 or 178.125 MHz JBM RCFREQ Data Rate/16 or Data Rate/64 Package Information Networking Products Copyright © 2006 by Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 1.5.2006